TPS24742RGER [TI]
具有功率限制功能和 ORing 的 2.5V 至 18V 热插拔控制器 | RGE | 24 | -40 to 125;型号: | TPS24742RGER |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有功率限制功能和 ORing 的 2.5V 至 18V 热插拔控制器 | RGE | 24 | -40 to 125 控制器 |
文件: | 总62页 (文件大小:3536K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Sample &
Buy
Support &
Community
Product
Folder
Tools &
Software
Technical
Documents
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
TPS2474x 2.5V 至 18V 高性能热插拔和 ORing 控制器
查询样片: TPS24740, TPS24741, TPS24742
1 特性
3 说明
1
•
2.5V 至 18V 总线操作(30V 绝对最大值)
可编程保护设置:
TPS2474x 是一款针对 2.5V 至 18V 系统的集成
ORing 和 热插拔控制器。 该控制器精确且具有可编程
保护设置,对设计故障隔离要求较高的高功率、高可用
性系统很有帮助。
•
–
–
–
电流限制:10mV 时为 ±5%
快速跳变:20mV 时为 ±10%
反向电压:–1mV 时为 ±1mV
该控制器还具有可编程电流限制、快速关断和故障定时
器功能,可在热短路等故障期间保护负载和电源。 可
调整快速关断阈值和响应时间,以确保快速响应实际故
障,同时避免误跳变。 该器件具有可编程的 SOA(安
全工作区域)保护和浪涌定时器,可在所有工作条件下
对金属氧化物半导体场效应晶体管 (MOSFET) 加以保
护。 TPS2474x 将电源正常状态标志置为有效后,会
在过流事件期间运行故障定时器,但不会限制电流。
当故障定时器到期后,控制器会关断。 该控制器具有
两个独立定时器(浪涌/故障),用户可根据系统需求
定制保护功能。 用户可利用 TPS2474x 的 ORing 功
能来编程反向电压阈值和响应时间,以简化冗余电源系
统的设计。
•
•
•
•
•
•
•
•
•
•
快速跳变和反向电压可编程响应时间
可编程场效应管 (FET) 安全运行区域 (SOA) 保护
双定时器(浪涌/故障)
可互换的热插拔和 ORing
模拟电流监视器(25mV 时为 1%)
故障和电源正常状态标志
欠压 (UV) 和过压 (OV) 保护
热插拔与 ORing 独立使能
4mm × 4mm 24 引脚四方扁平无引线 (QFN) 封装
40 = 锁存,41 = 重试,42 = 快速锁存关闭
2 应用
•
•
•
•
企业级存储
器件信息(1)
电源多路复用
冗余电源
器件型号
TPS24740
封装
封装尺寸(标称值)
备用电池
TPS24741
TPS24742
VQFN (24)
4.00mm x 4.00mm
(1) 要了解所有可用封装,请见数据表末尾的可订购产品附录。
4 简化电路原理图
sp
HS FET
BS FET
TPS2474x(优先多路复用)
VOUT
RSENS
VIN
COUT
C1
CRV
CFST
MAIN
Hotswap
RHG
OR
TPS2474x
RBG
C
BGATE
A
RVSNM RVSNP VDD SET FSTP
SENM HGATE
To Load
OFF if
VMAIN > 11 V
CP
OUTH
PGHS
CP
AUX
Hotswap
TPS2474x
FLTb
IMONBUF
STAT
ENOR
OR
TPS2474x
ENHS
OV
PLIM
TINR
TFLT
IMON
GND
CINR
CFLT
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLVSCV6
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
目录
9.2 Functional Block Diagram ....................................... 13
9.3 Feature Description................................................. 14
9.4 Device Functional Modes........................................ 20
10 Application and Implementation........................ 23
10.1 Application Information.......................................... 23
10.2 Typical Application ............................................... 23
10.3 System Examples ................................................ 41
11 Power Supply Recommendations ..................... 51
12 Layout................................................................... 51
12.1 Layout Guidelines ................................................. 51
12.2 Layout Example .................................................... 52
13 器件和文档支持 ..................................................... 53
13.1 相关链接................................................................ 53
13.2 商标....................................................................... 53
13.3 静电放电警告......................................................... 53
13.4 术语表 ................................................................... 53
14 机械封装和可订购信息 .......................................... 53
1
2
3
4
5
6
7
8
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
简化电路原理图........................................................ 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
8.1 Absolute Maximum Ratings ...................................... 4
8.2 ESD Ratings ............................................................ 5
8.3 Recommended Operating Conditions....................... 5
8.4 Thermal Information ................................................. 5
8.5 Electrical Characteristics........................................... 6
8.6 Timing Requirements ............................................... 9
8.7 Typical Characteristics............................................ 10
Detailed Description ............................................ 13
9.1 Overview ................................................................. 13
9
5 修订历史记录
Changes from Original (January 2015) to Revision A
Page
•
Published full Production Data sheet to include Specification tables, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 4
2
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
6 Device Comparison Table
PART NUMBER(1)
TPS24740
LATCH / RETRY OPTION
Latch
TPS24741
Auto – Retry
TPS24742
Fast Latch Off
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
7 Pin Configuration and Functions
QFN 24-Pin with Thermal Pad
RGE Package
Top View
19
24
23
22
21
20
CP
HGATE
SENM
FSTP
SET
ENHS
ENOR
TPS2474x
FLTb
PGHS
STAT
VDD
IMONBUF
7
9
11
8
10
12
Table 1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
Voltage sense input that connects to the OR MOSFET's body diode's anode. Connect to the OR
MOSFET source in the typical configuration. A pin is used to supply power to the ORing block of the
TPS2474x under certain biasing conditions.
A
23
I/P
O
Connect to the gate of the external OR MOSFET. Controls the OR MOSFET to emulate a low forward-
voltage diode.
BGATE
C
22
20
Voltage sense input that connects to the OR MOSFET's body diode's cathode. Connect to the OR
MOSFET drain in the typical configuration. C pin is used to supply power to the ORing block of the
TPS2474x under certain biasing conditions.
I/P
CP
1
2
3
I/O
Connect a storage capacitor from CP to A for fast turn-on of blocking Gate.
Active-high enable input of Hot-swap. Logic input. Connects to resistor divider.
Active-high enable input of Oring. Logic input. Connects to resistor divider.
ENHS
ENOR
I
I
(1) I = Input; O = Output ; P = Power
Copyright © 2015, Texas Instruments Incorporated
3
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
Table 1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
FLTb
4
O
I
Active-low, open-drain output indicating various faults.
Fast trip programming set pin for hot-swap. A resistor is connected from positive terminal of the sensing
resistor to FSTP.
FSTP
16
GND
10
18
12
13
–
O
Ground.
HGATE
IMON
Gate driver output for external Hot Swap MOSFET.
Analog current monitor and load current limit program point. Connect RIMON to ground.
Voltage output proportional to the load current (0V–3.0V).
I/O
O
IMONBUF
Output voltage sensor for monitoring Hot Swap MOSFET power. Connects to the source terminal of the
hot-swap N channel MOSFET.
OUTH
19
I
Overvoltage comparator input. Connects to resistor divider. HGATE and BGATE are pulled low when
OV exceeds the threshold. Connect to ground when not used.
OV
9
5
I
O
I
PGHS
PLIM
Active-high, open-drain power-good indicator.
Power-limiting programming pin. A resistor from this pin to GND sets the maximum power dissipation for
the Hot Swap FET.
11
Positive input of the reverse voltage comparator. Connect a resistor from RVSNP to C to set the reverse
voltage trip point of the blocking FET.
RVSNP
RVSNM
SENM
21
24
17
I
I
I
Negative input of the reverse voltage comparator.
Current-sensing input for the sensing resistor. Directly connects to the negative terminal of the sensing
resistor.
Current-limit programming set pin for hot-swap. A resistor is connected from positive terminal of the
sensing resistor.
SET
15
I
STAT
TFLT
TINR
VDD
6
8
O
I/O
I/O
P
High when BGATE is ON.
Fault timer, which runs when the device goes from regular operation to an over-current condition.
Inrush timer, which runs during the inrush operation (start-up) if the part is in current limit or power limit.
Power Supply.
7
14
8 Specifications
8.1 Absolute Maximum Ratings
Unless otherwise noted, these apply over recommended operating junction temperature: -40°C ≤ TJ ≤ 125°C.
(1)
MIN
MAX
UNIT
CP, BGATE
–0.3
40
V
VDD,SET, FSTP,SENM, OUTH, C, RVSNP, RVSNM, A, ENHS, ENOR, FLTb, PGHS, OV,
STAT
–0.3
30
V
CP, BGATE to A
HGATE to OUTH
SET to VDD
–0.3
–0.3
–0.3
–0.6
–30
12
15
0.3
0.3
7
V
V
V
V
V
Input Voltage
SENM, FSTP to VDD
A to C
RVSNM, to A, C, RVSNP
RVSNP to A, C, RVSNM
–30
30
V
TINR, TFLT, PLIM, IMON,
IMONBUF
–0.3
–0.3
3.6
7
V
V
Sink Current
FLTb, PGHS, STAT
5
mA
mA
°C
Source Current IMON, IMONBUF
Storage temperature range, Tstg
5
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
4
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
8.2 ESD Ratings
VALUE
±1500
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(2)
Charged-device model (CDM), per JEDEC specification JESD22-C101(3)
Electrostatic
discharge
(1)
V(ESD)
V
(1) Electrostatic discharge (ESD) measures device sensitivity and immunity to damage caused by assembly line electrostatic discharges
into the device.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
These apply over recommended operating junction temperature: -40°C ≤ TJ ≤ 125°C.
MIN
2.5
0
MAX
18
UNIT
VDD, SENM, SET(1), FSTP
Input voltage
ENHS, ENOR, FLTb, PGHS, STAT, OUTH
18
V
(2)
A, C, RVSNM, RVSNP;
0.7
0
18
Sink current
FLTb, PGHS, STAT
IMON
2
mA
mA
kΩ
kΩ
Ω
Source current
0
1
PLIM
4.99
1
500
6
IMON
External resistance
RVSNP
FSTP
10
10
10
10
3
1000
4000
400
70
Ω
SET
Ω
(3)
w/o RSTBL
RIMON / RSET
With appropriate RSTBL
10
CP, FSTP, RVSNP
1
1000
1
nF
µF
nF
pF
pF
°C
(4)
HGATE, BGATE
0
External capacitor
TINR, TFLT
IMON
1
30
100
125
IMONBUF
Operating junction temperature, TJ
–40
(1) Do not apply voltage to these pins.
(2) For the HS then ORing application these pins may be below the recommended minimum during start-up. The part is designed to
function properly under these scenarios. However the part should not be used with a bus voltage below the recommended voltage.
(3) Refer to RSTBL Requirement for RIMON / RSET < 10 describe in section Select RSNS and VSNS,CL Setting.
(4) External capacitance tied to HGATE, BGATE should be in series with a resistor no less than 1kΩ.
8.4 Thermal Information
TPS2470, TPS24741,
TPS24742
THERMAL METRIC(1)
UNIT
RGE (24 PINS)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
34.6
38.4
12.9
0.5
RθJC(top)
RθJB
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
12.9
3.2
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2015, Texas Instruments Incorporated
5
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
8.5 Electrical Characteristics
Unless otherwise noted these limits apply to the following: -40°C ≤ TJ ≤ 125°C; 2.5V < VVDD , VOUTH < 18V; 0.7 V < VA , VC ,
VRVSNM < 18 V; VENHS = VENOR = 2 V, VOV = 0 V; VBGATE, VHGATE, VPGHS, VSTAT, VFLTb, and VIMONBUF are floating; CCP = 100 nF,
CINR = 1 nF, CFLT = 1 nF, RSET = 44.2 Ω, RIMON = 2.98 kΩ, RFSTP = 200 Ω, RRV = 200 Ω, and RPLIM = 52 kΩ.
PARAMETER
TEST CONDITION
Device on, VENHS = VENOR = 2V
0 ≤ VENHS ≤ 30V
MIN
TYP
MAX
2.45
6
UNIT
INPUT SUPPLY (VDD)
VUVR
VUVhyst
IQON
UVLO threshold, rising
UVLO hysteresis
2.2
2.32
0.1
V
V
Supply current: IVDD+IA+IC+ IOUTH
4.2
mA
HOT SWAP FET ENABLE (ENHS)
VENHS
Threshold voltage, rising
1.3
–1
1.35
50
1.4
1
V
VENHShyst
IENHS
Hysteresis
mV
µA
Input Leakage Current
BLOCKING (ORING) FET ENABLE (ENOR)
VENOR
Threshold voltage, rising
Hysteresis
1.3
–1
1.35
50
0
1.4
1
V
VENORhyst
IENOR
mV
µA
Input leakage current
0 V ≤ VENOR ≤ 30V
OVER VOLTAGE (OV)
VOVR
VOVhyst
IOV
Threshold voltage, rising
1.3
–1
1.35
50
1.4
1
mV
mV
µA
Hysteresis
Input leakage current
0 ≤ VOV ≤ 30V
POWER LIMIT PROGRAMING (PLIM)
VPLIM,BIAS
Bias voltage
Sourcing 10μA
0.66
114.75
56.95
18.9
0.675
0.69
V
RPLIM = 52 kΩ; VSENM-OUTH=12V;
RPLIM = 105 kΩ; VSENM-OUTH=12V;
RPLIM = 261 kΩ; VSENM-OUTH=12V;
RPLIM = 105 kΩ; VSENM-OUTH=2V;
RPLIM = 105 kΩ; VSENM-OUTH=18V;
135 155.25
67
27
77.05
35.1
VIMON,PL
Regulated IMON voltage during power limit
mV
341.7
38.25
402
45
462.3
51.75
SLOW TRIP THRESHOLD (SET)
VOS_SET Input referred offset (VSNS to VIMON scaling)
VGE_SET
Gain error (VSNS to VIMON scaling)(1)
FAST TRIP THRESHOLD PROGRAMMING (FSTP)
–150
150
µV
RSET = 44.2Ω; RIMON=3kΩ to 1.2kΩ (corresponds to
VSNS,CL=10mV to 25mV)
–0.4%
0.4%
IFSTP
FSTP input bias current
VFSTP=12V
95
18
100
20
105
22
µA
RFSTP = 200 Ω, VSNS when VHGATE
↓
VFASTRIP
Fast trip threshold
RFSTP = 1 kΩ, VSNS when VHGATE
RFSTP = 4 kΩ, VSNS when VHGATE
↓
95
100
400
105
420
mV
↓
380
CURRENT MONITOR and CURRENT LIMIT PROGRAMING (IMON)
VIMON,CL Slow trip threshold at summing node IMON↑, when ITFLT starts sourcing
CURRENT MONITOR (IMONBUF)
V
660
675
690
mV
VOS_IMONBUF
GAINIMONBUF
BWIMONBUF
Buffer offset
VIMON = 50mV to 675mV, Input referred
ΔVIMONBUFF / ΔVIMON
–3
0
2.99
1
3
mV
V
Buffer voltage gain
Buffer closed loop bandwidth
2.97
3.01
CIMONBUF = 75pF
MHz
(1) Specified by characterization, not production tested.
6
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
Electrical Characteristics (continued)
Unless otherwise noted these limits apply to the following: -40°C ≤ TJ ≤ 125°C; 2.5V < VVDD , VOUTH < 18V; 0.7 V < VA , VC ,
VRVSNM < 18 V; VENHS = VENOR = 2 V, VOV = 0 V; VBGATE, VHGATE, VPGHS, VSTAT, VFLTb, and VIMONBUF are floating; CCP = 100 nF,
CINR = 1 nF, CFLT = 1 nF, RSET = 44.2 Ω, RIMON = 2.98 kΩ, RFSTP = 200 Ω, RRV = 200 Ω, and RPLIM = 52 kΩ.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
HOT SWAP GATE DRIVER (HGATE)
5 ≤ VVDD ≤ 16V; measure VGATE-OUTH
12
7
13.6
7.95
15.5
15
V
V
VHGATE
HGATE output voltage
2.5V <VVDD < 5V;
16V <VVDD < 20V measure VGATE-OUTH
VHGATEmax
IHGATEsrc
IHGATEfastSink
IHGATEsustSink
Clamp voltage
Inject 10μA into HGATE, measure V(HGATE – OUTH)
VHGAT-OUTH = 2V-10V
12
44
13.9
55
1
15.5
66
V
µA
A
Sourcing current
Sinking current for fast trip
Sustained sinking current
VHGATE-OUTH = 2V -15V; V(FSTP – SENM) = 20mV
Sustained, VHGATE-OUTH = 2V – 15V; VENHS = 0
0.45
30
1.6
60
44
mA
CURRENT SENSE NEGATIVE INPUT (SENM)
ISENM Input bias current
INRUSH TIMER (TINR)
VSENM = 12V
15
20
µA
ITINRsrc
ITINRsink
VTINRup
Sourcing current
VTINR = 0V, In power limit or current limit
VTINR = 2V, In regular operation
8
1.5
1.3
10.25
2
12.5
2.5
µA
µA
V
Sinking current
Upper threshold voltage
Raise VTINR until HGATE starts sinking
1.35
1.4
Raise VTINR to 2V. Reduce VTINR until ITINR is
sinking.
VTINRlr
Lower threshold voltage
0.33
0.35
0.37
v
RTINR
Bleed down resistance
Pulldown current
VVDD = 0V, VTINR = 2V
70
2
104
4.2
130
7
kΩ
ITINR-PD
VTINR = 2V, when VENHS = 0V
mA
RPLIM = 52kΩ, VSENM = 12V, VOUTH = 0 V. Raise
IMON voltage and record IMON when TINR starts
sourcing current
(2)
VIMON,TINR
See
47.75
90 132.25
mV
RPLIM = 52kΩ, VSENM = 12V, VOUTH = 0 V. Raise
IMON voltage and record IMON when IHGATE starts
sourcing current
(2)
VIMON,PL
See
114.75
23
135 155.25
mV
mV
RPLIM = 52kΩ, VSENM = 12V, VOUTH = 0 V.
ΔVIMON,TINR = VIMON,PL – VIMON,TINR
(2)
ΔVIMON,TINR
See
45
67
FAULT TIMER (TFLT)
ITFLTsrc
ITFLTsink
VTFLTup
RTFLT
Sourcing current
VTFLT = 0V, PGHS is hi and in overcurrent
VTFLT = 2V, Not in overcurrent
Raise VTFLT until HGATE starts sinking
VVDD = 0V, VTFLT = 2V
8
1.5
1.3
70
2
10.25
2
12.5
2.5
1.4
130
7
µA
µA
V
Sinking current
Upper threshold voltage
Bleed down resistance
Pulldown current
1.35
104
5.6
kΩ
mA
ITFLT-PD
VTFLT = 2V, when VENHS = 0V
HOT SWAP OUTPUT (OUTH)
IOUTH, BIAS
Input bias current
VOUTH = 12V
30
70
µA
kΩ
V
CHARGE PUMP FOR BGATE (CP)
ICP
CP Equivalent charging resistance
VA = 12 V , 1mA CP current
5
9
5
8
8.7
10
12.5
11
Max(VA, VC, VVDD) > 6 V, Measure VCP-A
6V > Max(VA, VC, VVDD) > 4V, Measure VCP-A
Max(VA, VC, VVDD) = 2.5 V, Measure VCP-A
VCP
CP Output voltage
5.9
9.8
11
11
BLOCKING/ORING GATE DRIVER (BGATE)
VAC = 20mV, pulse
30
0.3
0.9
35
mA
mA
A
IBGATE_CHRG
BGATE Pull up current
BGATE Sinking current
VAC = 20mV, sustained
Fast turnoff, VBGATE-A = 7V
Sustained, VBGATE-A = 2V to 11V
0.2
0.4
19
0.4
1.4
65
IBGATEsustSink
mA
(2) For more detail on the definition and usage of these parameters refer to section Using SoftStart – IHGATE and TINR Considerations.
Copyright © 2015, Texas Instruments Incorporated
7
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
Electrical Characteristics (continued)
Unless otherwise noted these limits apply to the following: -40°C ≤ TJ ≤ 125°C; 2.5V < VVDD , VOUTH < 18V; 0.7 V < VA , VC ,
VRVSNM < 18 V; VENHS = VENOR = 2 V, VOV = 0 V; VBGATE, VHGATE, VPGHS, VSTAT, VFLTb, and VIMONBUF are floating; CCP = 100 nF,
CINR = 1 nF, CFLT = 1 nF, RSET = 44.2 Ω, RIMON = 2.98 kΩ, RFSTP = 200 Ω, RRV = 200 Ω, and RPLIM = 52 kΩ.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
BLOCKING/ORing ANODE (A)
IA
Input current(3)
2.5 V ≤ VA ≤ 18V
3
mA
V
VA_UVLO
VA_UVLO_hyst
Undervoltage lockout
VA increasing and VVDD=VC=0.7V
1.85
1.93
0.1
2.05
Undervoltage lockout hysteresis
V
BLOCKING/ORing CATHODE (C)
IC
Input current(3)
2.5 V ≤ VC ≤ 18V
3
mA
V
VC_UVLO
VC_UVHyst
VFWDTH
Undervoltage lockout
Hysteresis
VC increasing and VDD=VA=0.7V
1.85
7.5
1.93
100
10
2.05
mV
mV
Forward turn-on voltage
Measure VAC when VBGATE ↑
12.5
POSITIVE INPUT OF REVERSE VOLTAGE COMPARATOR (RVSNP)
VRVSNP = 12V, sinking current; 0.7V < VA,
VRVSNM < 20V
IRVSNP
RVSNP Input bias current
93
-1
99
0
105
1
µA
VRVTRIP1
Reverse Comparator Offset
RRV=10Ω, Measure VRVSNP-RVSNM, when BGATE↓
mV
NEGATIVE INPUT OF REVERSE VOLTAGE COMPARATOR (RVSNM)
IRVSNM Leakage current
FAULT INDICATOR (FLTb)
VOL_FLTb Output low voltage
IFLTb Input Leakage Current
VHSFLT_IMON
VHSFL_hyst
–2
2
µA
Sinking 2 mA
0.11
0
0.25
1
V
VFLTb = 0V, 30V
–1
88
µA
mV
mV
VIMON threshold to detect Hot Swap FET short VENHS = 0V, Measured VIMON ↑ to GND when FLTb ↓
101
25
115
Hysteresis
A-C threshold to detect OPEN Blocking/ORing
VENOR=3V, Measure VA-C to FLTb↓, VCP-A > 7V
FET fault
VBFET, OPEN, FLT
350
410
490
mV
Measure VCP-A ↓ when FLTb↓, 4V ≤ VVDD < 18V
CP fault threshold
5
5.5
3.75
1.5
6
V
V
V
V
VCP_FLT
Measure VCP-A ↓ when FLTb↓, 2.5V < VVDD < 4V
3.3
4.2
4V ≤ VVDD < 18V
VCP, FLT, hyst
Hysteresis
2.5V < VVDD < 4V
1.1
HOT SWAP POWER GOOD OUTPUT (PGHS)
VPGHSth
VPGHShyst
VOL_PGHS
IPGHS
PGHS Threshold
Measure VSENM-OUTH ↓ when PGHS↑
VSENM-OUTH
170
–1
270
80
375
mV
mV
V
PGHS hysteresis
↑
PGHS Output low voltage
PHGS Input leakage current
Sinking 2mA
0.11
0
0.25
1
VPGHS=0V to 30V
µA
STATUS INDICATOR (STAT)
4V ≤ VVDD < 20V , Measure VBGATE – A ↑, when
STAT↑
5
3.6
4
6
4
7
4.4
6
V
V
V
V
VSTATon
Status ON threshold
2.5V < VVDD < 4V , Measure VBGATE – A ↑, when
STAT↑
4V < VVDD < 20V , Measure VBGATE – A ↓, when
STAT↓
5
VSTAToff
Status OFF threshold
2.5V <VVDD < 4V , Measure VBGATE – A ↑, when
STAT↑
2
2.7
3.4
VSTAT,LOWoff
ISTAT,LEAK
STAT Output low voltage
STAT Input leakage current
Sinking 2 mA
0.11
0
0.25
1
V
VSTAT = 0 V, 30 V
–1
µA
THERMAL SHUTDOWN (OTSD)
TOTSD
Thermal shutdown threshold
Hysteresis
Temperature rising
140
10
°C
°C
TOTSD,HYST
(3) The TPS2474x is set up to be powered from A, C, or VDD depending on the biasing condition. See Internal Power ORing of TPS24740
To obtain the total current draw from A, C, VDD, and OUTH refer to the spec for Input Supply (VDD)..
8
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
8.6 Timing Requirements
PARAMETER
TEST CONDITION
MIN
TYP
14
MAX UNIT
INPUT SUPPLY (VDD)
DEGLUVLO
HOT SWAP FET ENABLE (ENHS)
DEGLENHS Deglitch time
UVLO deglitch
Both rising and falling
µs
Both rising and falling
Both rising and falling
Both rising and falling
CP ↑ to IHGATE sourcing
2.2
1.7
2.2
3.8
3.5
3.9
1.9
5.5
5
µs
µs
µs
ms
BLOCKING (ORING) FET ENABLE (ENOR)
DEGLENOR Deglitch time
OVER VOLTAGE (OV)
DEGLOV
HOT SWAP GATE DRIVER (HGATE)
tHGATEdly Turn on delay
FAST TRIP (FSTP)
Deglitch time
5.7
V(FSTP – SENM) : –5mV to 5mV, CHGATE = 0 pF
V(FSTP – SENM) : -20mV to 20mV CHGATE = 0 pF
600
300
63
tFastOffDly
Fast turn-off delay
ns
µs
tFastOffDur
Strong pull down current duration
53
73
INRUSH TIMER (TINR)
NRETRY
Number of TINR cycles before retry
TPS24741 only
64
0.35%
0.7%
TINR not connected to TFLT
TINR connected to TFLT
RETRYDUTY Retry duty cycle
BLOCKING/ORING GATE DRIVER (BGATE)
tFastOffDur
tFastOnDur
Strong pull down current duration
Strong pull up current duration
10
10
15
20
20
30
µs
µs
POSITIVE INPUT OF REVERSE VOLTAGE COMPARATOR (RVSNP)
V(RVSNP –RVSNM) = –5mV → 5mV,
340
150
CBGATE = 0 pF
tFastOffDly
Turn-off delay
ns
V(RVSNP –RVSNM) = –20mV → +20mV,
CBGATE = 0 pF
FAULT INDICATOR (FLTb)
tFLT_degl
HS / OR Fault Deglitch
Both HS and ORing faults
2.2
3.9
32
5.3
ms
ms
tFLT_CP_degl CP fault deglitch
HOT SWAP POWER GOOD OUTPUT (PGHS)
26.5
37.2
Rising
Falling
0.7
7
1
8
1.3
9
tPGHSdegl
PGHS deglitch time
ms
ms
STATUS INDICATOR (STAT)
tSTATdegl
STAT Delay (deglitch) time
Rising or falling edge
0.4
0.95
1.5
Copyright © 2015, Texas Instruments Incorporated
9
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
8.7 Typical Characteristics
Unless otherwise noted these limits apply to the following: VVDD = VA = VC = VRVSNM = VOUTH = 12 V; VENHS = VENOR = 2 V, VOV
= 0 V; VBGATE, VHGATE, VPGHS, VSTAT, VFLTb, and VIMONBUF are floating; CCP = 100 nF, CINR = 1 nF, CFLT = 1 nF, RSET = 44.2 Ω,
RIMON = 2.98 kΩ, RFSTP = 200 Ω, RRV = 200 Ω, and RPLIM = 52 kΩ.
10
8
20
15
10
5
6
4
2
T=25°C
T=-40°C
T=125°C
T=125°C
T=-40°C
T=25°C
0
0
0
5
10
15
20
0
5
10
15
20
Input Voltage (V)
VDD (V)
C001
C002
Iq = IVDD + IA + IC + IOUTH
Figure 1.
Figure 2.
12
10
8
0.5
0.4
0.3
0.2
0.1
0.0
6
4
T=125°C
T=25°C
T=-40°C
2
Vstat
0
0
2
4
6
8
10
12
14
16
18
20
0
50
100
150
±50
VDD (V)
Temperature (C)
C003
C004
ISTAT = 2mA
Figure 3.
Figure 4.
0.50
0.40
0.30
0.20
0.10
0.00
1.40
1.38
1.36
1.34
1.32
1.30
1.28
1.26
1.24
1.22
1.20
Rising
Falling
Vpghs
0
50
100
150
0
50
100
150
±50
±50
Temperature (C)
Temperature (C)
C005
C006
IPGHS = 2mA
Figure 5.
Figure 6.
10
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
Typical Characteristics (continued)
Unless otherwise noted these limits apply to the following: VVDD = VA = VC = VRVSNM = VOUTH = 12 V; VENHS = VENOR = 2 V, VOV
= 0 V; VBGATE, VHGATE, VPGHS, VSTAT, VFLTb, and VIMONBUF are floating; CCP = 100 nF, CINR = 1 nF, CFLT = 1 nF, RSET = 44.2 Ω,
RIMON = 2.98 kΩ, RFSTP = 200 Ω, RRV = 200 Ω, and RPLIM = 52 kΩ.
1.40
1.38
1.36
1.34
1.32
1.30
1.28
1.26
1.24
1.22
1.20
1.40
1.38
1.36
1.34
1.32
1.30
1.28
1.26
1.24
1.22
1.20
Rising
Falling
Rising
Falling
0
50
100
150
0
50
100
150
±50
±50
Temperature (C)
Temperature (C)
C007
C008
Figure 7.
Figure 8.
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
2.0
0.5
RPLIM=51.1k
RPLIM=105k
RPLIM=261k
1.5
1.0
0.4
0.3
0.2
0.1
0
0.5
0.0
-0.5
-1.0
-1.5
T=25°C
T=-40°C
T=125°C
Vsns
-0.1
0
1
2
3
4
5
6
7
8
9
10 11 12
0
20
40
60
80
100
±20
VIN - VOUTH (V)
Time (µs)
C009
C010
VIMON during Power Limiting
VHGATE - VOUTH
=
10V
Figure 9.
Figure 10.
1.0
0.5
0.10
0.08
0.06
0.04
0.02
0.00
2.0
0.2
T=25°C
T=-40°C
T=125°C
Vsns
T=25°C
T=-40°C
T=125°C
Vrvsnp-rvsnm
0.18
0.16
0.14
0.12
0.1
1.5
1.0
0.5
0.0
0.0
0.08
0.06
0.04
0.02
0
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-0.02
100
-0.02
-50
0
50
-20
-10
0
10
20
30
40
50
Time (µs)
Time(µs)
C011
C012
VHGATE - VOUTH
=
VBGATE - VA = 10V
2V
Figure 11.
Figure 12.
Copyright © 2015, Texas Instruments Incorporated
11
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
Typical Characteristics (continued)
Unless otherwise noted these limits apply to the following: VVDD = VA = VC = VRVSNM = VOUTH = 12 V; VENHS = VENOR = 2 V, VOV
= 0 V; VBGATE, VHGATE, VPGHS, VSTAT, VFLTb, and VIMONBUF are floating; CCP = 100 nF, CINR = 1 nF, CFLT = 1 nF, RSET = 44.2 Ω,
RIMON = 2.98 kΩ, RFSTP = 200 Ω, RRV = 200 Ω, and RPLIM = 52 kΩ.
2.0
0.2
50
40
30
20
10
0
1.5
0.15
0.1
1.0
0.5
0.0
0.05
0
-0.5
-1.0
-1.5
-2.0
T=25°C
T=-40°C
T=125°C
Vrvsnp-rvsnm
T=25°C
T=-40°C
T=125°C
-0.05
-20
-10
0
10
20
30
40
50
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
Time (µs)
C013
VHGATE - VOUTH (V)
C014
VBGATE - VA = 4V
Figure 14.
Figure 13.
30
0.20
0.15
0.10
50
40
30
20
10
0
25
20
15
10
5
0.05
T=25°C
T=-40°C
T=125°C
Vsns
0.00
T=25°C
T=-40°C
T=125°C
0
-0.05
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
Time (µs)
C016
0
1
2
3
4
5
6
7
8
9
10 11 12
VBGATE - VA
C015
Figure 16.
Figure 15.
30
60
40
Ihgate
Itinr
0.04
0.02
0
25
20
15
10
5
20
0
-0.02
-0.04
±20
±40
±60
T=25°C
T=-40°C
T=125°C
Vrvsnp-rvsnm
0
-0.06
0.6
-0.6
-0.4 -0.2
0
0.2
0.4
0
50
100
150
200
250
300
Time (µs)
VIMON
C017
C018
Figure 17.
Figure 18.
12
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
9 Detailed Description
9.1 Overview
TPS2474x is a Hot Swap and ORing controller with many programmable settings. In addition the ORing and Hot
Swap blocks are set-up independently, which allows for the interchangeable order of Hot Swap and ORing. For
the ORing controller the RVSNM and RVSNP serve as a way to program the reverse voltage threshold and
sense the reverse voltage. The Hot Swap features a programmable current limit, power limit, and fast trip
threshold. It also has dual timers: one for inrush and one during over current faults. Finally it features an analog
current monitor that can be used to provide current information to a microcontroller.
9.2 Functional Block Diagram
HS FET
ORing FET
VOUT
+ VSNS
–
VIN
RSNS
CRV
CCP
RVSNM
VDD
CP
A
BGATE
RVSNP
C
SET
FSTP
SENM
HGATE
OUTH
15
16
17
18
19
24
14
1
23
22
21
20
Fast
+ Comp
99 μA
100 μA
HS
Charge
Pump
ORing
Charge
Pump
270 mV
55 μA
i_rev
+
ORing
Control
dis_HS
i_forw
10 mV
+
44 mA
ORing_ON
FET_ON
HS_ON
CP_up
410 mV
OR_OPEN
GAT_HI
+
PGHS
5
HS
Control
EN_AMP
AMP
+
ENHS
2
+
4 V / 6 V
Power
Limit
Engine
Main
Control
ENOR
OV
HS_SHORT
HS_ON
OUTH
+
3
9
101 mV
LMT/OC
Timer
2.32 V
1.35 V
3x
7
6
4
10
12
11
8
13
FLTB
PLIM
RPLIM
GND
IMON
RIMON
TFLT
STAT
TINR
IMONBUF
Copyright © 2015, Texas Instruments Incorporated
13
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
9.3 Feature Description
9.3.1 Internal Power ORing of TPS24740
The TPS2474x runs from an internal bus (VINT), which is derived from ORing A, C, and VDD. This ensures that
the TPS2474x can stays powered and functions properly, even if the input or output are shorted to GND. The
IC’s UVLO is derived based on the VINT rail. This does mean that the part can draw up to 3 mA from the A or C
pin. Hence it is recommended to keep those traces fairly short and to avoid adding resistors in the path.
Figure 19. Power ORing
9.3.2 Enable and Over-voltage Protection
Both the Hot Swap section and the ORing section can be independently enabled with the ENHS and ENOR pins
respectively. The part is enabled when the pin voltage exceeds 1.35V and is disabled when the pin voltage falls
under 1.3V providing 50mV of hysteresis. A resistor divider can be connected to these pins to turn on the
TSP2474x at a certain bus voltage. Both the ORing and the Hot Swap FETs will be turned off if the OV pin
exceeds 1.35V.
9.3.3 Current Limit and Power Limit During Start-up
The current limit and power limit of the TPS2474x are programmable to protect the load, power supply, and the
Hot Swap MOSFET. During start-up the active control loop will regulate the gate to ensure that the current
through the MOSFET and the power dissipation of the MOSFET is below their respective pre-programmed
thresholds. The maximum current allowed through the MOSFET (ILIM) is determined with Equation 1. ILIM,CL is the
programmed current limit, PLIM is the programmed power limit, and VDS is the drain to source voltage across the
Hot Swap MOSFET.
æ
LIM ö
P
ILIM = MIN I
ç LIM,CL
,
÷
VDS
è
ø
(1)
This results in an IV curve shown in Figure 20. ILIM,PL denotes the maximum allowed MOSFET current (IDS) when
the part is in power limit. As VDS increases, ILIM,PL decreases and ILIM,PL,MIN denotes the lowest ILIM,PL, which
occurs at the largest VDS (VDS,MAX). The TPS2474x enforce this by regulating the voltage across RSNS (VSNS).
VSNS,PL denotes VSNS when power limiting is active. Similarly to ILIM,PL, VSNS,PL decreases as VDS increases and
VSNS,PL,MIN corresponds to the lowest VSNS,PL, which occurs at VDS,MAX. VSNS,CL is a current limiting sense voltage,
which is programmable in the TPS2474x.
14
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
Feature Description (continued)
VSNS,CL
ILIM,CL
VSNS,PL
ILIM,CL
ILIM,PL,MIN
VSNS,PL,MIN
VDS
VDS,MAX
VDS
VDS,MAX
Figure 20. Current vs VDS and VSNS vs VDS Programmed by Power Limit Engine
The current and power limit can be programmed using the equations below.
0.675´RSET
=
VSNS,CL
RIMON
(2)
(3)
(4)
sp
sp
VSNS,CL
0.675´RSET
=
ILIM,CL
=
RSNS
RIMON ´RSNS
84375´RSET
PLIM ´RSNS ´RIMON
P
=
LIM
R
Note, that the error is largest at VSNS,PL,MIN due to offset of the internal amplifier. Also the operation at VDS,MAX is
most critical because it corresponds to the short circuit condition and has the biggest impact on start time. Thus it
is critical to consider VSNS,PL,MIN during design. Equation 5 shows the relationship of VSNS,PL,MIN as a function of
PLIM, ILIM,CL, VSNS,CL, and VDS,MAX. Note that ILIM,CL and VDS,MAX are usually determined by the system
requirements. The designer will have control over PLIM and VSNS,CL. In general, there will be a desire to reduce
the power limit to allow for smaller MOSFETs and to reduce the VSNS,CL to improve efficiency (lower RSNS).
However, this will also reduce VSNS,PL,MIN and the designer should ensure that it's above the miminum
recommended value of 1.5mV.
P
LIM ´ VSNS,CL
VSNS,PL,MIN
=
VDS,MAX ´ILIM,CL
(5)
9.3.4 Two Level Protection During Regular Operation
After the TPS2474x has gone through start-up it will no longer actively control HGATE. Instead it will run the
timer when the current is between the current limit and the fast trip threshold. Once the timer has expired the
gate will be pulled down. If the current ever exceeds the fast trip threshold, HGATE will be pulled down
immediately.
9.3.5 Dual Timer (TFLT and TINR)
TPS2474x has two timer pins to allow the user to customize the protection. The TINR pin sources 10.25 µA
when the device is in start-up mode and is actively regulating the gate to limit the MOSFET power or current. It
sinks 2 µA otherwise. The TFLT pin sources 10.25 µA when the device is in regular operation and the FET
current exceeds the current limit. It sinks 2 µA otherwise. If either of the timer pins exceeds 1.35, the TPS2474x
times out. The TPS24740 and TPS24742 latches off. The TPS24741 goes through 64 cycles of TINR and
attempts to start-up again.
Copyright © 2015, Texas Instruments Incorporated
15
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
Feature Description (continued)
Since the TINR usually runs when the MOSFET is being stressed, TINR should be sized to maintain the FET
within its SOA. In general TFLT runs when the load is drawing more current than expected, which can stress the
load and the power supply. Thus TFLT should be programmed to have the right protection settings for the power
supply and the load. In some systems the load is allowed to draw current above the current limit for a prolonged
time. In that case a large TFLT is required, but a short TINR may still be desired to minimize the worst case FET
stress. In other applications a long TINR may be required to due to large downstream capacitances, but drawing
excessive current from the power supply for more than 5ms is not desired. In that case a short TFLT and a long
TINR should be used. Finally, many applications can use the same TINR and TFLT setting, in which case the
pins can be tied together and a single capacitor can be used. The two different options are shown in Figure 21.
TINR
TFLT
TINR
TFLT
CFLT
CINR
CTMR
Figure 21. Timer Configurations
If two separate timer capacitors are used their values can be computed with Equation 6 and Equation 7:
CINR = 7.59 μF × TINR
(6)
(7)
sp
CFLT = 7.59 μF × TFLT
If a single capacitor is used CTMR can be computed with Equation 8.
sp
CTMR = 6.11 µF × TTMR
(8)
9.3.6 Using SoftStart – IHGATE and TINR Considerations
During start-up the TPS2474x regulates the HGATE to keep the FET power dissipation within PLIM. This is
accomplished by an amplifier that monitors the IMON voltage and an internal reference voltage. The TPS24740
will source current into HGATE if VIMON is lower than the reference voltage and will sink current into HGATE if
VIMON is above the reference voltage. In steady state, the VIMON will be regulated to the VIMON,PL point, where
IHGATE equals zero. Note that VIMON,PL is determined by RPLIM and the VSENM – VOUTH
.
The same amplifier feeds into the inrush timer circuitry to run the timer when the part is in power limit. The VIMON
threshold at which the timer starts to source current is denoted as VIMON, TINR. Note that VIMON,TINR is lower than
VIMON,PL to account for tolerances and ensure that the timer is always active when the device is in power limit.
The difference between the two thresholds is defined as ΔVIMON, TINR. A typical curve of the IHGATE and ITINR is
available in the typical characteristics section.
Figure 22. IHGATE Current and TINR Relationship
16
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
Feature Description (continued)
It is critical to consider ΔVIMON,
and Figure 22 if a soft start circuit is used. Typically, the soft start is
TINR
implemented by limiting the gate dv/dt with a capacitor, which in turn limits the inrush current to the output
capacitor. Often times, the inrush current is kept below ILIM,PL to keep the timer from running. Note that the ILIM,PL
is based on the VIMON,PL threshold and thus TINR can be activated even if the inrush current is below ILIM,PL. To
prevent the timer from running unintentionally, it's important that the minimum power limit (typical PLIM
-
tolerance) is above PLIM,MIN,SS, which can be computed as shown in Equation 9 below. As an example, consider
the usage case where the maximum inrush current (IINR,MAX) is 2A, the maximum input voltage (VIN,MAX) is 13V
and RSET, RIMON, and RSNS are 100Ω, 2.7kΩ, and 1mΩ respectively. For that case the power limit should be set
to at least 58.3 W + PLIM tolerance to ensure that the inrush timer does not run.
RSET
P
= (I
+ DV
×
) × V
IN,MAX
LIM,MIN, SS
INR,MAX
IMON,TINR,MAX
RIMON × RSNS
100W
æ
ö
=
2A + 67mV ×
× 13V = 58.3W
ç
÷
2.7kW × 1mW
è
ø
(9)
9.3.7 Three Options for Response to a Fast Trip
The TPS24740, TPS24741, and TPS24742 have difference responses to a fast trip event to accommodate
different design requirements. When the current exceeds the fast trip threshold, the gate is quickly pulled down to
minimize damage that can be caused due to a short circuit. Figure 23 shows the response of the variate devices
options to a Hotshort on the output. The TPS24740 (latch) attempts to re-start once after the hot-short is
observed and then stay off. The TPS24741 continuously retries with a duty cycle of ~0.5% (0.7% if TFLT and
TINR are connected, 0.35% if TFLT and TINR are not connected); and, the TPS24742 shuts off and never retries
again. In general the TPS24742 (Fast/immediate Latch Off) places the least amount of stress on the MOSFET,
but is the least likely to recover from a nuisance trip.
Hotshort Occurs
HGATE
TPS24740 - Latch
Retry Once
VIN
HGATE
VIN
TPS24741 - Retry
Retries Continuously.
~ 0.5% Duty Cycle
HGATE
VIN
Shuts Off and No
Retry
TPS24742 -
Immediate Latch Off
Figure 23. TPS24740/1/2 Response to a Short Circuit
Copyright © 2015, Texas Instruments Incorporated
17
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
Feature Description (continued)
9.3.8 Programmable Reverse Voltage Threshold
The TPS2474x has a programmable reverse voltage threshold. An internal comparator detects a reverse current
condition when RVSNP is above RVSNM. This is signal is used to shut off the ORing MOSFET. RRV along with a
99µA current source pre-bias RVSNP to below the real source voltage of the MOSFET and effectively set the
reverse voltage threshold. CRV along with RRV filters transients across the drain to source of the ORing FET.
ORing FET
VIN
CRV
BGATE
RVSNM
RVSNP
A
24
23
22
21
99 μA
i_rev
TPS2474x
+
Figure 24. Programming and Sensing Reverse Voltage
Note that the RVSNM and RVSNP can be connected at various places. One option is to connect it across the
drain to source of the ORing FET (Figure 24), which would result in a reverse current threshold of VRV/RDSON
.
Another option is to connect across the RSNS as shown in Figure 25. This could be useful if a precise threshold is
desired and RSNS is larger than the RDSON of the ORing FET.
HS FET
BS FET
VOUT
VIN
RSNS
CP
COUT
C1
CFST
CRV
RBG
RHG
470 μF
0.1 μF
VDD SET FSTP SENM RVSNM RVSNP HGATE OUTH CP
A
BGATE
C
PGHS
FLTb
ENHS
TPS2474x
IMON
ENOR
OV
IMONBUF
STAT
PLIM
GND
TINR
TFLT
CINR
CFLT
Figure 25. Sensing Reverse Voltage Across Hot Swap Sense Resistor
18
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
Feature Description (continued)
9.3.9 Analog Current Monitor
The TPS2474x also features two analog current monitoring outputs: IMON and IMONBUF. Each has their own
advantages and disadvantages. The IMON is more accurate, because it doesn’t have the error added from the
second stage. However it is a high impedance output and leakage current on that node would result in
monitoring error. In addition it can only support 30pF of capacitance and its full scale range is 675mV (this is
where current limit kicks in). The IMONBUF takes the IMON signal and buffers it 3x. This introduces more error,
but the output is low impedance, has a larger full scale range, and can drive up to 100pF of capacitance.
HS FET
+ VSNS
RSNS
–
VIN
SET
SENM
HGATE
OUTH
15
17
18
19
x
3x
TPS2474x
12
13
IMON
RIMON
IMONBUF
Figure 26. Current Monitoring Circuitry
9.3.10 Power Good Flag
The TPS2474x has a power good flag, which should be used to turn on downstream DC/DC converters. This
reduces the stress on the Hot Swap MOSFET during start-up. The PGHS pin of the TPS2474x is asserted (with
1 ms deglitch) when both:
•
•
Hot Swap is enabled and
VDS of Hot Swap MOSFET is below 240 mV.
PGHS is de-asserted (with 8 ms deglitch) when either:
•
•
•
Hot Swap is disabled.
VDS of Hot Swap MOSFET is above 310 mV
In an overcurrent condition that causes the timer to time out and latch off.
9.3.11 ORing MOSFET Status Indicator
The TPS2474x, features a STAT flag that indicates whether the BGATE (ORing FET driver) is ON or OFF. In
general it is good practice to have the ORing FETs ON before drawing any significant load to prevent the ORing
FET from overheating.
Copyright © 2015, Texas Instruments Incorporated
19
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
Feature Description (continued)
9.3.12 Fault Reporting
TPS 2474x will assert a fault by pulling down on the FLTb pin if any of the following occur:
•
•
•
•
•
Hot Swap MOSFET Shorted Fault ( ENHS = LO, but VIMON > 101 mV)
Hot Swap timer times out.
ORing MOSFET Open Fault (ENOR = HI, CP up, but VAC > 410 mV)
CP is down for more than 32 ms
Over Temperature Shut Down (OTSD)
Figure 27 shows the logic for the fault conditions.
Timer Timed Out (TO)
OTSD
VIMON > 100 mV
FLTb
Deglitch
3.9 ms Rising
and Falling
FET
Shorted
Hotswap_Disabled
FLT
OR_enabled
CP_up
Deglitch
3.9 ms Rising
and Falling
FET
Open
VAC > 410 mV
Deglitch
32 ms when rising
Starts as No Fault
CP_up
Figure 27. Logic for Fault Reporting
9.4 Device Functional Modes
The Hot Swap and ORing section of the TPS2474x are for the most part independent. The only exception is that
the Hot Swap is gated by the charge pump being up. This ensures that the ORing FET is ON before the Hot
Swap turns on to avoid a possible glitch from a fast ORing turn on.
9.4.1 ORing Functional Modes
Figure 28 shows the state machine for the ORing portion of the controller. It has three modes listed below:
•
•
•
Precharge CP: Here the TPS2474x charges the CP node before beginning regular operation. This state is
entered after POR/UVLO or if the CP voltage falls below 3.7V. Whenever the CP voltage is above 5.5V the
FET OFF state is entered
FET OFF: In this state the ORing FET is OFF and is pulled down to A with a 35mA current source. If a
forward voltage drop is detected across the FET (VAC > 10mV) the TPS2474x enters the FET ON state.
There is a 30mA fast pull up that lasts 20µs, followed by a sustained 0.3 mA pull up.
FET ON: In this state the ORing FET is pulled up to the CP voltage. If reverse current is detected (RVSNP >
RVSNM) the TPS2474x will enter the OFF state. There is a 0.9A pull down current that lasts 15 µs, followed
by a sustained 35mA pull down.
20
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
Device Functional Modes (continued)
A
+
CP_UP = 1
I_forw
C+10 mV
Precharge
CP
FET OFF:
POR
CP_UP = 0
RVSNP
RVSNM
+
+
I_rev
I_rev = 1
I_forw = 1
CP
CP_UP
FET ON:
5.5V / 3.7V + A
CP_UP = 0
Figure 28. ORing State Machine
9.4.2 Hot Swap Functional Modes
The state machine for the Hot Swap section is shown in Figure 29. After a POR / UVLO event the Hot Swap
waits 1.9ms after the charge pump is up before starting up. Once operational the Hot Swap has the following
functional modes:
•
Inrush Mode (INR): In this state the Hot Swap controller is actively regulating the HGATE to meet the current
limit and power limit settings. The inrush timer is running if the controller is in power or current limiting. If the
inrush timer times out the gate will be pulled down. The TPS24740 and TPS24742 will go to latched mode
and TPS24741 will go into retry mode.
•
Regular Operation Mode (REG): In this mode everything is operating properly so both the timers are
discharged and the HGATE is high. If there is an overcurrent condition (VSNS > VSNS,CL), the device will go
into fault mode. If there is a fast trip condition (VSNS > VFSTP), the gate will be pulled down with a 1A / 63 µs
pulse. The TPS24742 will go to the latched state and the TPS24740 and TPS24741 will go back to inrush for
a retry.
•
•
•
Fault Mode (FLT): In this mode the TPS2474x runs the fault timer. Once the timer expires the TPS24740
and TPS24742 will go to latch mode while TPS24741 will go to retry mode. If the overcurrent condition is
removed the controller will go back to the regular operation mode.
Latched Mode (Latched): In the latched mode the HGATE is low, the timer is being discharged, and the
FLTb is asserted. If there is a rising edge on ENHS the part will discharge the timers and go to the inrush
mode.
Retry Mode (Retry): Here the part charges and discharges the inrush timer 64 times before attempting
another retry.
Copyright © 2015, Texas Instruments Incorporated
21
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
Device Functional Modes (continued)
TPS24740/1
FSTRP = 1
REG:
TPS24742
Latched
RST
Discharge
Timers
EN_RE
ITINR = –2 µA
ITFLT = –2 µA
HGATE: Low
TPS24740/2
INR:
EN_RE
ITFLT = –2 µA
ITINR = –2 µA
EN_AMP = 0
HGATE: High
LMT =1: ITINR = 10 µA
LMT=0: ITINR = 0
ITFLT = –2 µA
CP_up
PGHS = 1
1.9 ms
Deglitch
UVLO
EN_AMP = 1
HGATE: regulating
Count = 63
Count < 63
Retry Mode
Auto_Chg
ITINR = 10 µA
ITFLT = –2 µA
HGATE: Low
OC = 1
OC = 0
VTINR > 1.35
Legend:
LMT: In power or current limit
FLT:
OC: Over Current (VIMON > 675 mV)
EN_RE: Rising edge on ENHS
TO: Timer Timed Out
VTINR >1.35
ITFLT = +10 µA
ITINR = –2 µA
EN_AMP = 0
HGATE: High
VTFLT>1.35
Auto_Disch
VTINR<0.35
Count +1
HGATE: Low
EN_AMP: Enable current limit and
power limit amplifier, which actively
regulates the sense voltage.
ITINR = –2 µA
ITFLT = –2 µA
HGATE: Low
TPS24741
FSTRP: Fast trip comparator is tripped
ILO: Immediate Latch Off. OTP setting
for no re-start after Fast Trip
Figure 29. Hot Swap State Machine
22
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPS2474x controls an ORing MOSFET and a Hot Swap MOSFET to provide complete protection in
redundant systems. The two sections are mostly independent and the Hot Swap and ORing settings can be
chosen independently. In addition the TPS2474x supports various system level configurations shown in System
Examples. Since the ORing and Hot Swap control are independent the design procedure shown in the Typical
Application section can be used for these different configurations as well. Note that the component selection can
often be iterative; and, it is recommended to use the publically available excel calculators to crunch the numbers.
See Tools & Software link on the Product folder.
10.2 Typical Application
Two application examples are provided. The first one is an OR then Hot Swap 30A design with a current
monitoring requirement, which uses the TPS24740. The second design is a Hot Swap then ORing 40A design
with a transient load requirement and a large output capacitor that uses the TPS24742. Note that there are a lot
of calculations necessary for these designs and it is easy to make mistakes. For this reason it is recommended
to use TI design calculators, which follow a very similar procedure. See Tools & Software link on the Product
folder. These written examples should be used as reference to better understand the calculations implemented in
the design calculators.
10.2.1 30A Single channel OR then Hot Swap With Current Monitoring
Figure 30 shows the application schematic for a single channel OR then Hot Swap configuration.
HS FET
BS FET
CSD16415
RSNS
CSD16415
VIN
VOUT
0.5 mΩ
COUT
1 µF
CP
D1
D2
MBRS330T3G
CRV
33 nF
CIN
CFST
RHG
0.1 µF
2 nF
SMDJ14
RBG
10 Ω
0.1 µF
10 Ω
10 Ω
CP
A
BGATE
C
RVSNM RVSNP VDD SET FSTP
SENM
HGATE OUTH
PGHS
ENOR
ENHS
OV
49.9 kΩ
2.21 kΩ
5.62 kΩ
FLTb
IMONBUF
STAT
TPS24740
CMID
0.1 µF
TINR
TFLT
PLIM
GND
IMON
CTMR
33 nF
2670 Ω
113 kΩ
Figure 30. Application Schematic for ORing then Hot Swap
Copyright © 2015, Texas Instruments Incorporated
23
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
Typical Application (continued)
10.2.2 Design Requirements
Table 2 summarizes the design parameters that must be known before designing a Hot Swap circuit. When
charging the output capacitor through the Hot Swap MOSFET, the FET’s total energy dissipation equals the total
energy stored in the output capacitor (1/2CV2). Thus both the input voltage and output capacitance determines
the stress experienced by the MOSFET. The maximum load current drives the current limit and sense resistor
selection. In addition, the maximum load current, maximum ambient temperature, and the thermal properties of
the PCB (RθCA) drives the selection of the MOSFET RDSON and the number of MOSFETs used. RθCA is a strong
function of the layout and the amount of copper that is connected to the drain of the MOSFET. Air cooling also
reduces RθCA. It is also important to know if there are any transient load requirements. Finally, whether current
monitoring is needed and its accuracy requirement drives the selection of RSNS, RIMON, and RSET
.
Table 2. Design Requirements for 30A ORing then Hot Swap
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
11 V – 13 V
Maximum DC load current
30A
Maximum Output Capacitance of the Hot Swap
Maximum Ambient Temperature
Minimum Ambient Temperature
MOSFET RθCA (function of layout)
Transient load requirement
1500 µF
55°C
0°C
30°C/W
No
Pass “Hot-Short” on Output?
Pass a “Start into short”?
Yes
Yes
Is the load off until PG asserted?
Current Monitoring Required (accuracy?)
IC used
Yes
Yes (<2.5% full scale)
TPS24740
10.2.3 Detailed Design Procedure
10.2.3.1 Select RSNS and VSNS,CL Setting
TPS2474x has a programmable VSNS,CL with a recommended range of 10 mV to 67.5 mV. It can be used with a
VSNS,CL up to 200 mV, but that requires a resistor (RSTBL) between SET and SENM to ensure stability of an
internal loop. RSTBL should be set larger than RIMON x RSET / (10xRSET- RIMON). This is shown in Figure 31.
For the majority of applications 25mV (RSTBL is not needed) is a good starting target for VSNS,CL. Targeting a
current limit of 35A to allow margin for the load, the sense resistor can be calculated as follows
VSNS,TGT
25 mV
35 A
RSNS,CLC
=
=
= 0.71 mW
ILIM
(10)
Since 0.71 mΩ resistors aren’t available, the closest standard resistor should be chosen. To have better
efficiency, a 0.5 mΩ resistor is chosen. Next the VSNS,CL should be computed based on the actual RSNS and then
used to compute RSET and RIMON. RSET is chosen to target 250 µA of current through SET and IMON pins during
current limit.
VSNS,CL = ILIM ´ VSNS,CL = 35 A ´0.5 mW = 17.5 mV
(11)
VSNS,CL
RSET,CLC
=
= 70 W
250 mA
(12)
Choose RSET to equal 69.8Ω, which is the closest available standard resistor. Next obtain the calculated RIMON
(RIMON,CLC) as follows:
sp
R
SET ´675 mV
69.8 W ´675 mV
RIMON,CLC
=
=
= 2.692 kW
VSNS,CL
17.5 mV
(13)
24
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
Choose 2.67kΩ resistor for RIMON, which is the closest available standard resistor. Since precision current
monitoring is desired, 0.1% resistors were used for RIMON and for RSET and a 4 terminal sense resistor
(WSL4026L5000) was used for RSNS
.
0.675 V ´RSET
0.675 V ´ 69.8 W
ILIM,CL
=
=
= 35.3 A
RIMON ´RSNS
2.67 kW ´0.5 mW
(14)
(15)
sp
R
IMON ´RSNS
0.5 mW ´ 2.67 kW
V
=
=
= 19.13 mV / A
IMON,GAIN
RSET
69.8
HS FET
VIN
RSNS
C1
0.1 μF
CFST
RHG
RSTBL
VDD SET FSTP
SENM
HGATE
ENHS
ENOR
OV
TPS2474x
PLIM
IMON
GND
Figure 31. Adding RSTBL for VSNS,CL > 67.5mV
10.2.3.2 Selecting the Fast Trip Threshold and Filtering
The TPS2474x allows the user to program the fast trip threshold. When this threshold is exceeded the gate is
quickly pulled down. CFSTP can be added to include some filtering into the comparator. The selection of the fast
trip threshold and filtering is influenced by the systems environment and requirements. In general picking a larger
threshold and larger filtering time will result in more immunity to nuisance trips, but also a slower response
(possibly inadequate) to real fault conditions. It’s best to fine tune these threshold after testing the real system.
As a starting point it is recommended to set the fast trip threshold at least 1.25x larger than then current limit. For
this design example a 50A fast trip threshold along with a 500ns filtering time constant were targeted. The value
for RFSTP and CFSTP can be computed as shown below:
I
FSTP ´RSNS
50 A ´ 0.5 mW
RFSTP
=
=
= 250 W
100 µA
100 µA
(16)
sp
tFSTP
500 ns
CFSTP
=
=
= 2 nF
RFSTP
250 W
(17)
The next closest standard resistor and capacitor values should be chosen. In this case RFSTP = 249Ω and
CFSTP=2nF.
10.2.3.3 Selecting the Hot Swap FET(s)
It is critical to select the correct MOSFET for a Hot Swap design. The device must meet the following
requirements:
Copyright © 2015, Texas Instruments Incorporated
25
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
•
The VDS rating should be sufficient to handle the maximum system voltage along with any ringing caused by
transients. For most 12V systems a 25 V or 30V FET is a good choice.
•
•
The SOA of the FET should be sufficient to handle all usage cases: start-up, hot-short, start into short.
RDSON should be sufficiently low to maintain the junction and case temperature below the maximum rating of
the FET. In fact, it is recommended to keep the steady state FET temperature below 125°C to allow margin to
handle transients.
•
•
Maximum continuous current rating should be above the maximum load current and the pulsed drain current
must be greater than the current threshold of the circuit breaker. Most MOSFETs that pass the first three
requirements will also pass these two.
A VGS rating of +16 V is required, because the TPS2474x can pull up the gate as high as 15.5 V above
source.
For this design the CSD16415Q was selected for its low RDSON and superior SOA. After selecting the MOSFET,
the maximum steady state case temperature can be computed as follows:
TC,MAX = TA,MAX + RqCA ´IL2OAD,MAX ´RDSON
T
( )
J
(18)
Note that the RDSON is a strong function of junction temperature, which for most MOSFETS will be very close to
the case temperature. A few iterations of the above equations may be necessary to converge on the final RDSON
and TC,MAX value. According to the CSD16415Q datasheet, its RDSON is about 1.3x greater at 100°C compared to
room temperature. The equation below uses this RDSON value to compute the TC,MAX. Note that the computed
TC,MAX is close to the junction temperature assumed for RDSON. Thus no further iterations are necessary.
C
TC,MAX = 55°C + 30° ´ 30A 2 ´ 1.3´1 mW = 90.1°C
W
(
) (
)
(19)
10.2.3.4 Select Power Limit
In general, a lower power limit setting is preferred to reduce the stress on the MOSFET. However, at low power
limit levels both the VSNS and VIMON become very low, which results in more error caused by offsets. It is
recommended to keep VSNS above 1.5mV and VIMON above 27mV to ensure reasonable accuracy of the power
limit engine. Based on these requirements the minimum power limit can be computed as seen in Equation 20.
V
VIMON,MIN ´RSET
æ
ö
÷
ø
IN,MAX
P
=
´MIN V
,
ç
LIM,MIN
SNS,MIN
RSNS
RIMON
è
13 V
27 mV ´ 69.8 W
2.67 kW
æ
ö
=
´MIN 1.5 mV,
= 39 W
ç
÷
0.5 mW
è
ø
(20)
In most applications the power limit can be set to PLIM,MIN using Equation 21. Here RSNS and RPWR are in Ωs and
PLIM is in Watts.
84375´RSET
84375´ 69.8 W
RPLIM
=
=
= 113.1 kW
R
SNS ´RIMON ´P
0.5 mW ´ 2.67 kW ´39
LIM
(21)
The closest available resistor should be selected. In this case it is a 113 kΩ.
10.2.3.5 Set Fault Timer
The inrush timer runs when the Hot Swap is in power limit or current limit, which is the case during start-up. Thus
the timer has to be sized large enough to prevent a time-out during start-up. If the part starts directly into current
limit (ILIM × VIN < PLIM) the maximum start time can be computed with Equation 22:
C
OUT ´ V
IN,MAX
tstart,max
=
ILIM
(22)
For most designs (including this example) ILIM × VIN > PLIM so the Hot Swap will start in power limit and transition
into current limit. In that case the maximum start time can be computed as seen in Equation 23:
2
IN,MAX
2
é
ê
ë
ù
é
ù
ú
V
COUT
2
P
2
ILIM
1500 mF (13 V)
39 W
LIM ú
tstart,max
=
´
+
=
´
+
= 3.27ms
ê
ê
ë
2 ú
û
P
2
39 W
ê
ú
(35 A)
LIM
û
(23)
26
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
Note that the above start-time is based on typical current limit and power limit values. To ensure that the timer
never times out during start-up it is recommended to set the fault time (TINR) to be 1.5x tstart,max or 4.9 ms. This
will account for the variation in power limit, timer current, and timer capacitance.
Next the design should decide if having equal TINR and TFLT is acceptable. If there is no transient load
requirement this is usually fine. For this example the same capacitor is connected to both TINR and TFLT to
save on BOM cost. In this case the time out (TTMR) should be set based on the TINR requirements. When these
pins are connected the CTMR can be computed as follows:
CTMR = 6.11 µF × TTMR = 6.11 µF × 4.9 ms = 29.9 nF
(24)
The next largest available CTMR is chosen as 33nF. Once the CTMR is chosen the actual programmed time out
can be computed as seen in Equation 25.
sp
CTMR
33 nF
TTMR
=
=
6.11 mF 6.11 mF
= 5.4 ms
(25)
10.2.3.6 Check MOSFET SOA
Once the power limit and fault timer are chosen, it is critical to check that the FET remains within its SOA during
all test conditions. For this design example the TPS24740 is used, which retries once during a hot-short.
During a “Hot-Short” the circuit breaker trips and the TPS24740 re-starts into power limit until the timer runs out.
In the worst case the MOSFET’s VDS will equal VIN,MAX, IDS will equal PLIM / VIN,MAX and the stress event will last
for TTMR. For this design example the MOSFET will have 13 V, 3 A across it for 5.6 ms.
Based on the SOA of the CSD16415Q, it can handle 13 V, 100 A for 1 ms and it can handle 13 V, 15 A for 10
ms. The SOA for 5.6 ms can be extrapolated by approximating SOA vs time as a power function as shown in
Equation 26:
ISOA t = a´ tm
( )
100 A
15 A
æ
ö
ln
ln
ç
÷
ln I
(
t
/ I
t
SOA ( 1)
( )
)
SOA 2
è
ø
m =
=
= -0.82
ln t / t
(
1 ms
æ
ö
)
1
2
ç
è
÷
ø
10 ms
ISOA
t
( 1) =
100 A
0.82
( )
a =
= 100 A ´ ms
-0.82
t1m
1 ms
(
)
ISOA 5.4 ms = 100 A ´(ms)0.82 ´(5.4 ms)-0.82 = 25.1 A
(
)
(26)
Note that the SOA of a MOSFET is specified at a case temperature of 25°C, while the case temperature can be
much hotter during a hot-short. The SOA should be de-rated based on TC,MAX using Equation 27:
TJ,ABSMAX - TC,MAX
150°C - 90.1°C
150°C - 25°C
ISOA 5.4 ms,T
= I
5.4 ms,25°C ´
= 25.1 A ´
= 12 A
(
)
(
)
C,MAX
SOA
TJ,ABSMAX - 25°C
(27)
Based on this calculation the MOSFET can handle 11.67 A, 13 V for 5.6 ms at elevated case temperature, but is
only required to handle 3A (39 W / 13 V) during a hot-short. Thus there is good margin and this will be a robust
design. In general, it is recommended that the MOSFET can handle 1.3x more than what is required during a
hot-short. This provides margin to cover the variance of the power limit and fault time.
10.2.3.7 Choose ORing MOSFET
When selecting the ORing MOSFET the considerations are similar to the Hot Swap MOSFET, but the SOA is no
longer critical. In addition the lower RDSON is not always ideal, because that would result in a larger reverse
current for the same reverse voltage threshold. Of course a lower RDSON would provide better efficiency. For
consistency sake a single CSD16415Q FET was used for the ORing section as well. It is important to check its
steady state temperature at max load using the same equation that was used for the Hot Swap.
C
TC,MAX = 55°C + 30° ´ 30A 2 ´ 1.3´1 mW = 90.1°C
W
(
) (
)
(28)
27
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
10.2.3.8 Choose Reverse Current Threshold and Filtering
When setting the reverse current threshold, it is often desired to set a very low value to minimize the maximum
DC reverse current. However, the accuracy of the reverse voltage threshold should be considered. The
TPS2474x has a 1mV offset on the reverse voltage comparator. Thus setting a very low reverse voltage setting
can result in some boards to trip at positive current. This would lead to oscillations at zero load condition as the
ORing gate turns ON and OFF, which is typically not desired. Note that applications that always have a
significant forward current will not experience this problem.
For this design example a reverse voltage of 1.5mV was targeted to keep the threshold low, but to also ensure
that the device never trips at positive current. Just like the filtering on the fast trip threshold for the Hot Swap, the
optimum time constant for filtering the reverse voltage threshold will depend on the system environment and
requirements. Again, this is a trade-off between avoiding nuisance trips and a fast response to actual faults. In
general a 500ns time constant is a good starting point. Based on these target thresholds, RRV and CRV can be
computed using Equation 29 and Equation 30.
VRV
1.5 mV
RRV
=
=
= 15.2 W
99 µA
99 µA
(29)
sp
tRV
500 ns
CRV
=
=
RRV 15.2 W
= 32.9 nF
(30)
Choose closest available standards values: RRV = 15Ω and CRV = 33nF.
10.2.3.9 Choose Under Voltage and Over Voltage Settings
The TPS2474x has comparators with 1.35V threshold on the ENHS, ENOR, and OV pins. A resistor divider can
be used to set Undervoltage and Overvoltage thresholds for the bus. For this design example 10V and 14V were
chosen as the limits to allow some margin for the 11V to 13V input bus. Once these limits are known, RDIV2 and
RDIV3 can be computed using Equation 31, Equation 32, and Equation 33. RDIV1 was set to 49.9 kΩ, which keeps
the power consumption reasonably low without being too susceptible to leakage currents.
R
DIV1 ´1.35 V
49.9 kW ´1.35 V
RDIV2,3 = RDIV2 + RDIV3
=
=
= 7.79 kW
VUV -1.35 V
10 V -1.35 V
(31)
sp
sp
R
DIV1 + RDIV2,3 ´1.35 V
)
49.9 kW + 7.79 kW ´1.35 V
)
(
(
RDIV3
=
=
= 5.56 kW
VOV
14 V
(32)
(33)
RDIV2 = RDIV2,3 - RDIV1 = 7.79 kW - 5.56 kW = 2.23 kW
Choose closest available standard 1% resistors: RDIV2 = 2.21 kΩ and RDIV3 = 5.62 kΩ. The actual Under Voltage
and Over Voltage settings can be computed for the chosen resistors as shown in Equation 34 and Equation 35:
R
DIV1 + RDIV2 + RDIV3
2.21 kW + 5.62 kW + 49.9 kW
2.21 kW + 5.62 kW
VUV _ act = 1.35V ´
= 1.35 V ´
= 9.95 V
RDIV2 + RDIV3
(34)
(35)
sp
R
DIV1 + RDIV2 + RDIV3
2.21 kW + 5.62 kW + 49.9 kW
5.62 kW
VOV _ act = 1.35 V ´
= 1.35 V ´
= 13.87 V
RDIV3
10.2.3.10 Selecting CIN, COUT, and CMIDDLE
It is recommended to add ceramic bypass capacitors to help stabilize the voltages on the input, output, and the
intermediate node. Since CIN and CMIDDLE will be charged directly on hot-plug, their value should be kept small.
0.1µF is a good target. Since COUT doesn’t get charged during hot-plug, a larger value such as 1 µF could be
used.
28
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
10.2.3.11 Selecting D1 and D2
During hot plug and hot short events there could be significant transients on the input and output of the hotswap
that could cause operation outside of the IC specifications. To ensure reliable operation a TVS on the input and a
Schottky diode on the output are recommended. In this example a SMDJ14A and MBRS330T3G are used.
10.2.3.12 Ensuring Stability
For most applications, the TPS2474x is stable whithout any additional components. However in some cases
additional CGS,EXT is required as shown in Figure 32 to help stabilize the current and power limit loop. Typically
this is for low current limits and low sense voltages. It is easy to check whether these extra components are
needed using the equations below. Note that the transconductance ( also referred to as gm and gfs) of the FET
will vary based on the current and thus gm' is used in the equations as a normalizing parameter. The CSD16415
has a gm of 168 siemens at 40A of IDS, resulting in gm' of 26.56. For this example, CGS,MIN was computed to be
0.9nF, while the CISS of the CSD16415 is 3.15nF providing plenty of margin for the design. In general it is
recommended to have a 2x margin from the typical CISS and CGS,MIN to account for any variation that the FET
would have. If the CISS of the MOSFET isn't large enough an external RC should be added as shown in the
figure below. Note that if parallel FETs are used CGS,MIN (per FET) is reduced by square root of two or by 1.41.
æ
ç
è
ö1.5
÷
ø
RIMON
RSET
CGS,MIN = 6.54´10-12 ´ gm'´
´ RSNS
(36)
gm
I
(DS )
168
40
gm'
=
=
= 26.56
IDS
(37)
(38)
1.5
2.67k
æ
ö
CGS,MIN = 6.54´10-12 ´ 26.56´
´ 0.5m = 0.9nF
ç
÷
69.8
è
ø
CGS,EXT
RHG
1 kꢀ
Figure 32. Ensuring Stability
10.2.3.13 Compute Tolerances
After finishing a design it is often desired to know the variations of each setting. Often times there are multiple
error sources and there are two common ways to analyze the circuit. One is worst case, which adds all of the
error sources. The other one is root mean square (RMS), which is less conservative. When error sources are
independent using the RMS method provides a more statistically accurate view of the tolerances. This method is
used in this section. Note that the error calculations are quite long and tedious and it is recommended to use TI’s
excel tools, which support both worst case and RMS analysis. For this example the tolerances in Table 3 are
assumed. See Tools & Software link on the Product folder.
Table 3. Component Tolerances
COMPONENTS
RIMON and RSET
RSNS
TOLERANCE
0.1%
1%
RDIV1, RDIV2, RDIV3, RPLIM, RFST
,
1%
CTMR
10%
Copyright © 2015, Texas Instruments Incorporated
29
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
First, the tolerance of the current monitoring and current limit is computed.
There are 5 error sourcing contributing to the current monitoring accuracy on the IMON pin: tolerance of RSET
(ERSET), tolerance of RIMON (ERIMON), tolerance of RSNS (ERSNS), the IC gain error (ERGAIN), and the IC offset
error (EROS). All of these errors are in % with the exception of the offset error. To get a percent error due to the
offset error (EROS%) simply divide the offset by the sense voltage. For the TPS2474x, ERGAIN is 0.4%, and EROS
is 150 µV.
Based on these values the full scale (IFS,ERR,IMON) and 20% of full scale (I20FS,ERR,IMON) current monitoring
accuracy at the Imon pin can be computed with Equation 39 and Equation 40.
æ
ç
è
ö2
÷
ø
EROS
2
2
2
2
)
IFS,ERR,IMON
=
ER
(
+ ER
+ ER
+ ER
+
SET ) ( SNS ) ( IMON ) (
GAIN
RSNS ´ILIM
2
)
=
0.1%2 +1%2 + 0.1%2 + 0.4%2 + 150 µV / 17.7 mV = 1.4%
(
(39)
(40)
sp
æ
ç
è
ö2
÷
ø
EROS
RSNS ´ 0.2´ILIM
2
2
2
2
)
I20FS,ERR,IMON
=
ER
(
+ ER
+ ER
+ ER
+
= 4.4%
SET ) ( SNS ) ( IMON ) (
GAIN
Note that the TPS24740 detects the current limit when the IMON pin exceeds 675 mV. Thus the current limit
error ILIM,ER is a combination of the IFS,ERR,IMON and the current limit error at the IMON pin (ILIM,ERR,IMON). The 675
mV threshold varies up to 15 mV so ILIM,ERR,IMON is 2.3% and the current limit error can be computed as seen in
Equation 41:
2
FS,ERR,IMON ) (LIM,ERR,IMON )
2
ILIM,ERR
=
I
(
+ I
= 1.4%2 + 2.3%2 = 2.7%
(41)
If the current is monitored at the IMONBUF pin, there is additional error introduced due to the internal buffer,
which has a gain error of 0.66% (EROS,BUF) and an offset error of 3mV (EROS,BUF) referred to the IMON pin. Note
that VIMON equals 675 mV at full scale and 135 mV at 20% of full scale. Thus the total current monitoring error at
the IMONBUF pin for full scale (IFS,ERR,IMONBUF) and 20% of full scale (I20FS,ERR,IMONBUF) can be found using
Equation 42 and Equation 43 :
sp
ö2
÷
ø
ER
æ
ç
è
2
2
OS,BUF
IFS,ERR,IMONBUF
=
I
(
+ ER
+
FS,ERR,IMON ) (
)
GAIN,BUF
675 mV
3 mV
æ
ö2
= 1.4%2 + 0.66%2 +
= 1.6%
ç
÷
675 mV
è
ø
(42)
sp
I20FS,ERR,IMONBUF
ö2
÷
ø
ER
æ
ç
è
2
2
OS,BUF
=
I
(
+ ER
+
20FS,ERR,IMON ) (
)
GAIN,BUF
135mV
3mV
æ
ö2
=
4.4%2 + 0.66%2 +
= 5.0%
ç
÷
135mV
è
ø
(43)
Next the power limit error is computed. This error is made up of three sources: the error from external
components (ERRCOMP), the error when translating the sense voltage to IMON (IPL,ERR,IMON), and the error of the
power limit engine at IMON (ERRIMON,PL). Both ERRSNS and ERRIMON, PL are a function of the operating point of
the power limit engine. Note that this error is greatest at largest VDS, since VSNS,PL is smallest (refer to Figure 20).
For this example VDS is largest when VIN = 13 V (maximum VIN) and VOUT = 0 V and thus the error is computed
at this operating point. The sense voltage (VSNS) and the voltage at the IMON pin (VIMON) should be computed for
this operating point using Equation 44 and Equation 45:
30
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
P
LIM ´RSNS
39 W ´0.5 mW
VSNS
=
=
= 1.5 mV
VDS
13 V
(44)
sp
V
SNS ´RIMON
1.5 mV ´ 2670 W
69.8 W
V
=
=
= 57.4 mV
IMON
RSET
(45)
The IPL,ERR,IMON can be computed similarly to IFS,ERR,IMON using Equation 46.
æ
ç
è
ö2
÷
ø
2
EROS
VSNS
150 µV
1.5 mV
2
)
2
)
æ
ö
IPL,ERR,IMON
=
ER
(
+
=
0.4%
(
+
= 10%
GAIN
ç
÷
è
ø
(46)
The tolerance of the power limit engine is specified at three VIMON points in the datasheet: 135 mV (±20.3 mV),
67.5 mV (±10.1 mV), and 27 mV (±8.1 mV). To get the % error at the real operating point, the absolute error
should be extrapolated and divided by VIMON as shown in Equation 47. This is graphically depicted in Figure 33.
10.1 mV-8.1 mV
8.1 mV + (57.4 mV - 27 mV)´ 67.5 mV-27 mV
ERRIMON,PL
=
= 16.7%
57.4 mV
(47)
20.3
10.1
9.6
8.1
27
57.4 67.5
135
VIMON,PL (mV)
Figure 33. Extrapolating Power Limit Error
Once ERRIMON,PL and IPL,ERR,IMON are known the total power limit error (PLERR,TOT) can be computed using
Equation 48. The component error comes from RSNS (1%), RPLIM (1%), RSET (0.1%), and RIMON (0.1%) resulting in
a total component error of 1.4%.
2
2
2
)
PLERR,TOT
=
=
ERR
+ I
+ ERR
COMP
(
IMON,PL ) (PL,ERR,IMON )
(
2
2
2
)
16.7% + 10% + 1.4% = 19.5%
(
) ( ) (
(48)
After computing the fast trip voltage threshold to be 24.9 mV (100 µA × 249 Ω), the fast trip threshold error
resulting from the IC (FSTERR, IC) can be computed using a similar extrapolation method as used for power limit.
The component error of RSNS and RFST should be added to obtain the total fast trip error (FSTERR,TOT) showin in
Equation 49 and Equation 50 below.
5 mV-2 mV
2 mV + 24.9 mV - 20 mV ´
)
(
100 mV-20 mV
FSTERR,IC
=
= 8.8%
24.9 mV
(49)
(50)
sp
2
2
2
FSTERR,TOT
=
8.8% + 1% + 1% = 8.9%
(
) ( ) ( )
Copyright © 2015, Texas Instruments Incorporated
31
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
The IC error of the UV/OV threshold is always 3.7% (0.05 V/1.35 V). Assuming that all resistors have a 1% error
the component error is 1.41% (2 resistors). When using the RMS method the total error is 4%. For the timer
error, the IC contributes 22% and 10% comes from the component. When using the RMS method the total error
becomes 24.1%.
Table 4 summarizes the final tolerances of the design:
Table 4. Design Tolerances
SETTINGS
ACCURACY
2.7%
Current Limit
Fast Trip
Power Limit
8.9%
19.5%
24.1%
4.0%
Timer
UV/OV
Current Monitoring at IMON (Full Scale)
Current Monitoring at IMON (20% of Full Scale)
Current Monitoring at IMONBUF (Full Scale)
Current Monitoring at IMONBUF (20% of Full Scale)
1.4%
4.4%
1.6%
5.0%
32
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
10.2.4 Application Curves
Figure 34. Start up (COUT= 440 µF)
Figure 35. Start up (COUT= 440 µF)
Figure 36. Start up (COUT=1500 µF)
Figure 37. Hot Short on VOUT (zoomed out)
Figure 38. Hot Short on VOUT (zoomed in)
Figure 39. Under/Over Voltage with VIN Rising
Copyright © 2015, Texas Instruments Incorporated
33
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
Figure 40. Under/Over Voltage with VIN Falling
Figure 41. Start Up with VOUT Shorted
Figure 42. Load Step 32A to 40A
Figure 43. Hot – Short on VIN
Figure 44. Gradual Reverse Current
34
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
10.2.5 40 A Single Channel Hot Swap then ORing
CMIDDLE
0.1 µF
HS FET
CSD16415
BS FET
CSD16415
RSNS
0.5 mΩ
VIN
VOUT
COUT
D2
1µF
CIN
0.1 µF
CFST
1.5 nF
CRV
33 nF
D1
SMDJ14
C
P
RHG
10 Ω
RBG
MBRS33
0T3G
10 Ω
VDD SET FSTP
SENM HGATE OUTH CP
A
BGATE RVSNM RVSNP
C
49.9 kΩ
ENOR
PGHS
ENHS
OV
TPS24742
FLTb
IMONBUF
STAT
2.21 kΩ
5.62 kΩ
CENHS
33 nF
PLIM
GND
IMON
TINR
TFLT
RPLIM
143 kΩ
RIMON
2.74 kΩ
CINR
330 nF
CFLT
2.2 µF
Figure 45. Application Schematic for Hot Swap then ORing
10.2.5.1 Design Requirements
This second design example is similar to the first one, but has a few key differences. First of all, the maximum
output capacitance is much larger, and the maximum current is also larger, which puts more stress on the
MOSFET. On the flip side, the TPS24742 IC is used, which results in less MOSFET stress during a hot-short
event, because there is no restart. Finally, there is a requirement that the design should allow for 60A to pass
through for 200 ms without shutting down. This requires the use of two timers. In addition, there is no
requirement for accurate current monitoring and hence it’s not necessary to use a 4 terminal sense resistor.
Table 5. Design Requirements for 40A ORing then Hot Swap
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
11 V – 13 V
Maximum DC load current
40A
Maximum Output Capacitance of the Hot Swap
Maximum Ambient Temperature
MOSFET RθCA (function of layout)
Transient load requirement
10,000 µF
55°C
30°C/W
Yes, 60A for 200ms
Pass “Hot-Short” on Output?
Pass a “Start into short”?
Yes
Yes
Is the load off until PG asserted?
IC used
Yes
TPS24742
No
Current Monitoring Required
Can a hot board be unplugged and plugged back in?
No
10.2.5.2 Design Procedure
10.2.5.2.1 Select RSNS and VSNS,CL Setting
Similarly to the previous design example, 25mV is used as a starting target for VSNS,CL. Targeting a current limit
of 45A to allow margin for the load, the sense resistor can be computed as follows:
Copyright © 2015, Texas Instruments Incorporated
35
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
VSNS,TGT
25 mV
45 A
RSNS,CLC
=
=
= 0.55 mW
ILIM
(51)
Since 0.55 mΩ resistors aren’t available, the closest standard resistor should be chosen. To have better
efficiency, a 0.5 mΩ resistor is chosen. Next the VSNS,CL should be computed based on the actual RSNS and then
used to compute RSET and RIMON. RSET is chosen to target 250 µA of current through SET and IMON pins during
current limit.
VSNS,CL = ILIM × VSNS,CL = 45 A × 0.5 mΩ = 22.5 mV
(52)
sp
RSET,CLC = VSNS,CL/250 µA = 90 Ω
(53)
Chose RSET to equal 90.9Ω, which is the closest available standard resistor. Next obtain the calculated RIMON
(RIMON,CLC) as follows:
R
SET ´675 mV
90.9 W ´675 mV
RIMON,CLC
=
=
= 2.727 kW
VSNS,CL
22.5 mV
(54)
Choose 2.74kΩ resistor for RIMON, which is the closest available standard resistor. Since precision current
monitoring is not needed 1% resistors were used for RIMON and for RSET and a 2 terminal sense resistor
(HCS2512FTL500) was used for RSNS
.
Finally, compute the actual current limit (ILIM,CL) :
0.675 V ´RSET
0.675 V ´90.9 W
2.74 kW ´0.5 mW
ILIM,CL
=
=
= 44.8 A
RIMON ´RSENSE
(55)
10.2.5.2.2 Selecting the Fast Trip Threshold and Filtering
The TPS2474x allows the user to program the fast trip threshold. When this threshold is exceeded the gate is
quickly pulled down. CFSTP can be added to include some filtering into the comparator. The selection of the fast
trip threshold and filtering is influenced by the systems environment and requirements. In general picking a larger
threshold and larger filtering time will result in more immunity to nuisance trips, but also a slower response
(possibly inadequate) to real fault conditions. It’s best to fine tune these threshold after testing the real system.
As a starting point it is recommended to set the fast trip threshold at least 1.25x larger than then current limit. For
this design example a 65A fast trip threshold along with a 500ns filtering time constant were targeted to make
sure that the 60A load transient can be passed. The value for RFSTP and CFSTP can be computed as shown in
Equation 56 and Equation 57:
I
FSTP ´RSNS
65 A ´ 0.5 mW
RFSTP,CLC
=
=
= 325 W
100 µA
100 µA
(56)
sp
tFSTP
500 ns
CFSTP
=
=
= 1.54 nF
RFSTP
324 W
(57)
The next closest standard resistor and capacitor values should be chosen. In this case RFSTP = 324Ω and
CFSTP=1.5nF.
10.2.5.2.3 Selecting the Hot Swap FET
It is critical to select the correct MOSFET for a Hot Swap design. The device must meet the following
requirements:
•
The VDS rating should be sufficient to handle the maximum system voltage along with any ringing caused by
transients. For most 12V systems a 25 V or 30V FET is a good choice.
•
•
The SOA of the FET should be sufficient to handle all usage cases: start-up, hot-short, start into short.
RDSON should be sufficiently low to maintain the junction and case temperature below the maximum rating of
the FET. In fact, it is recommended to keep the steady state FET temperature below 125°C to allow margin to
handle transients.
•
Maximum continuous current rating should be above the maximum load current and the pulsed drain current
must be greater than the current threshold of the circuit breaker. Most MOSFETs that pass the first three
requirements will also pass these two.
36
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
•
A VGS rating of +16 V is required, because the TPS2474x can pull up the gate as high as 15.5 V above
source.
For this design the CSD16415Q was selected for its low RDSON and superior SOA. After selecting the MOSFET,
the maximum steady state case temperature can be computed as seen in Equation 58:
TC,MAX = TA,MAX + RqCA ´IL2OAD,MAX ´RDSON
T
( )
J
(58)
Note that the RDSON is a strong function of junction temperature, which for most MOSFETS will be very close to
the case temperature. A few iterations of the above equations may be necessary to converge on the final RDSON
and TC,MAX value. According to the CSD16415Q datasheet, its RDSON is about 1.4 × greater at 120°C compared
to room temperature. Equation 59 uses this RDSON value to compute the TC,MAX. Note that the computed TC,MAX is
close to the junction temperature assumed for RDSON. Thus no further iterations are necessary.
C
TC,MAX = 55°C + 30°
´ 40A 2 ´ 1.4´1 mW = 122.2°C
(
) (
)
W
(59)
10.2.5.2.4 Select Power Limit
In general, a lower power limit setting is preferred to reduce the stress on the MOSFET. However, at low power
limit levels both the VSNS and VIMON become very low, which results in more error caused by offsets. It is
recommended to keep VSNS above 1.5mV and VIMON above 27mV to ensure reasonable accuracy of the power
limit engine. Based on these requirements the minimum power limit can be computed as shown in Equation 60:
V
VIMON,MIN ´RSET
æ
ö
÷
ø
IN,MAX
P
=
=
´MIN V
,
ç
LIM,MIN
SNS,MIN
RSNS
RIMON
è
13 V
27 mV ´90.9 W
2.74 kW
æ
ö
´MIN 1.5 mV,
= 39 W
ç
÷
0.5 mW
è
ø
(60)
In most applications the power limit can be set to PLIM,MIN using the equation below. Here RSNS and RPWR are in
Ωs and PLIM is in Watts.
84375´RSET
84375´90.9 W
RPLIM
=
=
= 143.5 kW
R
SNS ´RIMON ´P
0.5 mW ´ 2.74 kW ´39
LIM
(61)
The closest available resistor should be selected. In this case it is a 143 kΩ.
10.2.5.2.5 Set Fault Timer
The inrush timer runs when the Hot Swap is in power limit or current limit, which is the case during start-up. Thus
the timer has to be sized large enough to prevent a time-out during start-up. If the part starts directly into current
limit (ILIM × VIN < PLIM) the maximum start time can be computed with Equation 62:
C
OUT ´ V
IN,MAX
tstart,max
=
ILIM
(62)
For most designs (including this example) ILIM × VIN > PLIM so the Hot Swap will start in power limit and transition
into current limit. In that case the maximum start time can be computed as seen in Equation 63:
2
IN,MAX
2
é
ê
ë
ù
é
ù
ú
V
COUT
2
P
2
ILIM
10000 mF (13 V)
39 W
LIM ú
tstart,max
=
´
+
=
´
+
= 21.76 ms
ê
ê
ë
2 ú
û
P
2
39 W
ê
ú
(45 A)
LIM
û
(63)
Note that the above start time is based on typical current limit and power limit values. To ensure that the timer
never times out during start-up it is recommended to set the fault time (TINR) to be 1.5x tstart,max or 32.6 ms. This
will account for the variation in power limit, timer current, and timer capacitance.
Next the designer should decide if having equal TINR and TFLT is acceptable. Note that to pass the load
transient the fault timer needs to be longer than 200 ms. If the inrush time is this long, it will place too much
stress on the MOSFET during a start into short. For this reason, it’s ideal to have two separate timers. To ensure
proper start up and to pass the load transient a target inrush time (TINR,TGT) of 32.6 ms and a target fault time
(TFLT,TGT) of 250ms is used. CINR,CLC and CFLT,CLC is computed as seen in Equation 64 and Equation 65 :
CINR,CLC = 7.59 mF´ T
= 7.59 mF´32.6 ms = 247 nF
INR,TGT
(64)
Copyright © 2015, Texas Instruments Incorporated
37
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
sp
CFLT,CLC = 7.59 mF´ TFLT,TGT = 7.59 mF´ 250 ms = 1898 nF
(65)
The next largest available CINR is chosen as 330nF and the next largest available CFLT is chosen as 2.2µF
Next, the actual TINR and TFLT can be computed as shown below: Once CTMR and CFLT is chosen the actual
programmed time out can be computed as shown in Equation 66 and Equation 67.
CINR
330 nF
T
=
=
7.407 mF 7.59 mF
= 43.5 ms
= 290 ms
INR
(66)
sp
CFLT
7.407 mF 7.59 mF
2.2 mF
TFLT
=
=
(67)
10.2.5.2.6 Check MOSFET SOA
Once the power limit and fault timer are chosen, it’s critical to check that the FET will stay within its SOA during
all test conditions. For this design example the TPS24742 is used, which does not retry during a hot-short. Thus
the worst condition is a start-up with output shorted to GND. In this case the TPS24742 will start into a power
limit and regulate at that point for 43.5 ms (TINR). Based on the SOA of the CSD16415Q, it can handle 13 V, 15
A for 10 ms and it can handle 13 V, 4 A for 100 ms. The SOA for 43.5 ms can be extrapolated by approximating
SOA vs time as a power function as shown in Equation 68:
ISOA t = a´ tm
( )
15 A
4 A
æ
ö
ln
ç
÷
ln I
(
t
/ I
t
SOA ( 1)
( )
)
SOA 2
è
ø
m =
=
= -0.57
ln t / t
(
10 ms
æ
ö
)
1
2
ln
ç
÷
ø
100 ms
è
ISOA
t
( 1) =
15 A
0.57
( )
a =
= 56.25 A ´ ms
-0.57
t1m
10 ms
(
)
ISOA 43.5 ms = 56.25 A ´(ms)0.57 ´(43.5 ms)-0.57 = 6.55 A
(
)
(68)
Note that the SOA of a MOSFET is specified at a case temperature of 25°C, while the case temperature can be
hotter during a start into a short. It is important to understand the hottest temperature that a MOSFET can be
during a start-up (TC, MAX, START). If a board has been off for a while and then it’s turned on TA, MAX is a good
estimate for TC,MAX, START. However, if a board is on and then gets power cycled TC,MAX should be used for
TC,MAX,START. This will depend on system requirements. For this design example it is assumed that the board can
only be plugged in cold and TA,MAX is used to estimate TC,MAX,START
.
TJ,ABSMAX - TA,MAX
ISOA 43.5 ms,T
(
= I
43.5 ms, 25°C ´
( )
)
C,MAX,START
SOA
TJ,ABSMAX - 25°C
150°C - 55°C
150°C - 25°C
= 6.55 A ´
= 4.98 A
(69)
Based on this calculation the MOSFET can handle 4.98 A, 13 V for 43.5 ms at 55°C elevated case temperature,
but is only required to handle 3A during a hot-short. Thus there is good margin and this will be a robust design.
In general, it is recommended that the MOSFET can handle 1.3x more than what is required during a worst case
operating condition. This provides margin to cover the variance of the power limit and fault time.
10.2.5.2.7 Checking Stability of Hot Swap Loop
Using the same method as shown for the OR then Hot Swap example, Ensuring Stability, the minimum required
CGS is computed to be 0.6 nF. Again the CISS is 3.1nF and there is plenty of margin to ensure stability.
38
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
10.2.5.2.8 Choose ORing MOSFET
When selecting the ORing MOSFET, the considerations are similar to the Hot Swap MOSFET, but the SOA is no
longer critical. In addition the lower RDSON is not always ideal, because that would result in a larger reverse
current for the same reverse voltage threshold. Of course a lower RDSON would provide better efficiency. For
consistency sake a single CSD16415Q FET was used for the ORing section as well. It’s important to check its
steady state temperature at max load using the same equation that was used for the Hot Swap.
C
TC,MAX = 55°C + 30°
´ 40 A 2 ´ 1.4´1 mW = 122.2°C
(
) (
)
W
(70)
10.2.5.2.9 Choose Reverse Current Threshold and Filtering
Same settings were used as the previous design example.
10.2.5.2.10 Choose Under Voltage and Over Voltage Settings
Same settings were used as the previous design example.
10.2.5.2.11 Selecting CIN, COUT, CMIDDLE, and Transient Protection
Same settings were used as the previous design example
10.2.5.2.12 Adding CENHS
When the ENHS pulled below its threshold and raised back up the IC will reset. Note that during a hot short the
input voltage can easily droop below the UV threshold and cycle the ENHS pin. For the TPS24740 and
TPS24741 IC’s this will not cause any issues. However, when using the TPS24742 the cycling of the ENHS will
result in the IC attempting to restart, which is undesired (this is the main reason why someone would use the
TPS24742). To avoid this behavior a capacitor should be added to the ENHS to provide filtering. For this
example 33 nF was chosen.
10.2.5.3 Application Curves
Figure 46. Start up (COUT=440µF)
Figure 47. Start up (COUT=10,000µF, VIN = 13V)
Copyright © 2015, Texas Instruments Incorporated
39
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
Figure 48. Start up Into Short on VOUT
Figure 49. Hot Short on VOUT
Figure 50. Hot – Short on VOUT(zoomed in)
Figure 51. Under/Over Voltage with VIN Rising
Figure 52. Short Vin (ILOAD = 10A)
Figure 53. Gradual Reverse Current
40
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
Figure 54. 60A Load Step for 200 ms
Figure 55. Load Step 40A to 60A
Figure 56. Gradual Overcurrent
10.3 System Examples
The TPS2474x is a flexible Hot Swap and ORing controller that can supports many redundant configurations.
The following section goes through the various system level configurations and the advantages of each one. It
also shows how the TPS2474x will behave under system level tests.
10.3.1 TPS2474x in Battery Back Up
Some battery back-up units are set up to support both charging and discharging from the same terminal. In this
case a configuration shown in Figure 57 can be used. In normal operation the load is power from the AC/DC,
while the BBU is charged from the mid-point. The Hot Swap will provide inrush and fault protection to the load. If
the AC/DC fails the ORing will prevent the reverse current to the AC/DC and the load will get powered from the
BBU.
Copyright © 2015, Texas Instruments Incorporated
41
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
System Examples (continued)
Hotswap
To Load
AC/DC
BBU
OR
TPS2474x
Figure 57. Block Diagram for Hot Swap and ORing in BBU Applications
Figure 58 shows the schematic for this implementation. It is important to connect VDD to the mid-point to ensure
that the IC has power even if VIN goes away. In addition the ENHS pin should be based on the mid-point voltage
to ensure that the Hot Swap stays ON even if the VIN power goes away.
VBBU
BS FET
HS FET
RSENS
VOUT
VIN
COUT
RRV
C1
0.1 μF
CRV
CFST
RBG
RHG
CP
470 μF
CP
A
BGATE
C
RVSNP RVSNM VDD SET FSTP SENM HGATE OUTH
PGHS
ENOR
TPS2474x
FLTb
ENHS
OV
IMONBUF
STAT
PLIM
IMON
GND
TINR
TFLT
CINR
CFLT
Figure 58. Application Schematic for TPS2474x in BBU Applications
Figure 59 shows a switch over from the AC/DC power (VIN) to BBU power with a 12A load. The BBU is modeled
as drawing 4A when VMIDDLE > 12V and supplying up to 20A when VMIDDLE < 12V. Note that when VIN collapses
the BBU current goes from negative to positive and the BGATE goes down to prevent the AC/DC from draining
power from the BBU.
42
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
System Examples (continued)
Figure 59. Switch Over to Battery Power
10.3.2 TPS2474x in Priority Muxing
Priority muxing is used in the following scenario:
1. The system should be powered from Main when it’s present
2. The system should be powered from Auxiliary when Main goes away.
3. Auxiliary voltage may be above the Main voltage.
4. The system should support a short to ground on both Main and Aux.
Due to condition 3, the 2 supplies can’t be simply ORed together because the load could start drawing power
from AUX. That’s why an additional Hot Swap is required on the AUX rail to prevent the forward current flow. The
OV pin of the TPS2474x can be used to keep the Auxiliary Hot Swap OFF unless the voltage on MAIN falls
below a certain threshold.
Hotswap
MAIN
OR
TPS2474x
To Load
OFF if
VMAIN > 11 V
Hotswap
AUX
OR
TPS2474x
Figure 60. Block Diagram for Priority Muxing
Copyright © 2015, Texas Instruments Incorporated
43
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
System Examples (continued)
CMIDDLE
BS FET
HS FET
RSNS
VAUX
VOUT
COUT
CIN
CCP
CFST
CRV
0.1 µF
RBG
RHG
VDD SET FSTP
ENOR
SENM HGATE OUTH CP
A
BGATE RVSNM RVSNP
C
PGHS
ENHS
OV
TPS24742
FLTb
IMONBUF
STAT
VMAIN
CENHS
PLIM
GND
IMON
TINR
TFLT
CINR
CFLT
Figure 61. OV Pin Hook Up on the AUX Channel
The following waveforms show the performance of the priority mux using the settings from the Hot Swap then
ORing design example. The OV pin on the AUX side was set to make it turn on once Main was below 11V. Note
that for a 10A load the switch over occurs without any issues, but the system cannot handle it at 30A. This
occurs due to VAUX being higher than VMAIN and VOUT drooping after the main channel shuts down and the
AUX channel coming back up. As a result there is a voltage drop across the Hot Swap MOSFET (VAUX – VOUT
)
and the TPS24742 limits the input current to PLIM/VDS. If the supplied current is lower than the load current the
output capacitor continues to discharge and the system shuts down. When the power limit was increased to
160W the switch over occurred without any issues, because sufficient current was supplied to power the load
and charge the output capacitor.
Figure 62. Switch from Main to Aux (VMAIN = 12V, VAUX = 14V, ILOAD = 10A)
44
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
System Examples (continued)
PLIM = 160W
PLIM = 39W
Figure 63. Switch from Main to Aux with VMAIN = 12V, VAUX = 14V, ILOAD = 30A
(left: PLIM = 39W, right; PLIM = 160W)
10.3.3 TPS2474x with Multiple Loads and Multiple Supplies
Figure 64 applies to systems that have multiple supplies and multiple loads. The ORing after each supply
ensures that the loads won’t lose power if any of the supplies fail and the Hot Swap in front of each load ensures
that a failure on one load doesn’t affect the operation of the other loads. The node on the output of ORing and
input of the Hot Swaps is referred to as VMIDDLE
.
Hotswap
AC/DC1
OR
To Load1
To Load2
TPS2474x
Hotswap
AC/DC2
OR
TPS2474x
Figure 64. Block Diagram for Systems with Multiple Supplies and Loads
Figure 65 shows a hot-short on load 1, which results in a shutdown of the first Hot Swap gate. Note that the
second load continues to be powered as both HGATE2 and VMIDDLE stay high.
Copyright © 2015, Texas Instruments Incorporated
45
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
System Examples (continued)
Figure 65. Hot Short on Load 1, Load 2 Not Interrupted
The main purpose of the ORing controller is to protect the loads when one of the input supplies has a failure. The
two waveforms below show this scenario. The left waveform shows a condition where both of the power supplies
are at the same voltage and both of the BGATEs are ON. When VIN1 goes to ground BGATE1 quickly turns
OFF, while BGATE2 remains ON. In the waveform on the right VIN1 is above VIN2 so the system starts by with
only BGATE1 being ON. When VIN1 goes to ground, BGATE1 quickly turns off and BGATE2 turns ON. There is
a short delay between BGATE1 turning off and BGATE2 turning ON. This pause is due to VMIDDLE discharging
from 12.5V to 12V (BGATE2 will only turn on when VIN2 > VMIDDLE)
VIN1 = VIN2 = 12V
VIN1 =12.5V, VIN2 = 12V
Figure 66. Hot Short on VIN1
(left: VIN1 = VIN2 = 12V; right VIN1 =12.5V, VIN2 = 12V, ILOAD1 = ILOAD2 = 12A )
46
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
System Examples (continued)
Figure 67 shows a system configuration where VIN1 equals VIN2 and VIN2 is hot plugged. Note that when BGATE2
comes up almost immediately and VIN1 raises as well. This is due to the fact that VIN1 had some voltage droop
due to the IR drop of the input impedance. When a second supply was placed in parallel the load was shared
reducing the droop. The quick input spike on VIN2 is due input inductance.
Figure 67. Hot Plug VIN2 (VIN1 = 12V; VIN2 = 12V; ILOAD1 = ILOAD2 = 12A)
10.3.4 Two Supplies Powering a Load
Figure 68 can be used when ORing two power supplies together to drive a single load. The ORing provide
protection in case one of the AC/DC’s fail and the Hot Swap provides protection if there is a failure at the load
and if one of the AC/DC output voltages has an overvoltage condition.
AC/DC1
AC/DC2
Hotswap
Hotswap
OR
OR
TPS2474x
TPS2474x
To Load
Figure 68. Block Diagram for ORing Two Power Supplies
Figure 69 and Figure 70 shows a hot plug event on power supply A, when power supply B is already up. If VINA
is above VINB, the blocking gate of channel B turns off and the load is powered from channel A. If VINA is below
VINB, BGATEA doesn’t enhance and the power continues to be supplied from channel B.
Copyright © 2015, Texas Instruments Incorporated
47
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
System Examples (continued)
Figure 69. Hot Plug VINA (VINA =12.5, VINB = 12V,
Figure 70. Hot Plug VINA (VINA =11.5V, VIN2 = 12V,
RLOAD = 10Ω)
RLOAD = 10Ω)
Figure 71 shows power switching from VINA to VINB after VINA shorts to ground. Note that VOUT droops until it is at
the same level as VINB when BGATEB turns on.
Figure 71. Short on VINA Zoomed In and Zoomed Out View (ILOAD=10A, VINA = 12V, VINB = 11.5V)
Figure 72 shows the same event when VINA and VINB are equal and both channels are on before VINA shorts to
ground. Note channel B stays on and channel A shuts down.
48
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
System Examples (continued)
Figure 72. Short on VINA (ILOAD=10A, VINA = 12V, VINB = 12V)
10.3.5 TPS2474x in Redundant DC/DC Applications
In systems that require zero down time, redundant DC/DCs may be used. The goal is to maintain the output
voltage bus even if one of the DC/DCs fail. Consider a case when there is a short on the high-side MOSFET.
This would effectively short the input bus to the output bus through an inductor resulting in a system failure.
Adding Hot Swap before the DC/DC will protect both the input bus and the output bus by disconnecting power to
the faulty DC/DC module. Next consider a case when the low side MOSFET is shorted. This would pull down the
output bus causing system failure as well. To prevent this and ORing controller should be added on the output of
the DC/DC controller.
TPS2474x is ideal for this application because it can provide both the hot swap and ORing functionality. Note
that the combination of the DC/DC and TPS2474x can be made into hot-swappable modules. That way these
can be replaced without turning OFF the system.
12 V_IN
Hotswap
DC/DC
OR
TPS2474x
Hotswap
DC/DC
OR
TPS2474x
Figure 73. Block Diagram for Systems With Redundant DC/DC
Copyright © 2015, Texas Instruments Incorporated
49
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
System Examples (continued)
DC/DC
12 V
0.9 V – 5 V
CONVERTER
CRV
HS FET
BS FET
VIN
RSNS
VOUT
COUT
C1
RRV
CFST
CP
RHG
RBG
0.1 μF
VDD SET FSTP
SENM HGATE OUTH
CP RVSNM
A
BGATE
C
RVSNP
ENOR
ENHS
OV
PGHS
TPS2474x
FLTb
IMONBUF
STAT
PLIM
IMON
GND
TINR
TFLT
CINR
CFLT
Figure 74. Application Schematic for Hot Swap, DC/DC, ORing Configuration
50
Copyright © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
11 Power Supply Recommendations
In general, operation is best when the input supply isn’t noisy and doesn’t have significant transients. For noisier
environments filtering on input, output, fast trip, and reverse trip should be adjusted to avoid nuisance trips.
12 Layout
12.1 Layout Guidelines
When doing the layout of the TPS2474x in the ORing then hot swap configuration the following are considered
best practice.
•
•
•
•
Ensure proper Kelvin Sense of RSNS
Keep the filtering capacitors CFSTP and CRV as close to the IC as possible.
Keep the traces from CCP to CP and A as short as possible.
Run a separate trace from A and RVSNM to ORing FET source. This will prevent the charge pump noise
along with a DC bias (due to supply current draw) from interfering with the reverse current threshold.
•
•
•
Run a separate trace from C and from RRV to ORing FET drain.
Place a Schottky diode and a ceramic bypass capacitor close to the source of the Hot Swap MOSFET.
Place a TVS and a ceramic bypass capacitor between VIN and ground close to the source of the ORing
MOSFET.
•
•
Use a separate trace to connect to VDD and SENM.
Note that special care must be taken when placing the bypass capacitor for the VDD pin. During Hot Shorts,
there is a very large dv/dt on input voltage during the MOSFET turn off. If the bypass capacitor is placed right
next to the pin and the trace from RSNS to the pin is long, an LC filter is formed. As a result a large differential
voltage can develop between VDD and SENM if there is a large transient on Vin. This could result in a
violation of the abs max rating from VDD to SENM. To avoid this, place the bypass capacitor close to RSNS
instead of the VDD pin.
SENM
Vdd
Trace
inductance
Figure 75. Layout Don'ts
Copyright © 2015, Texas Instruments Incorporated
51
TPS24740
TPS24741
TPS24742
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
www.ti.com.cn
12.2 Layout Example
Power Flow
G
S
HS FET
D
ORING FET
S
RSNS
VIN
D
G
V
OUT
RRV
CRV
OUTH
24
23 22
21 20 19
CP
HGATE
ENHS
ENOR
SENM
FSTP
FLTb
TPS2474X
SET
VDD
PGHS
STAT
IMONBUF
10 11 12
7
8
9
layer1
layer2
via
Power_GND
Figure 76. Layout Example for ORing then Hot Swap Configuration
52
版权 © 2015, Texas Instruments Incorporated
TPS24740
TPS24741
TPS24742
www.ti.com.cn
ZHCSDD2A –JANUARY 2015–REVISED FEBRUARY 2015
13 器件和文档支持
13.1 相关链接
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件,并且可以快速访问样片或购买
链接。
表 6. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
请单击此处
TPS24740
TPS24741
TPS24742
13.2 商标
All trademarks are the property of their respective owners.
13.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
13.4 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
14 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本,请查阅左侧的导航栏。
版权 © 2015, Texas Instruments Incorporated
53
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS24740RGER
TPS24740RGET
TPS24741RGER
TPS24741RGET
TPS24742RGER
TPS24742RGET
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGE
24
24
24
24
24
24
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TPS
24740
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
RGE
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
TPS
24740
RGE
TPS
24741
RGE
TPS
24741
RGE
TPS
24742
RGE
TPS
24742
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS24740RGER
TPS24740RGET
TPS24741RGER
TPS24741RGET
TPS24742RGER
TPS24742RGET
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGE
RGE
RGE
RGE
RGE
RGE
24
24
24
24
24
24
3000
250
330.0
180.0
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
1.15
1.15
1.15
1.15
1.15
1.15
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS24740RGER
TPS24740RGET
TPS24741RGER
TPS24741RGET
TPS24742RGER
TPS24742RGET
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGE
RGE
RGE
RGE
RGE
RGE
24
24
24
24
24
24
3000
250
346.0
210.0
346.0
210.0
346.0
210.0
346.0
185.0
346.0
185.0
346.0
185.0
33.0
35.0
33.0
35.0
33.0
35.0
3000
250
3000
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
RGE0024B
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
0.5
0.3
PIN 1 INDEX AREA
4.1
3.9
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 2.5
(0.2) TYP
2.45 0.1
7
12
EXPOSED
SEE TERMINAL
DETAIL
THERMAL PAD
13
6
2X
SYMM
25
2.5
18
1
0.3
24X
20X 0.5
0.2
19
24
0.1
C A B
SYMM
24X
PIN 1 ID
(OPTIONAL)
0.05
0.5
0.3
4219013/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGE0024B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.45)
SYMM
24
19
24X (0.6)
1
18
24X (0.25)
(R0.05)
TYP
25
SYMM
(3.8)
20X (0.5)
13
6
(
0.2) TYP
VIA
7
12
(0.975) TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219013/A 05/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGE0024B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.08)
(0.64) TYP
19
24
24X (0.6)
1
25
18
24X (0.25)
(R0.05) TYP
SYMM
(0.64)
TYP
(3.8)
20X (0.5)
13
6
METAL
TYP
7
12
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219013/A 05/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,
不保证没有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更,恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务,TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023,德州仪器 (TI) 公司
相关型号:
©2020 ICPDF网 联系我们和版权申明