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TPS2547

ZHCSGL1A –MAY 2017–REVISED MAY 2017

TPS2547 带负载检测功能的 USB 充电端口控制器和 3A 电源开关

1 特性

3 说明

1

•

符合 USB BC 1.2 规范的 D+/D– CDP/DCP 模式

符合中国电信行业标准 YD/T 1591-2009 的

D+/D– 短路模式

TPS2547 是一款集成有 USB 2.0 高速数据线路

(D+/D-) 开关的 USB 充电端口控制器和电源开关。

TPS2547 可在 D+/D– 上提供电气信号，从而为特性

说明部分中列出的充电方案提供支持。TI 使用

TPS2547 对常用的移动电话、平板电脑以及媒体设备

进行充电测试，以确保其既与符合 BC1.2 的器件兼容

也与不符合 BC1.2 的器件兼容。

•

通过自动选择以下模式支持非 BC1.2 充电模式：

–

D+/D– 分压器模式（2V/2.7V 和 2.7V/2V）

D+/D– 1.2V 模式

•

支持休眠模式充电和鼠标/键盘唤醒

负载检测（针对 S4/S5 充电过程中的电源控制以及

所有充电模式下的端口电源管理）

除了支持对常用设备进行充电，TPS2547 还支持两种

不同的电源管理功能，分别为电源唤醒和端口电源管

理 (PPM)（通过 STATUS 引脚实现）。电源唤醒允许

在 S4/S5 充电中进行电源控制，PPM 支持在多端口系

统中进行智能端口电源管理。此外，TPS2547 完全支

持带有鼠标/键盘（适用于低速和高速）的系统唤醒

（从 S3 唤醒）。

•

可兼容 USB 2.0 和 3.0

集成 73mΩ（典型值）高侧金属氧化物半导体场效

应晶体管 (MOSFET)

•

3A 可编程 I_LIMIT支持 15W 负载

工作电压范围：4.5V 至 5.5V

禁用和启用时为 2 µA/270 µA I_Q

插入式，BOM 与 TPS2543/46 兼容

16 引脚 WQFN 封装 (3.00 mm × 3.00 mm)

DM/DP 引脚上的静电放电 (ESD) 额定值达 8kV

UL 认证文件号E169910 和 CB 认证 - 待审批

TPS2547 73mΩ 配电开关专门用于可能面临高容性

负载和短路问题的应用。凭借两个可编程电流阈值，该

器件可灵活设置电流限值和负载检测阈值。

器件信息⁽¹⁾

器件型号

TPS2547

封装

WQFN (16)

封装尺寸（标称值）

2 应用

3.00mm x 3.00mm

•

USB 端口（主机和集线器）

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

笔记本和台式机

通用墙式充电适配器

简化原理图

To Portable Device

à

0.1 uF

4.5V – 5.5V

Power Bus

IN

OUT

VBUS

D-

D+

TPS2547

C_USB

R_STATUS

(10 kW)

R_FAULT

(10 kW)

ILIM_LO

ILIM_HI

GND

STATUS

STATUS Signal

Fault Signal

ILIM Select

R_{ILIM_HI}

R_{ILIM_LO}

GND

FAULT

USB

Connector

ILIM_SEL

DM_IN

DP_IN

Power Switch EN

Mode Select I/O

EN

CTL1

CTL2

CTL3

DM_OUT

DP_OUT

To Host Controller

à

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLVSE11

TPS2547

ZHCSGL1A –MAY 2017–REVISED MAY 2017

www.ti.com.cn

8.3 Feature Description................................................. 15

8.4 Device Functional Modes........................................ 26

Application and Implementation ........................ 29

9.1 Application Information............................................ 29

9.2 Typical Application .................................................. 30

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Electrical Characteristics: High-Bandwidth Switch.... 6

6.7 Electrical Characteristics: Charging Controller ......... 7

6.8 Typical Characteristics.............................................. 9

Parameter Measurement Information ................ 13

Detailed Description ............................................ 14

8.1 Overview ................................................................. 14

8.2 Functional Block Diagram ....................................... 15

9

10 Power Supply Recommendations ..................... 32

11 Layout................................................................... 32

11.1 Layout Guidelines ................................................. 32

11.2 Layout Example .................................................... 33

12 器件和文档支持 ..................................................... 34

12.1 文档支持 ............................................................... 34

12.2 接收文档更新通知 ................................................. 34

12.3 社区资源................................................................ 34

12.4 商标....................................................................... 34

12.5 静电放电警告......................................................... 34

12.6 Glossary................................................................ 34

13 机械、封装和可订购信息....................................... 34

7

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (May 2017) to Revision A

Page

•

Changed Equation 1 ............................................................................................................................................................ 30

Changed Equation 2 ............................................................................................................................................................ 31

Changed Equation 3 ............................................................................................................................................................ 31

2

TPS2547

www.ti.com.cn

ZHCSGL1A –MAY 2017–REVISED MAY 2017

5 Pin Configuration and Functions

RTE Package

16-Pin WQFN

Top View

IN

DM_OUT

DP_OUT

ILIM_SEL

1

2

3

4

12

11

10

9

OUT

DM_IN

DP_IN

Thermal Pad

STATUS

Not to scale

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NO.

NAME

Input voltage and supply voltage; connect 0.1 μF or greater ceramic capacitor from IN to GND as close

to the device as possible.

1

IN

P

2

3

DM_OUT

DP_OUT

I/O

D– data line to USB host controller.

D+ data line to USB host controller.

Logic-level input signal used to control the charging mode, current limit threshold, and load detection;

see Table 3. Can be tied directly to IN or GND without pullup or pulldown resistor.

4

ILIM_SEL

I

Logic-level input for turning the power switch and the signal switches on/off; logic low turns off the signal

and power switches and holds OUT in discharge. Can be tied directly to IN or GND without pullup or

pulldown resistor.

5

EN

I

Logic-level input used to control the charging mode and the signal switches; see Table 3. Can be tied

directly to IN or GND without pullup or pulldown resistor.

6

7

8

CTL1

CTL2

CTL3

I

Logic-level input used to control the charging mode and the signal switches; see Table 3. Can be tied

directly to IN or GND without pullup or pulldown resistor.

Logic-level input used to control the charging mode and the signal switches; see Table 3. Can be tied

directly to IN or GND without pullup or pulldown resistor.

9

STATUS

DP_IN

DM_IN

OUT

O

I/O

P

Active-low open-drain output, asserted in load detection conditions.

D+ data line to downstream connector.

10

11

12

13

14

D– data line to downstream connector.

Power-switch output.

FAULT

GND

O

Active-low open-drain output, asserted during overtemperature or current limit conditions.

Ground connection.

P

External resistor connection used to set the low current-limit threshold and the load detection current

threshold. A resistor to ILIM_LO is optional; see Current-Limit Settings in Detailed Description.

15

16

—

ILIM_LO

ILIM_HI

I

External resistor connection used to set the high-current-limit threshold.

Thermal

Pad

Internally connected to GND; used to heatsink the part to the circuit board traces. Connect to GND

plane.

—

(1) G = ground, I = input, O = output, P = power.

3

TPS2547

ZHCSGL1A –MAY 2017–REVISED MAY 2017

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

IN, EN, ILIM_LO, ILIM_HI, FAULT, STATUS,

ILIM_SEL, CTL1, CTL2, CTL3, OUT

–0.3

7

Voltage

V

IN to OUT

–7

DP_IN, DM_IN, DP_OUT, DM_OUT

–0.3

(IN + 0.3) or 5.7

±20

Input clamp current

DP_IN, DM_IN, DP_OUT, DM_OUT

mA

Continuous current in SDP or CDP

mode

DP_IN to DP_OUT or DM_IN to DM_OUT

±100

±50

Continuous current in BC1.2 DCP mode DP_IN to DM_IN

Continuous output current

OUT

Internally limited

25

Internally limited

Continuous output sink current

Continuous output source current

Operating junction temperature, T_J

FAULT, STATUS

ILIM_LO, ILIM_HI

mA

°C

–40

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

HBM

±2000

Human-body model (HBM), per

ANSI/ESDA/JEDEC JS-001⁽¹⁾

Electrostatic

discharge

HBM wrt GND and each other, DP_IN,

DM_IN, OUT

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

±8000

±500

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

voltages are referenced to GND (unless otherwise noted)

MIN MAX UNIT

V_IN

Input voltage, IN

4.5

0

5.5

V_IN

V

Input voltage, logic-level inputs, EN, CTL1, CTL2, CTL3, ILIM_SEL

Input voltage, data line inputs, DP_IN, DM_IN, DP_OUT, DM_OUT

High-level input voltage, EN, CTL1, CTL2, CTL3, ILIM_SEL

Low-level input voltage, EN, CTL1, CTL2, CTL3, ILIM_SEL

Continuous current, data line inputs, SDP or CDP mode, DP_IN to DP_OUT, DM_IN to DM_OUT

Continuous current, data line inputs, BC1.2 DCP mode, DP_IN to DM_IN

0

V

V_IH

V_IL

1.8

V

0.8

±30

±15

2.5

3.0

10

V

mA

T_J= –40°C to 125°C

Continuous output current, OUT

0

I_OUT

A

T_J= –40°C to 115°C

Continuous output sink current, FAULT, STATUS

mA

kΩ

°C

R_{ILIM_XX}Current-limit set resistors

T_JOperating virtual junction temperature

15.4 750

–40 125

4

TPS2547

www.ti.com.cn

ZHCSGL1A –MAY 2017–REVISED MAY 2017

6.4 Thermal Information

TPS2547

THERMAL METRIC⁽¹⁾

RTE (WQFN)

16 PINS

53.4

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

51.4

17.2

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

3.7

ψ_JB

20.7

R_θJC(bot)

3.9

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

Unless otherwise noted: –40 ≤ T_J≤ 125°C, 4.5 V ≤ V_IN≤ 5.5 V, V_EN= V_IN, V_{ILIM_SEL}= V_IN, V_CTL1= V_CTL2= V_CTL3= V_IN. R_FAULT

R_STATUS= 10 kΩ, R_{ILIM_HI}= 20 kΩ, R_{ILIM_LO}= 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages

are with respect to GND.

=

PARAMETER

POWER SWITCH

TEST CONDITIONS

MIN

TYP MAX UNIT

T_J= 25°C, I_OUT= 2 A

73

84

R_DS(on)

ON resistance⁽¹⁾

–40°C ≤ T_J≤ 85°C, I_OUT= 2 A

–40°C ≤ T_J≤ 125°C, I_OUT= 2 A

73 105

73 120

mΩ

t_r

OUT voltage rise time

OUT voltage fall time

OUT voltage turnon time

OUT voltage turnoff time

0.7

0.2

1

0.35

2.7

1.6

0.5

4

V_IN= 5 V, C_L= 1 µF, R_L= 100 Ω (see Figure 23 and

Figure 24)

ms

t_f

t_on

t_off

V_IN= 5 V, C_L= 1 µF, R_L= 100 Ω (see Figure 23 and

Figure 25)

ms

µA

1.7

3

V_OUT= 5.5 V, V_IN= V_EN= 0 V, –40 ≤ T_J≤ 85°C,

Measure I_OUT

I_REV

Reverse leakage current

2

DISCHARGE

R_DCHG

t_{DCHG_L}

t_{DCHG_S}

OUT discharge resistance

400

1.3

500 630

2.9

310 450

Ω

s

Long OUT discharge hold time

Short OUT discharge hold time

Time V_OUT< 0.7 V (see Figure 26)

2

205

ms

EN, ILIMSEL, CTL1, CTL2, CTL3 INPUTS

Input pin rising logic threshold

voltage

1

1.35

1.7

V

Input pin falling logic threshold

voltage

0.85

1.15 1.45

Hysteresis⁽²⁾

200

0.5

mV

µA

Input current

Pin voltage = 0 V or 5.5 V

–0.5

ILIMSEL CURRENT LIMIT

V_{ILIM_SEL}= 0 V, R_{ILIM_LO}= 210 kΩ

V_{ILIM_SEL}= 0 V, R_{ILIM_LO}= 80.6 kΩ

V_{ILIM_SEL}= 0 V, R_{ILIM_LO}= 22.1 kΩ

V_{ILIM_SEL}= V_IN, R_{ILIM_HI}= 20 kΩ

213

598

250 287

650 708

2365 2530

2610 2800

3085 3300

3375 3600

2200

2425

2875

3150

I_OS

OUT short-circuit current limit⁽¹⁾

mA

µs

V_{ILIM_SEL}= V_IN, R_{ILIM_HI}= 16.9 kΩ

V_{ILIM_SEL}= V_IN, R_{ILIM_HI}= 15.4 kΩ, T_J= –40°C to 115°C

V_IN= 5 V, R = 0.1Ω, lead length = 2 inches

(see Figure 27)

Response time to OUT short-

circuit⁽²⁾

t_IOS

1.5

(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; Thermal effects must be taken into account

separately.

(2) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's

product warranty.

5

TPS2547

ZHCSGL1A –MAY 2017–REVISED MAY 2017

www.ti.com.cn

Electrical Characteristics (continued)

Unless otherwise noted: –40 ≤ T_J≤ 125°C, 4.5 V ≤ V_IN≤ 5.5 V, V_EN= V_IN, V_{ILIM_SEL}= V_IN, V_CTL1= V_CTL2= V_CTL3= V_IN. R_FAULT

R_STATUS= 10 kΩ, R_{ILIM_HI}= 20 kΩ, R_{ILIM_LO}= 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages

are with respect to GND.

=

PARAMETER

SUPPLY CURRENT

TEST CONDITIONS

MIN

TYP MAX UNIT

I_{IN_OFF}

Disabled IN supply current

Enabled IN supply current

V_EN= 0 V, V_OUT= 0 V, –40 ≤ T_J≤ 85°C

0.1

2

µA

V_CTL1= V_CTL2= V_IN, V_CTL3= 0 V, V_{ILIM_SEL}= 0 V

V_CTL1= V_CTL2= V_CTL3= V_IN, V_{ILIM_SEL}= 0 V

V_CTL1= V_CTL2= V_IN, V_CTL3= 0 V, V_{ILIM_SEL}= V_IN

V_CTL1= V_CTL2= V_IN, V_CTL3= VIN, V_{ILIM_SEL}= V_IN

V_CTL1= 0 V, V_CTL2= V_CTL3= V_IN

165 220

175 230

185 240

195 250

215 270

I_{IN_ON}

UNDERVOLTAGE LOCKOUT

V_UVLO

IN rising UVLO threshold voltage

3.9

4.1

4.3

V

Hysteresis⁽²⁾

100

mV

FAULT

Output low voltage

OFF-state leakage

I_FAULT= 1 mA

V_FAULT= 5.5 V

100

1

mV

µA

Overcurrent FAULT rising and

falling deglitch

5

8.2

12

ms

STATUS

Output low voltage

OFF-state leakage

I_STATUS= 1 mA

V_STATUS= 5.5 V

100

1

mV

µA

THERMAL SHUTDOWN

Thermal shutdown threshold

155

135

Thermal shutdown threshold in

current-limit

°C

Hysteresis⁽²⁾

20

6.6 Electrical Characteristics: High-Bandwidth Switch

Unless otherwise noted: –40 ≤ T_J≤ 125°C, 4.5 V ≤ V_IN≤ 5.5 V, V_EN= V_IN, V_{ILIM_SEL}= V_IN, V_CTL1= V_CTL2= V_CTL3= V_IN. R_FAULT

R_STATUS= 10 kΩ, R_{ILIM_HI}= 20 kΩ, R_{ILIM_LO}= 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages

are with respect to GND.

=

PARAMETER

TEST CONDITIONS

MIN TYP MAX UNIT

HIGH-BANDWIDTH ANALOG SWITCH

V_{DP/DM_OUT}= 0 V, I_{DP/DM_IN}= 30 mA

V_{DP/DM_OUT}= 2.4 V, I_{DP/DM_IN}= –15 mA

V_{DP/DM_OUT}= 0 V, I_{DP/DM_IN}= 30 mA

V_{DP/DM_OUT}= 2.4 V, I_{DP/DM_IN}= –15 mA

2

3

4

6

DP/DM switch ON resistance

Ω

0.05 0.15

Switch resistance mismatch between

DP / DM channels

Ω

V_EN= 0 V, V_{DP/DM_IN}= 0.3 V, V_ac= 0.6 V_pk–pk

f = 1 MHz

,

DP/DM switch OFF-state capacitance⁽¹⁾

DP/DM switch ON-state capacitance⁽²⁾

OFF-state isolation⁽³⁾

3

3.6

6.2

pF

V_{DP/DM_IN}= 0.3 V, V_ac= 0.6 V_pk-pk, f = 1 MHz

V_EN= 0 V, f = 250 MHz

5.4

33

52

pF

dB

O_IRR

X_TALK

ON-state cross channel isolation⁽³⁾

f = 250 MHz

V_EN= 0 V, V_{DP/DM_IN}= 3.6 V, V_{DP/DM_OUT}= 0 V,

measure I_{DP/DM_OUT}

OFF-state leakage current

0.1

1.5

µA

BW

t_pd

Bandwidth (–3 dB)⁽³⁾

Propagation delay⁽³⁾

R_L= 50 Ω

2.6

GHz

ns

0.25

(1) The resistance in series with the parasitic capacitance to GND is typically 250 Ω.

(2) The resistance in series with the parasitic capacitance to GND is typically 150 Ω

(3) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's

product warranty.

6

TPS2547

www.ti.com.cn

ZHCSGL1A –MAY 2017–REVISED MAY 2017

Electrical Characteristics: High-Bandwidth Switch (continued)

Unless otherwise noted: –40 ≤ T_J≤ 125°C, 4.5 V ≤ V_IN≤ 5.5 V, V_EN= V_IN, V_{ILIM_SEL}= V_IN, V_CTL1= V_CTL2= V_CTL3= V_IN. R_FAULT

=

R_STATUS= 10 kΩ, R_{ILIM_HI}= 20 kΩ, R_{ILIM_LO}= 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages

are with respect to GND.

PARAMETER

TEST CONDITIONS

MIN TYP MAX UNIT

0.1 0.2 ns

Skew between opposite transitions of the

t_SK

same port (t_PHL– t_PLH

)

6.7 Electrical Characteristics: Charging Controller

Unless otherwise noted: –40 ≤ T_J≤ 125°C, 4.5 V ≤ V_IN≤ 5.5 V, V_EN= V_IN, V_{ILIM_SEL}= V_IN, V_CTL1= 0 V, V_CTL2= V_CTL3= V_IN.

R_FAULT= R_STATUS= 10 kΩ, R_{ILIM_HI}= 20 kΩ, R_{ILIM_LO}= 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All

voltages are with respect to GND.

PARAMETER

TEST CONDITIONS

MIN TYP MAX UNIT

SHORTED MODE (BC1.2 DCP)

DP_IN / DM_IN shorting resistance

VCTL1 = VIN, VCTL2 = VCTL3 = 0 V

125 200

Ω

1.2 V MODE

DP_IN /DM_IN output voltage

1.19 1.25 1.31

V

VCTL1 = VIN, VCTL2 = VCTL3 = 0 V

DP_IN /DM_IN output impedance

60

75

94

kΩ

DIVIDER1 MODE

DP_IN divider1 output voltage

1.9

2.57

8

2

2.1

V

DM_IN divider1 output voltage

DP_IN output impedance

DM_IN output impedance

2.7 2.84

10.5 12.5

kΩ

8

DIVIDER2 MODE

DP_IN divider2 output voltage

DM_IN divider2 output voltage

DP_IN output impedance

2.57

1.9

8

2.7 2.84

V

2

2.1

IOUT = 1 A

10.5 12.5

kΩ

DM_IN output impedance

8

CHARGING DOWNSTREAM PORT

VCTL1 = VCTL2 = VCTL3 = V_{DP_IN}= 0.6 V,

V_{DM_SRC}

V_{DAT_REF}

DM_IN CDP output voltage

0.5

0.6

0.7

0.4

V

VIN

–250 µA < I_{DM_IN}< 0 µA

DP_IN rising lower window threshold

for V_{DM_SRC}activation

0.25

V

Hysteresis⁽¹⁾

50

mV

V

VCTL1 = VCTL2 = VCTL3 = VIN

VCTL1 = VCTL2 = VCTL3 =

DP_IN rising upper window threshold

for V_{DM_SRC}de-activation

Hysteresis⁽¹⁾

V_{LGC_SRC}

0.8

40

1

100

mV

µA

I_{DP_SINK}

DP_IN sink current

V_{DP_IN}= 0.6 V

70 100

VIN

LOAD DETECT – NON-POWER WAKE

IOUT rising load detect current

threshold

I_LD

635 700 765

mA

Hysteresis⁽¹⁾

50

mA

ms

s

VCTL1 = VCTL2 = VCTL3 = VIN

t_{LD_SET}

Load detect set time

Load detect reset time

140 200 275

1.9

3

4.2

(1) These parameters are provided for reference only and do not constitute part of Texas Instrument's published device specifications for

purposes of Texas Instrument's product warranty.

7

TPS2547

ZHCSGL1A –MAY 2017–REVISED MAY 2017

www.ti.com.cn

Electrical Characteristics: Charging Controller (continued)

Unless otherwise noted: –40 ≤ T_J≤ 125°C, 4.5 V ≤ V_IN≤ 5.5 V, V_EN= V_IN, V_{ILIM_SEL}= V_IN, V_CTL1= 0 V, V_CTL2= V_CTL3= V_IN.

R_FAULT= R_STATUS= 10 kΩ, R_{ILIM_HI}= 20 kΩ, R_{ILIM_LO}= 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All

voltages are with respect to GND.

PARAMETER

TEST CONDITIONS

MIN TYP MAX UNIT

LOAD DETECT – POWER WAKE

I_{OS_PW}

Power wake short-circuit current limit

32

23

55

45

5

78

67

mA

I_OUTfalling power wake reset current

detection threshold

Reset current hysteresis⁽¹⁾

VCTL1 = VCTL2 = 0 V, VCTL3 = VIN

mA

s

Power wake reset time

10.7

15 20.6

8

TPS2547

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6.8 Typical Characteristics

100

90

80

70

60

50

0.3

0.25

0.2

0.15

0.1

0.05

0

−40 −25 −10

5

20 35 50 65 80 95 110 125

−40 −25 −10

5

20 35 50 65 80 95 110 125

Junction Temperature (°C)

G001

G002

Figure 1. Power Switch ON Resistance vs Temperature

Figure 2. Reverse Leakage Current vs Temperature

580

3500

V_IN= 4.5 V

V_IN= 5 V

V_IN= 5.5 V

560

3000

2500

2000

540

520

500

480

460

1500

R_{ILIM_LO}= 210 kΩ

R_{ILIM_LO}= 80.6 kΩ

R_{ILIM_HI}= 20 kΩ

1000

R_{ILIM_HI}= 16.9 kΩ

500

0

−40 −25 −10

5

20 35 50 65 80 95 110 125

−40 −25 −10

5

20 35 50 65 80 95 110 125

Junction Temperature (°C)

G003

G004

Figure 3. OUT Discharge Resistance vs Temperature

Figure 4. OUT Short-Circuit Current Limit vs Temperature

1.2

190

V_IN= 5.5 V

V_IN= 4.5 V

V_IN= 5 V

V_IN= 5.5 V

180

1

0.8

0.6

0.4

0.2

0

170

160

150

Device configured for SDP

V_ILIMSEL= 0 V

140

130

−40

−20

0

20

40

60

80

100

−40 −25 −10

5

20 35 50 65 80 95 110 125

Junction Temperature (°C)

G005

G006

Figure 5. Disabled in Supply Current vs Temperature

Figure 6. Enabled in Supply Current - SDP vs Temperature

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Typical Characteristics (continued)

220

240

230

220

210

200

190

180

V_IN= 4.5 V

V_IN= 5 V

V_IN= 4.5 V

V_IN= 5 V

V_IN= 5.5 V

210

200

190

180

170

Device configured for CDP

20 35 50 65 80 95 110 125

Device configured for DCP AUTO

20 35 50 65 80 95 110 125

160

−40 −25 −10

5

−40 −25 −10

5

Junction Temperature (°C)

G007

G008

Figure 7. Enabled in Supply Current - CDP vs Temperature

Figure 8. Enabled in Supply Current - DCP Auto

vs Temperature

0

700

T_J= −40°C

T_J= 25°C

T_J= 125°C

600

-5

500

400

300

200

100

-10

-15

-20

V_IN= 4.5 V

10

0

1

2

3

4

5

6

7

8

9

0.01

0.1

Frequency - GHz

1

10

Sinking Current (mA)

G009

Figure 9. Status and Fault Output Low Voltage

vs Sinking Current

Figure 10. Data Transmission Characteristics vs Frequency

60

50

40

30

20

10

0

80

70

60

50

40

30

20

10

0

0.01

0.1

Frequency - GHz

1

10

0.01

0.1

Frequency - GHz

1

10

Figure 12. ON-State Cross-Channel Isolation vs Frequency

Figure 11. OFF-State Data Switch Isolation vs Frequency

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Typical Characteristics (continued)

0.5

0.4

0.3

0.2

0.1

0

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.1

–0.2

–0.3

–0.4

–0.5

–0.3

–0.4

–0.5

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

Time (ns)

G013

G014

Figure 13. Eye Diagram Using USB Compliance Test Pattern

(With No Switch)

Figure 14. Eye Diagram Using USB Compliance Test Pattern

(With Data Switch)

740

230

225

220

215

210

205

200

R_{ILIM_LO}= 80.6 kΩ

720

700

680

660

640

620

I_OS- OUT Short Circuit Current Limit

I_LD- I_OUTRising Load Detect Threshold

600

−40 −25 −10

5

20 35 50 65 80 95 110 125

−40 −25 −10

5

20 35 50 65 80 95 110 125

Junction Temperature (°C)

G015

G016

Figure 15. IOUT Rising Load Detect Threshold and Out

Short-Circuit Current Limit vs Temperature

Figure 16. Load Detect Set Time vs Temperature

59

58

57

56

55

54

53

52

V_OUT

2 V/div

V_EN

5 V/div

R_LOAD= 5 Ω

I_IN

C_LOAD= 150 µF

500 mA/div

−40 −25 −10

5

20 35 50 65 80 95 110 125

Junction Temperature (°C)

G017

t - Time - 1 ms/div

Figure 18. Turnon Response

G021

Figure 17. Power Wake Current Limit vs Temperature

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ZHCSGL1A –MAY 2017–REVISED MAY 2017

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Typical Characteristics (continued)

V_/FAULT

5 V/div

V_OUT

2 V/div

V_EN

5 V/div

R_LOAD= 5 Ω

C_LOAD= 150 µF

R_{ILM_LO}= 80.6 kΩ

I_IN

500 mA/div

t - Time - 2 ms/div

G023

t - Time - 1 ms/div

G022

Figure 20. Device Enabled Into Short-Circuit

Figure 19. Turnoff Response

R_{ILM_HI}= 20 kΩ

V_/FAULT

5 V/div

V_/FAULT

5 V/div

V_EN

5 V/div

V_OUT

R

_{ILIM_HI}= 20 kΩ

2 V/div

R_LOAD= 5 Ω

C_LOAD= 150 µF

I_IN

1 A/div

2 A/div

t - Time - 5 ms/div

G024

t - Time - 2 ms/div

G025

Figure 21. Device Enabled Into Short-Circuit - Thermal

Cycling

Figure 22. Short-Circuit to Full Load Recovery

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7 Parameter Measurement Information

OUT

R_L

C_L

Figure 23. Out Rise/Fall Test Load

90%

10%

t_r

t_f

V_OUT

Figure 24. Power-ON and OFF Timing

50 %

V_EN

t_on

t_off

90 %

V_OUT

10 %

Figure 25. Enable Timing, Active High Enable

5 V

t_DCHG

V_OUT

0 V

Figure 26. Out Discharge During Mode Change

I_OS

I_OUT

t_IOS

Figure 27. Output Short-Circuit Parameters

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ZHCSGL1A –MAY 2017–REVISED MAY 2017

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8 Detailed Description

8.1 Overview

The following overview references various industry standards. TI recommends consulting the most up-to-date

standard to ensure the most recent and accurate information. Rechargeable portable equipment requires an

external power source to charge its batteries. USB ports are a convenient location for charging, because of an

available 5-V power source. Universally accepted standards are required to make sure host and client-side

devices operate together in a system to ensure power management requirements are met. Traditionally, host

ports following the USB 2.0 specification must provide at least 500 mA to downstream client-side devices.

Because multiple USB devices can attach to a single USB port through a bus-powered hub, it is the responsibility

of the client-side device to negotiate its power allotment from the host, ensuring the total current draw does not

exceed 500 mA. In general, each USB device is granted 100 mA, and may request more current in 100-mA unit

steps up to 500 mA. The host may grant or deny based on the available current. A USB 3.0 host port not only

provides higher data rate than USB 2.0 port, but also raises the unit load from 100 mA to 150 mA. It is also

required to provide a minimum current of 900 mA to downstream client-side devices.

Additionally, the success of USB makes the mini-USB connector a popular choice for wall adapter cables. This

allows a portable device to charge from both a wall adapter, and USB port with only one connector. As USB

charging has gained popularity, the 500-mA minimum defined by USB 2.0 or 900 mA for USB 3.0 has become

insufficient for many handset and personal media players, which need a higher charging rate. Wall adapters can

provide much more current than 500 mA/900 mA. Several new standards have been introduced, defining

protocol handshaking methods that allow host and client devices to acknowledge and draw additional current

beyond the 500 mA/900 mA minimum defined by USB 2.0 and 3.0, while still using a single micro-USB input

connector.

The TPS2547 supports four of the most common USB charging schemes found in popular handheld media and

cellular devices:

•

USB Battery Charging Specification BC1.2

Chinese Telecommunications Industry Standard YD/T 1591-2009

Divider Mode

1.2-V Mode

YD/T 1591-2009 is a subset of BC1.2 specifications supported by vast majority of devices that implement USB

changing. Divider and 1.2-V charging schemes are supported in devices from specific, yet popular device

makers.

BC1.2 lists three different port types:

•

Standard Downstream Port (SDP)

Charging Downstream Port (CDP)

Dedicated Charging Port (DCP)

BC1.2 defines a charging port as a downstream facing USB port that provides power for charging portable

equipment. Under this definition, CDP and DCP are defined as charging ports.

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8.2 Functional Block Diagram

Current

Sense

IN

CS

OUT

Disable +UVLO+Discharge

ILIM_HI

Current Limit

select

Current

Limit

Charge

Pump

GND

ILIM_LO

OC

8-ms Deglitch

OTSD

UVLO

Thermal

Sense

ILIM_SEL

EN

Driver

FAULT

LD cur set

8-ms Deglitch

(falling edge)

discharge

DM_IN

DP_IN

DM_OUT

DP_OUT

ILIM_SEL

OC

CTL1

CTL2

CTL3

Divider

Mode

DCP

Detection

LD cur set

Discharge

Auto-Detection

CDP

Detection

Logic

control

STATUS

TPS2543

Only

Discharge

8.3 Feature Description

8.3.1 Standard Downstream Port (SDP) USB 2.0/USB 3.0

An SDP is a traditional USB port that follows USB 2.0 and 3.0 protocol, and supplies a minimum of 500 mA for

USB 2.0 and 900 mA for USB 3.0 per port. USB 2.0 and 3.0 communications is supported, and the host

controller must be active to allow charging. TPS2547 supports SDP mode in system power state S0, when

system is completely powered ON, and fully operational. For more details on control pin (CTL1-CTL3) settings to

program this state, see Table 3.

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Feature Description (continued)

8.3.2 Charging Downstream Port (CDP)

A CDP is a USB port that follows USB BC1.2 and supplies a minimum of 1.5 A per port. It provides power and

meets USB 2.0 requirements for device enumeration. USB 2.0 communications is supported, and the host

controller must be active to allow charging. What separates a CDP from an SDP is the host-charge handshaking

logic that identifies this port as a CDP. A CDP is identifiable by a compliant BC1.2 client device, and allows for

additional current draw by the client device.

The CDP process is done in two steps. During step one, the portable equipment outputs a nominal 0.6-V output

on the D+ line, and reads the voltage input on the D– line. The portable device detects it is connected to an SDP

if the D– voltage is less than the nominal data detect voltage of 0.3 V. The portable device detects that it is

connected to a Charging Port if the D– voltage is greater than the nominal data detect voltage of 0.3 V, and

optionally less than 0.8 V.

The second step is necessary for portable equipment to determine if it is connected to CDP or DCP. The

portable device outputs a nominal 0.6 V output on its D– line, and reads the voltage input on its D+ line. The

portable device detects it is connected to a CDP if the data line being read remains less than the nominal data

detect voltage of 0.3 V. The portable device detects it is connected to a DCP if the data line being read is greater

than the nominal data detect voltage of 0.3 V.

TPS2547 supports CDP mode in system power state S0 when system is completely powered ON, and fully

operational. For more details on control pin (CTL1-CTL3) settings to program this state, see Table 3.

8.3.3 Dedicated Charging Port (DCP)

A DCP only provides power but does not support data connection to an upstream port. As shown in following

sections, a DCP is identified by the electrical characteristics of the data lines. The TPS2547 emulates DCP in

two charging states, namely DCP Forced and DCP Auto as shown in Figure 37. In DCP Forced state the device

supports one of the two DCP charging schemes, namely Divider1 or Shorted. In the DCP Auto state, the device

charge detection state machine is activated to selectively implement charging schemes involved with the

Shorted, Divider1, Divider2, and 1.2-V modes. Shorted DCP mode complies with BC1.2 and Chinese

Telecommunications Industry Standard YD/T 1591-2009, while the Divider and 1.2-V modes are employed to

charge devices that do not comply with BC1.2 DCP standard.

8.3.3.1 DCP BC1.2 and YD/T 1591-2009

Both standards define that the D+ and D– data lines must be shorted together with a maximum series impedance

of 200 Ω. This is shown in Figure 28.

TPS2547

D- Out

VBUS

D-

2.0 V

CDP

Detect Detect

Auto

1.2 V

2.7 V

D+

GND

D+ Out

Figure 28. DCP Supporting BC1.2/YD/T 1591-2009

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Feature Description (continued)

8.3.3.2 DCP Divider Charging Scheme

There are two Divider charging scheme supported by the device, Divider1 and Divider2 as shown in Figure 29

and Figure 30. In Divider1 charging scheme the device applies 2 V and 2.7 V to D+ and D– data line

respectively. This is reversed in Divider2 mode.

TPS2547

D- Out

VBUS

D-

2.7 V

CDP

Detect Detect

Auto

1.2 V

2.0 V

D+

GND

D+ Out

Figure 29. DCP Divider1 Charging Scheme

D- Out

TPS2547

VBUS

2.0 V

D-

1.2 V

2.7 V

CDP

Detect Detect

Auto

D+

GND

D+ Out

Figure 30. Divider2 Charging Scheme

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Feature Description (continued)

8.3.3.3 DCP 1.2-V Charging Scheme

1.2-V charging scheme is used by some handheld devices to enable fast charging at 2 A. TPS2547 supports this

scheme in the DCP-Auto mode before the device enters BC1.2 shorted mode. To simulate this charging scheme

D+/D– lines are shorted and pulled-up to 1.2 V for fixed duration then device moves to DCP shorted mode as

defined in BC1.2 specification. This is shown in Figure 31.

D- Out

TPS2547

VBUS

2.0 V

D-

CDP

Detect Detect

Auto

1.2 V

2.7 V

D+

GND

D+ Out

Figure 31. DCP 1.2-V Charging Scheme

8.3.4 Wake on USB Feature (Mouse/Keyboard Wake Feature)

8.3.4.1 USB 2.0 Background Information

The TPS2547 data lines interface with USB 2.0 devices. USB 2.0 defines three types of devices according to

data rate. These devices and their characteristics relevant to TPS2547 Wake on USB operation are shown

below.

Low-speed USB devices:

•

1.5 Mbps

Wired mice and keyboards are examples

No devices that need battery charging

All signaling performed at 2 V and 0.8 V hi/lo logic levels

D– high to signal connect and when placed into suspend

D– high when not transmitting data packets

Full-speed USB devices:

•

12 Mbps

Wireless mice and keyboards are examples

Legacy phones and music players are examples

Some legacy devices that need battery charging

All signaling performed at 2 V and 0.8 V hi/lo logic levels

D+ high to signal connect and when placed into suspend

D+ high when not transmitting data packets

High-speed USB devices:

•

480 Mbps

Tablets, phones and music players are examples

Many devices that need battery charging

Connect and suspend signaling performed at 2 V and 0.8 V hi/lo logic levels

Data packet signaling performed a logic levels below 0.8 V

D+ high to signal connect and when placed into suspend (same as a full-speed device)

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Feature Description (continued)

•

D+ and D– low when not transmitting data packets

8.3.4.2 Wake On USB

Wake on USB is the ability of a wake configured USB device to wake a computer system from its S3 sleep state

back to its S0 working state. Wake on USB requires the data lines to be connected to the system USB host

before the system is placed into its S3 sleep state, and remain continuously connected until they are used to

wake the system.

The TPS2547 supports low-speed and high-speed HID (human interface device like mouse/key board) wake

function. There are two scenarios under which wake on mouse are supported by the TPS2547. The specific CTL

pin changes that the TPS2547 overrides are shown below. The information is presented as CTL1, CTL2, CTL3.

The ILIM_SEL pin plays no role.

1. 111 (CDP/SDP2) to 011 (DCP-Auto)

2. 010 (SDP1) to 011 (DCP-Auto)

NOTE

The 110 (SDP1) to 011 (DCP-Auto) transition is not supported. This is done for practical

reasons, because the transition involves changes to two CTL pins. Depending on which

CTL pin changes first, the device sees either a temporary 111 or 010 command. The 010

command is safe but the 111 command causes an OUT discharge as the TPS2547

instead proceeds to the 111 state.

8.3.4.3 USB Slow-Speed and Full-Speed Device Recognition

TPS2547 is capable of detecting LS or FS device attachment when TPS2547 is in SDP or CDP mode. Per USB

specification, when no device is attached, the D+ and D– lines are near ground level. When a low-speed

compliant device is attached to the TPS2547 charging port, D– line is pulled high in its idle state

(mouse/keyboard not activated). However, when a FS device is attached then the opposite is true in its idle state,

that is, D+ is pulled high and D– remains at ground level.

TPS2547 monitors both D+ and D– lines while CTL pin settings are in CDP or SDP mode to detect LS or FS HID

device attachment. To support HID sleep wake, TPS2547 must first determine that it is attached to a LS or FS

device when system is in S0 power state. TPS2547 does this as described above. While supporting a LS HID

wake is straight forward, supporting FS HID requires making a distinction between a FS and a HS device. This is

because a high-speed device always presents itself initially as a full speed device (by a 1.5-K pullup resistor on

D+). The negotiation for high speed then makes the distinction whereby the 1.5-K pullup resistor gets removed.

TPS2547 handles the distinction between a FS and HS device at connect by memorizing if the D+ line goes low

after connect. A HS device after connect always undergoes negotiation for HS, which requires the 1.5-kΩ resistor

pullup on D+ to be removed. To memorize a FS device, TPS2547 requires the device to remain connected for at

least 60 seconds while the system is in S0 mode, before placing it in sleep or S3 mode.

NOTE

If system is placed in sleep mode earlier than the 60 second window, a FS device may not

get recognized and hence could fail to wake system from S3. This requirement does not

apply for LS device.

8.3.4.3.1 No CTL Pin Timing Requirement After Wake Event and Transition from S3 to S0

Unlike the TPS2543, there is no CTL pin timing requirement for the TPS2547 when the wake configured USB

device wakes the system from S3 back to S0. The TPS2543 requires the CTL pins to transition from the DCP-

Auto setting back to the SDP/CDP setting within 64 ms of the attached USB device signaling a wake event (for

example, mouse clicked or keyboard key pressed). No such timing condition exists for the TPS2547.

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Feature Description (continued)

8.3.5 Load Detect

TPS2547 offers system designers unique power management strategy not available in the industry from similar

devices. There are two power management schemes supported by the TPS2547 through the STATUS pin, they

are:

•

Power Wake (PW)

Port Power Management (PPM)

Either feature may be implemented in a system depending on power savings goals for the system. In general,

Power Wake feature is used mainly in mobile systems, like a notebook, where it is imperative to save battery

power when system is in deep sleep (S4/S5) state. Oppositely, Port Power Management feature would be

implemented where multiple charging ports are supported in the same system, and system power rating is not

capable of supporting high-current charging on multiple ports simultaneously.

8.3.6 Power Wake

The goal of the power wake feature is to save system power when the system is in S4/S5 state. In the S4/S5

state, the system is in deep sleep and typically running off the battery; so every mW in system power savings

translates to extending battery life. In this state, the TPS2547 monitors charging current at the OUT pin and

provide a mechanism through the STATUS pin to switch out the high-power DC-DC controller and switch in a low

power LDO when charging current requirement is < 45 mA (typical). This would be the case when no peripheral

device is connected at the charging port or if a device has attained its full battery charge and draws <45 mA. A

power wake flow chart and description is shown in Figure 32.

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Feature Description (continued)

Load being Charged

ñ

TPS2547 is asserting power wake

System power is at its full capability

Load can charge at high current

TPS2547 monitors port to detect when charging load is

done charging or removed

Case 1

LOAD DETECTED

Charging Load Detected

ñ

TPS2547 is asserting power wake

Power Wake Asserted

/STATUS = 0

Current Limit = ILIM_HI setting

System power turns on to its full power state

Load Vbus is held low for 2 s to give the

power system time to turn on before the

load tries to pull charging current again

CHARGING

OUT DISCHARGE

OUT Discharge

Power Wake Asserted

/STATUS = 0

Current Limit = 55 mA

NOT

CHARGING

Charging

Current

Detected

Case 2A&2B

NO LOAD DETECTED

Load Current > 55 mA

Power Wake De-asserted

/STATUS = 1

Current Limit = 55 mA

Charging Load Not Detected.

ñ

TPS2547 is not asserting power wake. System power is in

a low power state to save energy.

ñ

TPS2547 monitors port to detect when charging load is

attached and tries to charge

Figure 32. Power Wake Flow Chart

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Feature Description (continued)

8.3.6.1 Implementing Power Wake in Notebook System

An implementation of power wake in notebook platforms with the TPS2547 is shown in Figure 33 to Figure 35.

Power wake function is used to select between a high-power DC-DC converter, and low-power LDO (100 mA)

based on charging requirements. System power saving is achieved when under no charging conditions (the

connected device is fully charged or no device is connected) the DC-DC converter is turned off (to save power

because it is less efficient in low-power operating region) and the low-power LDO supplies standby power to the

charging port.

Power wake is activated in S4/S5 mode (0011 setting, see Table 3), TPS2547 is charging connected device as

shown in Figure 33, STATUS is pulled LO (Case 1) which switches-out the LDO and switches-in the DC-DC

converter to handle high-current charging.

LDO Disconnected/Shut-Down

DC-DC Switched-In

POWER Block

19

V

EN

ilimit set by

Rlim_Hi

TPS2547

5 V_DC/DC

5V_LDO

IN

EN

ILIM_SEL

Connected

Embedded

Controller

LO

OUT

DM_IN

DP_IN

GND

VBUS

D-

D+

STATUS

Peripheral

Device

CHARGING

GND

Switches Power

between LDO and

DC/DC based on

/STATUS

DM

DM_OUT

DP_OUT

FAULT

DP

OC

USB

Receptacle

I/O_EN

EN

CTL1

CTL2

CTL3

I/O_Sx

4

USB Host

Controller

0011

Figure 33. Case 1: System in S4/S5, Device Charging

As shown in Figure 34 and Figure 35, when connected device is fully charged or gets disconnected from the

charging port, the charging current falls. If charging current falls to < 45 mA and stays below this threshold for

over 15 s, TPS2547 automatically sets a 55-mA internal current limit and STATUS is de-asserted (pulled HI). As

shown in Figure 34 and Figure 35. This results in DC-DC converter turning off, and the LDO turning on. Current

limit of 55 mA is set to prevent the low-power LDO output voltage from collapsing in case there is a spike in

current draw due to device attachment or other activity such as display panel LED turning ON in connected

device.

Following Power Wake flow chart (Figure 32) when a device is attached and draws > 55 mA of charging current

the TPS2547 hits its internal current limit. This triggers the device to assert STATUS (LO), and turn on the DC-

DC converter and turn off the LDO. TPS2547 discharges OUT for > 2 s (typical), allowing the main power supply

to turn on. After the discharge, the device turns back on with current limit set by ILIM_HI (Case 1).

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Feature Description (continued)

DC-DC Disconnected/Shut-Down

LDO Switched-In

Charging current falls to <45 mA and stays <45

mA for 15 sec, ilimit set to 55 mA

Turns HI after 15 s

POWER Block

19 V

Not

Connected

TPS2547

5V_DC/DC

EN

IN

5V_LDO

ILIM_SEL

Embedded

Controller

LO à HI

VBUS

D-

D+

OUT

DM_IN

DP_IN

GND

STATUS

Peripheral

Device

GND

Switches Power

between LDO and

DC/DC based on

/STATUS

DM

DM_OUT

DP_OUT

FAULT

EN

DP

OC

USB Receptacle

I/O_EN

CTL1

CTL2

CTL3

I/O_Sx

4

USB Host

Controller

0011

Figure 34. Case 2A: System in S4/S5, No Device Attached

DC-DC Disconnected/Shut-Down

LDO Switched-In

Turns HI after 15 s

Charging current falls to <45 mA and stays

<45 mA for 15 sec, ilimit set to 55 mA

POWER Block

19 V

TPS2547

IN

5V_DC/DC

EN

5V_LDO

EN

ILIM_SEL

Connected

OUT

DM_IN

DP_IN

GND

Embedded

Controller

VBUS

D-

D+

STATUS

Peripheral

Device is

CHARGED!

LOà

HI

GND

Switches Power

between LDO and

DC/DC based on

/STATUS

DM

DP

DM_OUT

DP_OUT

FAULT

USB

Receptacle

OC

I/O_EN

EN

CTL1

CTL2

CTL3

I/O_Sx

4

USB Host

Controller

0011

Figure 35. Case 2B: System in S4/S5, Attached Device Fully Charged

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www.ti.com.cn

Feature Description (continued)

8.3.7 Port Power Management (PPM)

PPM is the intelligent and dynamic allocation of power for systems that have multiple charging ports but cannot

power them all simultaneously. The goals of this feature are:

•

Enhance user experience because user does not have to search for charging port

Ensure the power supply only has to be designed for a reasonable charging load

Initially all ports are allowed to broadcast high-current charging, charging current limit is based on ILIM_HI

resistor setting. System monitors STATUS to see when high-current loads are present. Once allowed number of

ports assert STATUS, remaining ports are toggled to a non-charging port. Non-charging ports are SDP ports with

current limit based on ILIM_LO. TPS2547 allows for a system to toggle between charging and non-charging ports

either with an OUT discharge or without an OUT discharge.

8.3.7.1 Benefits of PPM

•

Delivers better user experience

Prevents overloading of system's power supply

Allows for dynamic power limits based on system state

Allows every port to potentially be a high-power charging port

Allows for smaller power supply capacity because the loading is controlled

8.3.7.2 PPM Details

All ports are allowed to broadcast high-current charging – CDP or DCP. Current limit is based on ILIM_HI and

system monitors STATUS pin to see when high-current loads are present. Once allowed number of ports assert

STATUS, remaining ports are toggled to a SDP non-charging port. SDP current limit is based on ILIM_LO

setting. SDP ports are automatically toggled back to CDP or DCP mode when a charging port de-asserts

STATUS.

Based on CTL settings there is a provision for a port to toggle between charging and non-charging ports either

with a Vbus discharge or without a Vbus discharge. For example when a port is in SDP2 mode (1110) and its

ILIM_SEL pin is toggled to 1 due to another port releasing its high-current requirements. The SDP2 port

automatically reverts to CDP mode (1111) without a discharge event. This is desirable if this port was connected

to a media device where it was syncing data from the SDP2 port; a discharge event would disrupt the syncing

activity on the port and cause user confusion.

STATUS trip point is based on the programmable ILIM_LO current limit set point. This does not mean STATUS

is a current limit – the port itself is using the ILIM_HI current limit. Since ILIM_LO defines the current limit for a

SDP port, it works well to use the ILIM_LO value to define a high-current load. STATUS asserts in CDP and

DCP when load current is above ILIM_LO+60 mA for 200 ms. STATUS also asserts in CDP when an attached

device does a BC1.2 primary detection. STATUS de-asserts in CDP and DCP when the load current is below

ILIM_LO+10 mA for 3 s.

8.3.7.3 Implementing PPM in a System with Two Charging Ports

Figure 36 shows implementation of two charging ports, each with its own TPS2547. In this example 5-V power

supply for the two charging ports is rated at < 3 A or < 15 W maximum. Both devices have R_LIMchosen to

correspond to the low (0.9 A) and high (1.5 A) current limit setting for the port. In this implementation the system

can support only one of the two ports at 1.5-A charging current while the other port is set to SDP mode and I_LIMIT

corresponding to 0.9 A.

24

TPS2547

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ZHCSGL1A –MAY 2017–REVISED MAY 2017

Feature Description (continued)

TPS2547 Port 1

IN

5V

EN_1

FAULT_1

OUT

DM_IN

DP_IN

EN

USB Charging

Port #1

FAULT

S0_S3

STATUS

ILIM_LO

ILIM_HI

CTL3

CTL2

CTL1

ILIM_SEL

GND

29.8 K

(1.5 A)

48.7 K

(0.9 A)

100 K

TPS2547 Port 2

IN

5 V

EN_2

OUT

EN

USB Charging

Port #2

FAULT_2

DM_IN

DP_IN

FAULT

STATUS

ILIM_LO

ILIM_HI

CTL3

CTL2

GND

29.8 K

(1.5 A)

48.7 K

(0.9 A)

CTL1

ILIM_SEL

100 K

Figure 36. Implementing Port Power Management in a System Supporting Two Charging Ports

8.3.8 Overcurrent Protection

When an overcurrent condition is detected, the device maintains a constant output current and reduces the

output voltage accordingly. Two possible overload conditions can occur. In the first condition, the output has

been shorted before the device is enabled or before VIN has been applied. The TPS2547 senses the short and

immediately switches into a constant-current output. In the second condition, a short or an overload occurs while

the device is enabled. At the instant the overload occurs, high currents may flow for nominally one to two

microseconds before the current-limit circuit can react. The device operates in constant-current mode after the

current-limit circuit has responded. Complete shutdown occurs only if the fault is present long enough to activate

thermal limiting. The device remains off until the junction temperature cools approximately 20°C and then re-

starts. The device continues to cycle on/off until the overcurrent condition is removed.

8.3.9 FAULT Response

The FAULT open-drain output is asserted (active low) during an overtemperature or current limit condition. The

output remains asserted until the fault condition is removed. The TPS2547 is designed to eliminate false FAULT

reporting by using an internal de-glitch circuit for current limit conditions without the need for external circuitry.

This ensures that FAULT is not accidentally asserted due to normal operation such as starting into a heavy

capacitive load. overtemperature conditions are not de-glitched and assert the FAULT signal immediately.

8.3.10 Undervoltage Lockout (UVLO)

The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO

turnon threshold. Built-in hysteresis prevents unwanted oscillations on the output due to input voltage drop from

large current surges.

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Feature Description (continued)

8.3.11 Thermal Sense

The TPS2547 protects itself with two independent thermal sensing circuits that monitor the operating temperature

of the power distribution switch and disables operation if the temperature exceeds recommended operating

conditions. The device operates in constant-current mode during an overcurrent condition, which increases the

voltage drop across power switch. The power dissipation in the package is proportional to the voltage drop

across the power switch, so the junction temperature rises during an overcurrent condition. The first thermal

sensor turns off the power switch when the die temperature exceeds 135°C and the part is in current limit. The

second thermal sensor turns off the power switch when the die temperature exceeds 155°C regardless of

whether the power switch is in current limit. Hysteresis is built into both thermal sensors, and the switch turns on

after the device has cooled by approximately 20°C. The switch continues to cycle off and on until the fault is

removed. The open-drain false reporting output FAULT is asserted (active low) during an overtemperature

shutdown condition.

8.4 Device Functional Modes

Table 1 shows the differences between these ports.

Table 1. Operating Modes

SUPPORT USB

2.0 COMMUNICATION

MAXIMUM ALLOWABLE CURRENT

DRAW BY PORTABLE DEVICE (A)

PORT TYPE

SDP (USB 2.0)

SDP (USB 3.0)

CDP

Yes

No

0.5

0.9

1.5

DCP

8.4.1 DCP Auto Mode

As mentioned above the TPS2547 integrates an auto-detect state machine that supports all the above DCP

charging schemes. It starts in Divider1 scheme, however if a BC1.2 or YD/T 1591-2009 compliant device is

attached, the TPS2547 responds by discharging OUT, turning back on the power switch and operating in 1.2 V

mode briefly and then moving to BC1.2 DCP mode. It then stays in that mode until the device releases the data

line, in which case it goes back to Divider1 scheme. When a Divider1 compliant device is attached the TPS2547

stays in Divider1 state.

Also, the TPS2547 automatically switches between the Divider1 and Divider2 schemes based on charging

current drawn by the connected device. Initially the device sets the data lines to Divider1 scheme. If charging

current of > 750 mA is measured by the TPS2547 it switches to Divider2 scheme and test to see if the peripheral

device still charges at a high current. If it does then it stays in Divider2 scheme otherwise it reverts to Divider1

scheme.

TPS2547

To USB 2.0 Host

BC1.2 CDP

D-

From Charging

Peripheral

BC1.2 DCP/

1.2V Mode

D+

Divider1/2

Controlled by CTL pins

settings

Figure 37. DCP Auto Mode

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TPS2547

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8.4.2 DCP Forced Shorted / DCP Forced Divider1

In this mode the device is permanently set to one of the DCP schemes (BC1.2/ YD/T 1591-2009 or Divider1) as

commanded by its control pin setting per Table 3.

8.4.3 High-Bandwidth Data Line Switch

The TPS2547 passes the D+ and D– data lines through the device to enable monitoring and handshaking while

supporting charging operation. A wide bandwidth signal switch is used, allowing data to pass through the device

without corrupting signal integrity. The data line switches are turned on in any of CDP or SDP operating modes.

The EN input also needs to be at logic High for the data line switches to be enabled.

NOTE

•

While in CDP mode, the data switches are ON even while CDP handshaking is

occurring

The data line switches are OFF if EN or all CTL pins are held low, or if in DCP mode.

They are not automatically turned off if the power switch (IN to OUT) is in current limit

The data switches are for USB 2.0 differential pair only. In the case of a USB 3.0 host,

the super speed differential pairs must be routed directly to the USB connector without

passing through the TPS2547

•

Data switches are OFF during OUT (VBUS) discharge

Table 2 can be used as an aid to program the TPS2547 per system states however not restricted to below

settings only.

Table 2. Control Pin Settings Matched to System Power States

SYSTEM

GLOBAL

POWER

STATE

CURRENT LIMIT

SETTING

TPS2547 CHARGING MODE

CTL1 CTL2 CTL3

ILIM_SEL

S0

SDP1

1

0

1

1 or 0

0

ILIM_HI / ILIM_LO

ILIM_LO

SDP2, no discharge to / from CDP

CDP, load detection with ILIM_LO + 60-mA thresholds or if a

BC1.2 primary detection occurs

S0

1

ILIM_HI

S4/S5

Auto mode, load detection with power wake thresholds

Auto mode, no load detection

0

1

0

ILIM_HI

S3/S4/S5

Auto mode, keyboard/mouse wake up, load detection with

ILIM_LO + 60 mA thresholds

S3

0

1

ILIM_HI

S3

Auto mode, keyboard/mouse wake-up, no load detection

SDP1, keyboard/mouse wake-up

0

1

0

ILIM_HI

1 or 0

ILIM_HI / ILIM_LO

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8.4.4 Device Truth Table (TT)

Device TT lists all valid bias combinations for the three control pins CTL1-3 and ILIM_SEL pin and their

corresponding charging mode. It is important to note that the TT purposely omits matching charging modes of the

TPS2547 with global power states (S0-S5) as device is agnostic to system power states. The TPS2547 monitors

CTL inputs and transitions to the charging state it is commanded to go to (except when LS/FS HID device is

detected). For example, if sleep charging is desired when system is in standby or hibernate state then the user

must set TPS2547 CTL pins to correspond to DCP_Auto charging mode as shown in the below table. When the

system resumes operation mode set the control pins to correspond to SDP or CDP mode, as seen in Table 3.

Table 3. Truth Table

CURRENT

LIMIT

SETTING

STATUS OUTPUT

(ACTIVE LOW)

CTL1 CTL2 CTL3 ILIM_SEL

MODE

COMMENT

0

1

0

1

0

Discharge

DCP_Auto

NA

OFF

OUT held low.

ILIM_HI

Data lines disconnected.

Data lines disconnected and load detect

function active.

0

1

DCP_Auto

I_{OS_PW}& ILIM_HI⁽¹⁾

DCP load present⁽²⁾

0

1

0

1

0

1

0

SDP1

ILIM_LO

ILIM_HI

OFF

Data lines connected.

DCP_Auto

Data lines disconnected.

Data lines disconnected and load detect

function active.

0

1

DCP_Auto

ILIM_HI

DCP load present⁽³⁾

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DCP _Shorted

DCP_Shorted

DCP / Divider1

SDP1

ILIM_LO

ILIM_HI

ILIM_LO

ILIM_HI

ILIM_LO

ILIM_HI

ILIM_LO

ILIM_HI

OFF

Device forced to stay in DCP BC1.2 charging

mode.

OFF

Device forced to stay in DCP divider1 charging

mode.

OFF

SDP1

SDP2⁽⁴⁾

CDP⁽⁴⁾

Data lines connected.

OFF

CDP load present⁽⁵⁾

Data lines connected and load detect active.

(1) TPS2547 : Current limit (I_OS) is automatically switched between I_{OS_PW}and the value set by ILIM_HI according to the Load Detect –

Power Wake functionality.

(2) DCP Load present governed by the Load Detection – Power Wake limits.

(3) DCP Load present governed by the Load Detection – Non Power Wake limits.

(4) No OUT discharge when changing between 1111 and 1110.

(5) CDP Load present governed by the Load Detection – Non Power Wake limits and BC1.2 primary detection.

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers must

validate and test their design implementation to confirm system functionality.

9.1 Application Information

Power-on-reset (POR) holds device in initial state while output is held in discharge mode. Any POR event returns

the device to initial state. After POR clears, device goes to the next state depending on the CTL lines as shown

in Figure 38.

weset

5/ꢀ_!uto

5/ꢀ_{IhwÇꢁ

5/ꢀ_5LëL59w

DCP Forced

(DCP Shorted or

Sample

CTL Pins

Divider 1)

5/Iꢁ{5ꢀꢁ/5ꢀ

5/I

5one

5/ꢀ_!uto

5/ꢀ_{IÇꢁ

5/ꢀ_5Lë

Discharge

5/Iꢁ{5ꢀꢁ/5ꢀ

{5ꢀ2

/5ꢀ

{5ꢀ1

DCP Auto

(Shorted/1.2V Pull-Up/

Divider 1/Divider 2)

(1110)

(1111)

(110óꢁ

010ó)

bot {5ꢀ1

SDP1

bot /5ꢀ

hr {5ꢀ2

CDP

/5ꢀ

(1111)

{5ꢀ2

(1110)

bot {5ꢀ2

hr /5ꢀ

SDP2

Figure 38. TPS2547 Charging States

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Application Information (continued)

9.1.1 Output Discharge

To allow a charging port to renegotiate current with a portable device, the TPS2547 device uses the OUT

discharge function. The device proceeds by turning off the power switch while discharging OUT. The device then

turns on the power switch again to reassert the OUT voltage. This discharge function is automatically applied, as

shown in Figure 26. There are two discharge times, t_{DCHG_L}and t_{DCHG_S}. t_{DCHG_L}is from SDP1/SDP2/CDP to

DCP_Auto, and t_{DCHG_S}is from DCP_Auto to SDP1/SDP2/CDP.

9.2 Typical Application

To Portable Device

à

0.1 uF

4.5V – 5.5V

Power Bus

IN

OUT

VBUS

D-

D+

TPS2547

C_USB

R_STATUS

(10 kW)

R_FAULT

(10 kW)

ILIM_LO

ILIM_HI

GND

STATUS

STATUS Signal

Fault Signal

R_{ILIM_HI}

R_{ILIM_LO}

GND

FAULT

USB

Connector

ILIM_SEL

ILIM Select

DM_IN

DP_IN

Power Switch EN

EN

CTL1

CTL2

CTL3

DM_OUT

DP_OUT

Mode Select I/O

To Host Controller

à

Figure 39. Typical Application Schematic USB Port Charging

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 4.

Table 4. Design Parameters

DESIGN PARAMETER

Input voltage, V_(IN)

EXAMPLE VALUE

5 V

Output voltage, V_(DC)

Maximum continuous output current, I_(OUT)

Current limit, I_{(LIM_LO)}at R_{ILIM_LO}= 80.6 kΩ

Current Limit, I_{(LIM_HI)}at R_{ILIM_HI}= 16.9 kΩ

2.5 A

0.625 A

2.97 A

9.2.2 Detailed Design Procedure

9.2.2.1 Current-Limit Settings

The TPS2547 has two independent current limit settings that are each programmed externally with a resistor.

The ILIM_HI setting is programmed with R_{ILIM_HI}connected between ILIM_HI and GND. The ILIM_LO setting is

programmed with R_{ILIM_LO}connected between ILIM_LO and GND. Consult the Device Truth Table (Table 3) to

see when each current limit is used. Both settings have the same relation between the current limit and the

programming resistor.

R_{ILIM_LO}is optional and the ILIM_LO pin may be left unconnected if the following conditions are met:

1. ILIM_SEL is always set high

2. Load Detection - Port Power Management is not used

Equation 1 programs the typical current limit:

51829

R_{LIM_XX}(kW) =

I_{OS_typ}(mA)

(1)

R_{ILIM_XX}corresponds to either R_{ILIM_HI}or R_{ILIM_LO}as appropriate.

30

TPS2547

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ZHCSGL1A –MAY 2017–REVISED MAY 2017

3500

3000

2500

2000

1500

1000

500

0

100

200

300

400

500

600

700

800

Current-Limit Programming Resistor (kW)

Full R_{ILIM_XX}Range

Figure 40. Typical Current Limit Setting vs Programming Resistor

Many applications require that the current limit meet specific tolerance limits. When designing to these tolerance

limits, both the tolerance of the TPS2547 current limit and the tolerance of the external programming resistor

must be taken into account. The following equations approximate the TPS2547 minimum and maximum current

limits to within a few mA, and are appropriate for design purposes. The equations do not constitute part of Texas

Instrument's published device specifications for purposes of Texas Instrument's product warranty. These

equations assume an ideal - no variation - external programming resistor. To take resistor tolerance into account,

first determine the minimum and maximum resistor values based on its tolerance specifications, and use these

values in the equations. Because of the inverse relation between the current limit and the programming resistor,

use the maximum resistor value in the Equation 2 and the minimum resistor value in the Equation 3.

52069

R_{LIM_XX}^(1.023)(kΩ)

I_{OS_min}(mA) =

(2)

52090

R_{LIM_XX}^(0.978)(kΩ)

I_{OS_max}(mA) =

(3)

3500

3000

2500

2000

1500

1000

500

600

500

400

300

200

100

0

Typ I_OS

Min I_OS

Max I_OS

Typ I_OS

Min I_OS

Max I_OS

0

10

20

30

40

50

60

70

80

90 100

100

200

300

400

500

600

700

Current-Limit Programming Resisitor (kW)

Current-Limit Programming Resistor (kW)

Figure 41. Current Limit Setting vs Programming

Resistor

Figure 42. Current Limit Setting vs Programming

Resistor

The traces routing the R_{ILIM_XX}resistors must be a sufficiently low resistance as to not affect the current-limit

accuracy. The ground connection for the R_{ILIM_XX}resistors is also very important. The resistors need to reference

back to the TPS2547 GND pin. Follow normal board layout practices to ensure that current flow from other parts

of the board does not impact the ground potential between the resistors and the TPS2547 GND pin.

31

TPS2547

ZHCSGL1A –MAY 2017–REVISED MAY 2017

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9.2.3 Application Curves

VBUS Current

5.00 ms/div

Figure 44. Low-Current Limit

Figure 43. High-Current Limit

USB 2.0

enumeration

Device

detects

connection

to CDP

Device detects

connection to a

charging port

D+

D–

VBUS

Device pulls correct

charging current

VBUS Current

D+ – 1.00 V/div

D– – 1.00 V/div

VBUS – 2.00 V/div

VBUS Current – 500 mA/div

Figure 45. Charging iPhone 5s with TPS2547

CDP (CTL1 = CTL2 = CTL3 = ILIM_SEL = 1)

10 Power Supply Recommendations

The TPS2547 device is designed for a supply-voltage range of 4.5 V ≤ VIN ≤ 5.5 V. If the input supply is located

more than a few inches from the device, an input ceramic bypass capacitor higher than 0.1 µF is recommended.

In order to avoid drops in voltage during overcurrent and short-circuit conditions, choose a power supply rated

higher than the TPS2547 current-limit setting.

11 Layout

11.1 Layout Guidelines

For the trace routing of DP_IN, DM_IN, DP_OUT, and DM_OUT: route these traces as micro-strips with nominal

differential impedance of 90 Ω. Minimize the use of vias in the high-speed data lines. Keep the reference GND

plane devoid from cuts or splits above the differential pairs to prevent impedance discontinuities. For more

information, see the High-Speed USB Platform Design Guidelines from Intel.

The trace routing from the upstream regulator to the TPS2547 IN pin must be as short as possible to reduce

voltage drop and parasitic inductance.

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Layout Guidelines (continued)

In order to meet IEC61000-4-2 level 4 ESD, external circuitry is required. Refer to the guidelines provided in the


型号：	TPS2547RTET
厂家：	TEXAS INSTRUMENTS
描述：	具有负载检测功能的 USB 充电端口控制器和 3A 电源开关 \| RTE \| 16 \| -40 to 115 开关控制器电源开关
文件：	总43页 (文件大小：2623K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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