TPS2549-Q1 [TI]
具有压降补偿功能的汽车类 USB 充电端口控制器;
| 型号： | TPS2549-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有压降补偿功能的汽车类 USB 充电端口控制器 控制器 |
| 文件： | 总46页 (文件大小：3005K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZHCSEA2C – OCTOBER 2015 – REVISED AUGUST 2020
TPS2549-Q1
TPS2546-Q1 具有电缆补偿功能的汽车类 USB 充电端口控制器和电源开关
充电电流过大也依然有效。这对于 USB 电缆较长的系
统而言至关重要，因为该系统在对便携式设备进行快速
充电的过程中会产生大幅压降。
1 特性
•
符合 AEC-Q100 标准，其中包括以下内容：
– 器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 H2
TP2549-Q1 47mΩ 电源开关具有两个可选的可编程电
流限值，可通过在相邻端口承载高负载时提供较低电流
限值来支持端口电源管理。这对于具有多个端口并且上
行电源无法同时为所有端口提供满载电流的系统而言至
关重要。
– 器件组件充电模式 (CDM) ESD 分类等级 C5
• 4.5V 至 6.5V 的工作范围
• 47mΩ（典型值）高侧 MOSFET
• 3.2A 最大连续输出电流
DCP_Auto 方案通过检测并选择合适的 D+ 和 D– 设
定与所连设备进行通信，以便在满载电流条件下完成快
速充电。集成的 CDP 检测支持针对多数采用同步数据
通 信 的 便 携 式 设 备 进 行 快 速 充 电 ， 充 电 电 流 高 达
1.5A。
•
•
用于电缆补偿的 ±5% 电流感测 (CS) 输出
充电下行端口 (CDP) 模式符合 USB 电池充电规范
1.2
•
自动专用充电端口 (DCP) 模式选择：
– 短路模式符合 BC1.2 和 YD/T 1591-2009
– 2.7V 分压器 3 模式
独特的客户端模式功能允许将软件更新为客户端设备，
同时在保持数据线连接的情况下通过关闭内部电源开关
来避免电源冲突。
– 1.2V 模式
•
面向系统更新的 D+ 和 D– 客户端模式
此外，TPS2549-Q1 器件集成了针对 D+ 和 D– 的
VBUS 短路保护功能，可避免在 D+ 和/或 D– 与 VBUS
之 间 意 外 短 路 时 造 成 损 坏 。 为 了 节 省 应 用 空 间 ，
TPS2549-Q1 器件还集成了 ESD 保护功能，无需在 D
+ 和 D–中应用外部电路即可符合 IEC61000-4-2 标
准。
• D+ 和 D– VBUS 短路保护
• D+ 和 D– ±8kV 接触放电和 ±15kV 空气放电 ESD
额定值 (IEC 61000-4-2)
•
运行结温范围：-40°C 至 125°C
• 16 引脚 3mm x 3mm 四方扁平无引线 (QFN) 封装
器件信息 (1)
2 应用
封装尺寸（标称值）
器件型号
封装
WQFN (16)
•
•
汽车类 USB 端口（USB 主机和集线器）
汽车娱乐信息系统
TPS2549-Q1
3.00mm × 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
3 说明
TPS2549-Q1 器件是一款具有电流感应输出（可控制
上行电源）的 USB 充电端口控制器和电源开关。该器
件可使 USB 端口电压维持在 5V 水平，即使
R(CABLE1)
4.5 V to 6.5 V
0.1 µF
V(BAT)
5 V
IN
OUT
TPS2549-Q1
Voltage
Regulator
R(STATUS)
C(OUT)
C(COMP)
R(FAULT)
R(FA)
LMR14030
LM53603-Q1
LM25117-Q1
TPS54340-Q1
DM_IN
DP_IN
R(CABLE2)
FAULT
FAULT
R(FB)
STATUS
GND
STATUS
CS
FB
ILIM_LO
ILIM_HI
EN
Power Switch EN
Mode Select I/O
R(G)
CTL1
R_HI
R_LO
DM_OUT
DP_OUT
To Host
Controller
GND
CTL2
CTL3
简化原理图
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSCE3
TPS2549-Q1
ZHCSEA2C – OCTOBER 2015 – REVISED AUGUST 2020
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes..........................................25
9 Application and Implementation..................................30
9.1 Application Information............................................. 30
9.2 Typical Application.................................................... 30
9.3 Application Curves....................................................34
10 Power Supply Recommendations..............................35
11 Layout...........................................................................35
11.1 Layout Guidelines................................................... 35
11.2 Layout Example...................................................... 36
12 Device and Documentation Support..........................37
12.1 Documentation Support.......................................... 37
12.2 Receiving Notification of Documentation Updates..37
12.3 Support Resources................................................. 37
12.4 Trademarks.............................................................37
12.5 Electrostatic Discharge Caution..............................37
12.6 Glossary..................................................................37
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................8
6.7 Typical Characteristics................................................9
7 Parameter Measurement Information..........................15
8 Detailed Description......................................................16
8.1 Overview...................................................................16
8.2 Functional Block Diagram.........................................17
8.3 Feature Description...................................................17
Information.................................................................... 37
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (July 2016) to Revision C (August 2020)
Page
•
更新了整个文档中的表格、图表和交叉参考的编号格式..................................................................................... 1
• Added Note (2) to Absolute Maximum Ratings table..........................................................................................4
• Added Footnote to Recommended Operating Conditions table......................................................................... 4
• Added paragraph to Typical Application section for clarification.......................................................................30
Changes from Revision A (October 2015) to Revision B (July 2016)
Page
•
将最大输出电流更改为 3.2A............................................................................................................................... 1
• Changed maximum output current in Recommended Operating Conditions .................................................... 4
• Changed minimum current-set resistance in Recommended Operating Conditions .........................................4
• Added a row to the CURRENT LIMIT section in Electrical Characteristics ....................................................... 5
• Added a row to the CABLE COMPENSATION section of Electircal Characteristics ......................................... 5
• Added Receiving Notification of Documentation Updates section....................................................................37
Changes from Revision * (October 2015) to Revision A (October 2015)
Page
•
将器件状态从“预量产”更改为“量产”...........................................................................................................1
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5 Pin Configuration and Functions
IN
DM_OUT
DP_OUT
CS
1
2
3
4
12
11
10
9
OUT
DM_IN
DP_IN
STATUS
Thermal
Pad
图 5-1. RTE Package 16-Pin WQFN Top View
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
Provide sink current proportional to output current. For cable compensation, connect to the
feedback divider of the up-stream voltage regulator.
CS
4
O
CTL1
6
7
I
Logic-level control inputs for controlling the charging mode and the signal switches; (see 表
CTL2
I
8-2). These pins tie directly to IN or GND without a pullup or pulldown resistor.
CTL3
8
I
DM_IN
DM_OUT
DP_IN
DP_OUT
11
2
I/O
I/O
I/O
I/O
D– data line to downstream connector
D– data line to upstream USB host controller
D+ data line to downstream connector
D+ data line to upstream USB host controller
10
3
Logic-level control input for turning the power switch and the signal switches on/off. When
EN is low, the device is disabled, the signal and power switches are OFF.
EN
5
I
Active-low open-drain output, asserted during overtemperature, overcurrent, and DP_IN and
DM_IN overvoltage conditions. See 表 8-1.
FAULT
13
O
GND
14
16
Ground connection; should be connected externally to the thermal pad.
Connect external resistor to ground to set the high current-limit threshold.
—
ILIM_HI
I
Connect external resistor to ground to set the low current-limit threshold and the load-
detection current threshold.
ILIM_LO
IN
15
1
I
Input supply voltage; connect a 0.1 µF or greater ceramic capacitor from IN to GND as close
to the IC as possible.
PWR
OUT
12
9
PWR
O
Power-switch output
STATUS
Active-low open-drain output, asserted when the load exceeds the load-detection threshold
Thermal pad on bottom of package. The thermal pad is internally connected to GND and is
used to heat-sink the device to the circuit board. Connect the thermal pad to the GND plane.
Thermal pad
—
—
(1) I = Input, O = Output, I/O = Input and output, PWR = Power
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6 Specifications
6.1 Absolute Maximum Ratings
Voltages are with respect to GND unless otherwise noted(1)
MIN
MAX
UNIT
Voltage range
CS, CTL1, CTL2, CTL3, EN, FAULT, ILIM_HI, ILIM_LO, IN,
7
V
–0.3
OUT, STATUS
DM_IN, DM_OUT, DP_IN, DP_OUT
IN to OUT
5.7(2)
7
V
V
–0.3
–7
Continuous current in SDP, CDP or
client mode
DP_IN to DP_OUT or DM_IN to DM_OUT
100
mA
–100
Continuous current in BC1.2 DCP
mode
DP_IN to DM_IN
35
mA
–35
Continuous output current
OUT
Internally limited
Internally limited
25
A
A
I(SRC)
I(SNK)
Continuous output source current
Continuous output sink current
ILIM_HI, ILIM_LO
FAULT, STATUS
CS
mA
A
Internally limited
TJ
Operating junction temperature
Storage temperature
Internally limited
150
°C
°C
–40
–65
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) If there is any risk for VBUS, DM_IN, DP_IN pins see voltage stresses beyond those listed under Absolute Maximum Ratings, for
example, shorting to Car battery, please check TPS25840-Q1 and TPS254900A-Q1 with higher absolute maximum ratings
6.2 ESD Ratings
VALUE
±2,000(2)
±750(3)
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
IEC61000-4-2 contact discharge, DP_IN and DM_IN
IEC61000-4-2 air di scharge, DP_IN and DM_IN
±8,000
IEC(4)
±15,000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) The passing level per AEC-Q100 Classification H2.
(3) The passing level per AEC-Q100 Classification C5
(4) Surges per IEC61000-4-2, 1999 applied between DP_IN/DM_IN and output ground of the TPS2549Q1EVM-729 (SLVUAK6)
evaluation module.
6.3 Recommended Operating Conditions
Voltages are with respect to GND unless otherwise noted.
MIN
4.5
0
NOM
MAX
6.5
UNIT
V
V(IN)
Supply voltage
Input voltage
IN
CTL1, CTL2, CTL3, EN
DM_IN, DM_OUT, DP_IN, DP_OUT
OUT (–40°C ≤ TA ≤ 85°C)
DP_IN to DP_OUT or DM_IN to DM_OUT
DP_IN to DM_IN
6.5
V
0
3.6
V
I(OUT)
Output continuous current
3.2(1)
30
A
Continuous current in SDP, CDP or client mode
Continuous current in BC1.2 DCP mode
Continuous output sink current
Current limit-set resistors
mA
mA
mA
kΩ
°C
–30
–15
15
FAULT, STATUS
10
R(ILIM_xx)
TJ
10.4
1000
125
Operating junction temperature
–40
(1) Operating at output continuous current greater than 3.2A is possible, however lifetime will be degraded.
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6.4 Thermal Information
TPS2549-Q1
THERMAL METRIC(1)
RTE (WQFN)
16 PINS
44.9
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
53.3
17.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1
ψJT
17.6
ψJB
RθJC(bot)
4.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
Unless otherwise noted, –40°C ≤ TJ ≤ 125°C and 4.5 V ≤ V(IN) ≤ 6.5 V, V(EN) = V(IN), V(CTL1) = V(CTL2) = V(CTL3) = V(IN)
.
R(FAULT) = R(STATUS) = 10 kΩ, R(ILIM_HI) = 19.1 kΩ, R(ILIM_LO) = 80.6 kΩ. Positive currents are into pins. Typical values are at
25°C. All voltages are with respect to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OUT – POWER SWITCH
rDS(on)
On-resistance(1)
TJ = 25°C
47
47
47
57
mΩ
72
80
–40°C ≤ TJ ≤ 85°C
–40°C ≤TJ ≤ 125°C
Ilkg(OUT)
Reverse leakage current on
OUT pin
2
µA
VOUT = 6.5 V, VIN = VEN = 0 V, –40°C ≤ TJ ≤
85°C, measure I(OUT)
OUT - DISCHARGE
R(DCHG)
OUT discharge resistance
400
500
630
Ω
EN, CTL1, CTL2, CTL3 INPUTS
Input pin rising logic
threshold voltage
1
1.35
1.15
200
2
V
V
Input pin falling logic
threshold voltage
0.85
1.65
Hysteresis(2)
mV
µA
Input current
Pin voltage = 0 V or 6.5 V
1
–1
CURRENT LIMIT
IOS
OUT short-circuit current
limit
205
600
255
660
305 mA
720
R(ILIM_LO) = 210 kΩ
R(ILIM_LO) = 80.6 kΩ
R(ILIM_LO) = 23.2 kΩ
R(ILIM_HI) = 20 kΩ
2145
2500
2620
3255
3411
3920
4830
5500
2300
2670
2800
3470
3637
4175
5145
7000
2455
2840
2975
R(ILIM_HI) = 19.1 kΩ
R(ILIM_HI) = 15.4 kΩ
R(ILIM_HI) = 14.7 kΩ
R(ILIM_HI) = 12.9 kΩ
R(ILIM_HI) = 10.4 kΩ
R(ILIM_HI) shorted to GND
3685
3862
4435
5460
8000
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Unless otherwise noted, –40°C ≤ TJ ≤ 125°C and 4.5 V ≤ V(IN) ≤ 6.5 V, V(EN) = V(IN), V(CTL1) = V(CTL2) = V(CTL3) = V(IN)
.
R(FAULT) = R(STATUS) = 10 kΩ, R(ILIM_HI) = 19.1 kΩ, R(ILIM_LO) = 80.6 kΩ. Positive currents are into pins. Typical values are at
25°C. All voltages are with respect to GND.
PARAMETER
SUPPLY CURRENT
I(IN_OFF)
I(IN_ON)
TEST CONDITIONS
MIN
TYP
MAX UNIT
Disabled IN supply current
Enabled IN supply current
0.1
220
226
150
115
5
300
300
220
190
µA
µA
V(EN) = 0 V, V(OUT) = 0 V, –40°C ≤ TJ ≤ 85°C
V(CTL)1 = V(CTL2) = V(CTL3) = V(IN)
V(CTL1) = V(CTL2) = 0 V, V(CTL3) = V(IN)
V(CTL2) = V(IN), V(CTL1) = V(CTL3) = 0 V
V(CTL1) = V(IN), V(CTL2) = V(CTL3) = 0 V
UNDERVOLTAGE LOCKOUT, IN
V(UVLO)
IN rising UVLO threshold
3.9
4.1
4.3
V
voltage
Hysteresis(3)
TJ = 25°C
100
mV
FAULT
Output low voltage
Off-state leakage
I(FAULT) = 1 mA
V(FAULT) = 6.5 V
100 mV
µA
2
STATUS
Output low voltage
Off-state leakage
I(STATUS) = 1 mA
V(STATUS) = 6.5 V
100 mV
2
µA
THERMAL SHUTDOWN
T(OTSD2) Thermal shutdown threshold
T(OTSD1)
155
135
°C
°C
Thermal shutdown threshold
in current-limit
Hysteresis(3)
20
°C
LOAD DETECT (VCTL1 = VCTL2 = VCTL3 = VIN)
I(LD)
IOUT load detection threshold
Hysteresis(3)
630
700
50
770 mA
mA
R(ILIM_LO) = 80.6 kΩ, rising load current
DP_IN AND DM_IN SHORT-TO-VBUS PROTECTION
V(OV)
Overvoltage protection trip
threshold
DP_IN and DM_IN rising
3.7
3.9
4.15
240
V
Hysteresis(3)
100
210
mV
R(DCHG_Data)
Discharge resistance after
OVP
V(DP_IN) = V(DM_IN) = 5 V
160
kΩ
CABLE COMPENSATION
I(CS) Sink current
228
214
171
149
70
240
225
180
158
75
252
236
189
166
80
µA
Load = 3.2 A, 2.5 V ≤ V(CS) ≤ 6.5 V
Load = 3 A, 2.5 V ≤ V(CS) ≤ 6.5 V
Load = 2.4 A, 2.5 V ≤ V(CS) ≤ 6.5 V
Load = 2.1 A, 2.5 V ≤ V(CS) ≤ 6.5 V
Load = 1 A, 2.5 V ≤ V(CS) ≤ 6.5 V
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Unless otherwise noted, –40°C ≤ TJ ≤ 125°C and 4.5 V ≤ V(IN) ≤ 6.5 V, V(EN) = V(IN), V(CTL1) = V(CTL2) = V(CTL3) = V(IN)
.
R(FAULT) = R(STATUS) = 10 kΩ, R(ILIM_HI) = 19.1 kΩ, R(ILIM_LO) = 80.6 kΩ. Positive currents are into pins. Typical values are at
25°C. All voltages are with respect to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
HIGH-BANDWIDTH ANALOG SWITCH
R(HS_ON)
DP and DM switch on-
resistance
V(DP_OUT) = V(DM_OUT) = 0 V, I(DP_IN) = I(DM_IN) = 30
mA
2
2.9
4
6
Ω
Ω
V(DP_OUT) = V(DM_OUT) = 2.4 V, I(DP_IN) = I(DM_IN)
=
–15 mA
Switch resistance mismatch V(DP_OUT) = V(DM_OUT) = 0 V, I(DP_IN) = I(DM_IN) = 30
between DP and DM
channels
0.05
0.05
6.7
0.15
0.15
|ΔR(HS_ON)
|
mA
V(DP_OUT) = V(DM_OUT) = 2.4 V, I(DP_IN) = I(DM_IN)
=
–15 mA
C(IO_OFF)
C(IO_ON)
DP/DM switch off-state
capacitance(4)
VEN = 0 V, V(DP_IN) = V(DM_IN) = 0.3 V,
Vac = 0.03 VPP , f = 1 MHz
pF
pF
DP/DM switch on-state
capacitance(4)
V(DP_IN) = V(DM_IN) = 0.3 V,
Vac = 0.03 VPP, f = 1 MHz
10
Off-state isolation(4)
VEN = 0 V, f = 250 MHz
f = 250 MHz
27
23
dB
dB
On-state cross-channel
isolation(4)
Ilkg(OFF)
BW
Off-state leakage current,
DP_OUT and DM_OUT
VEN = 0 V, V(DP_IN) = V(DM_IN) = 3.6 V, V(DP_OUT)
V(DM_OUT) = 0 V
=
0.1
1.5
µA
Bandwidth (–3 dB)(4)
R(L) = 50 Ω
925
MHz
CHARGING DOWNSTREAM PORT DETECT
V(DM_SRC)
V(DAT_REF)
DM_IN CDP output voltage
0.5
0.6
50
0.7
0.4
V
V
V(DP_IN) = 0.6 V, –250 µA < I(DM_IN) < 0 µA
DP_IN rising lower window
threshold for VDM_SRC
activation
0.36
Hysteresis(4)
mV
V
V(LGC_SRC)
DP_IN rising upper window
threshold for VDM_SRC de-
activation
0.8
40
0.88
V(LGC_SRC_HYS)
I(DP_SINK)
Hysteresis(4)
100
75
mV
µA
DP_IN sink current
V(DP_IN) = 0.6 V
100
200
BC1.2 DCP MODE
R(DPM_SHORT)
DP_IN and DM_IN shorting
resistance
125
Ω
DIVIDER3 MODE
V(DP_DIV3)
DP_IN output voltage
DM_IN output voltage
DP_IN output impedance
DM_IN output impedance
2.57
2.57
24
2.7
2.7
30
2.84
2.84
36
V
V
V(DM_DIV3)
R(DP_DIV3)
I(DP_IN) = –5 µA
I(DM_IN) = –5 µA
kΩ
kΩ
R(DM_DIV3)
1.2-V MODE
V(DP_1.2V)
24
30
36
DP_IN output voltage
DM_IN output voltage
DP_IN output impedance
DM_IN output impedance
1.12
1.12
84
1.2
1.2
1.26
1.26
126
126
V
V
V(DM_1.2V)
R(DP_1.2V)
100
100
I(DP_IN) = –5 µA
I(DM_IN = –5 µA
kΩ
R(DM_1.2V)
84
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account
separately.
(2) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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(3) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
(4) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
6.6 Switching Characteristics
Unless otherwise noted –40°C ≤ TJ ≤ 125°C and 4.5 V ≤ V(IN) ≤ 6.5 V, V(EN) = V(IN), V(CTL1) = V(CTL2) = V(CTL3) = V(IN)
.
R(FAULT) = R(STATUS) = 10 kΩ, R(ILIM_HI) = 19.1 kΩ, R(ILIM_LO) = 80.6 kΩ. Positive current is into pins. Typical value is at 25°C.
All voltages are with respect to GND.
PARAMETER
TEST CONDITIONS
MIN
0.7
TYP
1.14
0.35
4.15
1.8
MAX UNIT
tr
OUT voltage rise time
OUT voltage fall time
OUT voltage turnon time
OUT voltage turnoff time
2
0.6
6
ms
ms
ms
ms
s
V(IN) = 5 V, C(L) = 1 µF, R(L) = 100 Ω (see 图 7-1
and 图 7-2)
tf
0.2
ton
V(IN) = 5 V, C(L) = 1 µF, R(L) = 100 Ω (see 图 7-1
and 图 7-4)
toff
3
t(DCHG_L)
Long OUT discharge hold
time (SDP, CDP, or client
mode to DCP_Auto)
1.1
2
2.9
Time V(OUT) < 0.7 V (see 图 7-3)
t(DCHG_S)
Short OUT discharge hold
time (DCP_Auto to SDP,
CDP, or client mode)
186
320
450
ms
Time V(OUT) < 0.7 V (see 图 7-3)
t(IOS)
OUT short-circuit response
time(1)
2
8
µs
ms
ns
V(IN) = 5 V, R(SHORT) = 50 mΩ (see 图 6-25)
t(OC_OUT_FAULT)
OUT FAULT deglitch time
Bidirectional deglitch applicable to current limit
condition only (no deglitch assertion for OTSD)
5.5
11.5
tpd
Analog switch propagation
delay (1)
V(IN) = 5 V
0.14
0.02
t(SK)
Analog switch skew
V(IN) = 5 V
ns
between opposite transitions
of the same port (tPHL
–
(1)
tPLH
)
t(LD_SET)
t(LD_RESET)
t(OV_D)
Load-detect set time
120
1.8
210
3
280
4.2
ms
s
V(IN) = 5 V (See 图 6-27)
V(IN) = 5 V (See 图 6-28)
V(OUT) = 5 V (See 图 6-29)
Load-detect reset time
DP_IN and DM_IN over-
voltage protection response
time
2
µs
t(OV_D_FAULT)
DP_IN and DM_IN FAULT
degltich time
11
16
23
ms
V(OUT) = 5 V (See 图 6-30)
(1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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6.7 Typical Characteristics
70
65
60
55
50
45
40
35
30
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (ºC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (ºC)
D002
D001
VIN = 5 V
VIN = 5 V
图 6-2. Reverse Leakage Current vs Temperature
图 6-1. Power Switch On-Resistance vs
Temperature
550
4000
3500
3000
V(IN) = 4.5 V
V(IN) = 5 V
V(IN) = 6.5 V
540
530
520
510
500
490
480
470
2500
R(ILIM_LO) = 210 kW
2000
R(ILIM_LO) = 80.6 kW
R(ILIM_HI) = 20 kW
1500
R(ILIM_HI) = 19.1 kW
R(ILIM_HI) = 15.4 kW
1000
500
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (ºC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (ºC)
D004
D003
VIN = 5 V
A
图 6-4. OUT Short-Circuit Current Limit vs
图 6-3. OUT Discharge Resistance vs Temperature
Temperature
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14
280
260
240
220
200
180
V(IN) = 4.5 V
V(IN) = 5 V
V(IN) = 6.5 V
V(IN) = 4.5 V
V(IN) = 5 V
V(IN) = 6.5 V
12
10
8
6
4
2
0
-2
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (ºC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (ºC)
D006
D005
CTL1 = 1
CTL2 = 1
CTL3 = 1
CTL1 = 1
CTL2 = 1
CTL3 = 1
图 6-6. Enabled IN Supply Current – CDP (111) vs
图 6-5. Disabled IN Supply Current vs Temperature
Temperature
290
220
V(IN) = 4.5 V
V(IN) = 5 V
V(IN) = 6.5 V
V(IN) = 4.5 V
V(IN) = 5 V
V(IN) = 6.5 V
270
200
250
230
210
190
180
160
140
120
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (ºC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (ºC)
D007
D008
CTL1 = 0
CTL2 = 0
CTL3 = 1
CTL1 = 0
CTL2 = 1
CTL3 = 0
图 6-7. Enabled IN Supply Current – DCP_Auto
图 6-8. Enabled IN Supply Current – SDP (010) vs
(001) vs Temperature
Temperature
180
720
710
700
690
680
670
660
V(IN) = 4.5 V
V(IN) = 5 V
V(IN) = 6.5 V
160
140
120
100
80
650
640
I(LD), OUT Rising Load-Detect Threshold
IOS, OUT Short-Circuit Current
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (ºC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (ºC)
D009
D010
CTL1 = 1
CTL2 = 0
CTL3 = 0
R(ILIM_LO) = 80.6 kΩ
图 6-9. Enabled IN Supply Current – Client Mode
图 6-10. IOUT Rising Load-Detect Threshold and
(100) vs Temperature
OUT Short-Circuit Current Limit vs Temperature
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4.2
4.2
4.1
4
4.1
4
3.9
3.8
3.7
3.6
3.9
3.8
3.7
3.6
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (ºC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (ºC)
D012
D011
VIN = 5 V
VIN = 5 V
图 6-12. DM_IN Overvoltage Protection Threshold
图 6-11. DP_IN Overvoltage Protection Threshold
vs Temperature
vs Temperature
250
200
150
100
50
250
200
150
100
50
I(OUT) = 1 A
I(OUT) = 2.1 A
I(OUT) = 2.4 A
I(OUT) = 3 A
I(OUT) = 1 A
I(OUT) = 2.1 A
I(OUT) = 2.4 A
I(OUT) = 3 A
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (ºC)
2.5
3
3.5
4
4.5
CS Voltage (V)
5
5.5
6
6.5
D013
D014
VIN = 5 V
VCS = 2. 5 V
VIN = 6.5 V
图 6-13. ICS vs Temperature
图 6-14. ICS vs VCS Voltage
图 6-16. Off-State Data-Switch Isolation vs
图 6-15. Data Transmission Characteristics vs
Frequency
Frequency
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图 6-17. On-State Cross-Channel Isolation vs Frequency
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Forcing a page break between ImageMatrices
图 6-18. Eye Diagram Using USB Compliance Test 图 6-19. Eye Diagram Using USB Compliance Test
Pattern, Bypassing the TPS2549-Q1 Data Switch
Pattern, Through the TPS2549-Q1 Data Switch
V(EN)
V(EN)
5 V/div
5 V/div
V(OUT)
V(OUT)
2.5 V/div
2.5 V/div
I(IN)
I(IN)
0.5 A/div
0.5 A/div
C(LOAD) = 150 µF
t = 1 ms/div
C(LOAD) = 150 µF
t = 1 ms/div
R(LOAD) = 5 Ω
R(LOAD) = 5 Ω
图 6-20. Turnon Response
图 6-21. Turnoff Response
V(EN)
V(EN)
5 V/div
5 V/div
V(FAULT)
5 V/div
V(FAULT)
5 V/div
I(IN)
I(IN)
0.5 A/div
1 A/div
t = 2 ms/div
t = 4 ms/div
R(ILIM_HI) = 80.6 kΩ
R(ILIM_HI) = 19.1 kΩ
图 6-22. Enable Into Short
图 6-23. Enable Into Short – Thermal Cycling
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V(FAULT)
5 V/div
V(OUT)
2.5 V/div
V(OUT)
2.5 V/div
I(IN)
I(OUT)
2 A/div
10 A/div
t = 1 µs/div
t = 4 ms/div
R(SHORT) = 50 mΩ
R(ILIM_HI) = 19.1 kΩ
图 6-25. Hot-Short Response Time
图 6-24. Short-Circuit to Full-Load Recovery
V(EN)
V(OUT)
2.5 V/div
2.5 V/div
V(STATUS)
5 V/div
I(OUT)
I(OUT)
0.5 A/div
2 A/div
t = 100 ms/div
t = 1 ms/div
R(ILIM_LO) = 80.6 kΩ
R(ILIM_HI) = 19.1 kΩ R(SHORT) = 50 mΩ
图 6-27. Load-Detection Set Time
图 6-26. Hot Short
V(STATUS)
5 V/div
V(DM_IN)
V(OUT)
2.5 V/div
2.5 V/div
V(DM_OUT)
2.5 V/div
I(OUT)
0.5 A/div
t = 1 s/div
R(ILIM_LO) = 80.6 kΩ
t = 1 µs/div
R(DM_OUT) = 15 kΩ
图 6-28. Load Detection Reset Time
图 6-29. DM_IN Short to VBUS Response Time
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V(FAULT)
5 V/div
V(FAULT)
5 V/div
V(DM_IN)
2.5 V/div
V(DM_IN)
2.5 V/div
V(DM_OUT)
2.5 V/div
V(DM_OUT)
2.5 V/div
t = 1 µs/div
t = 4 ms/div
R(DM_OUT) = 15 kΩ
R(DM_OUT) = 15 kΩ
图 6-31. DM_IN Short-to-VBUS Recovery
图 6-30. DM_IN Short to VBUS
7 Parameter Measurement Information
OUT
90%
R(L)
tr
C(L)
tf
V(OUT)
10%
图 7-1. OUT Rise-Fall Test Load Figure
图 7-2. Power-On and -Off Timing
V(EN)
50%
50%
5 V
ton
toff
t(DCHG)
V(OUT)
90%
V(OUT)
0 V
10%
图 7-3. OUT Discharge During Mode Change
图 7-4. Enable Timing, Active-High Enable
IOS
I(OUT)
t(IOS)
图 7-5. Output Short-Circuit Parameters
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8 Detailed Description
8.1 Overview
The TPS2549-Q1 device is a USB charging controller and power switch which integrates D+ and D– short to
VBUS protection, cable compensation and IEC ESD protection, and is suitable for automotive USB charging and
USB port-protection applications.
The TPS2549-Q1 device integrates a current-limited, power-distribution switch using N-channel MOSFETs for
applications where short circuits or heavy capacitive loads can be encountered. The device allows the user to
program the current-limit threshold via an external resistor. The device enters constant-current mode when the
load exceeds the current limit threshold.
The TPS2549-Q1 device also integrates CDP mode, defined in the BC1.2 specification, to enable up to 1.5-A
fast charging of most of portable devices, meanwhile supporting data communication. In addition, the device
integrates the DCP-auto feature to enable fast-charging of most portable devices including pads, tablets, and
smart phones.
The TPS2549-Q1 device integrates a cable compensation (CS) feature to compensate the voltage drop in long
cables and keep the remote USB port output voltage constant.
Additionally, the device integrates an IEC ESD cell to provide ESD protection up to ±8 kV (contact discharge)
and ±15 kV (air discharge) per IEC 61000-4-2 on DP_IN and DM_IN, and integrates short-to-VBUS overvoltage
protection on DP_IN and DM_IN to protect the upstream USB transceiver.
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8.2 Functional Block Diagram
Current
Sense
CS
OUT
IN
Disable + UVLO
+ Discharge
ILIM_HI
ILIM_LO
EN
Current
Limit
Charge
Pump
8-ms
Deglitch
GND
OC
Driver
FAULT
UVLO
Thermal
Sense
I(CS) = I(OUT) × 75 µA/A
CS
16-ms
Deglitch
OTSD
OVP2
OVP1
DM_OUT
DP_OUT
DM_IN
DP_IN
CDP
Detection
CTL1
CTL2
DCP
(Auto-Detection)
STATUS
Logic
Control
CTL3
Discharge
8.3 Feature Description
8.3.1 FAULT Response
The device features an active-low, open-drain fault output. FAULT goes low when there is a fault condition. Fault
detection includes overtemperature, overcurrent, or DP_IN, DM_IN overvoltage. Connect a 10-kΩ pullup resistor
from FAULT to IN.
表 8-1 summarizes the conditions that generate a fault and actions taken by the device.
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表 8-1. Fault Conditions
EVENT
CONDITION
ACTION
Overcurrent on V(OUT)
I(OUT) > IOS
The device regulates switch current at IOS
until thermal cycling occurs. The fault
indicator asserts and de-asserts with an 8-ms
deglitch (The device does not assert FAULT
on overcurrent in SDP1 and DCP1 modes).
Overvoltage on the data lines
Overtemperature
DP_IN or DM_IN > 3.9 V
The device immediately shuts off the USB
data switches. The fault indicator asserts with
a 16-ms deglitch, and de-asserts without
deglitch.
TJ > OTSD2 in non-current-limited or TJ >
OTSD1 in current-limited mode.
The device immediately shuts off the internal
power switch and the USB data switches.
The fault indicator asserts immediately when
the junction temperature exceeds OTSD2 or
OTSD1 while in a current-limiting condition.
The device has a thermal hysteresis of 20°C.
8.3.2 Cable Compensation
When a load draws current through a long or thin wire, there is an IR drop that reduces the voltage delivered to
the load. In the vehicle from the voltage regulator 5-V output to the VPD_IN (input voltage of portable device),
the total resistance of power switch rDS(on) and cable resistance causes an IR drop at the PD input.. So the
charging current of most portable devices is less than their expected maximum charging current.
V(OUT) With Compensation
5.x
VBUS With Compensation
V(DROP)
VBUS Without Compensation
0
I(OUT) (A)
0.5
1
1.5
2
2.5
3
图 8-1. Voltage Drop
TPS2549-Q1 device detects the load current and generates a proportional sink current that can be used to
adjust output voltage of the upstream regulator to compensate the IR drop in the charging path. The gain G(CS)
of the sink current proportional to load current is 75 µA/A.
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rDS(on)
V(OUT)
To Regulator OUT
C(COMP)
To Load
VBUS
IN
OUT
R1
R2
R(WIRE)
R(LOAD)
R(FA)
C(OUT)
R(FB)
FB
To Regulator
Resistor Divider
CS
R(G)
图 8-2. Cable Compensation Equivalent Circuit
8.3.2.1 Design Procedure
To start the procedure, the total resistance, including power switch rDS(on) and wire resistance R(WIRE), must to be
known.
1. Choose R(G) following the voltage-regulator feedback resistor-divider design guideline.
2. Calculate R(FA) according to 方程式 1.
RFA = (rDS(on) + R(WIRE) ) / G(CS)
(1)
3. Calculate R(FB) according to Equation 2.
V
(OUT)
R(FB)
=
- R(G) - R(FA)
V
/ R(G)
(FB)
(2)
4. C(COMP) in parallel with R(FA) is needed to stablilize V(OUT) when C(OUT) is large. Start with C(COMP) ≥ 3 ×
G(CS) × C(OUT), then adjust C(COMP) to optimize the load transient of the voltage regulator output. V(OUT)
stability should always be verified in the end application circuit.
8.3.3 D+ and D– Protection
D+ and D– protection consists of ESD and OVP (overvoltage protection). The DP_IN and DM_IN pins integrate
an IEC ESD cell to provide ESD protection up to ±15 kV air discharge and ±8 kV contact discharge per IEC
61000-4-2 (See the ESD Ratings section for test conditions). Overvoltage protection (OVP) is provided for short-
to-VBUS conditions in the vehicle harness to prevent damaging the upstream USB transceiver. Short-to-GND
protection for D+ and D– is provided by the upstream USB transceiver.
The ESD stress seen at DP_IN and DM_IN is impacted by many external factors like the parasitic resistance and
inductance between ESD test points and the DP_IN and DM_IN pins. For air discharge, the temperature and
humidity of the environment can cause some difference, so the IEC performance should always be verified in the
end-application circuit.
8.3.4 Output and D+ or D– Discharge
To allow a charging port to renegotiate current with a portable device, the TPS2549-Q1 device uses the OUT
discharge function. This function turns off the power switch while discharging OUT with a 500-Ω resistance, then
turns the power switches to back on reassert the OUT voltage.
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For DP_IN and DM_IN, when OVP is triggered, the device turns on an internal discharge path with 210-Ω
resistance. On removal of OVP, this path can discharge the remnant charges to automatically turn on analog
switch and turn off this discharge path, thus back into normal mode.
8.3.5 Port Power Management (PPM)
PPM is the intelligent and dynamic allocation of power. PPM is for systems that have multiple charging ports but
cannot power them all simultaneously.
8.3.5.1 Benefits of PPM
The benefits of PPM include the following:
• Delivers better user experience
• Prevents overloading of system power supply
• Allows for dynamic power limits based on system state
• Allows every port to potentially be a high-power charging port
• Allows for smaller power-supply capacity because loading is controlled
8.3.5.2 PPM Details
All ports are allowed to broadcast high-current charging. The current-limit is based on ILIM_HI. The system
monitors the STATUS pin to see when high-current loads are present. Once the allowed number of ports asserts
STATUS, the remaining ports are toggled to a non-charging port. The non-charging port current-limit is based on
the ILIM_LO setting. The non-charging ports are automatically toggled back to charging ports when a charging
port de-asserts STATUS.
STATUS asserts in a charging port when the load current is above ILIM_LO + 40 mA for 210 ms (typical).
STATUS de-asserts in a charging-port when the load current is below ILIM_LO – 10 mA for 3 seconds (typical).
8.3.5.3 Implementing PPM in a System With Two Charging Ports (CDP and SDP1)
图 8-3 shows the implementation of the two charging ports with data communication, each with a TPS2549-Q1
device and configured in CDP mode. In this example, the 5-V power supply for the two charging ports is rated at
less than 3.5 A. Both TPS2549-Q1 devices have ILIM_LO of 1 A and ILIM_HI of 2.4 A. In this implementation,
the system can support only one of the two ports at 2.4-A charging current, whereas the other port is set to
SDP1 mode and I(LIMIT) corresponds to 1 A. In SDP1 mode, FAULT does not assert for overcurrent.
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TPS2549 -Q1 Port 1
USB Charging
Port 1
5 V
IN
OUT
EN1
EN
DM_IN
DP_IN
FAULT1
FAULT
STATUS
ILIM _LO
ILIM_HI
CTL1
CTL2
R_HI
R_LO
GND
100 kW
CTL3
TPS2549 -Q1 Port 2
USB Charging
Port 2
IN
OUT
DM_IN
DP_IN
EN2
EN
FAULT2
FAULT
STATUS
ILIM _LO
ILIM_HI
CTL1
CTL2
R_HI
R_LO
GND
100 kW
CTL3
图 8-3. PPM With CDP and SDP1
8.3.5.4 Implementing PPM in a System With Two Charging Ports (DCP and DCP1)
图 8-4 shows the implementation of the two charging-only ports, each with a TPS2549-Q1 device and configured
in DCP mode. In this example, the 5-V power supply for the two charging ports is rated at less than 3.5 A. Both
TPS2549-Q1 devices have ILIM_LO of 1 A and ILIM_HI of 2.4 A. In this implementation, the system can support
only one of the two ports at 2.4-A charging current, whereas the other port is set to DCP1 mode and I(LIMIT)
corresponds to 1 A. In DCP1 mode, FAULT does not assert for overcurrent.
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TPS2549 -Q1 Port 1
USB Charging
Port 1
5 V
IN
OUT
EN1
EN
DM_IN
DP_IN
FAULT1
FAULT
STATUS
ILIM _LO
ILIM_HI
CTL1
CTL2
R_HI
R_LO
GND
100 kW
CTL3
TPS2549 -Q1 Port 2
USB Charging
Port 2
IN
OUT
DM_IN
DP_IN
EN2
EN
FAULT2
FAULT
STATUS
ILIM _LO
ILIM_HI
CTL1
CTL2
R_HI
R_LO
GND
100 kW
CTL3
图 8-4. PPM With DCP and DCP1
8.3.6 CDP and SDP Auto Switch
The TPS2549-Q1 device is equipped with a CDP and SDP auto-switch feature to support some popular phones
in the market. These popular phones do not comply with the BC1.2 specification because they fail to establish a
data connection in CDP mode. These phones use primary detection (used to distinguish between an SDP and
different types of charging ports) to only identify ports as SDP (data, no charge) or DCP (no data, charge). These
phones do not recognize CDP (data, charge) ports. When connected to a CDP port, these phones classify the
port as a DCP and only charge the battery. Because the charging ports are configured as CDP, users do not
receive the expected data connection.
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Device never signals
connection and enumerates.
Data connection is lost.
Primary Detection
D+
D–
VBUS
VBUS Current
图 8-5. CDP and SDP Auto-Switch
To remedy this problem, the TPS2549-Q1 device employs a CDP and SDP auto-switch scheme to ensure these
BC1.2 noncompliant phones establish data connection using the following steps.
1. The TPS2549-Q1 device determines when a noncompliant phone has wrongly classified a CDP port as a
DCP port and has not made a data connection.
2. The TPS2549-Q1 device automatically completes an OUT (VBUS) discharge and reconfigures the port as an
SDP.
3. When reconfigured as an SDP, the phone detects a connection to an SDP and establishes a data connection.
4. The TPS2549-Q1 device then switches automatically back to a CDP without doing an OUT (VBUS) discharge.
5. The phone continues to operate as if connected to an SDP because OUT (VBUS) was not interrupted. The
port is now ready in CDP if a new device is attached.
8.3.7 Overcurrent Protection
When an overcurrent condition is detected, the device maintains a constant output current and reduces the
output voltage accordingly. Two possible overload conditions can occur. In the first condition, the output is
shorted before the device enables or before the application of V(IN). The TPS2549-Q1 device senses the short
and immediately switches into a constant-current output. In the second condition, a short or an overload occurs
while the device is enabled. At the instant the overload occurs, high currents flow for 2 μs (typical) before the
current-limit circuit reacts. The device operates in constant-current mode after the current-limit circuit has
responded. Complete shutdown occurs only if the fault is presented long enough to activate overtemperature
protection. The device remains off until the junction temperature cools to approximately 20°C and then restarts.
The device continues to cycle on and off until the overcurrent condition is removed.
8.3.8 Undervoltage Lockout
The undervoltage-lockout (UVLO) circuit disables the device until the input voltage reaches the UVLO turnon
threshold. Built-in hysteresis prevents unwanted oscillations on the output due to input voltage drop from large
current surges.
8.3.9 Thermal Sensing
Two independent thermal-sensing circuits protect the TPS2549-Q1 device if the temperature exceeds
recommended operating conditions. These circuits monitor the operating temperature of the power-distribution
switch and disable operation. The device operates in constant-current mode during an overcurrent condition,
which increases the voltage drop across power switch. The power dissipation in the package is proportional to
the voltage drop across the power switch, so the junction temperature rises during an overcurrent condition.
When the device is in a current-limiting condition, the first thermal sensor turns off the power switch when the die
temperature exceeds OTSD1. If the device is not in a current-limiting condition, the second thermal sensor turns
off the power switch when the die temperature exceeds OTSD2. Hysteresis is built into both thermal sensors,
and the switch turns on after the device has cooled by approximately 20°C. The switch continues to cycle off and
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then on until the fault is removed. The open-drain false-reporting output, FAULT, is asserted (low) during an
overtemperature shutdown condition.
8.3.10 Current Limit Setting
The TPS2549-Q1 has two independent current-limit settings that are each programmed externally with a resistor.
The ILIM_HI setting is programmed with R(ILIM_HI) connected between ILIM_HI and GND. The ILIM_LO setting is
programmed with R(ILIM_LO) connected between ILIM_LO and GND. Consult the device truth table (表 8-2) to see
when each current limit is used. Both settings have the same relation between the current limit and the
programming resistor.
R(ILIM_LO) is optional and the ILIM_LO pin may be left unconnected if the following conditions are met:
• The TPS2549-Q1 device is configured as DCP(001) or CDP(111).
• Load detection is not used.
The following equation calculates the value of resistor for programming the typical current limit:
53762 (V)
R(ILIM_ xx)1.0021 (kW)
I(OSnom) (mA) =
(3)
R(ILIM_xx) corresponds to either R(ILIM_HI) or R(ILIM_LO), as appropriate.
Many applications require that the current limit meet specific tolerance limits. When designing to these tolerance
limits, both the tolerance of the TPS2549-Q1 current limit and the tolerance of the external programming resistor
must be taken into account. The following equations approximate the TPS2549-Q1 minimum and maximum
current limits to within a few milliamperes and are appropriate for design purposes. The equations do not
constitute part of TI’s published device specifications for purposes of TI’s product warranty. These equations
assume an ideal—no variation—external programming resistor. To take resistor tolerance into account, first
determine the minimum and maximum resistor values based on its tolerance specifications and use these values
in the equations. Because of the inverse relation between the current limit and the programming resistor, use the
maximum resistor value in the I(OS_min) equation and the minimum resistor value in the I(OS_max) equation.
50409 (V)
R(ILIM_ xx)0.9982 (kW)
I(OSmin) (mA) =
- 35
+ 41
(4)
(5)
57813 (V)
R(ILIM_ xx)1.0107 (kW)
I(OSmax) (mA) =
4000
3500
3000
2500
2000
1500
1000
500
700
600
500
400
300
200
100
0
I(OSmin)
I(OStyp)
I(OSmax)
I(OSmin)
I(OStyp)
I(OSmax)
0
10
20
30
40
50
60
70
80
90
100
100 200 300 400 500 600 700 800 900 1000
Current Limit Resistor (kW)
Current Limit Resistor (kW)
D019
D020
图 8-6. Current Limit Setting vs Programming
图 8-7. Current Limit Setting vs Programming
Resistor I
Resistor II
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The routing of the traces to the R(ILIM_xx) resistors should have a sufficiently low resistance so as to not affect the
current-limit accuracy. The ground connection for the R(ILIM_xx) resistors is also very important. The resistors
must reference back to the TPS2549-Q1 GND pin. Follow normal board layout practices to ensure that current
flow from other parts of the board does not impact the ground potential between the resistors and the TPS2549-
Q1 GND pin.
8.4 Device Functional Modes
8.4.1 Device Truth Table (TT)
The device truth table (表 8-2) lists all valid combinations for the three control pins (CTL1 through CTL3), and the
corresponding charging mode of each pin combination. The TPS2549-Q1 device monitors the CTL inputs and
transitions to whichever charging mode it is commanded to go to. For example, if the USB port is a charging-only
port, then the user must set the CTL pins of the TPS2549-Q1 device to correspond to the DCP-auto charging
mode. However, when the USB port requires data communication, then the user must set control pins to
correspond to the SDP or CDP mode, and so on.
表 8-2. Truth Table
STATUS
OUTPUT
(ACTIVE-
LOW)
FAULT
OUTPUT
(ACTIVE-
LOW)
CURRENT
LIMIT
SETTING
CS FOR CABLE
COMPENSATION
CTL1
CTL2
CTL3
MODE
NOTES
0
0
0
Lo
Hi
DCP1(1)
OFF
ON(2)
ON
ON
DCP includes divider 3,
1.2-V mode, and BC1.2
mode
0
0
1
DCP(1)
ON
ON
DCP includes divider 3,
1.2-V mode, and BC1.2
mode
0
1
1
0
X
X
Lo
SDP
OFF
OFF
ON
ON
Standard SDP port
NA
Client mode
OFF
OFF
No current limit, power
switch disabled, data
switch bypassed
1
1
1
1
0
1
Lo
Hi
SDP1(3)
CDP(3)
OFF
ON
ON(2)
ON
ON
ON
Standard SDP port
CDP-SDP auto switch
mode
(1) No OUT discharge when changing between 000 and 001
(2) FAULT not asserted on overcurrent
(3) No OUT discharge when changing between 110 and 111
8.4.2 USB Specification Overview
The following overview references various industry standards. TI recommends consulting the most up-to-date
standards to ensure the most recent and accurate information. Rechargeable portable equipment requires an
external power source to charge batteries. USB ports are a convenient location for charging because of an
available 5-V power source. Universally accepted standards are required to ensure host and client-side devices
operate together in a system to ensure power-management requirements are met. Traditionally, host ports
following the USB-2.0 specification must provide at least 500 mA to downstream client-side devices. Because
multiple USB devices can be attached to a single USB port through a bus-powered hub, the client-side device
sets the power allotment from the host to ensure the total current draw does not exceed 500 mA. In general,
each USB device is granted 100 mA and can request more current in 100-mA unit steps up to 500 mA. The host
grants or denies additional current based on the available current. A USB-3.0 host port not only provides higher
data rate than a USB-2.0 port but also raises the unit load from 100 mA to 150 mA. Providing a minimum current
of 900 mA to downstream client-side devices is required.
Additionally, the success of USB has made the micro-USB and mini-USB connectors a popular choice for wall-
adapter cables. A micro-USB or mini-USB allows a portable device to charge from both a wall adapter and USB
port with only one connector. As USB charging has gained popularity, the 500-mA minimum defined by USB 2.0,
or 900 mA for USB 3.0, has become insufficient for many handset and personal media players, which require a
higher charging rate. Wall adapters provide much more current than 500 or 900 mA. Several new standards
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have been introduced defining protocol handshaking methods that allow host and client devices to acknowledge
and draw additional current beyond the 500-mA and 900-mA minimum defined by USB 2.0 and USB 3.0,
respectively, while still using a single micro-USB or mini-USB input connector.
The TPS2549-Q1 device supports four of the most-common USB-charging schemes found in popular hand-held
media and cellular devices.
• USB Battery Charging Specification BC1.2
• Chinese Telecommunications Industry Standard YD/T 1591-2009
• Divider 3 mode
• 1.2-V mode
The BC1.2 specification includes three different port types:
• Standard downstream port (SDP)
• Charging downstream port (CDP)
• Dedicated charging port (DCP)
BC1.2 defines a charging port as a downstream-facing USB port that provides power for charging portable
equipment. Under this definition, CDP and DCP are defined as charging ports.
表 8-3 lists the difference between these port types.
表 8-3. Operating Modes Table
PORT TYPE
SUPPORTS USB2.0 COMMUNICATION
MAXIMUM ALLOWABLE CURRENT
DRAWN BY PORTABLE EQUIPMENT (A)
SDP (USB 2.0)
SDP (USB 3.0)
CDP
YES
YES
YES
NO
0.5
0.9
1.5
1.5
DCP
8.4.3 Standard Downstream Port (SDP) Mode — USB 2.0 and USB 3.0
An SDP is a traditional USB port that follows USB 2.0 or USB 3.0 protocol. A USB 2.0 SDP supplies a minimum
of 500 mA per port and supports USB 2.0 communications. A USB 3.0 SDP supplies a minimum of 900 mA per
port and supports USB 3.0 communications. For both types, the host controller must be active to allow charging.
8.4.4 Charging Downstream Port (CDP) Mode
A CDP is a USB port that follows USB BC1.2 and supplies a minimum of 1.5 A per port. A CDP provides power
and meets the USB 2.0 requirements for device enumeration. USB-2.0 communication is supported, and the
host controller must be active to allow charging. The difference between CDP and SDP is the host-charge
handshaking logic that identifies this port as a CDP. A CDP is identifiable by a compliant BC1.2 client device and
allows for additional current draw by the client device.
The CDP handshaking process occurs in two steps. During step one, the portable equipment outputs a nominal
0.6-V output on the D+ line and reads the voltage input on the D– line. The portable device detects the
connection to an SDP if the voltage is less than the nominal data-detect voltage of 0.3 V. The portable device
detects the connection to a CDP if the D– voltage is greater than the nominal data detect voltage of 0.3 V and
optionally less than 0.8 V.
The second step is necessary for portable equipment to determine whether the equipment is connected to a
CDP or a DCP. The portable device outputs a nominal 0.6-V output on the D– line and reads the voltage input
on the D+ line. The portable device concludes the equipment is connected to a CDP if the data line being read
remains less than the nominal data detects voltage of 0.3 V. The portable device concludes it is connected to a
DCP if the data line being read is greater than the nominal data detect voltage of 0.3 V.
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8.4.5 Dedicated Charging Port (DCP) Mode
A DCP only provides power and does not support data connection to an upstream port. As shown in the
following sections, a DCP is identified by the electrical characteristics of the data lines. The TPS2549-Q1 only
emulates one state, DCP-auto state. In the DCP-auto state, the device charge-detection state machine is
activated to selectively implement charging schemes involved with the shorted, divider3 and 1.2 v modes. The
shorted DCP mode complies with BC1.2 and Chinese Telecommunications Industry Standard YD/T 1591-2009,
whereas the divider3 and 1.2 V modes are employed to charge devices that do not comply with the BC1.2 DCP
standard.
8.4.5.1 DCP BC1.2 and YD/T 1591-2009
Both standards specify that the D+ and D– data lines must be connected together with a maximum series
impedance of 200 Ω, as shown in 图 8-8.
VBUS
5 V
D–
200 Ω
(ma x.)
D+
GND
图 8-8. DCP Supporting BC1.2 and YD/T 1591-2009
8.4.5.2 DCP Divider-Charging Scheme
The device supports divider3, as shown in 图 8-9. In the Divider3 charging scheme the device applies 2.7 V and
2.7 V to D+ and D– data lines.
VBUS
5 V
D–
D+
2.7 V
2.7 V
GND
图 8-9. Divider 3 Mode
8.4.5.3 DCP 1.2-V Charging Scheme
The DCP 1.2-V charging scheme is used by some hand-held devices to enable fast charging at 2 A. The
TPS2549-Q1 device supports this scheme in DCP-auto state before the device enters BC1.2 shorted mode. To
simulate this charging scheme, the D+ and D– lines are shorted and pulled up to 1.2 V for a fixed duration.
Then the device moves to DCP shorted mode as defined in the BC1.2 specification and as shown in 图 8-10.
VBUS
5 V
200 Ω (ma x.) D–
D+
1.2 V
GND
图 8-10. 1.2-V Mode
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8.4.6 DCP Auto Mode
As previously discussed, the TPS2549-Q1 device integrates an auto-detect state machine that supports all the
DCP charging schemes. The auto-detect state machine starts in the Divider3 scheme. However, if a BC1.2 or
YD/T 1591-2009 compliant device is attached, the TPS2549-Q1 device responds by turning the power switch
back on without output discharge and operating in 1.2-V mode briefly before entering BC1.2 DCP mode. Then
the auto-detect state machine stays in that mode until the device releases the data line, in which case the auto-
detect state machine goes back to the Divider3 scheme. When a Divider3-compliant device is attached, the
TPS2549-Q1 device stays in the Divider3 state.
5 V
S1
Divider 3 Mode
VBUS
S1, S2: ON
S3, S4: OFF
D–
D+
DM_IN
DP_IN
GND
S2
S3
S4
Shorted Mode
S4 ON
S1, S2, S3: OFF
GND
1.2-V Mode
S1, S2: OFF
S3, S4: ON
2.7 V 2.7 V 1.2 V
图 8-11. DCP Auto Mode
8.4.7 Client Mode
The TPS2549-Q1 device integrates client mode as shown in 图 8-12. The internal power switch is OFF and only
the data analog switch is ON to block OUT power. This mode can be used for some software programming via
the USB port.
IN
OUT
DP_IN
DM_IN
OFF
DP_OUT
DM_OUT
图 8-12. Client-Mode Equivalent Circuit
8.4.8 High-Bandwidth Data-Line Switches
The TPS2549-Q1 device passes the D+ and D– data lines through the device to enable monitoring and
handshaking while supporting the charging operation. A wide-bandwidth signal switch allows data to pass
through the device without corrupting signal integrity. The data-line switches are turned on in any of the CDP,
SDP, or client operating modes. The EN input must be at logic high for the data line switches to be enabled.
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Note
• While in CDP mode, the data switches are ON, even during CDP handshaking.
• The data line switches are OFF if EN is low, or if in DCP mode. The switches are not automatically
turned off if the power switch (IN to OUT) is in current-limit.
• The data switches are only for a USB-2.0 differential pair. In the case of a USB-3.0 host, the super-
speed differential pairs must be routed directly to the USB connector without passing through the
TPS2549-Q1 device.
• Data switches are OFF during OUT (VBUS) discharge.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The TPS2549-Q1 device is a USB charging-port controller and power switch with cable compensation. It is
typically used for automotive USB port protection and as a USB charging controller. The following design
procedure can be used to select components for the TPS2549-Q1 device. This section presents a simplified
discussion of how to design cable compensation.
9.2 Typical Application
Automotive USB port charging requires a voltage regulator to convert battery voltage to 5-V VBUS output.
Because the VBUS, D+, and D– pins of a USB port are exposed, there is a need for a protection device that has
VBUS overcurrent and D+ and D– ESD protection. An additional need is a charging controller with integrated
CDP and DCP charging protocols on D+ and D– to support fast charging. A schematic of an application circuit
with cable compensation is shown in 图 9-1. An LMR14030 device is used as the voltage regulator, and the
TPS2549-Q1 device is used as the charging controller with protection features.
Nowadays, automotive products have higher safety requirements; the exposed pins including VBUS / D+ / D-
may also short to battery in real applications. More details can be learned through this application note:
SLVAEI5. The TPS2549-Q1 has short to VBUS protection, but does not support short to battery protection. If
short circuit to battery protection is needed, the TPS254900A-Q1 or TPS25830-Q1 are recommended options.
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0.1 µF
10 µH
SW
BOOT
12 V
VIN
LMR14030
GND
V(DC)
EN
60.4 kW
0.75 V
RT/SYNC
SS
FB
0.018 µF
To Portable Device
R(BUS)
0.1µF
47 mΩ
2 × 47 µF
IN
OUT
VBUS
TPS2549-Q1
DM_IN
DP_IN
R(GN D)
FAULT
1.5-m USB Cable
FAULT
STATUS
STATUS
GND
CS
ILIM_LO
ILIM_HI
EN
I/O
CTL1
20 kW
80.6 kW
DM_OUT
DP_OUT
CTL2
CTL3
ToHost
Controller
图 9-1. Typical Application Schematic: USB Port Charging With Cable Compensation
9.2.1 Design Requirements
For this design example, use the following as the input parameters.
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage, V(IN)
12 V
Output voltage, V(DC)
5 V
Total parasitic resistance including TPS2549-Q1 rDS(on)
Maximum continuous output current, I(OUT)
Current limit, I(LIM)
420 mΩ
2.4 A
2.5 A to 2.9 A
9.2.2 Detailed Design Procedure
To begin the design process, a few parameters must be decided upon. The designer needs to know the
following:
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• Total resistance including power switch rDS(on), cable resistance, and the contact resistance of connectors
• The maximum continuous output current for the charging port. The minimum current-limit setting of TPS2549-
Q1 device must be higher than this current.
• The maximum output current of the upstream dc-dc converter. The maximum current-limit setting of
TPS2549-Q1 device must be lower than this current.
9.2.2.1 Input and Output Capacitance
Input and output capacitance improves the performance of the device; the actual capacitance should be
optimized for the particular application. All protection circuits including the TPS2549-Q1 device have the
potential for input voltage droop, overshoot, and output-voltage undershoot.
For all applications, TI recommends a 0.1-µF or greater ceramic bypass capacitor between IN and GND, placed
as close as possible to the device for the local noise decoupling.
The TPS2549-Q1 device is used for 5-V power rail protection when a hot-short occurs on the output or when
plugging in a capacitive load. Due to the limited response time of the upstream power supply, a large load
transient can deplete the charge on the output capacitor of the power supply, causing a voltage droop. If the
power supply is shared with other loads, ensure that voltage droop from current surges of the other loads do not
force the TPS2549-Q1 device into UVLO. Increasing the upstream power supply output capacitor can reduce
this droop. Shortening the connection impedance (resistance and inductance) between the TPS2549-Q1 device
and the upstream power supply can also help reduce the voltage droop and overshoot on the TPS2549-Q1 input
power bus.
Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input
voltage in conjunction with input power-bus inductance and input capacitance when the IN terminal is in the
high-impedance state (before turnon). Theoretically, the peak voltage is 2 times the applied voltage. The second
cause is due to the abrupt reduction of output short-circuit current when the TPS2549-Q1 device turns off and
energy stored in the input inductance drives the input voltage high. Applications with large input inductance (for
example, connecting the evaluation board to the bench power supply through long cables) may require large
input capacitance to prevent the voltage overshoot from exceeding the absolute maximum voltage of the device.
For output capacitance, consider the following three application situations.
The first, output voltage undershoot is caused by the inductance of the output power bus just after a short has
occurred and the TPS2549-Q1 has abruptly reduced OUT current. Energy stored in the inductance will drive the
OUT voltage down and potentially negative as it discharges. Applications with large output inductance (such as
from a cable) benefit from use of a high-value output capacitor to control the voltage undershoot. Second, for
USB-port application, because the OUT pin is exposed to the air, the application must withstand ESD stress
without damage. Because there is no internal IEC ESD cell as on DP_IN and DM_IN, using a low-ESR
capacitance can make this pin robust. Third, when plugging in apacitive load such as the input capacitor of any
portable device, having a large output capacitance can help reduce the peak current and up-stream power
supply output voltage droop. So for TPS2549-Q1 output capacitance, recommended practice is typically adding
two 47-µF ceramic capacitors.
9.2.2.2 Cable Compensation Calculation
Based on the known total resistance, 表 9-1 shows the calculation.
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表 9-1. Cable Compensation Calculation
CALCULATION EQUATION(1)
CALCULATED VALUE
ASSEMBLY VALUE
V(DC) (V) without load
R(G) (kΩ)
5
6.8
6.8
0.42
0.075
5.6
R(total) (Ω)
G(CS) (mA/A)
R(FA) (kΩ)
R(FA) = R(total) / G(CS)
5.6
33
V(FB) (V)
0.75
32.93
R(FB) (kΩ)
R(FB) = [V(DC) / (V(FB) / R(G))] –
R
(G) – R(FA)
VCS = (V(FB) / R(G)) × (R(G)
R(FB)
V(CS) (V)(2)
+
4.39
)
2.84
6.25
Maximum IOS (A) at 20 kΩ
V(DC,max) output (V)(3)
V(DC,max) = 5 + I(OS,max)
G(CS,max) × R(FA)
×
C(OUT) (µF)
2 × 47
22
C(COMP) (nF)(4)
C(COMP) ≥ 3 × G(CS) × C(OUT)
≥21.15
(1) See 图 8-2 and Design Procedure.
(2) Ensure that VCS exceeds 2.5 V.
(3) Ensure that the maximum dc-dc output voltage is lower than 6.5 V when considering I(OS,max) and G(CS,max)
.
(4) CCOMP impacts load-transient performance, so the output performance should always be verified in the end application circuit.
9.2.2.3 Power Dissipation and Junction Temperature
The low on-resistance of the N-channel MOSFET allows small surface-mount packages to pass large currents. It
is good design practice to estimate power dissipation and junction temperature. The following analysis gives an
approximation for calculating junction temperature based on the power dissipation in the package. However, it is
important to note that thermal analysis is strongly dependent on additional system-level factors. Such factors
include air flow, board layout, copper thickness and surface area, and proximity to other devices dissipating
power. Good thermal design practice must include all system-level factors in addition to individual component
analysis. Begin by determining the rDS(on) of the N-channel MOSFET relative to the input voltage and operating
temperature. As an initial estimate, use the highest operating ambient temperature of interest and read rDS(on)
from the typical characteristics graph. Using this value, the power dissipation can be calculated by:
2
PD = rDS(on) ´ IOUT
(6)
where:
PD = Total power dissipation (W)
rDS(on) = Power-switch on-resistance (Ω)
IOUT = Maximum current-limit threshold (A)
This step calculates the total power dissipation of the N-channel MOSFET.
Finally, calculate the junction temperature:
TJ = PD ´ RqJA + TA
(7)
where:
TA = Ambient temperature (°C)
RθJA = Thermal resistance (°C/W)
PD = Total power dissipation (W)
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Compare the calculated junction temperature with the initial estimate. If they are not within a few degrees, repeat
the calculation using the refined rDS(on) from the previous calculation as the new estimate. Two or three iterations
are generally sufficient to achieve the desired result. The final junction temperature is highly dependent on
thermal resistance RθJA, and thermal resistance is highly dependent on the individual package and board
layout.
9.3 Application Curves
6.2
VBUS
V(DC)
6
5.8
5.6
5.4
V(DC) at 5-V Offset
100 mV/div
5.2
I(OUT)
5
200 mA/div
4.8
0
0.5
1
1.5
I(LOAD) (A)
2
2.5
D018
t = 20 ms/div
图 9-2. V(DC) and VBUS vs I(LOAD) Output
图 9-3. Plugging In a Portable Device, V(DC)
VBUS at 5-V Offset
10 mV/div
V(DC) at 5-V Offset
100 mV/div
I(OUT)
200 mA/div
I(OUT)
200 mA/div
t = 20 ms/div
t = 20 ms/div
图 9-4. Unplugging a Portable Device, V(DC)
图 9-5. Plugging In Portable Device, VBUS
V(DC) at 5-V Offset
200 mV/div
I(OUT)
200 mA/div
VBUS at 5-V Offset
100 mV/div
I(OUT)
1 A/div
t = 200 µs/div
t = 20 ms/div
图 9-7. 0.5-A ↔ 2.4-A Load Transient With 100-
图 9-6. Unplugging Portable Device, VBUS
mA/µs Slew Rate, V(DC)
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V(DC)
1 V/div
VBUS at 5-V Offset
200 mV/div
I(OUT)
I(OUT)
1 A/div
2 A/div
t = 200 µs/div
t = 200 µs/div
图 9-8. 0.5-A ↔ 2.4-A Load Transient With 100-
图 9-9. VBUS Shorted to GND, V(DC)
mA/µs Slew Rate, VBUS
10 Power Supply Recommendations
The TPS2549-Q1 device is designed for a supply-voltage range of 4.5 V ≤ VIN ≤ 6.5 V. If the input supply is
located more than a few inches from the device, an input ceramic bypass capacitor higher than 0.1 μF is
recommended. The power supply should be rated higher than the TPS2549-Q1 current-limit setting to avoid
voltage droops during overcurrent and short-circuit conditions.
11 Layout
11.1 Layout Guidelines
• For the trace routing of DP_IN, DM_IN, DP_OUT, and DM_OUT: Route these traces as micro-strips with
nominal differential impedance of 90 Ω. Minimize the use of vias in the high-speed data lines. Keep the
reference GND plane devoid from cuts or splits above the differential pairs to prevent impedance
discontinuities. For more information, see the High Speed USB Platform Design Guideline from Intel.
• The trace routing from the upstream regulator to the TPS2549-Q1 IN pin should as short as possible to
reduce the voltage drop and parasitic inductance.
• The traces routing from the RILIM_HI and RILIM_LO resistors to the device should be as short as possible to
reduce parasitic effects on the current-limit accuracy.
• The thermal pad should be directly connected to the PCB ground plane using a wide and short copper trace.
• The trace routing from the CS pin to the feedback divider of the upstream regulator should not be routed near
any noise sources that can capacitively couple to the feedback divider.
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11.2 Layout Example
Top Layer Signal Trace
Top Layer Signal Ground Plane
Bottom Layer Signal Trace
Via to Bottom Layer Signal Ground Plane
Via to Bottom Layer Signal
16 15 14 13
IN
1
12
OUT
2
3
4
11
10
9
DM_IN
DP_IN
DM_OUT
DP_OUT
CS
STATUS
5
6
7
8
图 11-1. TPS2549-Q1 Layout Diagram
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
High Speed USB Platform Design Guidelines, Intel
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most-
current data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS2549IRTERQ1
TPS2549IRTETQ1
ACTIVE
ACTIVE
WQFN
WQFN
RTE
RTE
16
16
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
2549Q
2549Q
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS2549IRTERQ1
TPS2549IRTETQ1
WQFN
WQFN
RTE
RTE
16
16
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS2549IRTERQ1
TPS2549IRTETQ1
WQFN
WQFN
RTE
RTE
16
16
3000
250
346.0
210.0
346.0
185.0
33.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RTE 16
3 x 3, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225944/A
www.ti.com
PACKAGE OUTLINE
RTE0016C
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(DIM A) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
17
1.5
1
12
0.30
16X
0.18
PIN 1 ID
(OPTIONAL)
13
16
0.1
C A B
SYMM
0.05
0.5
0.3
16X
4219117/B 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
17
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
8
(R0.05)
ALL PAD CORNERS
(0.58) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219117/B 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4219117/B 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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