TPS25750DRJKR_技术文档

TPS25750

_{SLVSFR7A – JULY 2020 – REVISED NOV}T_EMP_BS_E2_R5₂7₀5₂0₀

SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020

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TPS25750 USB Type-C® and USB PD Controller with Integrated Power Switches

Optimized for Power Applications

1 Features

2 Applications

•

Integrated fully managed power paths

– Integrated 5-V, 3-A, 36-mΩ sourcing switch

(TPS25750S/D)

– Integrated 28-V, 7-A, 16-mΩ bi-directional load

switch (TPS25750D only)

•

Power tools, power banks, retail automation and

payment

Wireless speakers, headphones

Other personal electronics and industrial

applications

•

Standalone USB Type-C PD solution

– No firmware development or external micro-

controller needed

3 Description

The TPS25750 is a highly integrated stand-alone USB

Type-C and Power Delivery (PD) controller optimized

for applications supporting USB-C PD Power. The

TPS25750 integrates fully managed power paths with

robust protection for a complete USB-C PD solution.

The TPS25750 also integrates control for external

battery charger ICs for added ease of use and

reduced time to market. The intuitive web based GUI

will ask the user a few simple questions on the

applications needs using clear block diagrams and

simple multiple-choice questions. As a result, the GUI

will create the configuration image for the user’s

application, reducing much of the complexity

associated with competitive USB PD solutions.

Integrated robust power path protection

– Integrated reverse current protection,

overvoltage protection, and slew rate control

the high-voltage bi-directional power path

– Integrated undervoltage and overvoltage

protection and current limiting for inrush current

protection for the 5V/3A source power path

– 26-V tolerant CC pins for robust protection

when connected to non-compliant devices

Optimized for power applications

– Integrated I2C control for TI battery chargers

– Web-based GUI and pre-configured firmware

– Optimized for power consumer only (sink)

(UFP) applications

•

Device Information

PART NUMBER⁽¹⁾

TPS25750D

PACKAGE

QFN (RJK)

QFN (RSM)

BODY SIZE (NOM)

4.0 mm x 6.0 mm

4.0 mm x 4.0 mm

– Optimized for power provider (source) and

power consumer (sink) (DRP) applications

USB Type-C power delivery (PD) controller

– 10 configurable GPIOs

TPS25750S

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

– BC1.2 charging support

5 A

– USB PD 3.0 compliant

5-20 V

– USB Type-C specification complaint

– Cable attach and orientation detection

– Integrated VCONN switch

3.3 V

LDO

TPS25750D

5 V

3.3 V

V_BUS

3 A

– Physical layer and policy engine

– 3.3-V LDO output for dead battery support

– Power supply from 3.3 V or VBUS source

CC1/2

2

CC

V_CONN

Type-C Rp/Rd & state

machine,

VCONN switches,

USB PD policy engine,

protocol and physical layer

Optional

Embedded

Controller

USB

Type-C

Connector

I2C

Slave

BQ

Battery

Charger

GND

I2C

Master

10 GPIO

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 7

7.1 Absolute Maximum Ratings........................................ 7

7.2 ESD Ratings............................................................... 8

7.3 Recommeded Operating Conditions...........................8

7.4 Recommended Capacitance.......................................9

7.5 Thermal Information..................................................10

7.6 Power Supply Characteristics................................... 11

7.7 Power Consumption..................................................11

7.8 PP_5V Power Switch Characteristics....................... 11

7.9 PPHV Power Switch Characteristics - TPS25750D..12

7.10 PP_EXT Power Switch Characteristics -

TPS25750S.................................................................14

7.11 Power Path Supervisory..........................................16

7.12 CC Cable Detection Parameters.............................16

7.13 CC VCONN Parameters......................................... 17

7.14 CC PHY Parameters...............................................18

7.15 Thermal Shutdown Characteristics.........................18

7.16 ADC Characteristics................................................19

7.17 Input/Output (I/O) Characteristics........................... 19

7.18 BC1.2 Characteristics............................................. 19

7.19 I2C Requirements and Characteristics................... 20

7.20 Typical Characteristics ...........................................22

8 Parameter Measurement Information..........................24

9 Detailed Description......................................................25

9.1 Overview...................................................................25

9.2 Functional Block Diagram.........................................26

9.3 Feature Description...................................................28

9.4 Device Functional Modes..........................................45

10 Application and Implementation................................49

10.1 Application Information........................................... 49

10.2 Typical Application.................................................. 49

11 Power Supply Recommendations..............................54

11.1 3.3-V Power............................................................ 54

11.2 1.5-V Power............................................................ 54

11.3 Recommended Supply Load Capacitance..............54

12 Layout...........................................................................55

12.1 TPS25750D - Layout.............................................. 55

12.2 TPS25750S - Layout...............................................60

13 Device and Documentation Support..........................67

13.1 Device Support....................................................... 67

13.2 Documentation Support.......................................... 67

13.3 Support Resources................................................. 67

13.4 Trademarks.............................................................67

13.5 Electrostatic Discharge Caution..............................67

13.6 Glossary..................................................................67

14 Mechanical, Packaging, and Orderable

Information.................................................................... 67

4 Revision History

Changes from Revision * (July 2020) to Revision A (November 2020)

Page

•

Changed data sheet status from "Advance Information" to "Production Data"...................................................1

2

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5 Device Comparison Table

INTEGRATED HIGH

HIGH VOLTAGE GATE DRIVER

DEVICE NUMBER

5-V SOURCE LOAD SWITCH

VOLTAGE BI-DIRECTIONAL FOR BI-DIRECTIONAL EXTERNAL

LOAD SWITCH (PPHV)

PATH (PP_EXT)

TPS25750D

TPS25750S

Yes

No

Yes

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6 Pin Configuration and Functions

37

36

35

34

33

32

31

30

29

28

27

38

26

LDO_3V3

ADCIN1

VBUS_IN

1

2

25

24

23

22

21

20

ADCIN2

LDO_1V5

GPIO0

VBUS_IN

PPHV

3

4

5

Thermal Pad

(GND)

Thermal Pad (DRAIN)

PPHV

GPIO1

PPHV

6

8

9

10

11

12

13

18

19

7

14

15

16

17

Not to Scale

Figure 6-1. Top View of the TPS25750D 38-pin QFN RJK Package

LDO_3V3

ADCIN1

ADCIN2

LDO_1V5

GPIO0

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

CC1

GPIO5/USB_N

GPIO4/USB_P

GATE_VBUS

GATE_VSYS

VSYS

Thermal

Pad

(GND)

GPIO1

GPIO2

GPIO3

I2Cs_SDA

I2Cm_IRQ

Not to Scale

Figure 6-2. Top View of the TPS25750S 32-pin QFN RSM Package

4

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Table 6-1. TPS25750D Pin Functions

TYPE⁽¹⁾RESET DESCRIPTION

NAME

NO.

2

ADCIN1

ADCIN2

I

Hi-Z

Configuration Input. Connect to a resistor divider to LDO_3V3.

3

I/O for USB Type-C. Filter noise with recommended capacitor to GND

(CCCy).

CC1

CC2

28

29

I/O

Hi-Z

I/O for USB Type-C. Filter noise with recommended capacitor to GND

(CCCy).

GND

11, 12, 14, 31

—

GPIO

O

—

Ground. Connect to ground plane.

GPIO0

GPIO1

GPIO2

GPIO3

5

6

Hi-Z

General purpose digital I/O. Tie to ground when unused.

7

19

O

General purpose digital I/O. Tie to ground when unused.This may be

connected to D+ for BC1.2 support.

GPIO4(USB_P)

GPIO5(USB_N)

26

27

I/O

Hi-Z

General purpose digital I/O. Tie to ground when unused. This may be

connected to D- for BC1.2 support.

GPIO6

GPIO7

37

36

O

Hi-Z

General purpose digital I/O. Tie to ground when unused.

I2C slave serial clock input. Tie to pullup voltage through a resistor. May be

grounded if unused.

I2Cs_SCL

I2Cs_SDA

I2Cs_IRQ

9

8

I

Hi-Z

I2C slave serial data. Open-drain input/output. Tie to pullup voltage through a

resistor. May be grounded if unused.

I/O

O

I2C slave interrupt. Active low. Connect to external voltage through a pull-up

resistor. This can be re-configured to GPIO10. Tie to ground if unused.

10

I²C master serial clock. Open-drain output. Tie to pullup voltage through a

resistor. Can be grounded if unused.

I2Cm_SCL

GPIO11

17

13

16

O

Hi-Z

General purpose digital I/O. Tie to ground when unused.

I²C master serial data. Open-drain input/output. Tie to pullup voltage through

a resistor. Can be grounded if unused.

I2Cm_SDA

I/O

I2C master interrupt. Active low. Connect to external voltage through a pull-up

resistor.Tie to ground when unused. This can be re-configured to GPIO12.

I2Cm_IRQ

LDO_1V5

LDO_3V3

18

4

I

Hi-Z

—

Output of the CORE LDO. Bypass with capacitance C_{LDO_1V5}to GND. This

pin cannot source current to external circuits.

O

Output of supply switched from VIN_3V3 or VBUS LDO. Bypass with

capacitance C_{LDO_3V3}to GND.

1

—

DRAIN

PP5V

PPHV

15, 30

34, 35

N/A

I

—

Connects to drain of internal FET.

5-V System Supply to VBUS, supply for CCy pins as VCONN.

High-voltage sinking node in the system.

20, 21, 22

I/O

VBUS_IN

23, 24, 25

5-V to 20-V input.

I/O

VBUS

32, 33

38

O

I

5-V output from PP5V input to LDO. Bypass with capacitance C_VBUSto GND.

Supply for core circuitry and I/O. Bypass with capacitance C_{VIN_3V3}to GND.

VIN_3V3

—

(1) I = input, O = output, I/O = input and output, GPIO = general purpose digital input and output

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Table 6-2. TPS25750S Pin Functions

TYPE⁽¹⁾RESET DESCRIPTION

NAME

NO.

2

ADCIN1

ADCIN2

I

Hi-Z

Configuration Input. Connect to a resistor divider to LDO_3V3.

3

I/O for USB Type-C. Filter noise with recommended capacitor to GND

(CCCy).

CC1

CC2

24

25

I/O

Hi-Z

I/O for USB Type-C. Filter noise with recommended capacitor to GND

(CCCy).

GATE_VSYS

GATE_VBUS

GND

20

O

Hi-Z

—

Connect to the N-ch MOSFET that has source tied to VSYS.

Connect to the N-ch MOSFET that has source tied to VBUS.

Ground. Connect to ground plane.

21

O

11, 12, 14

—

GPIO0

5

6

I/O

Hi-Z

General purpose digital I/O. Tie to ground when unused.

GPIO1

GPIO2

7

GPIO3

18

General purpose digital I/O. Tie to ground when unused. This may be

connected to D+ for BC1.2 support.

GPIO4 (USB_P)

GPIO5 (USB_N)

22

23

I/O

Hi-Z

General purpose digital I/O. Tie to ground when unused. This may be

connected to D- for BC1.2 support.

GPIO6

GPIO7

31

30

I/O

Hi-Z

General purpose digital I/O. Tie to ground when unused.

I2C slave serial clock input. Tie to pullup voltage through a resistor. May be

grounded if unused.

I2Cs_SCL

I2Cs_SDA

I2Cs_IRQ

9

8

I

Hi-Z

I2C slave serial data. Open-drain input/output. Tie to pullup voltage through a

resistor. May be grounded if unused.

I/O

O

I2C slave interrupt. Active low. Connect to external voltage through a pull-up

resistor. This can be re-configured to GPIO10. Tie to ground when unused.

10

I²C master serial clock. Open-drain output. Tie to pullup voltage through a

resistor when used or unused.

I2Cm_SCL

GPIO11

16

13

15

O

Hi-Z

General purpose digital I/O. Tie to ground when unused.

I²C master serial data. Open-drain input/output. Tie to pullup voltage through

a resistor when used or unused.

I2Cm_SDA

I/O

I2C master interrupt. Active low. Connect to external voltage through a pull-up

resistor. Tie to ground when unused. This can be re-configured to GPIO12.

I2Cm_IRQ

LDO_1V5

17

4

I

Hi-Z

—

Output of the CORE LDO. Bypass with capacitance C_{LDO_1V5}to GND. This

pin cannot source current to external circuits.

O

Output of supply switched from VIN_3V3 or VBUS LDO. Bypass with

capacitance C_{LDO_3V3}to GND.

LDO_3V3

PP5V

1

O

I

—

28, 29

5-V System Supply to VBUS, supply for CCy pins as VCONN.

High-voltage sinking node in the system. It is used to implement reverse-

current-protection (RCP) for the external sinking paths controlled by

GATE_VSYS.

VSYS

19

I

—

VBUS

26, 27

32

I/O

I

5-V to 20-V input. Bypass with capacitance C_VBUSto GND.

VIN_3V3

—

Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND.

(1) I = input, O = output, I/O = input and output, GPIO = general purpose digital input and output

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7 Specifications

7.1 Absolute Maximum Ratings

7.1.1 TPS25750D and TPS25750S - Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

-0.3

–0.3

–0.5

-0.3

MAX

6

UNIT

PP5V

VIN_3V3

4

V

ADCIN1, ADCIN2

VBUS_IN, VBUS⁽⁴⁾

CC1, CC2 ⁽⁴⁾

4

28

26

6.0

Input voltage range ⁽²⁾

V

GPIOx

I2Cm_SDA, I2Cm_SCL, I2Cm_IRQ,

I2Cs_IRQ,I2Cs_SCL, I2Cs_SDA

LDO_1V5⁽³⁾

LDO_3V3⁽³⁾

–0.3

4

–0.3

2

Output voltage range ⁽²⁾

4

internally limited

1

Source or sink current VBUS

Positive source current on CC1, CC2

Positive sink current on CC1, CC2 while VCONN

1

Source current

switch is enabled

A

Positive sink current for I2Cm_SDA, I2Cm_SCL,

I2Cm_IRQ, I2Cs_IRQ,I2Cs_SCL, I2Cs_SDA

internally limited

Positive source current for LDO_3V3, LDO_1V5

GPIOx

internally limited

0.005

175

A

T_JOperating junction temperature

T_STGStorage temperature

–40

–55

°C

150

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltage values are with respect to network GND. Connect the GND pin directly to the GND plane of the board.

(3) Do not apply voltage to these pins.

(4) A TVS with a break down voltage falling between the Recommended max and the Abs max value is recommended such as TVS2200.

7.1.2 TPS25750D - Absolute Maximum Ratings

MIN

MAX

28

UNIT

Input voltage range ⁽¹⁾

V_{PPHV_VBUS_IN}

PPHV

Source-to-source voltage

–0.3

V

28

V

Sink current

Continuous current to/from

VBUS_IN to PPHV

A

7

Pulsed current to/from

VBUS_IN to PPHV⁽²⁾

10

T_{J_PPHV}Operating

junction temperature

PP_HV switch

–40

175

°C

(1) All voltage values are with respect to network GND. Connect the GND pin directly to the GND plane of the board.

(2) Pulse duration ≤ 100 µs and duty-cycle ≤ 1%.

7.1.3 TPS25750S - Absolute Maximum Ratings

MIN

MAX

UNIT

GATE_VBUS,

GATE_VSYS⁽²⁾

Output voltage range ⁽¹⁾

–0.3

40

V

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7.1.3 TPS25750S - Absolute Maximum Ratings (continued)

MIN

MAX

V_{GATE_VBUS}- V_VBUS, V

_{GATE_SYS}- V_VSYS

V_GS

–0.5

12

V

(1) All voltage values are with respect to network GND. Connect the GND pin directly to the GND plane of the board.

(2) Do not apply voltage to these pins.

7.2 ESD Ratings

PARAMETER

TEST CONDITIONS

VALUE

UNIT

Human body model (HBM), per ANSI/

ESDA/JEDEC JS-001, all pins⁽¹⁾

±1000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per

JEDEC specificationJESD22-C101, all

pins⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommeded Operating Conditions

7.3.1 TPS25750D - Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

MIN

3.0

MAX

UNIT

VIN_3V3

PP5V

3.6

5.5

4.9

V_I

Input voltage range ⁽¹⁾

V

ADCIN1, ADCIN2,VBUS_IN,

VBUS ⁽²⁾

4

0

22

PPHV

I2Cx_SDA, I2Cx_SCL, I2Cx_IRQ,

ADCIN1, ADCIN2

3.6

V_IO

I/O voltage range ⁽¹⁾

V

GPIOx

0

5.5

3

CC1, CC2

VBUS

A

I_O

Output current (from PP5V)

CC1, CC2

315

7

mA

A

I_{PP_HV}

I_O

Current from VBUS_IN to PPHV

Output current (from LDO_3V3)

GPIOx

1

mA

I_O

Output current (from VBUS LDO) Current from LDO_3V3

5

I_{PP_5V}≤ 3 A, I_{PP_HV}= 0, I_{PP_CABLE}

≤ 315 mA

–40

85

105

45

I_{PP_5V}≤ 1.5 A, I_{PP_HV}= 0, I

_{PP_CABLE}≤ 315 mA

I_{PP_5V}= 0, I_{PP_HV}≤ 7 A, I_{PP_CABLE}

= 0

T_A

Ambient operating temperature

°C

I_{PP_5V}= 0, I_{PP_HV}≤ 6 A, I_{PP_CABLE}

= 0

65

I_{PP_5V}= 0, I_{PP_HV}≤ 5 A, I_{PP_CABLE}

≤ 315 mA

85

I_{PP_5V}= 0, I_{PP_HV}≤ 3.5 A, I

_{PP_CABLE}≤ 315 mA

105

T_{J_PPHV}

T_J

Operating junction temperature

PP_HV switch

–40

150

125

°C

(1) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.

(2) All VBUS and VBUS_IN pins be shorted together.

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7.3.2 TPS25750S - Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

3.0

4.9

4

MAX

3.6

5.5

22

UNIT

VIN_3V3

PP5V

V_I

Input voltage range ⁽¹⁾

V

VBUS

VSYS

0

22

I2Cx_SDA, I2Cx_SCL, I2Cx_IRQ,

ADCIN1, ADCIN2

0

3.6

V_IO

I/O voltage range ⁽¹⁾

V

GPIOx

0

5.5

3

CC1, CC2

VBUS

A

I_O

Output current (from PP5V)

CC1, CC2

315

mA

I_O

Output current (from LDO_3V3)

Output current (from VBUS LDO)

GPIOx

1

5

mA

sum of current from LDO_3V3 and

GPIOx

mA

I_{PP_5V}≤ 1.5 A, I_{PP_CABLE}≤ 315 mA

I_{PP_5V}≤ 3 A, I_{PP_CABLE}≤ 315 mA

–40

105

85

T_A

T_J

Ambient operating temperature

Operating junction temperature

°C

125

(1) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.

7.4 Recommended Capacitance

over operating free-air temperature range (unless otherwise noted)

PARAMETER⁽¹⁾

VOLTAGE RATING

MIN

5

NOM

10

MAX

UNIT

µF

C_{VIN_3V3}

C_{LDO_3V3}

C_{LDO_1V5}

C_VBUS

Capacitance on VIN_3V3

6.3 V

4 V

Capacitance on LDO_3V3

Capacitance on LDO_1V5

Capacitance on VBUS⁽⁴⁾

Capacitance on PP5V

5

10

25

12

10

µF

4.5

µF

25 V

10 V

1

4.7

47

µF

C_PP5V

120⁽²⁾

µF

Capacitance on VSYS Sink from

VBUS

C_VSYS(TPS25750S)

25 V

100

µF

Capacitance on PPHV Sink from

VBUS

C_PPHV(TPS25750D)

C_CCy

25 V

47

100

480

µF

pF

Capacitance on CCy pins⁽³⁾

6.3 V

200

400

(1) Capacitance values do not include any derating factors. For example, if 5.0 µF is required and the external capacitor value reduces by

50% at the required operating voltage, then the required external capacitor value would be 10 µF.

(2) This is a requirement from USB PD (cSrcBulkShared). Keep at least 10 µF tied directly to PP5V.

(3) This includes all external capacitance to the Type-C receptacle.

(4) The device can be configured to quickly disable the sinking power path upon certain events. When such a configuration is used, a

capacitance on the higher side of this range is recommended.

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7.5 Thermal Information

7.5.1 TPS25750D - Thermal Information

TPS25750D

QFN (RJK)

38 PINS

THERMAL METRIC⁽¹⁾

UNIT

Junction-to-ambient thermal resistance

(sinking through PP_HV)

57.4

46.5

30.5

20.3

21.1

11.1

18.2

1.0

°C/W

R_θJA

Junction-to-ambient thermal resistance

(sourcing through PP_5V)

Junction-to-case (top) thermal resistance

(sinking through PP_HV)

R_θJC(top)

Junction-to-case (top) thermal resistance

(sourcing through PP_5V)

Junction-to-board thermal resistance

(sinking through PP_HV)

R_θJB

Junction-to-board thermal resistance

(sourcing through PP_5V)

Junction-to-top characterization parameter

(sinking through PP_HV)

ψ_JT

Junction-to-top characterization parameter

(sourcing through PP_5V)

Junction-to-board characterization

parameter (sinking through PP_HV)

21.1

11.1

1.8

ψ_JB

Junction-to-board characterization

parameter (sourcing through PP_5V)

Junction-to-case (bottom GND pad)

thermal resistance

R_θJC(bot_GND)

Junction-to-case (bottom DRAIN pad)

thermal resistance

R_θJC(bot_DRAIN)

4.6

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5.2 TPS25750S - Thermal Information

TPS25750S

THERMAL METRIC⁽¹⁾

QFN (RSM)

32 PINS

30.5

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

Junction-to-case (top) thermal resistance

24.5

Junction-to-board (bottom) thermal

resistance

R_θJC

2

°C/W

R_θJB

ψ_JT

Junction-to-board thermal resistance

9.8

0.2

°C/W

Junction-to-top characterization parameter

Junction-to-board characterization

parameter

ψ_JB

9.7

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

10

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SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020

7.6 Power Supply Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤ V_{VIN_3V3}≤ 3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

VIN_3V3, VBUS

rising

falling

3.6

3.5

3.9

3.8

V_{VBUS_UVLO}

VBUS UVLO threshold

hysteresis

0.1

2.66

2.54

0.12

rising, V_VBUS= 0

falling, V_VBUS= 0

hysteresis

2.56

2.44

2.76

2.64

Voltage required on VIN_3V3 for

power on

V_{VIN3V3_UVLO}

V

LDO_3V3, LDO_1V5

V_{LDO_3V3}

V_{VIN_3V3}= 0 V, 10 µA ≤ I_LOAD

18 mA, _VBUS≥ 3.9 V

≤

Voltage on LDO_3V3

3.0

3.4

1.5

3.6

1.4

V

Ω

V

R_{LDO_3V3}

Rdson of VIN_3V3 to LDO_3V3 I_{LDO_3V3}= 50 mA

up to maximum internal loading

condition

V_{LDO_1V5}

Voltage on LDO_1V5

1.49

1.65

7.7 Power Consumption

Operating under these conditions unless otherwise noted: 3.0 V ≤ V_{VIN_3V3}≤ 3.6 V, no GPIO loading

PARAMETER

TEST CONDITIONS

MIN

TYP

3

MAX UNIT

I_{VIN_3V3,ActSrc}

I_{VIN_3V3,ActSnk}

I_{VIN_3V3,IdlSrc}

I_{VIN_3V3,IdlSnk}

Current into VIN_3V3

Active Source mode: V_VBUS= 5.0 V, V_{VIN_3V3}= 3.3 V

Active Sink mode: 22 V ≥ V_VBUS≥ 4.0 V, V_{VIN_3V3}= 3.3 V

Idle Source mode: V_VBUS= 5.0 V, V_{VIN_3V3}= 3.3 V

Idle Sink mode: 22 V ≥ V_VBUS≥ 4.0 V, V_{VIN_3V3}= 3.3 V

mA

Current into VIN_3V3

3

6

mA

1.0

Power drawn into PP5V CCm floating, V_CCn= 0.4 V, V_PP5V= 5 V, V_{VIN_3V3}= 3.3 V, V

and VIN_3V3 in Modern _VBUS= 5.0 V, GATE_VBUS, GATE_VSYS disabled, and T_J

P_MstbySnk

4.1

4.5

mW

Standby Sink Mode

= 25°C

Power drawn into PP5V

and VIN_3V3 in Modern

Standby Source Mode

CCm floating, CCn tied to GND through 5.1 kΩ, V_PP5V= 5

V, V_{VIN_3V3}= 3.3 V, I_VBUS= 0, T_J= 25°C

P_MstbySrc

Sleep source mode: V_{PA_VBUS}= 0 V, V_{PB_VBUS}= 0 V, V

_{VIN_3V3}= 3.3 V

I_PP5V,Sleep

Current into PP5V

2

µA

I_{VIN_3V3,Sleep}

Current into VIN_3V3

Sleep DRP mode: V_VBUS= 0 V, V_{VIN_3V3}= 3.3 V

56

7.8 PP_5V Power Switch Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤ V_{VIN_3V3}≤ 3.6 V

PARAMETER

TEST CONDITIONS

I_LOAD= 3 A, T_J= 25°C

I_LOAD= 3 A,T_J= 125°C

MIN

TYP

MAX

UNIT

R_{PP_5V}

Resistance from PP5V to VBUS

36

38

53

mΩ

V_PP5V= 0 V, V_VBUS= 5.5 V,

PP_5V disabled, T_J≤ 85°C,

measure I_PP5V

I_{PP5V_REV}

VBUS to PP5V leakage current

PP5V to VBUS leakage current

5

µA

V_PP5V= 5.5 V, V_VBUS= 0 V,

PP_5V disabled, T_J≤ 85°C,

measure I_VBUS

I_{PP5V_FWD}

15

I_LIM5V

Current limit setting

Configure to setting 0

Configure to setting 1

1.15

1.61

2.3

1.36

1.90

2.70

3.58

3.78

A

Configure to setting 3

Configure to setting 4

3.04

3.22

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SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020

Operating under these conditions unless otherwise noted: 3.0 V ≤ V_{VIN_3V3}≤ 3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PP5V to VBUS current sense

accuracy

I_VBUS

3.64 A ≥ I_VBUS≥ 1 A

3.05

3.5

3.75

A/V

RCP clears and PP_5V starts turning

on when V_VBUS– V_PP5V< V

_{PP_5V_RCP}. Measure V_VBUS– V_PP5V

V_{PP_5V_RCP}

10

20

mV

µs

VBUS to GND through 10

mΩ, C_VBUS= 0

t_{iOS_PP_5V}

Response time to VBUS short circuit

1.15

4.5

Enable PP_5V, I_RpDefbeing

drawn from PP5V,

configure V_OVP4RCPto

setting 2, ramp V_VBUSfrom

t_{PP_5V_ovp}

Response time to V_VBUS> V_OVP4RCP4V to 20 V at 100 V/ms, C

µs

_PP5V= 2.5 µF, measure

time from OVP detection

until reverse current < 100

mA

Response time to V_PP5V< V

R_L= 100 Ω, no external

_{PP5V_UVLO}, PP_VBUS is deemed off

capacitance on VBUS

t_{PP_5V_uvlo}

4

when V_VBUS< 0.8 V

V_PP5V= 5.5 V, I_RpDefbeing

drawn from PP5V, enable

PP_5V, configure V_OVP4RCP

to setting 2, ramp V_VBUS

Response time to V_PP5V< V_VBUS+ V from 4 V to 21.5 V at 10

t_{PP_5V_rcp}

0.7

µs

V/µs, measure V_PP5V. C

PP_5V_RCP

_PP5V= 104 µF, C_VBUS=10

µF, measure time from

RCP detection until reverse

current < 100 mA

t_ILIM

t_ON

Current clamping deglitch time

5.1

3.3

ms

From enable signal to VBUS at 90% R_L= 100 Ω, V_PP5V= 5 V, C

2.3

0.30

1.2

4.3

0.6

of final value

From disable signal to VBUS at 10% R_L= 100 Ω, V_PP5V= 5 V, C

of final value _L= 0

_L= 0

t_OFF

t_RISE

t_FALL

0.45

1.7

ms

VBUS from 10% to 90% of final value R_L= 100 Ω, V_PP5V= 5 V, C

_L= 0

2.2

VBUS from 90% to 10% of initial

value

R_L= 100 Ω, V_PP5V= 5 V, C

_L= 0

0.06

0.1

0.14

7.9 PPHV Power Switch Characteristics - TPS25750D

Operating under these conditions unless otherwise noted: 3.0 V ≤ V_{VIN_3V3}≤ 3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

T_{J_PPHV}= 25°C, I_PPHV= 6.5

A

16

19

mΩ

Resistance from VBUS_IN to PPHV T_{J_PPHV}= 125°C, I_PPHV

=

R_PPHV

24

27

6

29

32

10

12

14

16

power switch resistance

6.5A

T_{J_PPHV}= 150°C, I_PPHV

6.5 A

=

mΩ

mV

Setting 0, 4 V ≤ V_VBUS≤ 22

V, V_{VIN_3V3}≤ 3.63 V

2

4

6

8

setting 1, 4 V ≤ V_VBUS≤ 22

V, V_{VIN_3V3}≤ 3.63 V

8

Comparator mode RCP threshold, V

_PPHV- V_VBUS

V_RCP

Setting 2, 4 V ≤ V_VBUS≤ 22

V, V_{VIN_3V3}≤ 3.63 V

10

12

Setting 3, 4 V ≤ V_VBUS≤ 22

V, V_{VIN_3V3}≤ 3.63 V

12

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SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020

Operating under these conditions unless otherwise noted: 3.0 V ≤ V_{VIN_3V3}≤ 3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

4 V ≤ V_VBUS≤ 22 V, I_LOAD

100 mA, 500 pF < C

_{GATE_VSYS}< 16 nF,

measure slope from 10% to

90% of final VSYS value

=

Soft start slew rate for GATE_VSYS,

setting 0

0.35

0.41

0.47

4 V ≤ V_VBUS≤ 22 V, I_LOAD

100 mA, 500 pF < C

_{GATE_VSYS}< 16 nF,

measure slope from 10% to

90% of final VSYS value

=

Soft start slew rate for GATE_VSYS,

setting 1

0.67

1.33

2.8

0.81

1.7

0.95

2.0

SS

V/ms

4 V ≤ V_VBUS≤ 22 V, I_LOAD

100 mA, 500 pF < C

_{GATE_VSYS}< 16 nF,

measure slope from 10% to

90% of final VSYS value

=

Soft start slew rate for GATE_VSYS,

setting 2

4 V ≤ V_VBUS≤ 22 V, I_LOAD

100 mA, 500 pF < C

_{GATE_VSYS}< 16 nF,

measure slope from 10% to

90% of final VSYS value

=

Soft start slew rate for GATE_VSYS,

setting 3

3.3

3.80

1000

V_VBUS= 20 V, V_PPHV= 20 V

(initially), C_PPHV< 1 nF, I

_PPHV= 0.1 A, switch is off

Time allowed to disable the internal

PPHV switch in normal shutdown

mode

t_{PPHV_OFF}

400

µs

when V_{VBUS_IN}– V_PPHV

1V

>

OVP: V_OVP4RCP= setting

57, V_VBUS= 20 V initially,

then raised to 23 V in 50

Time allowed to disable the internal

PPHV switch in fast shutdown mode ns, V_PPHV= V

t_{PPHV_OVP}

2

4

(V_OVP4RCPexceeded), this includes

the response time of the comparator nF, I_PPHV= 0.1 A, switch is

off when V_{VBUS_IN}– V

_{VBUS_IN}(initially), C_PPHV< 1

_PPHV> 0.1 V

RCP: V_RCP= setting 0, V

_VBUS= 5 V, V_VSYS= 5 V

Time allowed to disable the internal

PPHV switch in fast shutdown mode with dV/dt = 0.1 V/µs, C

initially, then raised to 6 V

t_{PPHV_RCP}

1

2

µs

(V_RCPexceeded), this includes the

response time of the comparator

_VBUS=10 µF, measure time

from V_VSYS> V_BUS+ V_RCP

to the time of peak voltage

on VBUS

V_PPHV= 20 V (initially), V

_VBUS=20 V then raised to

23 V in 50 ns, r_OVP= 1, C

_PPHV< 1 nF, I_PPHV= 0.1 A,

switch is off when V_{VBUS_IN}

– V_PPHV> 0.5 V

Time allowed to disable the internal

PPHV switch in fast shutdown mode

(OVP)

t_{PPHV_FSD}

0.25

20

μs

V_{VBUS_IN}= 5 V, C_PPHV= 0, I

_PPHV= 0, measure time

from register write to

enable PPHV until V

_{VBUS_IN}- V_PPHV< 0.1 V,

soft start setting 3

Time to enable the internal PPHV

switch

t_{PPHV_ON}

1500

1800

2100

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SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020

7.10 PP_EXT Power Switch Characteristics - TPS25750S

Operating under these conditions unless otherwise noted: , 3.0 V ≤ V_{VIN_3V3}≤ 3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

0 ≤ V_{GATE_VSYS}- V_VSYS≤ 6

V, V_VSYS≤ 22 V, V_VBUS> 4

V, measure I_{GATE_VSYS}

8.5

11.5

µA

I_{GATE_ON}

Gate driver sourcing current

0 ≤ V_{GATE_VBUS}- V_VBUS≤ 6

V, 4 V ≤ V_VBUS≤ 22 V,

measure I_{GATE_VBUS}

8.5

6

11.5

12

µA

V

0 ≤ V_VSYS≤ 22 V, I

_{GATE_VSYS}< 4 µA, measure

V_{GATE_VSYS}– V_VSYS, V_VBUS

> 4 V

V_{GATE_ON}

Sourcing voltage (ON)

4 V ≤ V_VBUS≤ 22 V, I

_{GATE_VBUS}< 4 µA, measure

V_{GATE_VBUS}– V_VBUS

6

12

V

Setting 0, 4 V ≤ V_VBUS≤ 22

V, V_{VIN_3V3}≤ 3.63 V

2

4

6

8

6

8

10

12

14

16

mV

Setting 1, 4 V ≤ V_VBUS≤ 22

V, V_{VIN_3V3}≤ 3.63 V

Comparator mode RCP threshold, V

_VSYS- V_VBUS

V_RCP

Setting 2, 4 V ≤ V_VBUS≤ 22

V, V_{VIN_3V3}≤ 3.63 V

10

12

Setting 3, 4 V ≤ V_VBUS≤ 22

V, V_{VIN_3V3}≤ 3.63 V

Normal turnoff: V_VSYS= 5

V, V_{GATE_VSYS}= 6 V,

measure I_{GATE_VSYS}

13

µA

I_{GATE_OFF}

Sinking strength

Normal turnoff: V_VBUS= V

_VSYS= 5 V, V_{GATE_VBUS}= 6

V, measure I_{GATE_VBUS}

Fast turnoff: V_VSYS= 5 V, V

_{GATE_VSYS}= 6 V, assert

PPHV1_FAST_DISABLE,

measure R_{GATE_VSYS}

85

Ω

R_{GATE_FSD}

Sinking strength

Fast turnoff: V_VBUS= V_VSYS

= 5 V, V_{GATE_VBUS}= 6 V,

assert

PPHV1_FAST_DISABLE,

measure R_{GATE_VBUS}

V_{VIN_3V3}= 0 V, V_VBUS= 3.0

V, V_{GATE_VSYS}= 0.1 V,

measure resistance from

GATE_VSYS to GND

R_{GATE_OFF_UVLO}

Sinking strength in UVLO (safety)

1.5

MΩ

14

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SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020

Operating under these conditions unless otherwise noted: , 3.0 V ≤ V_{VIN_3V3}≤ 3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

4 V ≤ V_VBUS≤ 22 V, I_LOAD

100 mA, 500 pF < C

_{GATE_VSYS}< 16 nF,

measure slope from 10% to

90% of final VSYS value

=

Soft start slew rate for GATE_VSYS,

setting 0

0.35

0.41

0.47

4 V ≤ V_VBUS≤ 22 V, I_LOAD

100 mA, 500 pF < C

_{GATE_VSYS}< 16 nF,

measure slope from 10% to

90% of final VSYS value

=

Soft start slew rate for GATE_VSYS,

setting 1

0.67

1.33

2.8

0.81

1.7

0.91

1.80

3.80

4000

SS

V/ms

4 V ≤ V_VBUS≤ 22 V, I_LOAD

100 mA, 500 pF < C

_{GATE_VSYS}< 16 nF,

measure slope from 10% to

90% of final VSYS value

=

Soft start slew rate for GATE_VSYS,

setting 2

4 V ≤ V_VBUS≤ 22 V, I_LOAD

100 mA, 500 pF < C

_{GATE_VSYS}< 16 nF,

measure slope from 10% to

90% of final VSYS value

=

Soft start slew rate for GATE_VSYS,

setting 3

3.3

V_VBUS= 20 V, Q_Gof

Time allowed to disable the external external FET = 40 nC or C

t_{GATE_VBUS_OFF}

FET via GATE_VBUS in normal

_{GATE_VBUS}< 3 nF, gate is off

when V_{GATE_VBUS}– V_VBUS

< 1 V

450

µs

shutdown mode.⁽¹⁾

OVP: V_OVP4RCP= setting

Time allowed to disable the external 57, V_VBUS= 20 V initially,

FET via GATE_VBUS in fast

shutdown mode (V_OVP4RCP

exceeded), this includes the

response time of the comparator⁽¹⁾

then raised to 23 V in 50

ns, Q_Gof external FET = 40

nC or C_{GATE_VBUS}< 3 nF,

gate is off when V

t_{GATE_VBUS_OVP}

3

5

_{GATE_VBUS}– V_VBUS< 1 V

RCP: V_RCP= setting 0, V

Time allowed to disable the external _VBUS= 5 V, V_VSYS= 5 V

FET via GATE_VBUS in fast

shutdown mode (V_RCPexceeded),

initially, then raised to 5.5 V

in 50 ns, Q_Gof external

t_{GATE_VBUS_RCP}

1

2

µs

this includes the response time of the FET = 40 nC or C_{GATE_VBUS}

comparator⁽¹⁾

< 3 nF, gate is off when V

_{GATE_VBUS}– V_VBUS< 1 V

V_VSYS= 20 V, Q_Gof

Time allowed to disable the external external FET = 40 nC or C

t_{GATE_VSYS_OFF}

FET via GATE_VSYS in normal

_{GATE_VBUS}< 3 nF, gate is off

when V_{GATE_VSYS}– V_VSYS

< 1 V

450

4000

shutdown mode⁽¹⁾

V_VBUS= 20 V initially, then

raised to 23 V in 50 ns, Q_G

of external FET = 40 nC or

C_{GATE_VBUS}< 3 nF, gate is

off when V_{GATE_VSYS}– V

_VSYS< 1 V, r_OVP= 1

Time allowed to disable the external

FET via GATE_VSYS in fast

shutdown mode (OVP)⁽¹⁾

t_{GATE_VSYS_FSD}

0.25

20

2

μs

Measure time from when V

_GS= 0 V until V_GS>3 V,

t_{GATE_VBUS_ON}

Time to enable GATE_VBUS ⁽¹⁾

ms

where V_GS= V_{GATE_VBUS}

V_VBUS

–

(1) These values depend upon the characteristics of the external N-ch MOSFET. The typical values were measured when

Px_GATE_VSYS and Px_GATE_VBUS were used to drive two CSD17571Q2 in common drain back-to-back configuration.

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SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020

7.11 Power Path Supervisory

Operating under these conditions unless otherwise noted: 3.0 V ≤ V_{VIN_3V3}≤ 3.6 V

PARAMETER

TEST CONDITIONS

MIN

5.0

TYP

MAX

24

UNIT

VBUS overvoltage protection for RCP OVP detected when V_VBUS

>

V_OVP4RCP

V

programmable range

Hysteresis

V_OVP4RCP

V_OVP4RCPH

1.75

2

1

2.25

%

setting 0

setting 1

setting 2

setting 3

V/V

Ratio of OVP4RCP input used for

OVP4VSYS comparator. r_OVP× V

0.95

0.90

0.875

r_OVP

= V_OVP4RCP

OVP4VSYS

VBUS overvoltage protection range for OVP detected when r_OVP

×

V_OVP4VSYS

5

1.75

1.8

1.9

2

27.5

2.25

2.4

V

VSYS protection

Hysteresis

V_VBUS> V_OVP4RCP

VBUS falling, % of V

_OVP4VSYS, r_OVPsetting 0

2

2.1

2.2

2.3

VBUS falling, % of V

_OVP4VSYS, r_OVPsetting 1

V_OVP4VSYS

%

VBUS falling, % of V

2.5

_OVP4VSYS, r_OVPsetting 2

VBUS falling, % of V

_OVP4VSYS, r_OVPsetting 3

2.6

rising

3.9

3.8

4.1

4.0

0.1

4.3

4.2

V_{PP5V_UVLO}

Voltage required on PP5V

VBUS discharge current

falling

V

hysteresis

V_VBUS= 22 V, measure I

I_DSCH

4

15

mA

VBUS

7.12 CC Cable Detection Parameters

Operating under these conditions unless otherwise noted: 3.0 V ≤ V_{VIN_3V3}≤ 3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Type-C Source (Rp pullup)

Unattached CCy open circuit

voltage while Rp enabled, no load

V_{OC_3.3}

V_{OC_5}

V_{LDO_3V3}> 2.302 V, R_CC= 47 kΩ

V_PP5V> 3.802 V, R_CC= 47 kΩ

1.85

2.95

V

Attached CCy open circuit voltage

while Rp enabled, no load

V_CCy= 5.5 V, V_CCx= 0 V, V

_{LDO_3V3_UVLO}< V_{LDO_3V3}< 3.6 V, V

_PP5V= 3.8 V, measure current into

CCy

10

Unattached reverse current on

CCy

I_Rev

µA

V_CCy= 5.5 V, V_CCx= 0 V, V

_{LDO_3V3_UVLO}< V_{LDO_3V3}< 3.6 V, V

_PP5V= 0, T_J≤ 85°C, measure

current into CCy

I_RpDef

I_Rp1.5

Current source - USB Default

Current source - 1.5 A

0 < V_CCy< 1.0 V, measure I_CCy

64

80

96

µA

4.75 V < V_PP5V< 5.5 V, 0 < V_CCy

1.5 V, measure I_CCy

<

166

180

194

4.75 V < V_PP5V< 5.5 V, 0 < V_CCy

2.45 V, measure I_CCy

I_Rp3.0

Current source - 3.0 A

304

330

356

µA

V

Type-C Sink (Rd pulldown)

Open/Default detection threshold

when Rd applied to CCy

V_SNK1

rising

falling

0.2

0.24

0.20

Open/Default detection threshold

when Rd applied to CCy

0.16

V

V_SNK1

Hysteresis

0.04

16

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SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020

Operating under these conditions unless otherwise noted: 3.0 V ≤ V_{VIN_3V3}≤ 3.6 V

PARAMETER

TEST CONDITIONS

MIN

0.62

0.63

TYP

MAX

0.68

0.69

UNIT

V_SNK2

Default/1.5-A detection threshold

Hysteresis

falling

rising

V

0.66

0.01

1.5-A/3.0-A detection threshold

when Rd applied to CCy

V_SNK3

falling

rising

1.17

1.22

1.25

1.3

V

1.5-A/3.0-A detection threshold

when Rd applied to CCy

V

V_SNK3

Hysteresis

0.05

0.25 V ≤ V_CCy≤ 2.1 V, measure

resistance on CCy, after trimming

R_SNK

Rd pulldown resistance

4.6

4.0

5.6

kΩ

using trim_cd_rd, V_{LDO_3V3_UVLO}

V_{LDO_3V3}< 3.6 V,

<

0V ≤ V_CCy≤ 5.5 V, measure

resistance on CCy, after trimming

using trim_cd_rd

R_{VCONN_DIS}

VCONN discharge resistance

Dead battery Rd clamp

6.12

V_{VIN_3V3}= 0 V, 64 µA < I_CCy< 96

µA

0.25

0.65

1.20

500

1.32

2.18

V_{VIN_3V3}= 0 V, 166 µA < I_CCy

194 µA

<

V_CLAMP

V

V_{VIN_3V3}= 0 V, 304 µA < I_CCy

356 µA

<

V_VBUS= 0, V_{VIN_3V3}= 3.3 V, V_CCy

= 5 V, measure resistance on CCy

kΩ

Resistance from CCy to GND

when configured as open

R_Open

V_VBUS= 5 V, V_{VIN_3V3}= 0, V_CCy

=

5 V, measure resistance on CCy

7.13 CC VCONN Parameters

Operating under these conditions unless otherwise noted: 3.0 V ≤ V_{VIN_3V3}≤ 3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

V_PP5V= 5 V, I_L= 250 mA,

measure resistance from PP5V

to CCy

R_{PP_CABLE}

Rdson of the VCONN path

1.2

Ω

Setting 0, V_PP5V= 5 V, R_L=10

mΩ, measure I_CCy

I_LIMVC

Short circuit current limit

350

540

410

600

470

660

mA

Setting 1, V_PP5V= 5 V, R_L=10

mΩ, measure I_CCy

VCONN disabled, T_J≤ 85°C, V

_CCy= 5.5 V, V_PP5V= 0 V, V_VBUS

= 5 V, LDO forced to draw from

VBUS, measure I_CCy

Reverse leakage current

through VCONN FET

I_CC2PP5V

10

µA

Overvoltage protection

threshold for PP_CABLE

V_{VC_OVP}

V_PP5Vrising

5.6

60

5.9

6.2

340

470

V

V_PP5V≥ 4.9 V, V_CCy= V_PP5V, V

_CCxrising

200

mV

Reverse current protection

threshold for PP_CABLE,

sourcing VCONN through CCx

V_{VC_RCP}

V_PP5V≥ 4.9 V, V_CCy≤ 4 V, V_CCx

rising

210

340

1.3

mV

ms

t_VCILIM

Current clamp deglitch time

Time to disable PP_CABLE

t_{PP_CABLE_FSD}

after V_PP5V> V_{VC_OVP}or V_CCx- C_L= 0

V_PP5V> V_{VC_RCP}

0.5

µs

From disable signal to CCy at

10% of final value

I_L= 250 mA, V_PP5V= 5 V, C_L=

0

t_{PP_CABLE_off}

100

200

300

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Operating under these conditions unless otherwise noted: 3.0 V ≤ V_{VIN_3V3}≤ 3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

V_PP5V= 5 V, for short circuit R_L

= 10 mΩ

t_{iOS_PP_CABLE}

Response time to short circuit

2

µs

7.14 CC PHY Parameters

Operating under these conditions unless otherwise noted: and ( 3.0 V ≤ V_{VIN_3V3}≤ 3.6 V or V_VBUS≥ 3.9 V )

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Transmitter

V_TXHI

Transmit high voltage on CCy

Transmit low voltage on CCy

Standard External load

1.05

–75

1.125

1.2

75

V

V_TXLO

mV

Transmit output impedance while

driving the CC line using CCy

Z_DRIVER

measured at 750 kHz

33

54

75

Ω

Rise time. 10 % to 90 % amplitude

points on CCy, minimum is under

an unloaded condition. Maximum

set by TX mask

t_Rise

C_CCy= 520 pF

300

ns

Fall time. 90 % to 10 % amplitude

points on CCy, minimum is under

an unloaded condition. Maximum

set by TX mask

t_Fall

C_CCy= 520 pF

300

5.5

ns

V

0 ≤ V_{VIN_3V3}≤ 3.6 V, 0 ≤ V_PP5V

≤

OVP detection threshold for USB 5.5 V, V_VBUS≥ 4 V. Initially V_CC1

PD PHY 5.5 V and V_CC2≤ 5.5 V, then V_CCx

≤

V_{PHY_OVP}

8.5

rises

Receiver

Does not include pullup or

Z_BMCRX

Receiver input impedance on CCy pulldown resistance from cable

detect. Transmitter is Hi-Z

1

MΩ

Capacitance looking into the CC

Receiver capacitance on CCy⁽¹⁾

C_CC

120

551

866

270

578

pF

pin when in receiver mode

Rising threshold on CCy for

Sink mode (rising)

V_{RX_SNK_R}

V_{RX_SRC_R}

V_{RX_SNK_F}

V_{RX_SRC_F}

499

784

230

523

525

825

250

550

mV

receiver comparator

Rising threshold on CCy for

Source mode (rising)

receiver comparator

Falling threshold on CCy for

Sink mode (falling)

receiver comparator

Falling threshold on CCy for

Source mode (falling)

receiver comparator

(1) C_CCincludes only the internal capacitance on a CCy pin when the pin is configured to be receiving BMC data. External capacitance is

needed to meet the required minimum capacitance per the USB-PD Specifications (cReceiver). Therefore, TI recommends adding C

_CCyexternally.

7.15 Thermal Shutdown Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

Temperature rising

Hysteresis

MIN

TYP

160

15

MAX

UNIT

°C

145

175

T_{SD_MAIN}

Temperature shutdown threshold

°C

Temperature controlled shutdown Temperature rising

threshold. The power paths for

135

150

165

°C

each port sourcing from PP5V and

T_{SD_PP5V}

PP_CABLE power paths have

local sensors that disables them

when this temperature is exceeded

Hysteresis

10

°C

18

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7.16 ADC Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤ V_{VIN_3V3}≤ 3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

3.6-V max scaling, voltage

divider of 3

14

mV

LSB

Least significant bit

25.2-V max scaling, voltage

divider of 21

98

mV

mA

4.07-A max scaling

16.5

0.05 V ≤ V_ADCINx≤ 3.6 V, V

_ADCINx≤ V_{LDO_3V3}

–2.7

2.7

0.05 V ≤ V_GPIOx≤ 3.6 V, V_GPIOx

≤ V_{LDO_3V3}

GAIN_ERR

Gain error

%

2.7 V ≤ V_{LDO_3V3}≤ 3.6 V

0.6 V ≤ V_VBUS≤ 22 V

1 A ≤ I_VBUS≤ 3 A

–2.4

–2.1

2.4

2.1

0.05 V ≤ V_ADCINx≤ 3.6 V, V

_ADCINx≤ V_{LDO_3V3}

–4.1

4.1

0.05 V ≤ V_GPIOx≤ 3.6 V, V_GPIOx

≤ V_{LDO_3V3}

mV

mA

VOS_ERR

Offset error⁽¹⁾

2.7 V ≤ V_{LDO_3V3}≤ 3.6 V

0.6 V ≤ V_VBUS≤ 22 V

1 A ≤ I_VBUS≤ 3 A

–4.5

–4.1

–4.5

4.5

4.1

4.5

(1) The offset error is specified after the voltage divider.

7.17 Input/Output (I/O) Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤ V_{VIN_3V3}≤ 3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

USB_P, USB_N

GPIO_VIH

GPIOx high-Level input voltage V_{LDO_3V3}= 3.3 V

GPIOx low-level input voltage V_{LDO_3V3}= 3.3 V

GPIOx input hysteresis voltage V_{LDO_3V3}= 3.3 V

1.3

V

GPIO_VIL

0.54

GPIO_HYS

0.09

–1

V

GPIO_ILKG

GPIO_RPU

GPIOx leakage current

GPIOx internal pullup

GPIOx internal pulldown

GPIOx input deglitch

V_GPIOx= 3.45 V

Pullup enabled

Pulldown enabled

1

150

50

µA

kΩ

ns

50

100

20

GPIO_RPD

50

GPIO_DG

GPIO0-7 (Outputs)

GPIO_VOH

GPIOx output high voltage

GPIOx output low voltage

V_{LDO_3V3}= 3.3 V, I_GPIOx= -2 mA

V_{LDO_3V3}= 3.3 V, I_GPIOx= 2 mA

2.9

–1

V

GPIO_VOL

0.4

1

ADCIN1, ADCIN2

ADCIN_ILKG

ADCINx leakage current

V_ADCINx≤ V_{LDO_3V3}

µA

ms

Time from LDO_3V3 going high

until ADCINx is read for

configuration

t_BOOT

10

7.18 BC1.2 Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤ V_{VIN_3V3}≤ 3.6 V

PARAMETER

DATA CONTACT DETECT

I_{DP_SRC}DCD source current

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_{LDO_3V3}= 3.3 V

7

10

13

µA

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Operating under these conditions unless otherwise noted: 3.0 V ≤ V_{VIN_3V3}≤ 3.6 V

PARAMETER

TEST CONDITIONS

MIN

14.25

TYP

20

MAX

24.8

UNIT

kΩ

R_{DM_DWN}

R_{DP_DWN}

DCD pulldown resistance

V_{USB_N}= 3.6 V

V_{USB_P}= 3.6 V

20

kΩ

V_{USB_P}≥ V_{LGC_HI}, V_{LDO_3V3}= 3.3 V, R

_{USB_P}= 300 kΩ

V_{LGC_HI}

V_{LGC_LO}

Threshold for no connection

Threshold for connection

2

0

3.6

0.8

V

V_{USB_N}≤ V_{LGC_LO}, V_{LDO_3V3}= 3.3 V, R

_{USB_P}= 24.8 kΩ

Advertisement and Detection

V_{DX_SRC}

V_{DX_ILIM}

I_{DX_SNK}

Source voltage

VDX_SRC current limit

Sink Current

C_GPIO4≤ 600 pF

0.55

250

25

0.6

0.65

400

125

V

µA

V_{USB_P}≥ 250 mV

V_{USB_N}≥ 250 mV

75

Sink Current

25

0.5 V ≤ V_{USB_P}≤ 0.7 V, 25 µA ≤ I_{USB_N}

≤ 175 µA

R_{DCP_DAT}

Dedicated Charging Port Resistance

200

Ω

7.19 I2C Requirements and Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤ V_{VIN_3V3}≤ 3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I2Cs_IRQ

OD_VOL_IRQ

OD_LKG_IRQ

I2Cm_IRQ

Low level output voltage

Leakage Current

I_OL= 2 mA

0.4

1

V

Output is Hi-Z, V_{I2Cx_IRQ}= 3.45 V

–1

µA

IRQ_VIH

High-Level input voltage

V_{LDO_3V3}= 3.3 V

1.3

V

IRQ_VIH_THRESH

IRQ_VIL

High-Level input voltage threshold V_{LDO_3V3}= 3.3 V

0.72

1.3

0.54

1.08

low-level input voltage

low-level input voltage threshold

input hysteresis voltage

input deglitch

V_{LDO_3V3}= 3.3 V

V

IRQ_VIL_THRESH

IRQ_HYS

0.54

0.09

V

IRQ_DEG

20

ns

µA

IRQ_ILKG

I2C3m_IRQ leakage current

V_{I2C3m_IRQ}= 3.45 V

–1

1

SDA and SCL Common Characteristics (Master, Slave)

V_IL

Input low signal

V_{LDO_3V3}= 3.3 V

0.54

V

V_IH

Input high signal

V_{LDO_3V3}= 3.3 V

1.3

V_HYS

V_OL

I_LEAK

I_OL

Input hysteresis

V_{LDO_3V3}= 3.3 V

0.165

V

Output low voltage

Input leakage current

Max output low current

I_OL= 3 mA

0.36

3

V

Voltage on pin = V_{LDO_3V3}

V_OL= 0.4 V

–3

15

20

12

µA

mA

ns

pF

I_OL

V_OL= 0.6 V

V_DD= 1.8 V, 10 pF ≤ C_b≤ 400 pF

V_DD= 3.3 V, 10 pF ≤ C_b≤ 400 pF

80

150

50

Fall time from 0.7 × V_DDto 0.3 × V

t_f

DD

t_SP

C_I

I²C pulse width surpressed

Pin capacitance (internal)

10

Capacitive load for each bus line

(external)

C_b

400

pF

SDA and SCL Standard Mode Characteristics (Slave)

f_SCLS

Clock frequency for slave

Valid data time

V_DD= 1.8 V or 3.3 V

100

kHz

µs

Transmitting Data, V_DD= 1.8 V or

3.3 V, SCL low to SDA output valid

t_VD;DAT

3.45

20

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Operating under these conditions unless otherwise noted: 3.0 V ≤ V_{VIN_3V3}≤ 3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Transmitting Data, V_DD= 1.8 V or

3.3 V, ACK signal from SCL low to

SDA (out) low

t_VD;ACK

Valid data time of ACK condition

3.45

µs

SDA and SCL Fast Mode Characteristics (Slave)

f_SCLS

Clock frequency for slave

V_DD= 1.8 V or 3.3 V

100

400

0.9

kHz

µs

Transmitting data, V_DD= 1.8 V,

SCL

t_VD;DAT

Valid data time

low to SDA output valid

Transmitting data, V_DD= 1.8 V or

3.3 V, ACK

signal from SCL low to SDA (out)

low

t_VD;ACK

Valid data time of ACK condition

0.9

µs

SDA and SCL Fast Mode Plus Characteristics (Slave)

Clock frequency for Fast Mode

f_SCLS

V_DD= 1.8 V or 3.3 V

400

800

kHz

µs

Plus⁽¹⁾

Transmitting data, V_DD= 1.8 V or

3.3 V, SCL

t_VD;DAT

Valid data time

0.55

low to SDA output valid

Transmitting data, V_DD= 1.8 V or

3.3 V, ACK

signal from SCL low to SDA (out)

low

t_VD;ACK

Valid data time of ACK condition

0.55

410

µs

SDA and SCL Fast Mode Characteristics (Master)

f_SCLM

Clock frequency for master

V_DD= 3.3 V

390

kHz

µs

Start or repeated start condition

hold time

t_HD;STA

0.6

t_LOW

t_HIGH

Clock low time

Clock high time

V_DD= 3.3 V

1.3

0.6

µs

Start or repeated start condition

setup time

t_SU;STA

V_DD= 3.3 V

0.6

µs

t_SU;DAT

t_SU;STO

Serial data setup time

Transmitting data, V_DD= 3.3 V

V_DD= 3.3 V

100

0.6

ns

µs

Stop condition setup time

Bus free time between stop and

start

t_BUF

V_DD= 3.3 V

1.3

µs

Transmitting data, V_DD= 3.3 V,

SCL low to SDA output valid

t_VD;DAT

Valid data time

0.9

Transmitting data, V_DD= 3.3 V,

ACK signal from SCL low to SDA

(out) low

t_VD;ACK

Valid data time of ACK condition

µs

(1) Master must control fSCLS to ensure tLOW > tVD; ACK.

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7.20 Typical Characteristics

50

48

46

44

42

40

38

36

34

32

1.05

1

0.95

0.9

0.85

0.8

0.75

0.7

0.65

0.6

-20

0

20

40

60

T_J(^oC)

80

100

120

140

-20

0

20

40

60

T_J(^oC)

80

100

120

140

TypG

Figure 7-2. PP_CABLE Rdson vs. Temperature

Figure 7-1. PP_5V Rdson vs. Temperature.

7.5

5.8

V_{Px_VBUS}= 4V

V_{Px_VBUS}= 22V

5.78

5.76

5.74

5.72

5.7

7

6.5

6

5.5

5

-50

0

50

T_J(^oC)

100

150

-60

-30

0

30

60

90

120

150

T_J(^oC)

TypG

Figure 7-4. V_OVP4RCP(Setting 2) vs. Temperature

Figure 7-3. V_RCPvs. Temperature

100

28

26

24

22

20

18

16

14

Single Pulse Duration

70

50

100 ms

10 ms

1 ms

100 ms

10 ms

30

20

10

7

5

3

2

1

0.7

0.5

0.3

0.2

0.1

0.2 0.3

0.5 0.7

1

2

3

4

5

6 7 8 10

20 30 40 50

-20

0

20

40

60

80

100 120 140 160

Source-to-Source Voltage (V)

SOAf

T_J(^oC)

TypG

Figure 7-6. Safe-Operating-Area (SOA) of PPHV for TPS25750D

Figure 7-5. R_PPHVvs. Temperature for TPS25750D

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7.20 Typical Characteristics (continued)

10.2

10.15

10.1

10.05

10

9.4

9.2

I_{GATE_VBUS}

I_{GATE_VSYS}

9

GATE_VSYS: VSYS= 0 V

GATE_VSYS: VSYS= 22 V

8.8

GATE_VBUS

8.6

8.4

8.2

8

9.95

9.9

9.85

7.8

-40

-20

0

20

40

60

T_J(^oC)

80

100

120

140

-20

0

20

40

60

80

100 120 140

T_J(^oC)

TypG

Figure 7-8. V_{GATE_VSYS_ON}vs. Temperature for TPS25750S

Figure 7-7. V_{GATE_VBUS_ON}vs. Temperature for TPS25750S

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8 Parameter Measurement Information

t

f

t

r

t

SU;DAT

70 %

30 %

70 %

30 %

SDA

cont.

t

HD;DAT

VD;DAT

t

f

t

HIGH

t

r

70 %

30 %

70 %

30 %

70 %

30 %

70 %

30 %

SCL

t

HD;STA

t

LOW

th

9

clock

1 / f

S

SCL

st

1

clock cycle

t

BUF

SDA

SCL

t

VD;ACK

t

SU;STO

SU;STA

HD;STA

SP

70 %

30 %

Sr

P

S

th

9

clock

002aac938

Figure 8-1. I²C Slave Interface Timing

I_LIM5V, I_LIMVC

t_{iOS_PP_5V}, t_{iOS_PP_CABLE}

Figure 8-2. Short-circuit Response Time for Internal Power Paths PP_5Vx and PP_CABLEx

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9 Detailed Description

9.1 Overview

The TPS25750 is a fully-integrated USB Power Delivery (USB-PD) management device providing cable plug and

orientation detection for USB Type-C and PD receptacles. The TPS25750 communicates with the cable and

another USB Type-C and PD device at the opposite end of the cable. It also enables integrated port power

switch for sourcing, and controls a high current port power switch for sinking.

The TPS25750 is divided into several main sections:

•

USB-PD controller

Cable plug and orientation detection circuitry

Port power switches

Power management circuitry

Digital core

The USB-PD controller provides the physical layer (PHY) functionality of the USB-PD protocol. The USB-PD

data is output through either the CC1 pin or the CC2 pin, depending on the orientation of the reversible USB

Type-C cable. For a high-level block diagram of the USB-PD physical layer, a description of its features, and

more detailed circuitry, see USB-PD Physical Layer.

The cable plug and orientation detection analog circuitry automatically detects a USB Type-C cable plug

insertion the cable orientation. For a high-level block diagram of cable plug and orientation detection, a

description of its features, and more detailed circuitry, see Cable Plug and Orientation Detection.

The port power switches provide power to the VBUS pin and CC1 or CC2 pins based on the detected plug

orientation. For a high-level block diagram of the port power switches, a description of its features, and more

detailed circuitry, see Power Paths.

The power management circuitry receives and provides power to the TPS25750 internal circuitry and LDO_3V3

output. See Power Management for more information.

The digital core provides the engine for receiving, processing, and sending all USB-PD packets as well as

handling control of all other TPS25750 functionality. A portion of the digital core contains ROM memory, which

contains all the necessary firmware required to execute Type-C and PD applications. In addition, a section of the

ROM, called boot code, is capable of initializing the TPS25750, loading of the device configuration information,

and loading any code patches into volatile memory in the digital core. For a high-level block diagram of the

digital core, a description of its features, and more detailed circuitry, see Digital Core.

The TPS25750 has one I²C master to write to and read from external slave devices such as a battery charger or

an optional external EEPROM memory (see I2C Interface).

The TPS25750 also integrates a thermal shutdown mechanism and runs off of accurate clocks provided by the

integrated oscillator.

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9.2 Functional Block Diagram

PPHV

PP5V

VBUS_IN

VBUS

LDO_3V3

LDO_1V5

Power Supervisor

VIN_3V3

GND

ADCIN1

ADCIN2

3

I2Cm_SDA/SCL/IRQ

Core & Other Digital

3

I2Cs_SDA/SCL/IRQ

CC1

CC2

Cable Detect, Cable Power, & USB

PD PHY

9

GPIO0-7,11

Figure 9-1. TPS25750D

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PA_VBUS

PP5V

3A

LDO_3V3

LDO_1V5

VSYS

VIN_3V3

GND

Power Supervisor

ADCIN1

ADCIN2

3

I2Cm_SDA/SCL/IRQ

I2Cs_SDA/SCL/IRQ

Core & Other Digital

PA_CC1

Cable Detect, Cable Power, & USB

PD PHY

9

PA_CC2

GPIO0-7,11

Figure 9-2. TPS25750S

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9.3 Feature Description

9.3.1 USB-PD Physical Layer

Figure 9-3 shows the USB PD physical layer block surrounded by a simplified version of the analog plug and

orientation detection block.

Fast

current

limit

I_VCON

PP5V

CC1 Gate Control and Current

Limit

LDO_3V3

I_Rp

R_SNK

CC1

Digital

Core

USB-PD PHY

(Rx/Tx)

CC2

LDO_3V3

I_Rp

R_SNK

CC1 Gate Control and Current

Limit

Fast

current

limit

Figure 9-3. USB-PD Physical Layer and Simplified Plug and Orientation Detection Circuitry

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USB-PD messages are transmitted in a USB Type-C system using a BMC signaling. The BMC signal is output

on the same pin (CC1 or CC2) that is DC biased due to the Rp (or Rd) cable attach mechanism.

9.3.1.1 USB-PD Encoding and Signaling

Figure 9-4 illustrates the high-level block diagram of the baseband USB-PD transmitter. Figure 9-5 illustrates the

high-level block diagram of the baseband USB-PD receiver.

4b5b

Encoder

BMC

Encoder

Data

to PD_TX

CRC

Figure 9-4. USB-PD Baseband Transmitter Block Diagram

Data

BMC

Decoder

SOP

Detect

4b5b

Decoder

from PD_RX

CRC

Figure 9-5. USB-PD Baseband Receiver Block Diagram

9.3.1.2 USB-PD Bi-Phase Marked Coding

The USB-PD physical layer implemented in the TPS25750 is compliant to the USB-PD Specifications. The

encoding scheme used for the baseband PD signal is a version of Manchester coding called Biphase Mark

Coding (BMC). In this code, there is a transition at the start of every bit time and there is a second transition in

the middle of the bit cell when a 1 is transmitted. This coding scheme is nearly DC balanced with limited disparity

(limited to 1/2 bit over an arbitrary packet, so a very low DC level). Figure 9-6 illustrates Biphase Mark Coding.

0

1

0

1

0

1

0

1

0

1

0

1

Data in

BMC

Figure 9-6. Biphase Mark Coding Example

The USB PD baseband signal is driven onto the CC1 or CC2 pin with a tri-state driver. The tri-state driver is slew

rate to limit coupling to D+/D– and to other signal lines in the Type-C fully featured cables. When sending the

USB-PD preamble, the transmitter starts by transmitting a low level. The receiver at the other end tolerates the

loss of the first edge. The transmitter terminates the final bit by an edge to ensure the receiver clocks the final bit

of EOP.

9.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks

The USB-PD driver meets the defined USB-PD BMC TX masks. Since a BMC coded “1” contains a signal edge

at the beginning and middle of the UI, and the BMC coded “0” contains only an edge at the beginning, the masks

are different for each. The USB-PD receiver meets the defined USB-PD BMC Rx masks. The boundaries of the

Rx outer mask are specified to accommodate a change in signal amplitude due to the ground offset through the

cable. The Rx masks are therefore larger than the boundaries of the TX outer mask. Similarly, the boundaries of

the Rx inner mask are smaller than the boundaries of the TX inner mask. Triangular time masks are

superimposed on the TX outer masks and defined at the signal transitions to require a minimum edge rate that

has minimal impact on adjacent higher speed lanes. The TX inner mask enforces the maximum limits on the rise

and fall times. Refer to the USB-PD Specifications for more details.

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9.3.1.4 USB-PD BMC Transmitter

The TPS25750 transmits and receives USB-PD data over one of the CCy pins for a given CC pin pair (one pair

per USB Type-C port). The CCy pins are also used to determine the cable orientation and maintain the cable/

device attach detection. Thus, a DC bias exists on the CCy pins. The transmitter driver overdrives the CCy DC

bias while transmitting, but returns to a Hi-Z state, allowing the DC voltage to return to the CCy pin when it is not

transmitting. While either CC1 or CC2 can be used for transmitting and receiving, during a given connection only,

the one that mates with the CC pin of the plug is used, so there is no dynamic switching between CC1 and CC2.

Figure 9-7 shows the USB-PD BMC TX and RX driver block diagram.

LDO_3V3

PD_TX

Level Shifter

Driver

CC1

CC2

PD_RX

Level Shifter

Digitally

Adjustable

VREF (V_RXHI, V_RXLO

)

USB-PD Modem

Figure 9-7. USB-PD BMC TX/Rx Block Diagram

Figure 9-8 shows the transmission of the BMC data on top of the DC bias. Note that the DC bias can be

anywhere between the minimum and maximum threshold for detecting a Sink attach. This means that the DC

bias can be above or below the VOH of the transmitter driver.

VOH

DC Bias

VOL

VOH

DC Bias

VOL

Figure 9-8. TX Driver Transmission with DC Bias

The transmitter drives a digital signal onto the CCy lines. The signal peak, V_TXHI, is set to meet the TX masks

defined in the USB-PD Specifications. Note that the TX mask is measured at the far-end of the cable.

When driving the line, the transmitter driver has an output impedance of Z_DRIVER. Z_DRIVERis determined by the

driver resistance and the shunt capacitance of the source and is frequency dependent. Z_DRIVERimpacts the

noise ingression in the cable.

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Figure 9-9 shows the simplified circuit determining Z _DRIVER. It is specified such that noise at the receiver is

bounded.

R_DRIVER

Z_DRIVER

Driver

C_DRIVER

Figure 9-9. ZDRIVER Circuit

9.3.1.5 USB-PD BMC Receiver

The receiver block of the TPS25750 receives a signal that follows the allowed Rx masks defined in the USB PD

specification. The receive thresholds and hysteresis come from this mask.

Figure 9-10 shows an example of a multi-drop USB-PD connection (only the CC wire). This connection has the

typical Sink (device) to Source (host) connection, but also includes cable USB-PD Tx/Rx blocks. Only one

system can be transmitting at a time. All other systems are Hi-Z (Z _BMCRX). The USB-PD Specification also

specifies the capacitance that can exist on the wire as well as a typical DC bias setting circuit for attach

detection.

Source

System

Sink

System

Pullup for

Attach

Detection

Connector

Cable

CC wire

Tx

C_RECEIVER

Rx

C_{CablePlug_CC}

RD for

Attach

Detection

Rx

Tx

SOP‘ PD

communication only

(eMarker #1)

SOP‘‘ PD

communication only

(eMarker #2)

Figure 9-10. Example USB-PD Multi-Drop Configuration

9.3.1.6 Squelch Receiver

The TPS25750 has a squelch receiver to monitor for the bus idle condition as defined by the USB PD

specification. The CC line is deemed active (that is not idle) when a minimum of NCOUNT transitions occur at

the receiver within a time window of TTRANWIN. After waiting TTRANWIN without detecting NCOUNT

transitions, the bus is declared idle. The squelch receiver output reflects the state of the CC pin regardless of the

source of the tranmission.

9.3.2 Power Management

The TPS25750 power management block receives power and generates voltages to provide power to the

TPS25750 internal circuitry. These generated power rails are LDO_3V3 and LDO_1V5. LDO_3V3 can also be

used as a low power output for external EEPROM memory. The power supply path is shown in Figure 9-11.

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R_{LDO_3V3}

VIN_3V3

VBUS

VREF

LDO

LDO_3V3

VREF

LDO_1V5

LDO

Figure 9-11. Power Supplies

The TPS25750 is powered from either VIN_3V3 or VBUS. The normal power supply input is VIN_3V3. When

powering from VIN_3V3, current flows from VIN_3V3 to LDO_3V3 to power the core 3.3-V circuitry and I/Os. A

second LDO steps the voltage down from LDO_3V3 to LDO_1V5 to power the 1.5-V core digital circuitry. When

VIN_3V3 power is unavailable and power is available on VBUS, it is referred to as the dead-battery start-up

condition. In a dead-battery start-up condition, the TPS25750 opens the VIN_3V3 switch until the host clears the

dead-battery flag through I²C. Therefore, the TPS25750 is powered from the VBUS input with the higher voltage

during the dead-battery start-up condition and until the dead-battery flag is cleared. When powering from a

VBUS input, the voltage on VBUS is stepped down through an LDO to LDO_3V3.

9.3.2.1 Power-On And Supervisory Functions

A power-on reset (POR) circuit monitors each supply. This POR allows active circuitry to turn on only when a

good supply is present.

9.3.2.2 VBUS LDO

The TPS25750 contains an internal high-voltage LDO which is capable of converting VBUS to 3.3 V for

powering internal device circuitry. The VBUS LDO is only used when VIN_3V3 is low (the dead-battery

condition). The VBUS LDO is powered from VBUS.

9.3.3 Power Paths

The TPS25750 has internal sourcing power paths: PP_5V and PP_CABLE. TPS25750D has a integrated

bidirectional high voltage load switch for sinking power path: PPHV. TPS25750S has a high volatge gate driver

for sink path control: PP_EXT. Each power path is described in detail in this section.

9.3.3.1 Internal Sourcing Power Paths

Figure 9-12 shows the TPS25750 internal sourcing power paths available in both TPS25750D and TPS25750S.

The TPS25750 features two internal 5-V sourcing power paths. The path from PP5V to VBUS is called PP_5V.

The path from PP5V to CCx is called PP_CABLE. Each path contains two back-to-back common drain N-FETs,

with current clamping protection, overvoltage protection, UVLO protection, and temperature sensing circuitry.

PP_5V can conduct up to 3 A continuously, while PP_CABLE can conduct up to 315 mA continuously. When

disabled, the blocking FET protects the PP5V rail from high-voltage that can appear on VBUS.

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3A

Fast current clamp, I_LIM5V

VBUS

Temp

Sensor

PP_5V Gate Control and Sense

PP_5V

PP_CABLE

CC1 Gate Control

T_{SD_PP5V}

Fast current limit, I_VCON

CC1

CC2 Gate Control

Temp

Sensor

PP5V

CC2

Figure 9-12. Port Power Switches

9.3.3.1.1 PP_5V Current Clamping

The current through the internal PP_5V path are current limited to I_LIM5V. The I_LIM5Vvalue is configured by

application firmware. When the current through the switch exceeds I_LIM5V, the current limiting circuit activates

within t_{iOS_PP_5V}and the path behaves as a constant current source. If the duration of the overcurrent event

exceeds t_ILIM, the PP_5V switch is disabled.

9.3.3.1.2 PP_5V Local Overtemperature Shut Down (OTSD)

When PP_5V clamps the current, the temperature of the switch will begin to increase. When the local

temperature sensors of PP_5V or PP_CABLE detect that T_J> T_{SD_PP5V}, the PP_5V switch is disabled and the

affected port enters the USB Type-C ErrorRecovery state.

9.3.3.1.3 PP_5V OVP

The overvoltage protection level is automatically configured based on the expected maximum V _BUSvoltage,

which depends upon the USB PD contract. When the voltage on the VBUS pin of a port exceeds the configured

value (V_OVP4RCP) while PP_5V is enabled, then PP_5V is disabled within t_{PP_5V_ovp}and the port enters into the

Type-C ErrorRecovery state.

9.3.3.1.4 PP_5V UVLO

If the PP5V pin voltage falls below its undervoltage lock out threshold (V_{PP5V_UVLO}) while PP_5V is enabled, then

PP_5V is disabled within t_{PP_5V_uvlo}and the port that had PP_5V enabled enters into the Type-C ErrorRecovery

state.

9.3.3.1.5 PP_5Vx Reverse Current Protection

If V_VBUS- V_PP5V> V_{PP_5V_RCP}, then the PP_5V path is automatically disabled within t _{PP_5V_rcp}. If the RCP

condition clears, then the PP_5V path is automatically enabled within t_ON

.

9.3.3.1.6 PP_CABLE Current Clamp

When enabled and providing VCONN power, the TPS25750 PP_CABLE power switch clamps the current to I

_VCON. When the current through the PP_CABLE switch exceeds I_VCON, the current clamping circuit activates

within t_{iOS_PP_CABLE}and the switch behaves as a constant current source.

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9.3.3.1.7 PP_CABLE Local Overtemperature Shut Down (OTSD)

When PP_CABLE clamps the current, the temperature of the switch will begin to increase. When the local

temperature sensors of PP_5V or PP_CABLE detect that T_J>T_{SD_PP5V}, the PP_CABLE switch is disabled and

latched off within t_{PP_CABLE_off}. The port then enters the USB Type-C ErrorRecovery state.

9.3.3.1.8 PP_CABLE UVLO

If the PP5V pin voltage falls below its undervoltage lock out threshold (V_{PP5V_UVLO}), then the PP_CABLE switch

is automatically disabled within t_{PP_CABLE_off}

.

9.3.3.2 TPS25750D Internal Sink Path

The TPS25750D has internal controls for internal FETs (GATE_VSYS and GATE_VBUS as shown in Figure

9-13) that require that VBUS_IN be above V_{VBUS_UVLO}before being able to enable the sink path. Figure 9-13

shows a diagram of the sink path. When a sink path is enabled, the circuitry includes a slew rate control loop to

ensure that external switches do not turn on too quickly (SS). The TPS25750D senses the PPHV and VBUS

voltages to control the gate voltages to enable or disable the FETs.

The sink-path control includes overvoltage protection (OVP) and reverse current protection (RCP).

PP_HV

PPHV

VBUS

Gate Control and Sense

Figure 9-13. Internal Sink Path

9.3.3.2.1 Overvoltage Protection (OVP)

The application firmware enables the OVP and configures it based on the expected VBUS voltage. If the voltage

on VBUS surpasses the configured threshold VOVP4VSYS = VOVP4RCP/rOVP, then GATE_VSYS is

automatically disabled within tPPHV_FSD to protect the system. If the voltage on VBUS surpasses the

configured threshold VOVP4RCP, then GATE_VBUS is automatically disabled within tPPHV_OVP. When

VVBUS falls below VOVP4RCP - VOVP4RCPH, GATE_VBUS is automatically re-enabled within tPPHV_ON

since the OVP condition has cleared. This allows two sinking power paths to be enabled simultaneously and

GATE_VBUS will be disabled when necessary to ensure that VVBUS remains below VOVP4RCP.

While the TPS25750D is in BOOT mode in a dead-battery scenario (that is VIN_3V3 is low), it handles an OVP

condition slightly differently. As long as the OVP condition is present, GATE_VBUS and GATE_VSYS are

disabled. Once the OVP condition clears, both GATE_VBUS and GATE_VSYS are re-enabled. Since this is a

dead-battery condition, the TPS25750D will be drawing approximately IVIN_3V3, ActSnk from VBUS during this

time to help discharge it.

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Power Path Supervisor

V_OVP4RCP

V_OVP4VSYS= V_OVP4RCP/ r_OVP

Figure 9-14. Diagram for OVP Comparators

9.3.3.2.2 Reverse-Current Protection (RCP)

The VSYS gate control circuit monitors the PPHV and VBUS voltages and detects reverse current when the

VVSYS surpasses V_VBUSby more than V_RCP. When the reverse current condition is detected, GATE_VBUS is

disabled within tPPHV_RCP. When the reverse current condition is cleared, GATE_VBUS is re-enabled within

tPPHV_ON. This limits the amount of reverse current that can flow from PPHV to VBUS through the external N-

ch MOSFETs. In reverse current protection mode, the power switch controlled by GATE_VBUS is allowed to

behave resistively until the current reaches VRCP/ RPPHV and then blocks reverse current from PPHV to

VBUS.

I

1/R_PPHV

-V_RCP

V=V_VBUSœ V_PPHV

V_RCP/R_PPHV

Figure 9-15. Switch I-V Curve for RCP on Sink-path Switches.

9.3.3.2.3 VBUS UVLO

The TPS25750D monitors VBUS voltage and detects when it falls below VVBUS_UVLO. When the UVLO

condition is detected, GATE_VBUS is disabled within tPPHV_RCP. When the UVLO condition is cleared,

GATE_VBUS is reenabled within tPPHV_ON.

9.3.3.2.4 Discharging VBUS to Safe Voltage

The TPS25750D has an integrated active pulldown (IDSCH) on VBUS for discharging from high voltage to

VSAFE0V (0.8 V). This discharge is applied when it is in an Unattached Type-C state.

9.3.3.3 TPS25750S - External Sink Path Control PP_EXT

The TPS25750S has two N-ch gate drivers designed to control a sinking path from VBUS to VSYS. The charge

pump for these gate drivers requires VBUS to be above VVBUS_UVLO. When a sink path is enabled, the

circuitry includes a slew rate control loop to ensure that external switches do not turn on too quickly (SS). The

TPS25750S senses the VSYS and VBUS voltages to control the gate voltages to enable or disable the external

FETs.

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The sink-path control includes overvoltage protection (OVP), and reverse current protection (RCP). Adding

resistance in series with a GATE pin of the TPS25750S and the gate pin of the N-ch MOSFET will slow down the

turnoff time when OVP or RCP occurs. Any such resistance must be minimized, and not allowed to exceed 3 Ω.

PP_EXT

PP_EXT Gate Control and

Sense

Figure 9-16. PP_EXT External Sink Path Control

Figure 9-17 shows the GATE_VSYS gate driver in more detail.

switch enabled when

gate driver is disabled and

V_{VIN_3V3}< V_{VIN_3V3_UVLO}

V_{GATE_ON}

R_{GATE_FSD}

Regular enable/

disable

Fast

disable

I_{GATE_OFF}

I_{GATE_ON}

Charge

Pump

VBUS

R_{GATE_OFF_UVLO}

Figure 9-17. Details of the VSYS Gate Driver

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9.3.3.3.1 Overvoltage Protection (OVP)