TPS25762-Q1 [TI]
具有集成降压/升压稳压器的汽车类 USB Type-C® PD 控制器;
| 型号： | TPS25762-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成降压/升压稳压器的汽车类 USB Type-C® PD 控制器 控制器 光电二极管 稳压器 |
| 文件： | 总90页 (文件大小：11729K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS25762-Q1
ZHCSP88 – DECEMBER 2022
具有降压/升压稳压器的 TPS25762-Q1 汽车类 USB Type-C® 电力输送控制器
1 特性
3 说明
•
具有符合 AEC-Q100 标准的下列特性：
– 器件温度等级 1：–40°C 至 +125°C 环境工作温
度范围
– 器件 HBM ESD 分类等级 2
– 器件 CDM ESD 分类等级 C2B
– 增强型连接器引脚 ESD 保护功能
具有可编程电源 (PPS) 支持的 USB 电力输送 (PD)
控制器
TPS25762-Q1 是一款完全集成的 USB Type-C® 电力
输送 (PD) 解决方案，具有集成的降压/升压转换器，适
用于汽车单 USB 端口应用。功能包括：带 4 个电源
开关的集成式降压/升压转换器；一个 ARM® Cortex®-
M0；带 Type-C 电缆插拔和方向检测的 USB 端口控制
器；USB 电池充电规范版本 1.2 (BC1.2) 检测；USB
端点 PHY；器件电源管理和监控电路；连接器引脚过
压和短路保护。
•
– 宽 VIN：5.5V 至 18V（最大 40V）
– 集成降压/升压 4 个电源开关，支持高达 65W 的
USB PD 输出功率
一个智能的系统策略管理器有效地增加了传输的 USB
电力，同时保护系统免受汽车电池瞬态和过热情况的影
响。
– VBUS 输出：3V 至 21V，步长为 ±20mV
– IBUS 输出：0A 至 3A，电流限值步长为 ±50mA
– VBUS 短接 VBAT 和接地保护
– VBUS 电缆压降补偿
器件配置设置通过一个直观的图形用户界面 (GUI) 进行
选择。
器件信息
封装
– MFi 过流保护
器件型号
封装尺寸
– 开关频率：300kHz、400kHz、450kHz
– 具有抖动的直流/直流同步输入/输出
USB 端口配置选项
TPS25762-Q1
RQL (QFN-29)
6.00mm × 5.00mm
•
•
VBAT
– 1 USB-PD 端口 (TPS25762-Q1)
– 2 USB-PD 端口 (TPS25772-Q1)
符合 USB 要求
– USB Type-C® 电力输送 3.1 版
PGND
IN
ON
PA_CC1
PA_CC2
PA_DP
OFF
EN
LDO5V
PA_DM
CSN/BUS
CSP
•
•
CC 逻辑、VCONN 拉电流和放电电流
LDO3V3
LDO1V5
3-21V
USB 电缆极性检测
OUT
AGND
TVSP
3V3
– 电池充电规范 1.2 版
LS_GD
NTC
•
DCP：专用充电端口
•
传统快速充电
IRQ
E2PROM
(32kB)
SCL1
SDA1
– 2.7V 分压器 3 模式
– 1.2V 分压器模式
– 高压 DCP 协议
微控制器内核允许
GPIO0
GPIO1
•
•
– 固件更新
TPS25762-Q1
– 根据电源电压和温度提供电源管理
短接 VBUS 和 VBAT 保护
– VBUS
– Px_ DP 和 Px_DM
– Px_CC1 和 Px_CC2
2 应用
•
•
•
•
汽车类 USB 充电
汽车媒体中心
汽车音响主机
汽车后座娱乐系统
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSGL9
TPS25762-Q1
ZHCSP88 – DECEMBER 2022
www.ti.com.cn
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings .............................................................. 7
7.3 Recommended Operating Conditions.........................7
7.4 Recommended Components...................................... 8
7.5 Thermal Information....................................................9
7.6 Buck-Boost Regulator.................................................9
7.7 CC Cable Detection Parameters...............................13
7.8 CC VCONN Parameters........................................... 13
7.9 CC PHY Parameters.................................................14
7.10 Thermal Shutdown Characteristics.........................15
7.11 Oscillator Characteristics........................................ 15
7.12 ADC Characteristics................................................15
7.13 TVS Parameters..................................................... 16
7.14 Input/Output (I/O) Characteristics........................... 16
7.15 BC1.2 Characteristics............................................. 17
7.16 I2C Requirements and Characteristics................... 18
7.17 Typical Characteristics............................................21
8 Parameter Measurement Information..........................29
9 Detailed Description......................................................31
9.1 Overview...................................................................31
9.2 Functional Block Diagram.........................................32
9.3 Feature Description...................................................32
9.4 Device Functional Modes..........................................63
10 Application and Implementation................................65
10.1 Application Information........................................... 65
10.2 Typical Application.................................................. 65
11 Power Supply Recommendations..............................80
12 Layout...........................................................................81
12.1 Layout Guidelines................................................... 81
12.2 Layout Example...................................................... 82
13 Device and Documentation Support..........................83
13.1 Documentation Support.......................................... 83
13.2 接收文档更新通知................................................... 83
13.3 支持资源..................................................................83
13.4 Trademarks.............................................................83
13.5 Electrostatic Discharge Caution..............................83
13.6 术语表..................................................................... 83
14 Mechanical, Packaging, and Orderable
Information.................................................................... 84
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
December 2022
*
Initial Release
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5 Device Comparison Table
PART NUMBER
TPS25762-Q1
TPS25772-Q1
Port A
Port B
Port A Output Power
Port B Output Power
n/a
USB-PD
65 W
65 W
n/a
USB-PD
65 W
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6 Pin Configuration and Functions
GPIO2 | I2C_SCL2
GPIO1 | IRQ2(o)
GPIO0
1
2
3
4
5
6
7
25
24
23
22
21
GPIO6 | SYNC
GPIO9 | IRQ
I2C_SCL1
I2C_SDA1
AGND
TVSP
LDO_5V
EN/UVLO
LDO_1V5
20 PA_CC1
19
18
PA_CC2
PA_DP | GPIO8
8
GPIO5 | NTC
图 6-1. RQL Package 29-Pin (VQFN) Top View
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表 6-1. Pin Descriptions
PIN
DESCRIPTION
NAME
NO.
Enable pin. For EN/UVLO < 0.3 V, the TPS25762-Q1 is in a low current shutdown mode. For
EN/UVLO > 1.3 V, the full functionality is enabled, provided LDO_5V exceeds the LDO_5V UVLO
threshold.
EN/UVLO
6
The input supply pin to the IC. Connect VIN to a supply voltage between 5.5 V and 18 V (40-V
ABS MAX transient).
IN
15
PGND
SW1
13
14
12
Power ground of the IC. The high current ground connection to the low-side gate drivers.
The buck side switching node.
SW2
The boost side switching node.
An external capacitor is required between the BOOT1 and the SW1 pins to provide bias to the
high-side MOSFET gate drivers.
BOOT1
BOOT2
16
10
An external capacitor is required between the BOOT2 and the SW2 pins to provide bias to the
high-side MOSFET gate drivers.
AGND
OUT
5
Analog ground of the IC.
11
28
29
Output of the buck-boost regulator. Connect to bulk capacitance.
Positive input of the current sense amplifier.
CSP
CSN/BUS
Negative input of the current sense amplifier. This is the PA_VBUS supply.
Output of internal 5 V LDO for buck-boost low-side FET drivers, and Px_VCONN supply. Connect
bypass capacitor to PGND. May be overdriven from external 5-V supply.
LDO_5V
21
27
Output of internal 3.3-V LDO for analog circuitry and GPIO drivers. Connect bypass capacitor to
AGND.
LDO_3V3
LDO_1V5
I2C_SCL1
I2C_SDA1
7
3
Output of internal 1.5-V LDO for digital circuitry. Connect bypass capacitor to AGND.
Controller I2C Clock Input/Output.
4
Controller I2C Data Input/Output.
GPIO2 (I2C_SCL2)
GPIO3 (I2C_SDA2)
25
26
Multifunction pin. GPIO; or target I2C Clock Input.
Multifunction pin. GPIO; or target I2C Data Input.
Multifunction pin. Interrupt I/O and fault flag for I2C1 or I2C2; or GPIO depending upon firmware
configuration. Reports fault conditions set by application configuration firmware.
IRQ (GPIO9)
PA_CC1
2
Analog input/output. Port A Type-C current advertisement, VCONN, and USB PD modem.
Connect to Port A Type-C connector CC1 pin.
20
19
18
17
Analog input/output. Port A Type-C current advertisement, VCONN, and USB PD modem.
Connect to Port A Type-C connector CC2 pin.
PA_CC2
Multifunction pin. BC1.2 USB 2.0 D+ data line input/output. Connect to Port A Type-C USB data
line DP connector pins. May also be used as GPIO depending upon firmware configuration.
PA_DP (GPIO8)
PA_DM (GPIO7)
Multifunction pin. BC1.2 USB 2.0 D- data line input/output. Connect to Port A Type-C USB data
line DM connector pins. May also be used as GPIO depending upon firmware configuration.
GPIO0
23
24
GPIO
GPIO1 or IRQ2(o)
Multifunction pin. GPIO or Interrupt I/O depending upon firmware configuration.
Multifunction pin. GPIO; thermistor input (can use either negative temperature coefficient resistor
or positive temperature coefficient resistor).
GPIO5 (NTC)
8
1
Multifunction pin. GPIO; SYNC(o) - clock out to synchronize slave DC/DC regulators to internal
DC/DC switching frequency; SYNC(i) - clock input to synchronize internal DC/DC to an external
clock.
GPIO6 (SYNC)
PA_LSGD
TVSP
9
Charge pump output for external NFET for VBUS bulk capacitance blocking.
Transient voltage protection and firmware setting pin. See 表 9-3 for boot configuration. See 表
9-2 for R-C network component values.
22
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7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of -40°C to 150°C and AGND = PGND (unless otherwise
noted)(1) (2)
MIN
–0.3
–0.3
MAX
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Input voltage range
Input voltage range
Input voltage range
Input voltage range
Input voltage range
Input voltage range
Input voltage range
Input voltage range
Input voltage range
Input voltage range
Input voltage range
Input voltage range
Output voltage range
Output voltage range
Output voltage range
Output voltage range
I/O voltage range
I/O voltage range
I/O voltage range
I/O voltage range
I/O voltage range
I/O voltage range
I/O voltage range
I/O voltage range
I/O voltage range
I/O voltage range
I/O voltage range
I/O voltage range
I/O voltage range
I/O voltage range
I/O voltage range
I/O voltage range
I/O voltage range
I/O voltage range
IN (3) (4) to PGND
40
IN with respect to SW1
EN/UVLO (5) to AGND
BOOT1 with respect to SW1
BOOT2 with respect to SW2 (6)
SW1 (7) to PGND
25
–0.3 internally limited
–0.3
–0.3
–0.3
–0.3
6
6
24
24
17.5
24
24
0.3
0.3
24
6
SW2 (8) to PGND
SW2 to OUT
CSP to PGND
–0.3
–0.3
-0.3
CSN/BUS to PGND
CSP to CSN
AGND to PGND
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
OUT to PGND
LDO_5V to PGND
LDO_3V3 to AGND
LDO_1V5 to AGND
TVSP to PGND
6
2
30
6
I2C_SCL1 to AGND
I2C_SDA1 to AGND
GPIO9, IRQ1 to AGND
PA_CC1 to AGND
PA_CC2 to AGND
PA_DM to AGND
6
6
30
30
30
6
GPIO7 to AGND
PA_DP to AGND
30
6
GPIO8 to AGND
GPIO0 to AGND
6
GPIO1, IRQ2 to AGND
GPIO2, I2C_SCL2 to AGND
GPIO3, I2C_SDA2 to AGND
PA_LSGD to PGND
GPIO5, NTC to AGND
GPIO6, SYNC to AGND
PA_LSGD to CSN/BUS
6
6
6
30
6
6
10
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7.1 Absolute Maximum Ratings (continued)
Over the recommended operating junction temperature range of -40°C to 150°C and AGND = PGND (unless otherwise
noted)(1) (2)
MIN
MAX
UNIT
mA
A
Input current
EN/UVLO
0
2
Output current
Output current
Output current
Positive source current on PA_CC1, PA_CC2
GPIO 2, 3, 5, 6, 7, 8
internally limited
0.0010
A
GPIO 0, 1, 4, 9
0.005
A
positive sink current for I2C_SDA1, I2C_SCL1,
I2C_SDA2, I2C2_SCL2
Output current
Output current
internally limited
internally limited
A
A
positive source current for LDO_5V, LDO_3V3,
LDO_1V5
TA Operating ambient temperature
TJ Operating junction temperature
TSTG Storage temperature
–40
–40
–55
125
150
150
°C
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to PGND or AGND. Connect the PGND pin directly to the Ground plane of the board. The PGND
and AGND traces can be connected near the AGND pin.
(3) When the buck-boost is operating and VIN exceeds 18 V, the positive slew rate dVIN/dt must not exceed 200V/ms.
(4) When applying VIN, the time from VIN exceeding 5 V to VIN exceeding 25 V must not be less than 2 µs. This is normally achieved by
properly sizing the input EMI filter.
(5) EN/UVLO pin is internally clamped to 10V. Ensure input current rating is not exceeded by connecting current limit resistor.
(6) BOOT2 with respect to SW2 during OUT overvoltage conditions can be -15 V due to internal clamp.
(7) SW1 can undershoot PGND by -1 V during negative switching transients as up to 10A (peak) may flow through the body diode. Typical
duration ~20 ns. SW1 can overshoot OUT by 1 V during positive transients. Typical duration ~ 20 ns.
(8) SW2 can undershoot PGND by -2 V during switching transients as up to 10A (peak) may flow through the body diode. Typical duration
~20 ns. SW2 can overshoot OUT by 1 V during positive transients. Typical duration ~20 ns.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per
AEC Q100-002
V(ESD)
V(ESD)
V(ESD)
V(ESD)
V(ESD)
V(ESD)
Electrostatic discharge
Electrostatic discharge
Electrostatic discharge
Electrostatic discharge
Electrostatic discharge
Electrostatic discharge
±2000(1)
V
Charged-device model (CDM), per
AEC Q100-011
±750(2)
±2000(3)
±2000(3)
±2000(3)
±2000(3)
V
V
V
V
V
IEC61000-4-2 Contact discharge
150 pF, 330 Ω.
OUT, CSP, CSN/BUS, PA_CC1,
PA_CC2, PA_DP, PA_DM
IEC61000-4-2 Contact
discharge 150 pF, 330 Ω.
OUT, CSP, CSN/BUS, PA_CC1,
PA_CC2, PA_DP, PA_DM
ISO 10605 Contact discharge 330 OUT, CSP, CSN/BUS, PA_CC1,
pF, 330 Ω. PA_CC2, PA_DP, PA_DM
ISO 10605 Air-gap discharge 330 OUT, CSP, CSN/BUS, PA_CC1,
pF, 330 Ω. PA_CC2, PA_DP, PA_DM
(1) AEC Q100-002 indicates that HBM stressing shall be in accordancewith the ANSI/ESDA/JEDEC JS-001 specification.
(2) The passing level per AEC-Q100 Classification C2b.
(3) Test conducted on Texas Instruments evaulation board.
7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of -40°C to 150°C (unless otherwise noted)
MIN
MAX
UNIT
Input voltage range (up to 65W
output)
VI
VI
IN
IN
6.8
18
V
Input voltage range (up to 30W
output)
5.5
18
V
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7.3 Recommended Operating Conditions (continued)
Over the recommended operating junction temperature range of -40°C to 150°C (unless otherwise noted)
MIN
MAX
UNIT
V
VI
II
Input voltage range
Input current
EN/UVLO
EN/UVLO
0
7 (2)
0
1
mA
LDO_5V when overdriven by
external supply
VI
Input voltage range
Input voltage range
Input voltage range
Output voltage range
I/O voltage range
I/O voltage range
I/O voltage range
I/O voltage range
I/O voltage range
Output current(1)
4.75
0
5.5
22
V
V
VI
CSP, CSN/BUS
PB_VBUS (GPIO4 when
configured as PB_VBUS)
VI
3
22
V
VO
VIO
VIO
VIO
VIO
VIO
IO
OUT
0
21
V
PA_CC1, PA_CC2, PB_CC1,
PB_CC2
0
5.5
3.6
5.5
3.6
3.6
5
V
PA_DP, PA_DM, PB_DP, PB_DM
0
V
I2C_SDAn, I2C_SCLn, IRQn (n=1
or 2)
0
V
GPIOn (n = 0 - 9)
0
V
NTC monitor (GPIO5), SYNC
(GPIO6)
0
V
IOUT
A
PA_CC1, PA_CC2, PB_CC1,
PB_CC2
IO
Output current
225
10
mA
mA
kHz
IO
Output current (from LDO_3V3)
GPIOn (n = 0 - 9)
Buck-boost converter switching
frequency driven from SYNC pin
fsw
250
500
TA
TJ
Ambient operating temperature
Operating junction temperature
–40
–40
125
150
°C
°C
(1) Average LC filtered output current from buck-boost power stage. Operation with IOUT > 3A with VOUT > 10 V may result in thermal
shutdown.
(2) EN/UVLO MAX specification specification applies when current into pin is not externally limited.
7.4 Recommended Components
over operating free-air temperature range (unless otherwise noted)
PARAMETER (1)
VOLTAGE RATING
MIN
TYP
MAX
UNIT
CIN
Capacitance on VIN
40 V
10 V
22
47
µF
Capacitance on LDO_5V (supplied
internally)
CLDO_5V
4.7
10
10
µF
µF
Capacitance on LDO_5V (supplied
externally)
CLDO_5V
10 V
47
100
CLDO_3V3
CLDO_1V5
CPx_CCy
Capacitance on LDO_3V3
Capacitance on LDO_1V5
Capacitance on Px_CCy pins(2)
Boot charge capacitance
RC snubber resistor on SW1
RC snubber capacitor on SW1
RC snubber resistor on SW2
RC snubber capacitor on SW2
Capacitance on OUT (4)
6.3 V
6.3 V
6.3 V
10 V
4.7
4.7
10
10
µF
µF
pF
µF
Ω
200
0.08
330
0.1
1.1
1
480
0.3
CBOOT1, CBOOT2
RSnubber_SW1
CSnubber_SW1
RSnubber_SW2
CSnubber_SW2
COUT
35 V, 0.25 W
35 V
nF
Ω
35 V, 0.25 W
35 V
1.1
3.3
33
nF
µF
µF
µH
35 V
30
100
3.3
40
150
5.6
CBUS
Capacitance on PA_VBUS
Inductor (4)
35 V
120
4.7
L
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over operating free-air temperature range (unless otherwise noted)
PARAMETER (1)
VOLTAGE RATING
MIN
47
TYP
MAX
UNIT
kΩ
NTC
Thermistor
100
REN/UVLO
Enable/UVLO pull up resitance
47
kΩ
TVPS pin components
(CTVSP || (DamperR + C))
CTVSP Capacitance on TVSP pin
40 V
0.08
8
0.1
10
0.12
12
µF
Ω
(3)
TVPS pin components
(CTVSP || (DamperR + C)) network in Parallel with CTVSP
Damper resistor R of R + C
0.25W
40 V
TVPS pin components Damper capacitor C of R + C
(CTVSP || (DamperR + C)) network in Parallel with CTVSP
0.376
0.47 0.564
µF
mΩ
nH
TVSP Capacitor ESR (eq series
ESRCTVSP
resistance)
10
1
TVSP Capacitor ESL (eq series
inductance)
ESLCTVSP
(1) Capacitance values do not include any derating factors. For example, if 5.0 µF is required and the external capacitor value reduces by
50% at the required operating voltage, then the required external capacitor value would be 10 µF.
(2) This includes all capacitance to the Type-C receptacle.
(3) Maximum capacitance allowed on TVSP pin to ensure propoer decode of device configuration during boot.
(4) See applications section for recommended L and COUT combinations.
7.5 Thermal Information
TPS25762-Q1
THERMAL METRIC(1)
Hot Rod
29 PINS
33.3
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
13.1
7.3
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.3
ψJB
7.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Buck-Boost Regulator
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 150°C junction temperature
range unless otherwise stated.VIN = 13.5 V, VEN/UVLO = 2V unless otherwise stated. (1)
PARAMETER
SUPPLY VOLTAGE (VIN)
TEST CONDITION
MIN
TYP
MAX
UNIT
IQ
IQ
VIN shutdown current
VIN operating current
VEN/UVLO = 0 V
130
µA
VEN/UVLO = 2V, VOUT = 5 V, IOUT = 0
A
8
mA
VEN/UVLO = 1V, VOUT = 0 V, IOUT = 0
A
IQ
IQ
VIN operating current
VIN operating current
4.5
8
mA
mA
VEN/UVLO = 2V, VOUT = 0 V, IOUT = 0
A
VIN(OVP_R)
VIN(OVP_F)
VIN rising overvoltage threshold
VIN falling overvoltage threshold
hysteresis
VIN rising.
VIN falling.
18.4
18.0
19.2
18.8
0.4
20
V
V
V
V
V
V
19.6
VIN(UVLO_R)
VIN(UVLO_F)
VIN undervoltage lockout rising
VIN undervoltage lockout falling
hysteresis
VIN rising.
VIN falling.
5.14
5.04
5.30
5.20
0.1
5.46
5.36
LDO_5V OUTPUT
7V ≤ VIN ≤ 18 V, 0 < ILDO_5V
125mA, VEN = 2 V.
<
VLDO_5V
LDO_5V Output Regulation voltage
4.5
4.63
4.75
V
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Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 150°C junction temperature
range unless otherwise stated.VIN = 13.5 V, VEN/UVLO = 2V unless otherwise stated. (1)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
VLDO_5V(UVLO_R)
VLDO_5V(UVLO_F)
LDO_5V Undervoltage lockout rising
4.29
4.4
4.51
V
LDO_5V Undervoltage lockout
falling
4.09
4.2
4.31
V
Undervoltage hysteresis
drop out voltage
200
mV
V
VLDO_5V_DO
VIN = 5.5 V; ILDO_5V = 125mA
4.3
VLDO_V5V = 0 to 3.5 V,
RLDO_V5V_LOAD = 1 Ω
ILDO_5V(ILIMIT)
LDO_5V current limit
125
200
400
3.6
mA
LDO_3V3 OUTPUT
7V ≤ VIN ≤ 18 V, VEN = 2 V,
LDO_3V3 Output regulation voltage VLDO_5V(UVLO) < VLDO_5V < 5.5 V, 0
< ILDO_3V3 < 25mA
VLDO_3V3
3.4
3.5
3.3
V
LDO_3V3 Undervoltage lockout
rising
VLDO_3V3(UVLO_R)
VLDO_3V3(UVLO_F)
3.2
3.4
V
V
LDO_3V3 Undervoltage lockout
falling
3.05
3.15
150
3.25
Undervoltage hysteresis
mV
V
VLDO_3V3_DO
drop out voltage
VIN = 4.5 V, ILDO_3V3 = 30mA
3.3
35
VLDO_3V3 = 0 to 2.5 V, RLDO_3V3_LOAD
= 1 Ω
ILDO_3V3(ILIMIT)
LDO_1V5 OUTPUT
VLDO_1V5
LDO_3V3 current limit
50
80
mA
4.5 < VLDO_5V < 5.5V, 0 < ILDO_1V5
10 mA
<
LDO_1V5 Output Regulation voltage
1.49
1.44
1.37
1.55
1.49
1.65
1.54
1.47
V
V
LDO_1V5 Undervoltage lockout
rising
VLDO_1V5(UVLO_R)
VLDO_1V5(UVLO_F)
LDO_1V5 Undervoltage lockout
falling
1.42
70
V
Undervoltage hysteresis
LDO_1V5 current limit
mV
mA
VLDO_1V5 = 0 to 1.2 V, RLDO_1V5_LOAD
= 1 Ω
ILDO_1V5(ILIMIT)
EN/UVLO
15
20
28
EN input level required to turn on
internal LDOs
VEN(LDO_V5V_R)
EN/UVLO rising
1.05
V
V
V
EN input level required to turn off
internal LDOs
VEN(LDO_V5V_F)
VEN(OPER)
VEN(STBY)
VEN(HYS)
EN/UVLO falling
0.3
1.2
1.1
EN input level required to start
operation
EN/UVLO rising Precision EN
EN/UVLO falling
1.25
1.3
1.2
EN input level required to stop
operation
1.15
100
9
V
mV
V
Hysteresis
VEN/UVLO > VEN(CLAMP), 10 µA < IEN/
VEN(CLAMP)
EN input clamp voltage
Leakage current into EN pin
6
12
1
< 1 mA
UVLO
IEN(LEAK)
0 V < VEN < 6 V
µA
OUTPUT VOLTAGE
VCSN/BUS(3V)
VCSN/BUS(5V)
VCSN/BUS(21V)
VCNS/BUS regulation accuracy at 3V 0 ≤ IOUT ≤ 3A
VCNS/BUS regulation accuracy at 5V 0 ≤ IOUT ≤ 3A
VCNS/BUS regulation accuracy at 21V 0 ≤ IOUT ≤ 3A
2.9
4.85
3
5
3.1
5.15
V
V
V
20.48
21
21.53
Output voltage step size (12-bit
DAC)
VCSN/BUS_STP
VDAC Resolution
IDISCHG
10
12
mV
Bits
mA
Resolution of VBUS DAC
CSN/BUS discharge current when
transitioning to VSafe0V
VCSP = VCSN/BUS. VCSN/BUS = 3V.
Measure current into BUS.
40
VBUS = 21 V (max), CBULK =
220 µF, time to discharge BUS to <
5.5 V (per USB PD specification)
CSN/BUS discharge time when
transitioning to VSafe5V
tDISCHG
275
650
ms
ms
VBUS = 21 V (max), CBULK =
220 µF, time to discharge BUS to <
0.8 V (per USB PD specification)
CSN/BUS discharge time when
transitioning to VSafe0V
tDISCHG
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Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 150°C junction temperature
range unless otherwise stated.VIN = 13.5 V, VEN/UVLO = 2V unless otherwise stated. (1)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
Weak discharge resistance on BUS EN = 2V; measure BUS to PGND
RDISCHG
60
135
kΩ
pin when not sourcing VBUS
resistance.
BUS to GND resistance, RDISCH
disabled, not sourcing VBUS
EN = 2V measure BUS to PGND
resistance.
RBUS-GND(PWR)
RBUS-GND(UNPWR)
120
500
kΩ
kΩ
VIN = EN = 0V measure BUS to
PGND resistance.
BUS to GND resistance, unpowered
2
CABLE VOLTAGE DROP COMPENSATION
Gain setting = 0.1V/A: VCSP
VCSN/BUS = 50 mV
-
-
VOUT_CDC
VOUT_CDC
VOUT_CDC
VOUT_CDC
VOUT_CDC
VOUT_CDC
VOUT_CDC
VOUT_CDC
VOUT_CDC
ΔVOUT increase vs IOUT
ΔVOUT increase vs IOUT
ΔVOUT increase vs IOUT
ΔVOUT increase vs IOUT
ΔVOUT increase vs IOUT
ΔVOUT increase vs IOUT
ΔVOUT increase vs IOUT
ΔVOUT increase vs IOUT
ΔVOUT increase vs IOUT
465
85
500
100
375
75
535
115
404
89
mV
mV
mV
mV
mV
mV
mV
mV
mV
Gain setting = 0.1V/A: VCSP
VCSN/BUS = 10 mV
Gain stetting = 0.075V/A: VCSP
VCSN/BUS = 50 mV
-
346
61
Gain setting = 0.075V/A: VCSP
VCSN/BUS = 10 mV
-
Gain setting = 0.05V/A: VCSP
VCSN/BUS = 50 mV
-
227
37
250
50
273
63
Gain setting = 0.05V/A: VCSP
VCSN/BUS = 10 mV
-
Gain setting = 0.025V/A: VCSP
VCSN/BUS = 50 mV
-
-
109
14
125
25
141
36
Gain setting = 0.025V/A: VCSP
VCSN/BUS = 10 mV
Gain setting = 0V/A: 0 mV ≤ VCSP
VCSN/BUS ≤ 50 mV
-
-5
20
BUCK-BOOST PEAK CURRENT LIMITS
Boost peak current limit (in boost
IPEAK(BOOST)
IPEAK(BOOST)
IPEAK(BOOST)
IPEAK(BOOST)
IPEAK(BOOST)
IPEAK(BOOST)
IPEAK(BUCK)
IPEAK(BUCK)
IPEAK(BUCK)
IPEAK(BUCK)
IPEAK(BUCK)
IPEAK(BUCK)
IPEAK(BUCK)
IPEAK(BUCK)
INEG(BUCK)
12.3
10.8
9.3
7.9
6.3
4.8
8.2
9.0
9.7
10.4
5.3
6
14.5
12.8
11.0
9.3
16.7
14.7
12.6
10.6
8.6
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
mode)
Boost peak current limit (in boost
mode)
Boost peak current limit (in boost
mode)
Boost peak current limit (in boost
mode)
Boost peak current limit (in boost
mode)
7.5
Boost peak current limit (in boost
mode)
5.7
6.5
Buck peak current limit (in buck
mode)
9.7
11.2
12.1
13.1
14.1
7.2
Buck peak current limit (in buck
mode)
10.6
11.4
12.3
6.2
Buck peak current limit (in buck
mode)
Buck peak current limit (in buck
mode)
Buck peak current limit (in buck
mode)
Buck peak current limit (in buck
mode)
7.1
8.2
Buck peak current limit (in buck
mode)
6.8
7.5
-4.6
8.0
9.1
Buck peak current limit (in buck
mode)
8.8
10.1
-3
Buck negative current limit (in buck
mode)
- 3.8
OUT CURRENT DAC
IDAC_Resolution
8
Bits
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Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 150°C junction temperature
range unless otherwise stated.VIN = 13.5 V, VEN/UVLO = 2V unless otherwise stated. (1)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
CURRENT LIMIT
1 A ≤ IOUT ≤ 3 A, VCSN/BUS < 2.5 V;
RS = 10 mΩ.
ILIMIT_LO
Current limit accuracy
-250
-150
-20
250
150
20
mA
mA
%
1 A ≤ IOUT ≤ 3 A, VCSN/BUS ≥ 2.5
V; RS = 10 mΩ
ILIMIT_LO
ILIMIT_HI
ILIMIT_HI
Current limit accuracy < 1 A
Current limit accuracy > 3 A
Current limit accuracy > 3 A
IOUT > 3 A, VCSN/BUS < 2.5 V; RS
10 mΩ
=
=
IOUT > 3 A, VCSN/BUS ≥ 2.5 V; RS
10 mΩ
-5
1
5
%
ILIMIT_MIN
Minimum programmable current limit
Current limit step size
A
ICL_STEP
1 A ≤ IOUT ≤ 5 A; RS = 10 mΩ
50
mA
FREQUENCY
fSW(1)
Switching Frequency 1
Switching Frequency 2
Switching Frequency 3
285
380
428
300
400
450
315
420
473
kHz
kHz
kHz
fSW(2)
fSW(3)
FREQUENCY DITHER
Positive frequency deviation during
dither
FSSS
8
10
12
-8
%
%
Negative frequency deviation during
dither
-12
-10
FSSS_MOD
FSSS_MOD
Modulation frequency of dither
Modulation frequency of dither
DITHER_FREQ = 0
DITHER_FREQ = 1
9
10
25
11
kHz
kHz
22.5
27.5
OVERVOLTAGE PROTECTION
Fixed output overvoltage threshold
VCSN/BUS_OVP_R
22.0
20.5
23
24
V
at CSN/BUS pin
VCSN/BUS_OVP_F
Falling
21.5
1.5
22.5
V
V
Hysteresis
POWER SWITCHES
VIN = 12V; (VBOOT1 - VSW1) = 4.5V;
ISW1 = -1 A
RDS(ON)
M1
4.5
mΩ
RDS(ON)
RDS(ON)
M2
M4
VIN = 12V; ISW1 = 1 A
VIN = 12V; ISW2 = 1 A
20
6
mΩ
mΩ
VIN = VOUT = 12V: (VBOOT2 - VSW2) =
4.5V, ISW2 = -1 A
RDS(ON)
M3 + M5
18
4
mΩ
V
BOOT1 to SW1 rising UVLO
threshold
VUV_BOOT1_R
VUV_BOOT1_F
3.5
2.9
4.4
3.7
BOOT1 to SW1 falling UVLO
threshold
3.4
680
5.3
V
mV
V
BOOT1 to SW1 UVLO hysteresis
BOOT1 to SW1 rising OVP
threshold
VOV_BOOT1_R
VOV_BOOT1_F
4.6
5.9
BOOT1 to SW1 falling OVP
threshold
4.3
250
3.5
5
300
4
5.6
350
4.4
V
mV
V
BOOT 1 OVP hysteresis
BOOT2 to SW2 rising UVLO
threshold
VUV_BOOT2_R
VUV_BOOT2_F
BOOT2 to SW2 falling UVLO
threshold
2.9
4.6
3.4
680
5.3
3.7
5.9
V
mV
V
BOOT2 to SW2 UVLO hysteresis
BOOT2 to SW1 rising OVP
threshold
VOV_BOOT2_R
VOV_BOOT2_F
BOOT2 to SW1 falling OVP
threshold
4.3
5
5.6
V
BOOT2 OVP hysteresis
250
300
350
mV
BUCK-BOOST CHARACTERISTICS
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Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 150°C junction temperature
range unless otherwise stated.VIN = 13.5 V, VEN/UVLO = 2V unless otherwise stated. (1)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
tSS
Soft-start time
6
ms
(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and
applying statistical processcontrol.
7.7 CC Cable Detection Parameters
Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature
range unless otherwise stated.VIN = 13.5 V, EN =2 V, unless otherwise stated.
PARAMETER
Type-C Source (Rp pull-up)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Unattached Px_CCy open circuit
voltage while Rp enabled, no load
VOC_3.3
VOC_5
IRev
RCC = 47 kΩ
1.85
2.95
V
V
Attached Px_CCy open circuit
voltage while Rp enabled, no load
RCC = 47 kΩ
Unattached reverse current on
Px_CCy
VCCy = 5.5V, VCCx = 0V, measure
current into CCy
10
µA
IRpStd
IRp1.5
IRp3.0
current source - Standard
current source - 1.5A
current source - 3.0A
0 < VCCy < 1.0 V, measure ICCy
0 < VCCy < 1.5 V, measure ICCy
0 < VCCy < 2.45 V, measure ICCy
64
166
304
80
180
330
96
194
356
µA
µA
µA
Type-C Sink (Rd pull-down)
0V ≤ VPx_CCy ≤ 2.1 V, measure
resistance on Px_CCy
RSNK
Rd pulldown resistance
VCONN discharge resistance
4.6
4.0
5.6
6.6
kΩ
kΩ
0V ≤ VPx_CCy ≤ 5.5 V, measure
resistance on Px_CCy
RVCONN_DIS
Common (Source and Sink)
deglitch time for comparators on
Px_CCy, this applies for VSRC1
VSRC2, VSRC3, VSNK1, VSNK2
VSNK3, and VSNK4
,
tCC
2.56
ms
,
.
7.8 CC VCONN Parameters
Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature
range unless otherwise stated.VIN = 13.5 V, EN = 2 V unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VLDO_5V = 5V, IL = 200 mA,
measure resistance from
LDO_5V to Px_CCy
RPP_CABLE
Rdson of the VCONN path
1.2
Ω
setting 0, VLDO_5V = 5V,
RL=10mΩ , measure IPx_CCy
30
50
70
ILIMVC
short circuit current limit
mA
setting 1, VLDO_5V = 5V,
RL=10mΩ , measure IPx_CCy
235
275
315
VCONN disabled, TJ ≤
125 oC, VPx_CCy = 5.5 V,
measure IPx_CCy
Leakage current into Px_Cy
pins
ICCyLKG
-1
0
10
µA
V
Over-voltage protection
threshold for Px_CCy
VVC_OVP
VLDO_5V rising
5.6
5.9
6.2
Reverse current protection
threshold for Px_CCy,
sourcing VCONN through
CCx
VLDO_5V = 5 V, VCCx rising,
setting 1.
VVC_RCP
230
310
390
mV
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Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature
range unless otherwise stated.VIN = 13.5 V, EN = 2 V unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Reverse current protection
threshold for Px_CCy,
sourcing VCONN through
CCx
VLDO_5V = 5 V, VCCx rising,
setting 2.
VVC_RCP
60
155
250
mV
Time to disable Px_Cy
VCONN after VLDO_5V
VVC_OVP or VCCx - VLDO_5V
VVC_RCP
>
tPP_CABLE_FSD
CL=0
1.5
µs
>
from disable signal to
Px_CCy at 10% of final
value
IL = 200 mA, VLDO_5V = 5V,
CL=0
tPP_CABLE_off
tiOS_PP_CABLE
tiOS_PP_CABLE
100
225
300
2
µs
µs
µs
External VLDO_5V = 5V, for
response time to short circuit short circuit RL = 10mΩ. Set
VCONILIM = 1.
Internal VLDO_5V = 5V, for
response time to short circuit short circuit RL = 10mΩ. Set
VCONILIM = 0.
0.3
7.9 CC PHY Parameters
Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature
range unless otherwise stated.VIN = 13.5 V, EN = 2V unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Transmitter
Transmit high voltage on
Px_CCy
VTXHI
Standard External load
Standard External load
1.05
-75
1.125
1.2
75
V
Transmit low voltage on
Px_CCy
VTXLO
mV
Transmit output impedance
while driving the CC line
using Px_CCy
ZDRIVER
measured at 750 kHz
33
75
Ω
Rise time. 10 % to 90
% amplitude points on
tRise
Px_CCy, minimum is under CPx_CCy= 520 pF
an unloaded condition.
300
ns
Maximum set by TX mask
Fall time. 90 % to 10
% amplitude points on
tFall
Px_CCy, minimum is under CPx_CCy= 520 pF
an unloaded condition.
Maximum set by TX mask
300
5.5
ns
V
Initially VCC1 ≤ 5.5 V and
VCC2 ≤ 5.5 V, then VCCx
rises.
OVP detection threshold for
USB PD PHY.
VPHY_OVP
8.5
Receiver
Does not include pull-up
or pulldown resistance from
cable detect. Transmitter is
Hi-Z.
Receiver input impedance
on Px_CCy
(2)
ZBMCRX
1
MΩ
pF
Capacitance looking into the
CC pin when in receiver
mode
Receiver capacitance on
Px_CCy(1)
CCC
120
Rising threshold on Px_CCy
for receiver comparator
VRX_SNK_R
VRX_SRC_R
sink mode (rising)
499
784
525
825
551
866
mV
mV
Rising threshold on Px_CCy
for receiver comparator
source mode (rising)
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Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature
range unless otherwise stated.VIN = 13.5 V, EN = 2V unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Falling threshold on Px_CCy
for receiver comparator
VRX_SNK_F
VRX_SRC_F
sink mode (falling)
230
250
270
mV
Falling threshold on Px_CCy
for receiver comparator
source mode (falling)
523
550
578
mV
(1) CCC includes only the internal capacitance on a Px_CCy pin when the pin is configured to be receiving BMC data. External
capacitance is needed to meet the required minimum capacitance per the USB-PD Specifications (cReceiver). Therefore, TI
recommends adding CPx_CCy externally.
(2) Guaranteed, but not production tested.
7.10 Thermal Shutdown Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Temperature shutdown
threshold
TSD_BB
Temperature rising
160
167
175
°C
Temperature shutdown
hysteresis
TSD_HYS
hysteresis
18
166
20
°C
°C
°C
°C
°C
°C
°C
Temperature shutdown
threshold
TSD_PA_VCONN
TSD_HYS
TSD_PA_VBUS_DISCH
Temperature rising
hysteresis
152
155
165
179
177
188
Temperature shutdown
hysteresis
Temperature shutdown
threshold
Temperature rising
hysteresis
166
20
Temperature shutdown
hysteresis
TSD_HYS
TSD_LDO5V
TSD_HYS
Temperature shutdown
threshold
Temperature rising
hysteresis
177
15
Temperature shutdown
hysteresis
7.11 Oscillator Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature
range unless otherwise stated.VIN = 13.5 V, EN =2 V, unless otherwise stated.
PARAMETER
TEST CONDITIONS
Trimmed.
MIN
TYP
MAX
UNIT
FOSC(100K)
FOSC(24M)
100KHz oscillator
89
103
111
kHz
Trimmed. 0 ℃ ≤ TA ≤
70 ℃
24MHz oscillator
24MHz oscillator
23.64
23.3
24.2
24.2
24.36
24.5
MHz
MHz
Trimmed. -40 ℃ ≤ TA ≤
150 ℃
FOSC(24M)
7.12 ADC Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature
range unless otherwise stated.VIN = 13.5 V, EN =2 V, unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.6V max scaling, voltage
divider of 3
LSB
LSB
least significant bit
14
mV
25.2V max scaling, voltage
divider of 21
least significant bit
98
27
mV
(VCSP - VCSN/BUS)= 10 mV,
30 mV
LSB
EG
least significant bit
Gain error
mA
%
0 A ≤ ITVSP ≤ 0.9 mA
–2.7
2.7
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Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature
range unless otherwise stated.VIN = 13.5 V, EN =2 V, unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.05V ≤ VGPIOx
3.6V, VGPIOx ≤ VLDO_3V3
≤
EG
Gain error
–2.7
2.7
%
EG
EG
Gain error
Gain error
2.7V ≤ VLDO_3V3 ≤ 3.6V
0.6V ≤ VPx_VBUS ≤ 22V
–2.4
–2.4
2.4
2.4
%
%
(VCSP - VCSN/BUS)= 10 mV,
30 mV
EG
Gain error, current sense
–2.4
2.4
%
EG
Gain error
VIN
–2.4
–2.4
–4.1
2.4
2.4
15
%
%
EG
Gain error
4.3 V ≤ VLDO_5V ≤ 5.5V
0 A ≤ ITVSP ≤ 0.9 mA
VOS(E)
Offset error(1)
mV
0.05V ≤ VGPIOx
≤
VOS(E)
Offset error(1)
–4.1
4.1
mV
3.6V, VGPIOx ≤ VLDO_3V3
2.7V ≤ VLDO_3V3 ≤ 3.6V
0.6V ≤ VPx_VBUS ≤ 22V
VOS(E)
VOS(E)
Offset error(1)
Offset error(1)
-4.1
-4.1
4.1
4.1
mV
mV
(VCSP - VCSN/BUS)= 10 mV,
30 mV
VOS(E)
Offset error(1)
-4.5
4.5
mA
VOS(E)
VOS(E)
Offset error(1)
Offset error(1)
VIN
-4.1
-4.1
4.1
4.1
mV
mV
4.3 V ≤ VLDO_5V ≤ 5.5V
(1) The offset error is specified after the voltage divider.
7.13 TVS Parameters
VIN = 13.5V, EN = 2V. over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TVSP
Pull up voltage for
configuration (1)
VTVSP_PU
0 < ITVSP < 1 mA
5.3
5.5
5.7
V
Decode 0
Decode 1
Decode 2
Decode 3
Decode 4
Decode 5
Decode 6
Decode 7
Decode 8
Device configuration decode RTVS = Open
Device configuration decode RTVS = 93.1 kΩ
Device configuration decode RTVS = 47.5 kΩ
Device configuration decode RTVS = 29.4 kΩ
Device configuration decode RTVS = 20.0 kΩ
Device configuration decode RTVS = 14.7 kΩ
Device configuration decode RTVS = 11.0 kΩ
Device configuration decode RTVS = 8.45 kΩ
Device configuration decode RTVS = 6.65 kΩ
1
61.2
µA
µA
µA
µA
µA
µA
µA
µA
µA
56.9
111.6
180.3
265
120
193.9
285
360.5
481.8
627.2
797
387.8
518.2
674.6
857.1
CTVSP = open; RTVSP = open.
Current limit when TVSP is
sourcing.
All Px_Dy = 0 V and Px_CCy
= 0 V. VTVSP = 0 V. Measure
current flowing out of TVSP.
ITVSP(ILIMIT)
1.1
1.44
1.83
mA
(1) For proper device configuration, VIN must be ≥ 7.6 V at time of configuration read.
7.14 Input/Output (I/O) Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature
range unless otherwise stated.VIN = 13.5 V, EN =2 V, unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GPIO0-9 (Inputs) (1)
VIH
VIL
GPIOx high-Level input voltage
GPIOx low-level input voltage
1.3
V
V
0.54
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Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature
range unless otherwise stated.VIN = 13.5 V, EN =2 V, unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
0.09
–8
TYP
MAX
UNIT
GPIOx input hysteresis voltage
GPIOx leakage current
GPIOx internal pull-up
GPIOx internal pull-down
GPIOx input deglitch
V
II(LEAKAGE)
RPU
VGPIOx = 5.5 V
8
150
150
µA
kΩ
kΩ
ns
pull-up enabled
50
100
100
20
RPD
pull-down enabled
50
tDG
GPIO 2, 3, 5, 6 (Outputs)
VOH
GPIOx output high voltage
IGPIOx= -5mA
IGPIOx=5mA
2.9
2.9
V
V
VOL
GPIOx output low voltage
0.4
0.4
GPIO 0, 1, 4, 7, 8, 9 (Outputs) (2)
VOH
GPIOx output high voltage
IGPIOx= -2mA
IGPIOx=2mA
V
V
VOL
GPIOx output low voltage
SYNC OUT
Phase difference between fsw
and GPIO6 when configured as
SYNC(O).
GPIOx when configured as phase
shifted DC/DC fsw clock output
ϕ shift_00
ϕ shift_90
ϕ shift_120
ϕ shift_180
0
90
degrees
degrees
degrees
degrees
Phase difference between fsw
and GPIO6 when configured as
SYNC(O).
GPIOx when configured as phase
shifted DC/DC fsw clock output
Phase difference between fsw
and GPIO6 when configured as
SYNC(O).
GPIOx when configured as phase
shifted DC/DC fsw clock output
120
180
Phase difference between fsw
and GPIO6 when configured as
SYNC(O).
GPIOx when configured as phase
shifted DC/DC fsw clock output
SYNC IN
Valid external clock frequency
(fSW_internal = 300kHz)
fSYNC(300kHz)
250
334
376
353
470
530
kHz
kHz
kHz
Valid external clock frequency
(fSW_internal = 400kHz)
fSYNC(400kHz)
Valid external clock frequency
(fSW_internal = 450kHz)
fSYNC(450kHz)
LSGD
0 V ≤ VCSN/BUS ≤ 21 V; 0 V ≤
(VLSGD - VCSN/BUS) ≤ 4 V
ILSGD_ON
NFET driver sourcing current
Sourcing voltage while enabled
10
6
13
16
µA
0 V ≤ VCSN/BUS ≤ 21 V; ILSGD
4 µA. Measure voltage between
LSGD and CSN/BUS.
≤
VLSGD_ON
8
V
(VLSGD - VCSN/BUS
)
RLSGD_OFF
Sinking resistance when disabled
VLSGD = VCSN/BUS = 5 V
160
300
kΩ
(1) GPIO9 is normally configured as I2C_IRQ1m (master): input pin. I2C specification requires use of external pullup resistor. Input
thresholds (VIH; VIL) leakage current (II(LEAKAGE))and deglitch timing (tDG) specifications are apply when used as I2C_IRQ1m. Internal
pullup and pulldown resistors are not used during this mode of operation.
(2) GPIO9 or GPIO1 may be configured as I2C_IRQ2s (slave): open-drain output pin. I2C specification requires use of external pullup
resistor. Output threshold (VOL) applies. Internal pullup and pulldown resistors are not used during this mode of operation.
7.15 BC1.2 Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature
range unless otherwise stated.VIN = 13.5 V, EN =2 V, unless otherwise stated.
PARAMETER
BC1.2 RESISTANCES
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Dedicated Charging Port Resistance
between Px_DP and Px_DM
VPx_DP = 0.6 V, VPx_DM = 0V, measure
DP to DM shorted resistance
RDCP_DAT
200
Ω
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Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature
range unless otherwise stated.VIN = 13.5 V, EN =2 V, unless otherwise stated.
PARAMETER
RDM_DWN_15k Px_DM line pulldown resistance
RDM_DWN_20k Px_DM line pulldown resistance
DIVIDER MODES
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VPx_DM = 3.6V
12
15
18
kΩ
VPx_DM = 3.6V
14.25
19.53
24.8
kΩ
V2.7V
V2.7V
R2.7V
R2.7V
V1.2V
R1.2V
Output Voltage on DPy pin
Output Voltage on DMy pin
Output Impedance on DPy
Output Impedance on DMy
Output Voltage on DMy
No load on DPy pin
No load on DMy pin
5µA pulled from DPy pin
5µA pulled from DMy pin
No load on DMy
2.57
2.57
24
2.7
2.7
30
2.83
2.83
36
V
V
kΩ
kΩ
V
24
30
36
1.12
80
1.2
102
1.28
130
Output Impedance on DMy
5µA pulled from DMy
kΩ
HVDCP THRESHOLD VOLTAGES
Data detection voltage on DP or DM
VDAT_REF
0.25
1.8
0.325
2
0.4
2.2
V
V
pin
VSEL_REF
Output selection voltage DP or DM pin
DP AND DM OVERVOLTAGE PROTECTION
OVP detection threshold for USB
VDy_OVP
Initially VPxDy ≤ 3.6 V, then
VPx_Dy rises.
5.5
8.5
V
Px_DP and Px_DM pins
7.16 I2C Requirements and Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature
range unless otherwise stated.VIN = 13.5 V, EN =2 V, unless otherwise stated. VDD = I2C pullup voltage (3.3 V or 1.8 V)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I2C_IRQ1s, I2C_IRQ2
I2C_IRQ1m
SDA and SCL Characteristics (Standard, Fast, Fast-mode Plus)
VIL
VIH
Input low signal
Input high signal
0.54
0.9
V
V
1.3
VDD = 3.3 V INPUT LOGIC THRESHOLDS
VIL
Input low signal
V
V
V
VIH
Input high signal
2.31
VHYS
VOL
VOL
IOL
Input hysteresis
0.165
Output low voltage
Output low voltage
Max output low current
Input leakage current
pin capacitance (internal)
VDD = 1.8V, IOL=2 mA
0.36
0.4
VDD = 3.3V, IOL=3 mA
VOL=0.4 V
V
12
–5
mA
µA
pF
ILEAK
CI
Voltage on pin = 3.3V
5
10
Capacitive load for each bus line
(external). Applies in Standard-
mode and Fast-mode.
Cb
Cb
400
550
pF
pF
Capacitive load for each bus line
(external). Applies in Fast-mode
Plus.
COMMON TIMING
tSP
I2C pulse width surpressed
50
ns
SDA and SCL Characteristics (Standard Mode)
fSCLS
Clock frequency (slave)
VDD = 1.8V or 3.3V
VDD = 1.8V or 3.3V
100
kHz
µs
Start or repeated start condition
hold time
tHD;STA
4
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Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature
range unless otherwise stated.VIN = 13.5 V, EN =2 V, unless otherwise stated. VDD = I2C pullup voltage (3.3 V or 1.8 V)
PARAMETER
TEST CONDITIONS
MIN
4.7
4
TYP
MAX
UNIT
tLOW
tHIGH
SCL Clock low time
SCL Clock high time
VDD = 1.8V or 3.3V
µs
VDD = 1.8V or 3.3V
VDD = 1.8V or 3.3V
µs
Start or repeated start condition
setup time
tSU;STA
4.7
µs
Serial data hold time (1)
VDD = 1.8V or 3.3V
0 (2)
250
-
ns
ns
(3)
tHD;DAT
tSU;DAT
Serial data setup time
VDD = 1.8V or 3.3V
VDD = 1.8V or 3.3V; RPU = 2.8 kΩ;
tr
Rise time of SCL and SDA signals Cb = 400pF; measure 0.3 × VDD to
0.7 × VDD
1000
ns
Output fall time from VIH(MIN) to
VIL(MAX)
VDD = 1.8V or 3.3V; measure 0.3 ×
VDD to 0.7 × VDD
tof
tf
250 (4)
300
ns
ns
Fall time of SCL and SDA signals VDD = 1.8V, RPU = 2.8 kΩ; 10 pF ≤
(2) (4) (5)
Cb ≤ 400 pF
Fall time of SCL and SDA signals VDD = 3.3V, RPU = 2.8 kΩ; 10 pF ≤
tf
300
ns
µs
µs
(2) (4) (5)
Cb ≤ 400 pF
tSU;STO
tBUF
tVD;DAT
Stop condition setup time
VDD = 1.8V or 3.3V
VDD = 1.8V or 3.3V
4
Bus free time between stop and
start
4.7
Transmitting Data; VDD = 1.8V or
3.3V, SCL low to SDA output valid
Valid data time (6)
3.45 (3)
3.45 (3)
µs
µs
Transmitting Data; VDD = 1.8V or
3.3V, ACK signal from SCL low to
SDA valid
tVD;ACK
Valid data time of ACK condition
SDA and SCL Characteristics (Fast Mode)
fSCLS
Clock frequency (slave)
VDD = 1.8V or 3.3V
VDD = 1.8V or 3.3V
400
kHz
µs
Start or repeated start condition
hold time
tHD;STA
0.6
tLOW
tHIGH
SCL Clock low time
SCL Clock high time
VDD = 1.8V or 3.3V
VDD = 1.8V or 3.3V
1.3
0.6
µs
µs
Start or repeated start condition
setup time
tSU;STA
VDD = 1.8V or 3.3V
0.6
µs
(3)
tHD;DAT
tSU;DAT
Serial data hold time (1)
VDD = 1.8V or 3.3V
0 (2)
-
ns
ns
Serial data setup time
VDD = 1.8V or 3.3V
100 (7)
VDD = 1.8V or 3.3V; RPU = 850 Ω;
tr
Rise time of SCL and SDA signals Cb = 400 pF; measure 0.3 × VDD to
0.7 × VDD
20
300
ns
Output fall time from VIH(MIN) to
VIL(MAX)
VDD = 1.8V; measure 0.3 × VDD to
0.7 × VDD
tof
tof
tf
6.55
12
250 (4)
250 (4)
300
ns
ns
ns
Output fall time from VIH(MIN) to
VIL(MAX)
VDD = 3.3V; measure 0.3 × VDD to
0.7 × VDD
Fall time of SCL and SDA signals VDD = 1.8V; RPU = 850 Ω; 10 pF ≤
6.55
(2) (4) (5)
Cb ≤ 400 pF
Fall time of SCL and SDA signals VDD = 3.3V; RPU = 850 Ω; 10 pF ≤
tf
12
0.6
1.3
300
ns
µs
µs
(2) (4) (5)
Cb ≤ 400 pF
tSU;STO
tBUF
Stop condition setup time
VDD = 1.8V or 3.3V
VDD = 1.8V or 3.3V
Bus free time between stop and
start
Transmitting Data; VDD = 1.8V or
3.3V, SCL low to SDA output valid
tVD;DAT
Valid data time (6)
0.9 (3)
µs
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Typical values correspond to TJ = 25°C. Minimum and maximumlimits apply over the –40°C to 150°C junction temperature
range unless otherwise stated.VIN = 13.5 V, EN =2 V, unless otherwise stated. VDD = I2C pullup voltage (3.3 V or 1.8 V)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Transmitting Data; VDD = 1.8V or
3.3V, ACK signal from SCL low to
SDA (out) low
tVD;ACK
Valid data time of ACK condition
0.9 (3)
µs
(1) tHD;DAT = the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.
(2) A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(MIN) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
(3) The maximum tHD;DAT could be 3.45 µs and 0.9 µs for Standard-mode and Fast-mode, but must be less than the maximum tVD;DAT or
tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If
the clock stretches the SCL, the data must be valid by the setup time before it releases the clock.
(4) The maximum tf for the SDA and SCL bus lines is stated in these tables as 300 ns is longer than the specified maximum tof for the
output stages (250 ns). This allows series protection resistors (RS) to be connected between the SDA and SCL pins and the SDA and
SCL bus lines without exceeding the maximum specified tf.
(5) In Fast-mode Plus, fall time is specified the same for both ouput stage and bus timing. If series resistors (RS) are used, designers
should allow for this when considering bus timing.
(6) tVD;DAT = time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
(7) A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the
Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
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7.17 Typical Characteristics
At VIN = 12 V, fsw = 400 kHz, unless otherwise stated.
60
55
50
45
40
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
EN = 2 V
USB Port(s) not
connected
EN = 0 V
图 7-1. IQ VIN Shutdown Current vs Temperature
图 7-2. IQ VIN Standby Current vs Temperature
9
8.7
8.4
8.1
7.8
7.5
7.2
VIN = 6.8 V
VIN = 13.5 V
VIN = 18 V
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
图 7-3. ENABLE/UVLO Thresholds vs Temperature
图 7-4. EN Clamp Voltage vs Temperature
图 7-5. EN Leakage Current vs Temperature
图 7-6. VIN(UVLO) vs Temperature
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7.17 Typical Characteristics (continued)
At VIN = 12 V, fsw = 400 kHz, unless otherwise stated.
19.5
19
4.71
4.7
4.69
4.68
4.67
4.66
4.65
4.64
4.63
4.62
4.61
4.6
18.5
VIN = 6.8 V, 125 mA
VIN = 6.8 V, 0 mA
VIN = 13.5 V, 0 mA
VIN = 18 V, 0 mA
RISING
FALLING
18
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
Temperature (C)
图 7-7. VIN(OVP) vs Temperature
图 7-8. LDO_5V vs VIN and Temperature
图 7-9. LDO_5V Current Limit vs VIN and Temperature
图 7-10. LDO_3V3 vs VIN and Temperature
1.6
1.59
1.58
1.57
1.56
1.55
1.54
1.53
1.52
1.51
1.5
58
57
56
55
54
53
52
51
50
VIN = 6.8 V
VIN = 13.5 V
VIN = 18 V
VIN = 6.8 V, 10 mA
VIN = 6.8 V, 0 mA
VIN = 13.5 V, 0 mA
VIN = 18 V, 0 mA
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
Temperature (C)
图 7-11. LDO_3V3 Current Limit vs VIN and Temperature
图 7-12. LDO_1V5 vs VIN and Temperature
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7.17 Typical Characteristics (continued)
At VIN = 12 V, fsw = 400 kHz, unless otherwise stated.
22
21.5
21
20.5
20
VIN = 6.8 V
VIN = 13.5 V
VIN = 18 V
19.5
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
图 7-13. LDO_1V5 Current Limit vs VIN and Temperature
图 7-14. VTVSP_PU vs Temperature
1.51
40
35
30
25
20
15
10
5
1.5
1.49
1.48
1.47
1.46
M1
M2
M4
M3+M5
0
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
Temperature (C)
图 7-15. ITVSP(ILIMIT) vs Temperature
图 7-16. Buck-Boost Power FET RDS(ON) vs Temperature
图 7-17. Boost Peak Current Limit vs Temperature (upper
图 7-18. Boost Peak Current Limit vs Temperature (lower
settings)
settings)
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7.17 Typical Characteristics (continued)
At VIN = 12 V, fsw = 400 kHz, unless otherwise stated.
图 7-19. Buck Peak Current Limit vs Temperature (upper
图 7-20. Buck Peak Current Limit vs Temperature (lower
settings)
settings)
-3.8
-3.85
-3.9
-3.95
-4
-4.05
-4.1
-4.15
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
图 7-21. Buck Negative Current Limit vs Temperature
图 7-22. BOOTx UVLO vs Temperature
5.6
5.55
5.5
1.4
1.2
1
5.45
0.8
0.6
0.4
0.2
0
5.4
5.35
5.3
VOV_BOOT1_R
VOV_BOOT1_F
VOV_BOOT2_R
VOV_BOOT2_F
5.25
5.2
-0.2
5.15
5.1
-0.4
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
Temperature (C)
图 7-23. BOOTx OVP vs Temperature
Percentage Change from Nominal
图 7-24. Buck-Boost Switching Frequency Variation vs
Temperature
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7.17 Typical Characteristics (continued)
At VIN = 12 V, fsw = 400 kHz, unless otherwise stated.
11.5
11
VSNS = 10 mV, VBUS = 3 V
VSNS = 10 mV, VBUS = 12 V
VSNS = 10 mV, VBUS = 20 V
10.5
10
9.5
9
8.5
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
图 7-25. fSW Dither Modulation Frequency vs Temperature
Target VSNS for Current Limit = 10 mV
Current Limiting Engaged
图 7-26. Current Loop Regulation Voltage vs VBUS and
Temperature
31.5
52.5
VSNS = 30 mV, VBUS = 3 V
VSNS = 30 mV, VBUS = 12 V
VSNS = 30 mV, VBUS = 20 V
VSNS = 50 mV, VBUS = 3 V
VSNS = 50 mV, VBUS = 12 V
VSNS = 50 mV, VBUS = 20 V
52
31
30.5
30
51.5
51
50.5
50
49.5
49
29.5
29
48.5
48
28.5
47.5
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
Temperature (C)
Target VSNS for Current Limit = 30 mV
Current Limiting Engaged
Target VSNS for Current Limit = 50 mV
Current Limiting Engaged
图 7-27. Current Loop Regulation Voltage vs VBUS and
图 7-28. Current Loop Regulation Voltage vs VBUS and
Temperature
Temperature
150
500
Gain = 0.025V/A; VSNS = 10 mV
Gain = 0.050V/A; VSNS = 10 mV
Gain = 0.075V/A; VSNS = 10 mV
Gain = 0.100V/A; VSNS = 10 mV
Gain = 0.025V/A; VSNS = 50 mV
Gain = 0.050V/A; VSNS = 50 mV
450
400
350
300
250
200
150
100
100
50
0
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
Temperature (C)
图 7-29. Cable Voltage Droop Compensation vs Temperature
图 7-30. Cable Voltage Droop Compensation vs Temperature
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7.17 Typical Characteristics (continued)
At VIN = 12 V, fsw = 400 kHz, unless otherwise stated.
500
450
400
350
300
250
200
25
20
15
10
5
150
100
Gain = 0.075V/A; VSNS = 50 mV
Gain = 0.100V/A; VSNS = 50 mV
0
-40 -20
0
20
40
60
80 100 120 140 160
0
0.5
1
1.5
IBUS (A)
2
2.5
3
3.5
Temperature (C)
图 7-31. Cable Voltage Droop Compensation vs Temperature
VIN = 13.5 V
VBUS = 20 V (CV) ILIMIT = 3.15 A (CC)
图 7-32. Constant Voltage to Constant Current Transition
图 7-34. VBUS Discharge Current vs Temperature
IBUS = 0 A
图 7-33. Buck-boost Output Voltage Regulation vs Temperature
24.45
24.35
24.25
24.15
24.05
23.95
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
图 7-35. (M0) 24 MHz Oscillator vs Temperature
图 7-36. (M0) 100 kHz Oscillator vs Temperature
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7.17 Typical Characteristics (continued)
At VIN = 12 V, fsw = 400 kHz, unless otherwise stated.
图 7-38. Type-C Cable Detect: RSNK vs Temperature
图 7-37. Type-C Cable Detect: IRp vs Temperature
图 7-40. VCONN Power Path: Current Limit vs Temperature
图 7-39. VCONN Power Path: RDS(ON) vs Temperature
图 7-42. USB BC1.2: DP to DM Shorting Resistance, RDCP_DAT
图 7-41. Type-C Cable Detect & VCONN: Over-voltage Protection
Thresholds vs Temperature
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7.17 Typical Characteristics (continued)
At VIN = 12 V, fsw = 400 kHz, unless otherwise stated.
23
22
21
20
19
18
17
16
-40 -20
0
20
40
60
80 100 120 140
Temperature (C)
图 7-43. USB BC1.2: DM to AGND 15 kΩ Resistance,
图 7-44. USB BC1.2: DM to AGND 20 kΩ Resistance,
RDM_DWN_15k
RDM_DWN_20k
4
3.5
3
2.5
2
VOH
VOL
1.5
1
0.5
0
-40 -20
0
20
40
60
80 100 120 140
Temperature (C)
图 7-45. USB BC1.2: DP and DM Pin Over-voltage Protection
GPIO 0, 1, 4, 7, 8, 9
IO = ±2 mA
Thresholds vs Temperature
图 7-46. GPIO: Output Voltage vs Output Current and
Temperature
图 7-48. GPIO: Input Voltage Thresholds vs Temperature
GPIO 2, 3, 5, 6
IO = ±5 mA
图 7-47. GPIO: Output Voltage vs Output Current and
Temperature
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8 Parameter Measurement Information
t
f
t
r
t
SU;DAT
70 %
30 %
70 %
30 %
SDA
cont.
t
t
HD;DAT
VD;DAT
t
f
t
HIGH
t
r
70 %
30 %
70 %
30 %
70 %
30 %
70 %
30 %
SCL
cont.
t
HD;STA
t
LOW
th
9
clock
1 / f
S
SCL
st
1
clock cycle
t
BUF
SDA
SCL
t
VD;ACK
t
t
t
t
SU;STO
SU;STA
HD;STA
SP
70 %
30 %
Sr
P
S
th
9
clock
002aac938
图 8-1. I2C Slave Interface Timing
VPU 1.65 V VPU 5.5 V
RPU
From Output
Under Test
From Output
Under Test
1 M
1 M
CL
CL
Push-Pull Load Circuit
Open-Drain Load Circuit
Internal Signal from M0
Internal Signal from M0
tprop_delay_z
tprop_delay
tprop_delay
VOH
VOL
VPU
90%
90%
90%
90%
GPIOx Output
GPIOx Output
10%
10%
10%
10%
0 V
tr
tf
tf
tr
GPIO Push-Pull Output Timing Diagram
GPIO Open-Drain Output Timing Diagram
GPIO Input
tsu
th
VOH
VOL
Internal Signal to M0
GPIO Input Timing Diagram
图 8-2. GPIO Output Timing Diagram (rise/fall vs capacitive load)
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t
t
FALL_EP
RISE_EP
V
V
OH
OL
90%
90%
10%
10%
图 8-3. USB Endpoint Transmitter Rise and Fall Time
VOH
Differential
VCRS
VCRS
Data Lines
VOL
(a) Output Crossover Voltage
2.0 V
Differential
Data Lines
V
CRS
V
CRS
0.8 V
(b) Input Crossover Voltage
图 8-4. USB Endpoint Crossover Voltages
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9 Detailed Description
9.1 Overview
The TPS25762-Q1 is a fully-integrated AEC-Q100 USB Power Delivery (USB-PD) source intended for use in
12-V automotive battery systems. Input supply pin, VIN, must be connected to a load dump clamped battery
supply, VBAT, and never exceed 40 V (ABS MAX).
The device consists of seven sub-blocks: USB-PD controller; Type-C cable plug and orientation detection
circuitry; USB Endpoint; USB Battery Charging Specification Version 1.2 (BC1.2) detection circuitry; digital
core; device power management and supervisory circuitry; and a buck-boost converter integrated with 4 power
switches.
The USB-PD controller provides the physical layer (PHY) functionality of the USB-PD protocol. The USB-PD
data is output through either the Px_CC1 pin or the Px_CC2 pin, depending on the orientation of the reversible
USB Type-C cable. For a high-level block diagram of the USB-PD physical layer, a description of its features and
more detailed circuitry, see USB-PD Physical Layer.
The cable plug and orientation detection analog circuitry automatically detects a USB Type-C cable plug
insertion and also automatically detects the cable orientation. For a high-level block diagram of cable plug
and orientation detection, a description of its features and more detailed circuitry, see Cable Plug and Orientation
Detection.
A USB Endpoint is included for downloading configuration information and firmware updates. When enabled by
firmware, the USB Endpoint connects to the Port A DP and DM pins.
The USB BC1.2 sub-block contains circuitry to support legacy USB charging methods which signal on the USB
DP and DM data lines including: DCP, Divider-3, 1.2 V mode, and HVDCP. See BC 1.2, legacy and fast charging
modes (Px_DP, Px_DM).
The power management and supervisory circuitry generates the LDO_5V, LDO_3V3, and LDO_1V5 voltage
rails used by the device. LDO_5V supplies the LDO_3V3 and LDO_1V5 rails. For a high-level block diagram
of the power management circuitry, a description of its features and more detailed operation, see Internal LDO
Regulators section.
The digital core contains an ARM Cortex-M0 with 160-kB ROM and 27-kB RAM memory. The ROM contains
firmware code to execute device functionality. RAM stores application configuration code created using the
Graphical User Interface (GUI) and post-manufacturing firmware updates. The digital core is the engine for
autonomously managing the system including: USB port connection status and communication; system power
budget and allocation; system thermal monitoring and load shedding; and fault detection and reporting. All
devices contain one controller I2C port (I2C1) for controlling external peripherals such as external EEPROM
memory; DC/DC converters; USB data multiplexers/redrivers; GPIO expanders; and additional temperature
sensors. Some devices include an I2C target port (I2C2) for connection to an external processor, HUB or
embedded controller. An integrated 8-bit analog-to-digital converter ADC (see the ADC section), monitors USB
port telemetry information. USB port connection status, voltage, current and fault information can be read from
I2C2 target port. For a high-level block diagram of the digital core and a description of its features, see the Digital
Core section.
The integrated buck-boost converter is the PA_VBUS power source. It operates in buck mode when VIN is
greater than VOUT and boost mode when VIN is less than VOUT. When VIN and VOUT are nearly the same, it
operates in transition mode.
Single Port Device
TPS25762-Q1 is a single USB-PD port device. Refer to Device Comparison Table for dual port options. The
TPS25762-Q1 device consists of a single 3 to 21 V output internal buck-boost converter, one USB-PD port
controller providing cable plug and orientation detection, one internal VCONN source path, legacy USB Battery
Charging Specification v1.2 Dedicated Charging Port (DCP) as well as legacy (non-USB compliant) charger
detection including: Divider-3, 1.2 V, and HVDCP modes. The TPS25762-Q1 device communicates with its
connected USB Type-C cable and downstream USB device at the opposite end of the cable to determine
connection state and enables VBUS sourcing as appropriate.
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9.2 Functional Block Diagram
SW1
SW2
BOOT2
BOOT1
BUCK BOOST
OUT
IN
CSP
CURRENT SENSE,
CURRENT LIMIT, CABLE
COMPENSATION
EN/UVLO
CSN/VBUS
LDO_5V
MUXes
I/O
BUFFERS,
PD PHY
(Port A)
ENABLE, LDOs, BIAS,
VCONN SUPPLY
PA_CC1
PA_CC2
PA_CABLE
DET &
VCONN
LDO_1V5
PA_DP | GPIO8
PA_DM | GPIO7
LDO_3V3
TVSP
LDO_3V3
SYNC | GPIO6
NTC | GPIO5
M0
NTC
NFET
CHARGE
PUMPS
ADC
CONFIG,
ESD,
GPIO0
STBUS/STBAT
IRQ2(o) | GPIO1
GPIO2 | I2C_SCL2
GPIO3 | I2C_SDA2
MUXes,
I/O
IRQ | GPIO9
I2C_SCL1
PA_LSGD
BUFFERS
I2C PORT 1
CONTROLLER
I2C_SDA1
AGND
PGND
I2C PORT 2
TARGET
9.3 Feature Description
9.3.1 Device Power Management and Supervisory Circuitry
9.3.1.1 VIN UVLO and Enable/UVLO
The TPS25762-Q1 has one internally fixed VIN UVLO and one user programmable UVLO using the EN/UVLO
pin. Both thresholds must be cleared for the device to start up.
•
The fixed VIN(UVLO) has a rising threshold between 5 and 5.5 V to ensure internal circuits have sufficient
headroom for proper operation.
•
The EN/UVLO pin provides the user with a resistor programmable UVLO threshold and master enable /
disable for the device.
The EN/UVLO pin has three distinct voltage ranges: shutdown, standby, and operating. When the EN/UVLO
pin is below the standby threshold VEN(STBY), the device is disabled in a low power shutdown. When EN/UVLO
voltage is greater than the standby threshold VEN(STBY) but less than the operating threshold VEN(OPER), the
internal bias rails, LDO_5V, LDO_3V3, and LDO_1V5 regulators are enabled but remaining device functions
are disabled. When EN/UVLO is greater than the operating threshold VEN(OPER) and LDO_5V, LDO_3V3 and
LDO_1V5 regulators are above their respective undervoltage threshold UVLO thresholds, the device is fully
functional. The EN/UVLO pin includes fixed hysteresis between the shutdown mode and the standby mode.
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EN/UVLO
VEN(OP)
VLDO_5V(UVLO_R)
LDO_5V
VLDO_3V3(UVLO_R)
LDO_3V3
VLDO_1V5(UVLO_R)
LDO_1V5
3-4 ms
M0
Disabled
Enabled
trim enabled
图 9-1. EN/UVLO and LDO Sequencing
表 9-1. EN/UVLO and LDO_UVLO Operation
EN/UVLO (1)
LDOs
DEVICE OPERATION
Shutdown: LDO_5V, LDO_3V3
VEN/UVLO < VEN(LDO_V5V_F)
—
—
and LDO_1V5 OFF. M0 (MCU)
is OFF.
Standby: LDO_5V, LDO_3V3
and LDO_1V5 ON. M0 (MCU) is
OFF.
VEN(LDO_V5V_R) < VEN/UVLO
VEN(STBY)
<
LDO_5V < VLDO_5V(UVLO_R), or
LDO_3V3 < VLDO_3V3(UVLO_R); or
LDO_1V5 < VLDO_1V5(UVLO_R)
LDO_5V, LDO_3V3 and
LDO_1V5 ON, M0 (MCU) is
OFF.
VEN/UVLO > VEN(OPER)
LDO_5V > VLDO_5V(UVLO_R), and
LDO_3V3 > VLDO_3V3(UVLO_R), and
LDO_1V5 > VLDO_1V5(UVLO_R)
VEN/UVLO > VEN(OPER)
Operating: M0 (MCU) is ON.
(1) Valid when VIN > VIN(UVLO_R)
.
In some cases an input UVLO level different than that provided by the internal VIN(UVLO) is needed. This can
be accomplished by using the circuit shown in UVLO Threshold Programming. The input voltage at which the
device turns on is designated VON; while the turnoff voltage is VOFF. First a value for RENB is chosen in the range
of 13 kΩ to 22 kΩ. Use 方程式 1 and 方程式 2 to calculate RENT and VOFF
.
V
ON
R
=
− 1 × R
ENB
(1)
ENT
V
EN OPER
The hysteresis between the UVLO turn-on threshold and turn-off threshold is set by the upper resistor in the
EN/UVLO resistor divider and is given by:
V
EN HYS
V
= 1 −
× V
ON
(2)
OFF
V
EN OPER
VIN
RENT
EN/UVLO
RENB
AGND
图 9-2. UVLO Threshold Programming
Where
VON = VIN turn-on voltage
•
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•
VOFF = VIN turn-off voltage
Note: Ensure RENT ≥ 47 kΩ
If the programmable UVLO is not required, the EN/UVLO pin can be connected to the IN pin with a 47 kΩ, or
larger, resistor.
9.3.1.2 Internal LDO Regulators
Three internal LDOs provide regulated supplies for operation of internal circuitry.
•
LDO_5V: Supplies buck-boost gate drive circuitry, LDO_3V3, LDO_1V5, and PA and PB VCONN power
paths. External bypass capacitance, CLDO_5V is required for proper operation. It is highly recommended to
include an additional high frequency 0.1 μF capacitor in parallel with CLDO_5V. CLDO_5V and the parallel
high frequency should be placed as close to the LDO_5V pin as possible. This capacitance: 1) provides
energy storage for the buck-boost internal FET gate drivers, and 2) is required to stabilize the internal 5-V
LDO in applications where an external 5-V supply is not connected. The TPS25762-Q1 will not operate
(release reset) until VLDO_5V(UVLO_R) threshold is met. Hard reset occurs when VLDO_5V < VLDO_5V(UVLO_F)
threshold. Current from LDO_5V returns to PGND pin. The LDO_5V output may be used to supply a small
external loads such as indicator LEDs. When supplying external components, it is recommended that the
total external load current not exceed 25 mA (MAX).
– 0.1W VCONN: when enabled in the application configuration GUI, LDO_5V is capable of sourcing 20 mA
each to PA_VCONN and PB_VCONN.
– 1W VCONN: when enabled in the application configuration GUI, this mode of operation requires an
external 4.75 - 5.5 V, 500-mA capable supply connected to LDO_5V. Back-feeding of LDO_5V is allowed.
LDO_3V3: Supplies internal analog circuits, GPIO buffers, USB PD and the USB Endpoint PHYs. External
bypass capacitance of CLDO_3V3 is required for proper operation. An additional 0.1 μF capacitor in parallel
with CLDO_3V3 is highly recommended to filter high frequency noise from the I/O buffers and PHYs. The
LDO_3V3 can supply external circuits at up to 25 mA. Expected loads include: EEPROM (5mA), NTC resistor
divider network (< 1 mA). Current may be drawn up to ILDO_3V3(ILIMIT). Note: the USB PD and Endpoint PHYs
draw current from LDO_3V3. If a CCx or Dx pin is shorted to GND during a transmission the current drawn
may reach the current limit threshold. Similarly, if any GPIO pins are configured as push-pull outputs and a
GPIO short to GND event occurs, the LDO_3V3 current limit may be reached. Current returns to AGND pin.
LDO_1V5: Supplies digital core. External bypass capacitance of CLDO_1V5 is required for proper operation.
An additional 0.1 μF capacitor in parallel with CLDO_1V5 is highly recommended to filter noise generated by
the digital core. The M0 is held in reset until all three UVLO_R (rising) thresholds are met. Current returns to
AGND pin.
•
•
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VIN
LDO_5V
(125mA)
LDO_5V
PGND
LDO_3V3
(25 mA)
LDO_3V3
GND
LDO_1V5
(10 mA)
LDO_1V5
GND
Note: LDO_5V max regulation current includes LDO_3V3
(25 mA) and LDO_1V5 (10 mA)
图 9-3. Internal LDO Connection Diagram
9.3.2 TVSP Device Configuration and ESD Protection
The Transient Voltage protection and firmware Setting Pin (TVSP) has three functions: 1) Boot configuration
settings; 2) USB connector pin short to VBUS or VBAT protection; and 3) USB connector pin enhanced ESD
protection.
•
RTVSP: At power on, the resistance between the TVSP pin and PGND determines the boot method, USB PD
port I2C addresses and I2C logic thresholds. Refer to 表 9-3. The most common configuration is shown in 图
9-4 with RTVSP open, corresponding to TVSP Index 0. During device initialization and boot, typically within 4
seconds after power on, VIN must be above 7.6 V to ensure proper bias of the TVSP pin to 5.5 V. Once boot
is complete the device can operate over the full VIN range.
•
•
CTVSP: A 0.1-µF capacitor (CTVSP) must be connected to PGND. Place CTVSP as close to the TVSP pin
as possible to minimize parasitic inductance. CTVSP is part of the centralized protection circuitry fortifying
connector pins Px_CCy, Px_DP and Px_DM from damage during short to VBUS, VBAT and ESD events. A
40-V 0.1-µF capacitor is recommended for proper operation of the internal TVSP regulator circuit.
TVSP Damper Network: Capacitance, CDAMP, and resistance, RDAMP, form an RC network preventing
excessive current from flowing inside the device durging connector pin over-voltage and ESD events.
– CDAMP: A 0.47-µF capacitor must be connected in series with RDAMP to PGND. A 40-V 0.47-µF capacitor
is recommended.
– RDAMP: A 10-Ω resistor must be connected in series with CDAMP to PGND. A 0.25-W rating is
recommended.
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LDO5V
Px_DP
ESD
ESD
BC1.2
Functions
Bias
~5.5V
PGND
TVSP
Px_DM
Px_CC1
ESD
ESD
I mirror
to ADC
USB PD
Functions
1 kW
TVSP_PD_EN
Px_CC2
Recommended
component values
PGND
图 9-4. Basic TVSP Pin Connection
表 9-2. Recommended TVSP Components
CTVSP
RDAMP
CDAMP
0.1 μF
10 Ω
0.47 μF
表 9-3. RTVSP Configuration Settings
(1)
I2C Target Port
RTVSP (kΩ)
TVSP Index
ADC Value
I2C Logic (VDD
)
Boot Mode
Addresses (A | B)(2)
0x22 | 0x26
0x23 | 0x27
0x22 | 0x26
0x23 | 0x27
0x23 | 0x27
0x22 | 0x26
0x23 | 0x27
0x22 | 0x26
0x22 | 0x26
Open
93.1
47.5
29.4
20.0
14.7
11.0
8.45
6.65
0
1
2
3
4
5
6
7
8
≤ 10 (0x0A)
≤ 24 (0x18)
≤ 42 (0x2A)
≤ 63 (0x3F)
≤ 89 (0x59)
≤ 119 (0x77)
≤ 156 (0x9C)
≤ 201 (0xC9)
≤ 255 (0xFF)
3.3 V
3.3 V
1.8 V
1.8 V
3.3 V
3.3 V
1.8 V
1.8 V
3.3 V
EEPROM
External HUB/MCU
EEPROM
External HUB/MCU
EEPROM
External HUB/MCU
EEPROM
External HUB/MCU
Firmware Update
(1) 1% resistor required.
(2) 0x22h = 0100010; 0x26h = 0100110; 0x23h = 0100011; 0x27 = 0100111
Device firmware can be updated using the USB Endpoint on the PA_DP and PA_DM pins. To enable firmware
update mode, boot the device with a resistance corresponding to Index 8 between TVPS and PGND. A boot
cycle can be performed by power cycling the device or by pulling the EN/UVLO pin momentarily below VEN(OPER)
threshold. An example circuit to enable USB Endpoint firmware update mode is shown in 图 9-5
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LDO5V
Px_DP
ESD
ESD
BC1.2
Func ons
Bias
~5.5V
PGND
USB Endpoint
Firmware Update Mode
Px_DM
Px_CC1
TVSP
ESD
ESD
I mirror
to ADC
USB PD
Func ons
1 kꢀ
TVSP_PD_EN
Px_CC2
PGND
图 9-5. Example Circuit to Enable USB Endpoint Firmware Update Mode
9.3.3 Buck-Boost Regulator
9.3.3.1 Buck-Boost Regulator Operation
The TPS25762-Q1 devices utilize a fixed frequency, current mode control buck-boost converter. This converter
operates in forced continuous conduction mode (CCM) and therefore allows inductor current to flow in either
direction at light loads. The power train consists of five N-Channel power MOSFETs. See 图 9-6. Transistors
M1 and M2 are the high-side and low-side buck FETs. Transistors M3 and M4 are the high-side and low-side
boost FETs. Transistor M5 blocks reverse conduction from OUT to SW2 during input overvoltage transients as
explained in VIN Supply and VIN Over-Voltage Protection.
•
•
IN: Receives power from the battery. The input bulk capacitor must be connected between IN and PGND.
OUT: Delivers power from the switching converter. The output bulk capacitor connects between OUT to
PGND.
•
•
PGND: Ground return for the switching converter power train.
AGND: Ground return for everything except the power train. The voltage feedback divider returns to AGND.
PGND and AGND must connect together on the circuit board.
•
•
LDO_5V: Provides gate drive for M2 and M4 and current for the bootstrap circuits feeding BOOT1 and
BOOT2. A bypass capacitor must connect from LDO_5V to PGND. See Internal LDO Regulators for more
information on LDO_5V.
LDO_3V3: Analog circuitry power supply. A bypass capacitor must connect from LDO_3V3 to AGND. See
Internal LDO Regulators for more information on LDO_3V3.
•
•
•
•
•
BOOT1: Provides gate drive for M1. A bootstrap capacitor must connect from BOOT1 to SW1.
BOOT2: Provides gate drive for M3. A bootstrap capacitor must connect from BOOT2 to SW2.
SW1: Connects M1 and M2 to external inductor.
SW2: Connects M3 and M4 to external inductor.
CSP: Positive terminal of average current sense amplifier. Connects to positive terminal of output bulk
capacitor.
•
CSN/BUS: Negative terminal of average current sense amplifier. A 10-mΩ current sense resistor is externally
connected from CSP to CSN/BUS.
Depending upon the input voltage VIN and the output voltage VOUT, the converter can operate in one of four
different states, each of which is described in following sections.
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M1
M3
M5
IN
OUT
M2
M4
PGND
图 9-6. Buck-Boost Internal Power FETs
Buck State
When the input voltage VIN significantly exceeds the output voltage VOUT, the converter enters the buck region of
operation in which it performs an endless series of buck switching cycles Buck State. M3 and M5 are constantly
on and M4 is constantly off. When the clock signals that a switching cycle has begun, the controller turns on M2
and turns off M1. This switch configuration corresponds to the off-time interval of a traditional buck converter.
The voltage difference VSW1 – VSW2 across the inductor equals –VOUT. The inductor current IL ramps down until
it reaches a threshold IVALLEY set by the error amplifiers. The controller then turns off M2 and turns on M1. This
switch configuration corresponds to the on-time interval of a traditional buck converter. The voltage difference
VSW1 – VSW2 now equals VIN – VOUT. The inductor current now ramps up until the converter clock signals that
the end of the switching cycle has been reached.
The on-time ton equals the time interval during which M1 conducts. The off-time toff equals the time interval
during which M2 conducts. Because the converter operates in FCCM, the period τ equals the sum of ton and toff.
During the buck state, the controller regulates power flow by adjusting the buck duty cycle D, which equals the
ratio ton/τ.
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VSW1 t VSW2
VIN t VOUT
t
t VOUT
IL
IVALLEY
t
toff
ton
•
图 9-7. Buck State
Buck Transition State
When the input voltage VIN is only slightly larger than the output voltage VOUT, the converter enters the buck
transition region of operation in which it alternately performs buck and boost switching cycles Buck Transition.
M5 is always on. When the clock signals that a buck switching cycle has begun, the controller turns on M2
and M3, and it turns off M1 and M4. This switch configuration corresponds to the off-time of a traditional buck
converter. The inductor current IL ramps down until it reaches a threshold IVALLEY set by the error amplifiers. The
controller then turns off M2 and turns on M1. This switch configuration corresponds to the on-time of a traditional
buck converter. The inductor current now ramps up slowly until the clock signals the end of the buck switching
cycle. The next switching cycle is a boost switching cycle. When this cycle begins, the controller turns M3 off
and turns M4 on. M2 remains off, and both M1 and M5 remain on. This switch configuration corresponds to
the on-time of a traditional boost converter. The inductor current IL now ramps up rapidly until the fixed on-time
expires. The controller then turns off M4 and turns on M3. The inductor current now ramps down until the clock
signals the end of the boost switching cycle. The next switching cycle will be another buck cycle.
During the buck transition state, the controller regulates power flow by adjusting the buck duty cycle. The boost
duty cycle remains fixed. If the converter had remained in the buck state rather than move to the buck transition
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state, the buck on-time would have become so short that it would have become impossible to regulate power
flow without pulse skipping.
VSW1 t VSW2
VIN
VIN t VOUT
t
t VOUT
IL
IVALLEY
t
toff
ton
tB
•
Buck
•
Boost
图 9-8. Buck Transition
Boost Transition State
When the input voltage VIN is only slightly smaller than the output voltage VOUT, the converter enters the boost
transition region of operation in which it alternately performs boost and buck switching cycles Boost Transition.
M5 is always on. When the clock signals that a boost switching cycle has begun, the controller turns on M1
and M4, and it turns off M2 and M3. This switch configuration corresponds to the on-time of a traditional boost
converter. The inductor current IL ramps up until it reaches a threshold IPEAK set by the error amplifiers. The
controller then turns off M4 and turns on M3. This switch configuration corresponds to the off-time of a traditional
boost converter. The inductor current now ramps down slowly until the clock signals the end of the boost
switching cycle. The next switching cycle is a buck switching cycle. When this cycle begins, the controller turns
M1 off and turns M2 on. M4 remains off, and both M3 and M5 remain on. This switch configuration corresponds
to the off-time of a traditional buck converter. The inductor current IL now ramps down rapidly until the fixed
off-time expires. The controller then turns off M2 and turns on M1. The inductor current now ramps up until the
clock signals the end of the buck switching cycle. The next switching cycle will be another boost cycle.
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During the boost transition state, the controller regulates power flow by adjusting the boost duty cycle. The buck
duty cycle remains fixed. If the converter had remained in the boost state rather than move to the boost transition
state, the boost on-time would have become so short that it would have become impossible to regulate power
flow without pulse skipping.
VSW1 t VSW2
VIN
t
VIN t VOUT
t VOUT
IL
IPEAK
t
tE
ton
toff
•
Boost
•
Buck
图 9-9. Boost Transition
Boost State
When the input voltage VIN is significantly less than the output voltage VOUT, the converter enters the boost
region of operation in which it performs an endless series of boost switching cycles Boost State. M1 and M5 are
constantly on and M2 is constantly off. When the clock signals that a switching cycle has begun, the controller
turns on M4 and turns off M3. This switch configuration corresponds to the on-time interval of a traditional boost
converter. The voltage difference VSW1 – VSW2 across the inductor equals VIN. The inductor current IL ramps
up until it reaches a threshold IPEAK set by the error amplifiers. The controller then turns off M4 and turns on
M3. This switch configuration corresponds to the off-time interval of a traditional boost converter. The voltage
difference VSW1 – VSW2 now equals VIN – VOUT, which is negative. The inductor current now ramps down until
the converter clock signals that the end of the switching cycle has been reached.
The on-time ton equals the time interval during which M4 conducts. The off-time toff equals the time interval
during which M3 conducts. Because the converter operates in FCCM, the period τ equals the sum of ton and toff.
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During the boost state, the controller regulates power flow by adjusting the boost duty cycle D, which equals the
ratio ton/τ.
VSW1 t VSW2
VIN
t
VIN t VOUT
IL
IPEAK
t
ton
toff
•
图 9-10. Boost State
Boundaries of the Regions of Operation
Regions of Operation graphically depicts the four regions of operation and the boundaries between them. When
VBUS > kVIN, the converter remains in the boost region of operation. The value k is 1.2. When VIN < VBUS < kVIN,
the converter enters the boost transition region of operation. When VIN/k < VBUS < VIN, the converter enters the
buck transition region of operation. When VBUS < VIN/k, the converter enters the buck region of operation. The
converter will cease operating if VIN exceeds the OVP threshold, which lies between 18 and 20 V. Similarly, the
converter will also cease operating if VIN drops below either the internal UVLO threshold, which lies between
5 and 5.5 V, or the user programmed EN/UVLO threshold (see VIN UVLO and ENABLE/UVLO, whichever is
greater).
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VBUS=kVIN
VIN=VBUS
VBUS
21V
Boost
VIN=kVBUS
Buck
VIN
UVLO
OVP
图 9-11. Regions of Operation
9.3.3.2 Switching Frequency, Frequency Dither, Phase-Shift and Synchronization
The PWM oscillator frequency (fsw) is programmed by firmware using the application configuration GUI. The
switching converter is intended for operation below the AM radio band (520 kHz - 1730 kHz). Three nominal fsw
settings below are available: 300 kHz, 400 kHz and 450 kHz.
Frequency dithering can be enabled by firmware via the application GUI. When enabled, the nominal oscillator
frequency is dithered by ±FSSS (approximately ±10%) using triangular waveform modulation (see Dithering using
triangular waveform modulation). The dither period τM is the reciprocal of the dither modulation frequency
FSSS_MOD. Two firmware selectable dither modulation frequencies FSSS_M are available: 10 and 25 kHz.
Dithering spreads the spectral peaks generated by switching, thereby reducing the peak harmonic levels and
easing EMI filter design.
f
1.1fs
fs
0.9fs
t
tM
图 9-12. Dithering Using Triangular Waveform Modulation
Multiple converters can be synchronized using the SYNC pin. This pin can be firmware-configured as either an
output SYNC(o) or an input SYNC(i).
•
SYNC(o): The switching clock is placed on the SYNC(o) pin. This waveform will have a duty cycle of
approximately 50%. If frequency dithering is configured by firmware, this signal will also exhibit dithering.
Four phase settings are available by firmware configuration to shift the SYNC(o) output relative to the internal
switching clock by 0°, 90°, 120°, or 180°. SYNC(o) is used to slave other DC/DC converter clocks to the
switching converter clock inside the TPS25762-Q1. When two dc/dc converters operate out of phase, peak
input current from the battery is reduced and total input bulk capacitance requirements decrease.
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Internal PWM
Clock
Falling SWx edge triggers on rising edge of
internal PWM clock
Internal SWx
node(s)
period
~50%
duty
SYNC(o)
0º phase shift
90º
SYNC(o)
90º phase shift
120º
SYNC(o)
120º phase shift
180º
SYNC(o)
180º phase shift
图 9-13. SYNC(o) Phase Shift
SYNC(o)
Other DC/DC
Converter
TPS257xx-Q1
图 9-14. Using SYNC(o) to slave DC/DC Converter
•
SYNC(i): The internal clock is synchronized to the pulse train on the SYNC(i) pin. This feature is used
to slave the TPS25762-Q1 to an external clock. The period of this clock must meet synchronization
requirements in SYNC(i) frequency ranges or the TPS25762-Q1 will instead use its internal switching clock.
If an external clock deviates outside of the acceptable frequency range and then returns to within the
acceptable frequency range, the TPS25762-Q1 will resume operation from the external clock after counting 8
consecutive clocks meeting the criteria of 表 9-4. When SYNC(i) is configured, frequency dithering is disabled
when operating from the internal clock following a failure of the external clock.
表 9-4. SYNC(i) Frequency Ranges
fSW Firmware Setting
Allowed SYNC(i) Frequency Range
MIN
MAX
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表 9-4. SYNC(i) Frequency Ranges (continued)
fSW Firmware Setting
300 kHz
Allowed SYNC(i) Frequency Range
250 kHz
334 kHz
376 kHz
353 kHz
470 kHz
530 kHz
400 kHz
450 kHz
9.3.3.3 VIN Supply and VIN Over-Voltage Protection
VIN Supply
The voltage VIN at the input supply pin IN, measured with respect to AGND, must meet the following
requirements:
•
Overvoltage: The voltage VIN must never exceed an absolute maximum of 40 V, and should not exceed 36
V under anticipated operating conditions. Automotive applications will typically require an external transient
suppressor to meet this requirement.
•
•
•
Load dump: When the converter is running and VIN exceeds 18 V, the positive slew rate dVIN/dt must not
exceed 200 V/ms.
Double battery: When the converter is not running, the positive slew rate dVIN/dt must not exceed 10 V/µs.
The input EMI filter can help mitigate input voltage slew rates.
Reverse battery: The voltage VIN must never go below –0.3 V. Automotive applications will typically require
external reverse voltage blocking circuitry.
The buck-boost switching converter is capable of delivering its full rated output power of 65 W over an input
supply range 6.8 V < VIN < 18 V . The input voltage can dip down to the UVLO threshold providing that the
output power level is appropriately derated.
VIN Overvoltage Protection Circuitry
The TPS25762-Q1 contains circuitry that protects the power train against load dump and double battery
conditions. When VIN exceeds about 19 V, a comparator determines that an input overvoltage condition has
occurred. This comparator sends a signal that shuts the switching converter down. Transistors M1, M2, and M3
in Buck-Boost Internal Power FETs are turned off, and transistor M4 is turned on. However, current is still flowing
through the inductor. Two cases may exist: the current may flow forward (from SW1 to SW2) or in reverse (from
SW2 to SW1). Reverse current flow will forward-bias the body diode of M1. The voltage across the inductor
will then equal the sum of the forward voltage of this diode plus the input voltage, which is sufficient to cause
the inductor voltage to rapidly ramp down to zero. Forward current flow will forward-bias the body diode of M2.
After the inductor current is released, a small linear regulator biases SW1 to about 15 V. When the overvoltage
condition is removed, the switching regulator may resume operation.
9.3.3.4 Feedback Paths and Error Amplifiers
The TPS25762-Q1 includes not only a programmable voltage feedback path, but also a programmable average
current feedback path that can be used to limit the average current provided by the switching converter to the
USB cable. The voltage feedback path also includes provision for cable droop compensation. 图 9-15 shows a
simplified block diagram of the relevant portions of the integrated circuit.
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CSN/BUS
RF1
A1
A2
CSP
CSN/BUS
Avg
RF2
Current
Ampli er
Voltage EA
A3
I1
I1
Vcomp
1V
MAX
I2
A4
8
icode
vcode
IDAC
RC1
CC1
Current EA
CC2
12
VDAC
RF3
图 9-15. Simplified block diagram of feedback paths and error amplifiers.
9.3.3.5 Transconductors and Compensation
The TPS25762-Q1 is internally compensated. The overall slope compensation and loop compensation is
internally fixed based on inductor and capacitance values shown in 表 10-1.
9.3.3.6 Output Voltage DAC, Soft-Start and Cable Droop Compensation
The buck-boost output voltage is regulated at the CSN/VBUS pin. A 12-bit digital-to-analog converter, VDAC,
provides ±20-mV step voltage adjustments of VCSP/BUS as commanded by device firmware.
After a successful cable detect event, firmware sets the VDAC to output 5 V as measured on the VCSN/BUS
output. An internal clock steps up the VDAC codes from an initial 0 V to final 5-V setting producing a monotonic
ramp of VCSN/BUS to 5 V at tSS
.
In some applications, the USB-PD controller may be located 1 m, or more, from the USB receptacle. When
configured and enabled by firmware, cable droop compensation will increase the VCSP/BUS linearly with
increasing load current independent of the VDAC setting. Four selectable VOUT_CDC ranges are available. 500
mV is the maximum supported cable droop voltage and it is disabled by default during USB-PD PPS contracts.
9.3.3.7 VBUS Overvoltage Protection
A fixed threshold overvoltage comparator monitors the CSN/BUS pin for overvoltage conditions. When the
VCSN/BUS_OVP_R threshold is exceeded, output OV protection circuitry turns off the internal MOSFETs. Switching
resumes when VCSN/BUS decreases below VCSN/BUS_OVP_F
.
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+
–
CSN/BUS
Buck-Boost
State Machine
VCSN/BUS_OVP
M0
ADC
图 9-16. VBUS OVP and UVP
9.3.3.8 VBUS Undervoltage Protection
PA_VBUS undervoltage conditions are monitored by the internal ADC. In accordance with USB Power Delivery
specifications, the TPS25762-Q1 firmware configures the threshold based on USB PD contract with the attached
sink device.
9.3.3.9 Current Sense Resistor (RSNS) and Current Limit Operation
The CSP and CSN/BUS pins are the positive and negative inputs to the average current sense amplifier (CSA).
The TPS25762-Q1 devices sense port A load current across sense resistor, RSNS, located between the CSP and
CSN/BUS pins. A 10-mΩ, 1%, power resistor provides a 0 - 50-mV sense voltage over the range 0 ≤ IOUT ≤ 5 A.
A seven bit digital-to-analog converter, IDAC, provides ±50-mA step current limit adjustments and is
automatically programmed by device firmware.
9.3.3.10 Buck-Boost Peak Current Limits
The buck and boost peak current limits are adjustable by firmware using the application configuration GUI. Refer
to the BUCK-BOOST PEAK CURRENT LIMITS in 节 7.6 of the Electrical Characteristics tables for selectable
values.
In most applications it is desirable to limit input current to the automotive USB module to protect module
components, connectors and wiring from over-current conditions. The worst case input current condition occurs
when VIN is minimum and VCSN/BUS is maximum (21 V) while supplying maximum 3.25 A output current. When
VIN < VBUS, the internal DC/DC converter is operating in boost mode. Refer to the 表 10-6 tables in the Inductor
Currents section to estimate the peak current versus recommended inductor value for the application.
The buck peak current limit setting selection should be just lower than the boost peak current limit. Set as close
to the boost peak current limit as selections allow to prevent the possibility of limit cycling between the two peak
current limits under extreme transients. IPEAK(BUCK) ≅ IPEAK(BOOST)
.
When selecting an inductor, it is important select one with an appropriate saturation current rating, IL(SAT). The
inductor IL(SAT) rating should larger than the maximum (MAX) IPEAK(BOOST) limit from the Electrical Characteristics
tables to avoid excessive current flow in the TPS25762-Q1 or the inductor.
9.3.4 USB-PD Physical Layer
图 9-17 shows the USB PD physical layer block surrounded by a simplified version of the analog plug and
orientation detection block. This block applies to Port A.
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LDO_3V3
IRp
RSNK
Px_CC1
Px_CC2
Digital
Core
USB-PD PHY
(Rx/Tx)
LDO_3V3
IRp
RSNK
图 9-17. USB-PD Physical Layer and Simplified Plug and Orientation Detection Circuitry
USB-PD messages are transmitted in a USB Type-C system using a BMC (Biphase Mark Coding) signaling. The
BMC signal is output on the same pin (Px_CC1 or Px_CC2) that is DC biased due to the Rp (or Rd) cable attach
mechanism discussed in the USB-PD BMC Transmitter section.
9.3.4.1 USB-PD Encoding and Signaling
图 9-18 illustrates the high-level block diagram of the baseband USB-PD transmitter. 图 9-19 illustrates the
high-level block diagram of the baseband USB-PD receiver.
4b5b
Encoder
BMC
Encoder
Data
to PD_TX
CRC
图 9-18. USB-PD Baseband Transmitter Block Diagram
Data
BMC
Decoder
SOP
Detect
4b5b
Decoder
from PD_RX
CRC
图 9-19. USB-PD Baseband Receiver Block Diagram
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9.3.4.2 USB-PD Bi-Phase Marked Coding
The USB-PD physical layer implemented in the TPS25762-Q1 is compliant to the USB-PD Specifications. The
encoding scheme used for the baseband PD signal is a version of Manchester coding called Biphase Mark
Coding (BMC). In this code, there is a transition at the start of every bit time and there is a second transition in
the middle of the bit cell when a 1 is transmitted. This coding scheme is nearly DC balanced with limited disparity
(limited to 1/2 bit over an arbitrary packet, so a very low DC level). 图 9-20 illustrates Biphase Mark Coding.
0
1
0
1
0
1
0
1
0
0
0
1
1
0
0
0
1
1
Data in
BMC
图 9-20. Biphase Mark Coding Example
The USB PD baseband signal is driven onto the Px_CC1 or Px_CC2 pin with a tri-state driver. The tri-state driver
controls slew rate to limit coupling to D+/D– and to other signal lines in the Type-C fully featured cables. When
sending the USB-PD preamble, the transmitter starts by transmitting a low level. The receiver at the other end
tolerates the loss of the first edge. The transmitter terminates the final bit by an edge to ensure the receiver
clocks the final bit of EOP.
9.3.4.3 USB-PD Transmit (TX) and Receive (Rx) Masks
The USB-PD driver meets the defined USB-PD BMC TX masks. Since a BMC coded “1” contains a signal edge
at the beginning and middle of the UI, and the BMC coded “0” contains only an edge at the beginning, the
masks are different for each. The USB-PD receiver meets the defined USB-PD BMC Rx masks. The boundaries
of the Rx outer mask are specified to accommodate a change in signal amplitude due to the ground offset
through the cable. The Rx masks are therefore larger than the boundaries of the TX outer mask. Similarly, the
boundaries of the Rx inner mask are smaller than the boundaries of the TX inner mask. Triangular time masks
are superimposed on the TX outer masks and defined at the signal transitions to require a minimum edge rate
that has minimal impact on adjacent higher speed lanes. The TX inner mask enforces the maximum limits on the
rise and fall times. Refer to the USB-PD Specifications for more details.
9.3.4.4 USB-PD BMC Transmitter
The TPS25762-Q1 transmits and receives USB-PD data over one of the Px_CCy pins for a given CC pin pair
(one pair per USB Type-C port). The Px_CCy pins are also used to determine the cable orientation (see the
Cable Plug and Orientation Detection section) and maintain cable/device attach detection. Thus, a DC bias
exists on the Px_CCy pins. The transmitter driver overdrives the Px_CCy DC bias while transmitting, but returns
to a Hi-Z state allowing the DC voltage to return to the Px_CCy pin when not transmitting. While either Px_CC1
or Px_CC2 may be used for transmitting and receiving, during a given connection only the one that mates with
the CC pin of the plug is used; so there is no dynamic switching between Px_CC1 and Px_CC2. 图 9-21 shows
the USB-PD BMC TX and RX driver block diagram.
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LDO_3V3
Level Shifter
PD_TX
Driver
Px_CC1
Px_CC2
+
Level Shifter
PD_RX
œ
Digitally
Adjustable
VREF (VRXHI, VRXLO
)
USB-PD Modem
图 9-21. USB-PD BMC TX/Rx Block Diagram
图 9-22 shows the transmission of the BMC data on top of the DC bias. Note, The DC bias can be anywhere
between the minimum threshold for detecting a UFP attach and the maximum threshold for detecting a Sink
attach to a Source. This means that the DC bias can be above or below the VOH of the transmitter driver.
VOH
DC Bias
DC Bias
VOL
VOH
DC Bias
DC Bias
VOL
图 9-22. TX Driver Transmission with DC Bias
The transmitter drives a digital signal onto the Px_CCy lines. The signal peak, VTXHI, is set to meet the TX
masks defined in the USB-PD Specifications. Note that the TX mask is measured at the far-end of the cable.
When driving the line, the transmitter driver has an output impedance of ZDRIVER. ZDRIVER is determined by the
driver resistance and the shunt capacitance of the source and is frequency dependent. ZDRIVER impacts the
noise ingression in the cable.
RDRIVER
ZDRIVER
Driver
CDRIVER
图 9-23. ZDRIVER Circuit
9.3.4.5 USB-PD BMC Receiver
The receiver block of the TPS25762-Q1 receives a signal that falls within the allowed Rx masks defined in the
USB PD specification. The receive thresholds and hysteresis come from this mask.
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图 9-24 shows an example of a multi-drop USB-PD connection (only the CC wire). This connection has the
typical Sink (device) to Source (host) connection, but also includes cable USB-PD Tx/Rx blocks. Only one
system can be transmitting at a time. All other systems are Hi-Z (ZBMCRX). The USB-PD Specification also
specifies the capacitance that can exist on the wire as well as a typical DC bias setting circuit for attach
detection.
Source
System
Sink
System
Pullup for
Attach
Detection
Connector
Connector
Cable
CC wire
Tx
Tx
CRECEIVER
CRECEIVER
Rx
Rx
CCablePlug_CC
CCablePlug_CC
RD for
Attach
Detection
Rx
Rx
Tx
Tx
SOP‘ PD
communication only
(eMarker #1)
SOP‘‘ PD
communication only
(eMarker #2)
图 9-24. Example USB-PD Multi-Drop Configuration
9.3.4.6 Squelch Receiver
The TPS25762-Q1 has a squelch receiver to monitor for the bus idle condition as defined by the USB PD
specification. The squelch receiver output reflects the state of the CC pin regardless of the source of the
transmission.
9.3.5 VCONN
Internal VCONN sourcing power paths are firmware configurable. Using only the internal LDO_5V supply, PortA
is able to draw 20 mA continuously. If an external 5-V regulator is connected to the LDO_5V pin and the
application GUI settings are enabled, PortA is able to draw 200 mA continuously. When disabled, blocking FETs
in the PortA VCONN paths protect the LDO_5V rail from high-voltage and reverse current.
When VCONN power is enabled and provided, the internal VCONN power switches have a current limit of
ILIMVC. If the VCONN load current exceeds ILIMVC, the current clamping circuit activates within tiOS_PP_CABLE and
the switch behaves as a constant current source. Reverse current blocking is disabled when current is flowing to
Px_CC1 or Px_CC2.
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Px_CC1 Gate Control
TSD_Px_VCONN
Fast current limit, ILIMVC
LDO_5V
Px_CC1
Px_CC2 Gate Control
Temp
Sensor
Px_CC2
图 9-25. VCONN Power Switches
When operating in current limit, the VCONN FET temperature rises. Local temperature sensors disable the
Px_VCONN path in current limit when Tsensor > TSD_Px_VCONN within tPP_CABLE_off. The application firmware
enters USB Type-C Error Recovery on the affected port.
LDO_5V must remain above its under voltage lock out threshold (VLDO_5V(UVLO_F)) for Px_VCONN operation. If
the VLDO_5V(UVLO_F) threshold is reached, Px_VCONN paths are automatically disabled within tPP_CABLE_off
.
9.3.6 Cable Plug and Orientation Detection
图 9-26 shows the plug and orientation detection block at each Px_CCy pin (PA_CC1, PA_CC2, PB_CC1,
PB_CC2). Each CC pin has identical detection circuitry.
When the port is operating as a Type-C source, the VREFx nodes are multiplexed to the VSRC thresholds
corresponding to the advertised Type-C source capability current, IRp_
.
When the port is operating as a Type-C sink, the VREFx nodes are multiplexed to the VSNK thresholds
corresponding to sink detection.
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LDO_5V
LDO_3V3
IRpSTD
IRpSTD_5
IRp1.5
IRp3.0
IRp1.5
VREF1
VREF2
VREF3
Px_CCy
RSNK
图 9-26. Plug and Orientation Detection Block
9.3.6.1 Configured as a Source
When either of the PA or PB ports is configured as a Source, the device detects when a cable or a Sink is
attached using the Px_CC1 and Px_CC2 pins. When in a disconnected state, the device monitors the voltages
on these pins to determine what, if anything, is connected. See USB Type-C Specification for more information.
表 9-5 shows the Cable Detect States for a Source.
表 9-5. Cable Detect States for a Source
Px_CC1 Px_CC2
CONNECTION STATE
Open Nothing attached
Open Sink attached
RESULTING ACTION
Continue monitoring both Px_CCy pins for attach. Power is not applied to Px_VBUS
or VCONN.
Open
Rd
Monitor Px_CC1 for detach. Power is applied to Px_VBUS but not to VCONN
(Px_CC2).
Monitor Px_CC2 for detach. Power is applied to Px_VBUS but not to VCONN
(Px_CC1).
Open
Ra
Rd
Open
Ra
Sink attached
Powered Cable-No UFP
attached
Monitor Px_CC2 for a Sink attach and Px_CC1 for cable detach. Power is not
applied to Px_VBUS or VCONN (Px_CC1).
Powered Cable-No UFP
attached
Monitor Px_CC1 for a Sink attach and Px_CC2 for cable detach. Power is not
applied to Px_VBUS or VCONN (Px_CC2).
Open
Ra
Provide power on Px_VBUS and VCONN (Px_CC1) then monitor Px_CC2 for a Sink
detach. Px_CC1 is not monitored for a detach.
Rd
Powered Cable-UFP Attached
Powered Cable-UFP attached
Provide power on Px_VBUS and VCONN (Px_CC2) then monitor Px_CC1 for a Sink
detach. Px_CC2 is not monitored for a detach.
Rd
Ra
When a port is configured as a Source, a current IRp1.5A, is driven out of each Px_CCy pin and each pin is
monitored for different states. When a Sink is attached to the pin a pull-down resistance of Rd to GND exists.
The current IRp1.5A is then forced across the resistance Rd generating a voltage at the Px_CCy pin. The device
applies the configured IRp1.5A until the buck-boost regulator is enabled and operating at 5 V, at which time
application firmware may remain at IRp1.5A or change to IRp3.0A
.
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When the Px_CCy pin is connected to an electronically marked cable VCONN input, the pull-down resistance is
different (Ra). In this case the voltage on the Px_CCy pin will pull below VRDstd and the system recognizes the
electronically marked cable.
The VDstd1.5 or VD3.0 threshold is monitored to detect a disconnection depending upon which Rp current source
is active. When a connection has been recognized and the voltage on Px_CCy subsequently rises above the
disconnect threshold for tCC, the system registers a disconnection.
Source monitors for
connection
Sink monitors for
orientation
USB Type-C Cable
CC
+
IRp
Rd
Rd
IRp
Ra
Ra
GND
GND
GND
TPS257xx-Q1
(Type-C source)
Type-C Sink
图 9-27. Type-C Cable
9.3.6.2 Configured as a Sink
When the TPS25762-Q1 port is configured as a Sink, such as in Firmware Update Mode with TVSP Index 8,
the device presents a pull-down resistance RSNK on each PA_CCy pin and waits for a Source to attach and
pull-up the voltage on the pin. The Source pulls-up the PA_CCy pin by applying either a resistance or a current.
The Sink detects an attachment by the presence of VBUS. The Sink determines the advertised current from the
Source by the pull-up applied to the PA_CCy pin.
9.3.6.3 Overvoltage Protection (Px_CC1, Px_CC2)
Comparators on the Px_CCy pins detect when the voltage on CC1 or CC2 is too high, or there is reverse current
into the LDO_5V output. During an overvoltage event, VCONN is disabled within tPP_CABLE_FSD and the
associated USB PD transmitter is disabled.
max(VCC1, VCC2) œ VLDO_5V
VVC_RCP
LDO_5V
Control Logic
Disable PP_CABLE
And
VVC_OVP
Px_CC1
Px_CC2
USB PD PHY
VPHY_OVP
VPHY_OVP
图 9-28. Over-voltage and Reverse Current Protection
9.3.7 ADC
The ADC is shown in 图 9-29. The ADC is an 8-bit successive approximation ADC. The input to the ADC is an
analog input mux that supports multiple inputs from various voltages and currents in the device. The output from
the ADC is available to be read and used by application firmware.
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Voltage
Divider 4
IN
Voltage
Divider 2
PA_VBUS
PB_VBUS | GPIO4
LDO_5V
Voltage
Divider 2
Voltage
Divider 3
8 bits
Voltage
Divider 1
LDO_3V3
Input
Mux
ADC
PA_DM | GPIO7
PA_DP | GPIO8
PB_DP | GPIO2
PB_DM | GPIO3
NTC | GPIO5
Buffers &
Voltage
Divider 1
I_PA_VBUS
I_TVSP
I-to-V
I-to-V
图 9-29. SAR ADC
ADC
output
8h
7h
6h
5h
4h
3h
2h
1h
0h
LSB
VIN
图 9-30. ADC Conversion
9.3.7.1 ADC Divider Ratios
The ADC voltage inputs are each divided down to the full-scale input of 1.2 V. The ADC current sensing
elements are not divided.
表 9-6 shows the divider ratios for each ADC input. The application firmware may select any group of channels
to be auto-sequenced in the round robin automatic readout mode.
表 9-6. ADC Inputs
CHANNEL
SIGNAL
I_TVSP
IN
TYPE
Current
Voltage
Voltage
Voltage
DIVIDER RATIO
BUFFERED
0
1
2
3
n/a
17
3
No
No
No
No
LDO_3V3
PA_VBUS
21
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表 9-6. ADC Inputs (continued)
CHANNEL
SIGNAL
TYPE
DIVIDER RATIO
BUFFERED
4
5
GPIO4 | PB_VBUS
IPA_VBUS
Voltage
Current
Voltage
Voltage
Voltage
Voltage
Voltage
Voltage
21
n/a
3
No
No
6
GPIO2 | PB_DP
GPIO3 | PB_DM
GPIO5 | NTC
GPIO7 | PA_DM
GPIO8 | PA_DP
LDO_5V
Yes
Yes
Yes
Yes
Yes
No
7
3
8
3
9
3
10
11
3
5
9.3.8 BC 1.2, Legacy and Fast Charging Modes (Px_DP, Px_DM)
BC 1.2 downstream port charger emulation is application GUI configurable. The following charging modes can
be enabled or disabled:
•
•
•
•
DCP (Dedicated Charging Port) Shorted Mode
Divider-3 Mode
1.2-V Mode
HVDCP (High Voltage Dedicated Charging Port) Mode
The following table shows voltage sources, resistors and comparator hardware used in each mode. Symbol "X"
represents that the corresponding module is implemented.
RDM_DWN
(20 kΩ)
Application
2.7-V SRC 1.2-V SRC
RDCP_DAT
VDAT_REF
VSEL_REF
DCP
X
Divider-3
1.2 V
X
X
X
HVDCP
X
X
X
BC1P2 DCP &
Legacy Charging
HVDCP
OVP COMPARATORS
VDAT_REF
+
VSEL_REF
dp_ovp
+
+
RDCP_DAT
dm_ovp
SW
Px_DP
MUX
Digital Core
dm_ovp
SW
Px_DM
R_2.7V
R_2.7V
R_1.2V
+
+
dm_ovp
VSEL_REF
RDM_DWN
(20k)
+
VDAT_REF
V_2.7V
V_1.2V
图 9-31. BC1P2 Functional Diagram
9.3.9 USB2.0 Low-Speed Endpoint
The USB low-speed Endpoint is a USB 2.0 low-speed (1.5 Mbps) interface used to support HID class based
accesses. The TPS25762-Q1 supports control of endpoint EP0. This endpoint enumerates to a USB 2.0 host
during firmware update mode. Firmware update mode is entered with when the device is powered on with an
RTVSP corresponding to TVSP Index 8.
图 9-32 shows the USB Endpoint physical layer. The physical layer consists of the analog transceiver, the Serial
Interface Engine, and the Endpoint FIFOs and supports low-speed USB operation.
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LDO_3V3
RPU_EP
EP_TX_DP
EP_TX_DM
RS_EP
RS_EP
32
EP0
TX/RX
FIFO
+
-
To Digital
Core
PA_DP
PA_DM
Serial
Interface
Engine
+
-
EP_RX_RCV
RX/TX
Status
Control
Digital Core
Interrupts
and Control
EP_RX_DP
EP_RX_DM
Transceiver
图 9-32. USB Endpoint PHY
The transceiver is made up of a fully differential output driver, a differential to single-ended receive buffer and
two single-ended receive buffers on the D+/D– independently. The output driver drives the D+/D– through a
source resistance RS_EP. RPU_EP is disconnected during transmit mode of the transceiver.
When the endpoint is in receive mode, the resistance RPU_EP is connected to the PA_DM pin. The RPU_EP
resistance advertises low speed mode only.
9.3.10 Digital Interfaces
The TPS25762-Q1 contains one I2C controller which used for communicating with I2C target devices. Depending
upon application GUI firmware configuration, an I2C target and GPIOs may be available.
9.3.10.1 General GPIO
An application configuration GUI manages the multi-function pins which contain General Purpose Input/Output
functionality. Each buffer is configurable to be a push-pull output or open drain output. When configured as an
input, the signal can be a de-glitched digital input or an analog input to the ADC (only designated pins). The
push-pull output is a simple CMOS totem-pole structure. Independent pull-up and pull-down enables can be
configured using the application GUI. When interfacing with non 3.3-V I/O devices the output buffer should be
configured as an open drain output and an external pull-up resistor attached to the GPIO pin.
9.3.10.2 I2C Buffer
The TPS25762-Q1 features two I2C interfaces that each use an I2C I/O driver like the one shown in 图 9-33. This
I/O consists of an open-drain output and an input comparator with de-glitching.
deglitch
SCL/SDA
Digital
Core
GND
图 9-33. I2C Driver
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9.3.11 I2C Interface
The TPS25762-Q1 has two I2C ports. I2C1 is a controller interface. I2C2 is a target interface.
I2C1 is used to read from or write to external target devices. During boot I2C1 is configured to read firmware
patch and application configuration data from an external EEPROM with target address 0x50.
Depending upon application configuration, the TPS25762-Q1 may expose target port, I2C2, using multi-function
pins: GPIO2 (I2C_SCL2), GPIO3 (I2C_SDA2). When the TPS257xx-Q1 is used in systems with a HUB or MCU,
the I2C2 port can provide connection status and telemetry information as well as transfer firmware updates from
the HUB or MCU to an EEPROM connected on I2C1.
IRQ functionality depends upon firmware application configuration. IRQ is not always available on both I2C1 and
I2C2 simultaneously. the IRQ is available as follows:
•
•
Multi-function pin GPIO9: IRQ1(i), IRQ1(o), IRQ2(o)
Multi-function pin GPIO1: IRQ2(o)
Where (i) = operates as an input, and (o) = operates as output.
In HUB applications where I2C control is not used, GPIO9 can be configured as a simple FAULT pin reporting
port over-current conditions as required by the USB 2.0 specifications.
表 9-7. I2C Summary
I2C Bus
I2C1c
Type
Typical Usage
Max Bus Frequency
Connect to I2C EEPROM, USB Type-C mux, I2C temperature sensor, I2C
Controller GPIO expander, or other I2C target. Use LDO_5V or LDO_3V3 pin as the 1 MHz (Fast Mode Plus)
pull-up voltage. Multi-controller configuration is not supported.
I2C2t
Target
Connect to I2C capable USB HUB, MCU or automotive processor.
1 MHz (Fast Mode Plus)
9.3.11.1 I2C Interface Description
The I2C1 and I2C2 ports support Standard, Fast Mode, and Fast Mode Plus I2C interfaces. The bidirectional I2C
bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a supply
through a pull-up resistor. Data transfer may be initiated only when the bus is not busy.
A controller sending a Start condition, a high-to-low transition on the SDA input/output, while the SCL input is
high initiates I2C communication. After the Start condition, the device address byte is sent, most significant bit
(MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. On the I2C bus, only one data bit is transferred
during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period
as changes in the data line at this time are interpreted as control commands (Start or Stop). The controller sends
a Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high.
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period. When a
target receiver is addressed, it must generate an ACK after each byte is received. Similarly, the controller must
generate an ACK after each byte that it receives from the target transmitter. Setup and hold times must be met to
ensure proper operation.
A controller receiver signals an end of data to the target transmitter by not generating an acknowledge (NACK)
after the last byte has been clocked out of the target. The controller receiver holding the SDA line high does
this. In this event, the target transmitter must release the data line to enable the controller to generate a Stop
condition.
图 9-34 shows the start and stop conditions of the transfer. 图 9-35 shows the SDA and SCL signals for
transferring a bit. 图 9-36 shows a data transfer sequence with the ACK or NACK at the last clock pulse.
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SDA
SCL
S
P
Start Condition
Stop Condition
图 9-34. I2C Definition of Start and Stop Conditions
SDA
SCL
Data Line
Change
图 9-35. I2C Bit Transfer
Data Output
by Transmitter
Nack
Data Output
by Receiver
SCL From
Master
Ack
1
2
8
9
S
Clock Pulse for
Acknowledgement
Start
Condition
图 9-36. I2C Acknowledgment
9.3.11.2 I2C Clock Stretching
Clock stretching for I2C2. The target I2C port may hold the clock line (SCL) low after receiving (or sending) a
byte, indicating that it is not yet ready to process more data. The controller communicating with the target must
not finish the transmission of the current bit and must wait until the clock line actually goes high. When the target
is clock stretching, the clock line remains low.
The controller must wait until it observes the clock line transitioning high plus an additional minimum time (4 μs
for standard 100-kbps I2C) before pulling the clock low again.
Any clock pulse may be stretched but typically it is the interval before or after the acknowledgment bit.
9.3.11.3 I2C Address Setting
A HUB, MCU, or automotive processor host should only use I2C_SCL2 and I2C_SDA2 for loading a firmware
patches or general status communication. Once the boot process is complete, each I2C port is assigned a
unique target address as determined by the TVSP pin. The target address used by each port on the I2C2s bus
are determined from the application configuration.
9.3.11.4 Unique Address Interface
The Unique Address Interface allows for complex interaction between an I2C controller and a single TPS25762-
Q1. The I2C target sub-address is used to receive or respond to Host Interface protocol commands. 图 9-37 and
图 9-38 show the write and read protocol for the I2C target interface, and a key is included in 图 9-39 to explain
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the terminology used. The key to the protocol diagrams is in the SMBus Specification and is repeated here in
part.
1
7
1
1
8
1
8
1
8
1
S
Unique Address
Wr
A
Register Number
A
Byte Count = N
A
Data Byte 1
A
8
1
8
1
Data Byte 2
A
Data Byte N
A
P
图 9-37. I2C Unique Address Write Register Protocol
1
S
7
1
1
8
1
1
7
1
1
8
1
Unique Address
Wr
A
Register Number
A
Sr
Unique Address
Rd
A
Byte Count = N
A
8
1
8
1
8
1
Data Byte 1
A
Data Byte 2
A
Data Byte N
A
1
P
图 9-38. I2C Unique Address Read Register Protocol
1
7
1
1
A
x
8
1
A
x
1
S
Slave Address
Wr
Data Byte
P
S
Start Condition
SR
Rd
Wr
x
Repeated Start Condition
Read (bit value of 1)
Write (bit value of 0)
Field is required to have the value x
Acknowledge (this bit position may be 0 for an ACK or
1 for a NACK)
A
P
Stop Condition
Master-to-Slave
Slave-to-Master
Continuation of protocol
图 9-39. I2C Read/Write Protocol Key
9.3.11.5 I2C Pullup Resistor Calculation
Typical value for RP, the I2C pullup resistor is given by:
RP = tr / (0.8473 × Cb)
Refer to 表 9-8 for values of tr, Cb and VOL
.
表 9-8. Parametrics from I2C Specifications
Standard Mode
(Max)
Fast Mode
(Max)
Fast Mode Plus
(Max)
Parameter
SCL clock frequency
Unit
fSCL
tr
100
1000
400
400
300
400
1000
120
kHz
ns
Rise time of both SDA and SCL signals
Capacitive load for each bus line
Cb
550
pF
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表 9-8. Parametrics from I2C Specifications (continued)
Standard Mode
(Max)
Fast Mode
(Max)
Fast Mode Plus
Unit
Parameter
(Max)
Low-level output voltage (at 3-mA current sink, VDD
> 2 V)
0.4
–
0.4
0.4
V
V
VOL
Low-level output voltage (at 2-mA current sink, VDD
≤ 2 V)
0.2 × VDD
0.2 × VDD
For additional background regarding I2C pullup resistor calculations, please refer to application report, I2C Bus
Pullup Resistor Calculation.
9.3.12 Digital Core
图 9-40 shows a simplified block diagram of the digital core.
Memory
GPIO0-9
I2C to
HUB, MCU, or
Automotive
processor
I2C_SDA2
I2C
Port 2
(target)
Processor
I2C_SCL2
IRQ
MUX
I2C_IRQx
Digital Core
CBL_DET
Bias CTL
USB PD Phy
and USB-PD
I2C to EEPROM,
PB_DC/DC, USB
redrivers
I2C_SDA1
I2C_SCL1
I2C
Port 1
(controller)
Buck-Boost
Converter
Buck-Boost
Control
OSC
ADC Read
Temp
Sense
Thermal
Shutdown
ADC
图 9-40. Digital Core Simplified Block Diagram
9.3.12.1 Device Memory
The digital core contains a combination of ROM, SRAM, and OTP. ROM and SRAM function as the storage
and operational space for application firmware. OTP contains boot configuration settings. There are 27 kBytes of
SRAM, 160 kBytes of ROM, and 512 bytes of OTP.
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9.3.12.2 Core Microprocessor
The digital core is an ARM M0+ clocked at 24MHz with zero wait states.
9.3.13 NTC Input
The NTC pin is used by the device firmware to monitor system temperature. Rising or falling voltages on the
NTC pin indicate increasing or decreasing system temperatures, respectively. To achieve a positive temperature
slope on the TPS25762-Q1 NTC pin, thermistors should be connected to LDO_3V3 as shown in 图 9-41.
LDO_3V3
LDO_3V3
RNTC
RBIAS
NTC
NTC
ADC
ADC
RTMP61
RBIAS
(b) NTC Connection
图 9-41. Thermistor Connections (a) PTC, (b) NTC
(a) TI TMP61 Sensor
See 图 9-42 and 图 9-43. Using the application configuration GUI, the user can configure system power policy
management responses for up to three VNTC voltages.
LDO_3V3
VNTC
RNTC
3.3V
RNTC
VNTC_Ph3_R
VNTC_Ph3_F
VNTC_Ph2_R
VNTC_Ph2_F
VNTC
VNTC_Ph1_R
VNTC_Ph1_F
T (°C)
RBIAS
0V
25
50
75
100
T (°C)
125
图 9-42. NTC Response Curve
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LDO_3V3
VNTC
3.3V
RBIAS
VNTC_Ph3_R
VNTC_Ph3_F
VNTC_Ph2_R
VNTC_Ph2_F
VNTC_Ph1_R
VNTC_Ph1_F
VNTC
RTMP61
RTMP61
0V
25
50
75
100
T (°C)
125
T (°C)
图 9-43. TMP61 PTC Response Curve
备注
For optimum accuracy, use the VLDO_3V3 specifications in Electrical Characteristics tables when
performing resistor divider calculations.
9.3.14 Thermal Sensors and Thermal Shutdown
There are five internal thermal sensors in the TPS25762-Q1 devices:
•
TSD_BB. Two diode OR'ed thermal sensors to monitor buck-boost power FETs. Disables buck-boost regulator
when asserted. USB-PD engine enters error recovery.
•
TSD_PA_VCONN. One thermal sensor located in the PA_VCONN path. Opens PA_VCONN FET during over-
temperature event. USB-PD engine enters error recovery.
•
•
TSD_PA_VBUS_DISCH. One thermal sensor located in the PA_VBUS discharge path. Opens PA_VBUS discharge
FET during over-temperature. Closes PA_VBUS discharge FET when temperature decreases below falling
hysteresis. (TSD_HYS) if PA_VBUS is above discharge threshold set by firmware during decreasing VBUS
transition.
•
TSD_LDO5V. One thermal sensor located in the LDO_5V regulator. Operates as master thermal shutdown.
Disables device completely during over-temperature events causing M0 to hard reset. Allows device
operation when temperature decreases below falling hysteresis (TSD_HYS).
9.4 Device Functional Modes
Shutdown Mode
The EN/UVLO pin provides electrical ON and OFF control for the TPS25762-Q1. When VEN/UVLO is below 1.15
V (typ), the device is in shutdown mode in which the Cortex M0 is disabled and only minimal analog functions
are operating. Refer to VIN UVLO and Enable/UVLO section for the detailed description of the EN/UVLO pin
functionality.
Active Mode
The TPS25762-Q1 enters active mode when VEN/UVLO is above its rising threshold, VEN(OPER), and the supply
voltage on the IN pin is above the VIN undervoltage lockout threshold, VIN(UVLO_R). In active mode, the internal
analog circuits are fully operational with the M0 enabled and executing firmware from ROM.
At the onset of active mode, firmware boot code will attempt to measure the resistance on the TVSP pin and
decode a TVSP Index value. Upon successful configuration and firmware patch load, the device is ready to
begin operation per configuration settings stored on the external EEPROM. If the configuration and patch data
do not load successfully due to communications error the device will continue to operate with only Port A
enabled with standard Type-C functionality. Index value 8 is reserved for use when updating device configuration
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and firmware patch information through the TPS25762-Q1 GUI and Port A connection. Once device boot is
complete, device firmware will control and manage USB connections in accordance with loaded application
configuration settings.
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10 Application and Implementation
备注
以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
The TPS25762-Q1 application GUI provides default settings suitable for most applications.
The most common implementations are dual port USB PD charger and dual port USB PD with USB
HUB. Consult the TPS2576x, TPS2577x Configuration GUI User's Guide and application GUI for additional
configurations.
VBAT
PGND
IN
ON
PA_CC1
PA_CC2
GPIO7
OFF
EN
LDO5V
GPIO8
CSN/BUS
CSP
LDO3V3
LDO1V5
3-21V
OUT
AGND
TVSP
3V3
FW
Update
LS_GD
NTC
IRQ
SCL1
SDA1
GPIO0
GPIO1
图 10-1. Simplified Single USB PD Charger
VBAT
PGND
IN
ON
PA_CC1
PA_CC2
OFF
EN
DP
FAULT
GPIO7
GPIO8
CSN/BUS
CSP
SYNC
5V
DM
LDO_5V
BUCK
FW
Update
SYNC
3V3
TVSP
OUT
3V3
3V3
LDO
LSGD
NTC
LDO_3V3
LDO_1V5
TMP61
DP
DM
AGND
SCL1
SDA1
IRQ
MCU/HUB
GPIO0
GPIO1
SCL2
SDA2
图 10-2. Simplified Single USB PD with MCU/HUB
Typical Application describes a detailed step-by-step design procedure for a typical charger application circuit.
10.2 Typical Application
图 10-3 Shows a typical example of a 65 W output automotive USB Type-C Power Delivery port. The device is
internally compensated and optimized for components shown in 表 10-1.
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L
CBOOT1
CBOOT2
CSNB
CSNB
PGND
PGND
SW1
BOOT1
SW2
BOOT2
M1
M3
M5
LFILT
RCSN
CFILT
RCSP
7 ~ 18V
FB
CSN/BUS
IN
M2
M4
CFILT1
CFILT2
CFILT3
CFILT4
CIN_BULK
CIN
CIN_HF
TVS
FB
CSP
OUT
PGND
PGND
PGND
0.1 µF
LM74700
RSNS = 10 m
COUT
EN/UVLO
PGND
COUT_HF
CBUS
PGND
Input Overvoltage Protection, Reverse Polarity Protection and EMI Filter
PGND
AGND
AGND
PGND
5V
LDO_5V
330 pF
C5V
C5V_HF
AGND
AGND
330 pF
PA_CC1
PA_CC2
PA_DP
ESD
ESD
PGND
AGND
AGND
AGND
TVSP
PA_DM
CTVPS_REG
PA_LSGD
CTVPS_DAMP
ESD
ESD
FW
3V3
UPDATE
AGND
AGND
3V3
LDO_3V3
C3V3
C3V3_HF
PGND
AGND
I2C_SCL1
I2C_SDA1
IRQ
CBYP
EEPROM
NTC
1V5
LDO_1V5
AGND
GPIO0
GPIO1
C1V5
C1V5_HF
AGND
I2C_SCL2
I2C_SDA2
AGND
图 10-3. TPS25762-Q1 Application Schematic
表 10-1. Recommended Inductors, Input and Output Capacitance
fSW
300
400
400
450
CIN + CHF
L
MIN of COUT + CBUS
COUT + CHF
CBUS
22 µF + 2 × 0.1 µF
22 µF + 2 ×0.1 µF
22 µF + 2 × 0.1 µF
22 µF + 2 × 0.1 µF
4.7 µH
4.7 µH
3.3 µH
3.3 µH
160 µF
30 µF + 2 × 0.1 µF
30 µF + 2 × 0.1 µF
30 µF + 2 × 0.1 µF
30 µF + 2 × 0.1 µF
130 µF + 2 × 0.1 µF
90 µF + 2 × 0.1 µF
110 µF + 2 × 0.1 µF
110 µF + 2 × 0.1 µF
120 µF
140 µF
140 µF
•
50 V rated capacitors recommended.
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HF_CAP
HF_CAP
1
2
3
4
5
6
7
25
24
23
22
21
20
19
8
18
HF_CAP
HF_CAP
图 10-4. Input and Output CHF Capacitor Placement
To ensure adequate decoupling of VIN and VOUT and robust device operation, use two 0.1 μF, CHF capacitors
per node, placed on opposite sides of the IC package, as close to the pins as possible. Typically, the inductor is
placed on the same PCB layer (top or bottom) as the IC package. The CHF capacitors on the inductor end of the
IC package may be placed on the opposite side of the PCB (bottom or top) using vias to minimize trace length
from the inductor side IN and OUT pins to the physical location of these capacitors.
表 10-2. Recommended SWx Snubber and Current Sense Filter Components
SW1 (1)
RSNB (0.25 W)
2.2 Ω || 2.2 Ω
SW2 (2)
CSP & CSN Filter (3)
RCSN (0.1 W)
0 Ω
CSNB (50 V)
RSNB (0.25 W)
2.2 Ω || 2.2 Ω
CSNB (50 V)
RCSP (0.1 W)
CFLT (50 V)
1 nf
3.3 nF
10 Ω
0.22 μF
1. As needed for EMI mitigation - user optional. (Use of this snubber can also aid in supporting devices with
high initial inrush load current that exceeds the power delivery specification.)
2. Required for robust device operation.
3. Required to meet USB-IF current regulation requirements.
10.2.1 Design Requirements
For this example, 表 10-3 are used as the target parameters.
表 10-3. Design Inputs
DESIGN PARAMETER
Input Voltage Range
UVLO Turn on Voltage
USB PD Power
EXAMPLE VALUE
6.8 V to 18 V (transients to 36 V)
6.5 V
65 W
USB PD VBUS Voltages
Output
5 V, 9 V, 15 V, 20 V and 3.3 to 21 V (PPS)
3.3 - 21 V
PDO: 5 V, 3 A; 9 V, 3 A; 15 V, 3 A, 20 V, 3.25 A
APDO: 3.3 - 21 V, 3 A
Load Current
Switching Frequency
VCONN
400 kHz
0.1 W
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表 10-3. Design Inputs (continued)
DESIGN PARAMETER
EXAMPLE VALUE
Automotive Module Maximum Current
15 A
10.2.2 Detailed Design Procedure
10.2.2.1 Application GUI Selections
Use the application GUI to select the desired operating conditions. Once complete, save the settings to the
programming PC, flash the firmware to EEPROM, and power cycle device. Once complete the TPS25762-Q1
will be ready for operation.
表 10-4. Application GUI Selections
PARAMETER
GUI SELECTION
BUCK-BOOST AND USB INPUTS
Port A VBUS Power
65 W
PDO: 5 V, 3 A; 9 V, 3 A; 15 V, 3 A; 20 V, 3.25 A
APDO: 3.3 - 21 V, 3A
Port A PDOs and APDOs
Port A VCONN Power
0.1 W
400 kHz
4.7 µH
15 A
fSW Switching Frequency
L Inductor
Automotive Module Maximum Current
LOW BATTERY INPUTS
Engine ON voltage
12.5 V
Engine OFF voltage
11 V
Run timer after engine off
THERMAL MANAGEMENT INPUTS
VNTC_PHASE1
600 seconds
1.65 V
NTC_PHASE1 Power as Percentage of MAX
VNTC_PHASE2
50 %
2.1 V
NTC_PHASE2 Power as Percentage of MAX
VNTC_PHASE3
30 %
2.4 V
NTC_PHASE3 Power as Percentage of MAX
0 % (disable PA_VBUS)
10.2.2.2 EEPROM Selection
An EEPROM is required to store user application configuration data as any firmware patch updates released by
Texas Instruments during the life of the product.
Basic requirements:
•
•
•
•
32kB (256kb)
7 Bit I2C address (0x50)
Organization: 32kb x 8 (totals 256kb)
Active firmware image is stored in one 16kb x 8 partition. The previous firmware image is retained in the other
16kb x 8 partition for reliability.
•
Page size/buffer should be 64b
表 10-5. Suggested EEPROMs
Manufacturer
Part Number
On Semi
Microchip
ST Micro
Rohm
CAV24C256
24LC256
M24256
BRA24T512=3AM
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10.2.2.3 EN/UVLO
The TPS25762-Q1 has a fixed VIN(UVLO) with rising and falling thresholds between 5 and 5.5 V, refer to 节 7.6
for exact values. The falling threshold, VIN(UVLO_F), disables the device when the battery voltage is too low for
continued operation. To establish a turn on voltage higher than VIN(UVLO_R), connect a resistor divider from the IN
supply voltage to the EN/UVLO pin. When VEN/UVLO > VEN(OPER), nominally 1.25 V, the device exits low power
shutdown and begins to startup.
In this example a VIN turn on voltage of approximately 6.5 V is required. Use the equations and examples below
to determine the required resistor values.
•
•
Choose standard value RENB = 22 kΩ.
Calculate RENT
V
ON
R
=
− 1 × R
ENB
(3)
(4)
ENT
ENT
V
EN OPER
6.5 V
1.25 V
R
=
− 1 × 22 kΩ = 92.4 kΩ
•
•
Select a standard value of 91 kΩ.
Using 22 kΩ and 91 kΩ. Rearranging 方程式 3 results in
R
ENT
V
V
=
=
+ 1 × V
EN OPER
(5)
(6)
ON
R
ENB
91 kΩ
22 kΩ
+ 1 × 1.25 V = 6.42 V
ON
•
•
Calculate VOFF
V
EN HYS
V
V
= 1 −
= 1 −
× V
ON
(7)
(8)
OFF
V
EN OPER
0.1 V
1.25 V
× 6.42 V = 5.91 V
OFF
Lastly, confirm the selected resistors do not trigger the EN/UVLO pin MAX clamp voltage. Assuming 36 V as
a maximum VIN transient.
V
× R
ENB
IN MAX
+ R
V
V
=
=
(9)
EN/UVLO MAX
EN/UVLO MAX
R
ENT
ENB
36 V × 22 kΩ
22 kΩ + 91 kΩ
= 7 V
(10)
•
The result, 7 V, is less than the EN/UVLO pin maximum clamp voltage.
10.2.2.4 Sense Resistor, RSNS, RCSP, RCSN and CFILT
The TPS25762-Q1 requires a 10-mΩ resistance between the CSP and CSN/BUS pins. For accurate current limit
regulation, ±1% precision or better is required. For a DC output current of 3.25 A, the power dissipation in the
resistor is
I2R, or (3.25 A)² × 0.01 Ω = 0.106 W.
A power resistor with 0.33-W rating, ± 1% tolerance and 2010 case is chosen. Check the manufacturers power
derating curves when selecting the component. Most derate maximum power above 70°C.
An RC filter network is required on the CSP and CSN/BUS pins for proper USB PD PPS current limit accuracy.
A filter network with RCSP = 10 Ω, RCSN = 0 Ω, and filter capacitor, CFILT = 0.22 μF is recommended. Suggested
RC filter component ratings are shown in 表 10-2. RCSN must be zero ohm to avoid interfering with the VBUS
discharge functionality.
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RCSN
CFILT
RCSP
CSN/BUS
CSP
OUT
RSNS = 10 m
COUT
COUT_HF
CBUS
To Type-C
Connetor
PGND
AGND
PGND
AGND
图 10-5. Current Sense Amplifier: RC Filter Components
10.2.2.5 Inductor Currents
表 10-1 lists recommended inductor values based on desired switching frequency, fSW. The following equations
were used to derive the values in the Buck Calculation and Boost Calculation results tables below.
VOUT
DBUCK
=
VIN(MAX) × ꢀ
(11)
(12)
VIN(MIN) × ꢀ
DBOOST = 1 -
VOUT
where
•
•
•
•
•
•
VIN(MAX) = maximum input voltage
VIN(MIN) = minimum input voltage
VOUT = output voltage
DBUCK = minimum duty cycle for buck mode
DBOOST = maximum duty cycle for boost mode
η = estimated efficiency calculated at VIN, VOUT, and IOUT
Buck Mode
DIL_BUCK(MAX)
I
+
OUT
ISW_BUCK(MAX)
=
2
(13)
(14)
(VIN(MAX) - VOUT(MIN)) × DBUCK
DIL_BUCK(MAX)
=
fSW × L
where
•
•
•
•
VIN(MAX) = maximum input voltage
VOUT(MIN) = minimum output voltage
IOUT = maximum DC output current
ΔIL-BUCK(MAX) = maximum ripple current through the inductor when in buck operation
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•
•
•
•
ISW_BUCK(MAX) = maximum switch current when in buck operation
DBUCK = minimum duty cycle for buck operation
fSW = switching frequency of the converter
L = selected inductor value
DIL_BUCK(MAX)
IMAXOUT(BUCK) = IPEAK(BUCK)
œ
2
(15)
where
•
•
•
IMAXOUT(BUCK) = maximum deliverable current through inductor by the converter
IPEAK(BUCK) = buck switch peak current limit from Electrical Characteristics table
ΔIL_BUCK(MAX) = Ripple current through the inductor calculated in 方程式 14.
Boost Mode
DIL_BOOST(MAX)
IOUT
ISW_BOOST(MAX)
=
+
2
1 œ DBOOST
(16)
(17)
VIN(MIN) × DBOOST
fSW × L
DIL_BOOST(MAX)
=
where
•
•
•
•
•
•
•
•
VIN(MIN) = minimum input voltage
VOUT(MAX) = desired output voltage
IOUT = desired output current
ΔIL_BOOST(MAX) = maximum ripple current through the inductor in boost operation
ISW_BOOST(MAX) = maximum switch current in boost operation
DBOOST = maximum duty cycle for boost operation
fSW= switching frequency of the converter
L = selected inductor value
DIL_BOOST(MAX)
IMAXOUT(BOOST) = IPEAK(BOOST)
(
œ
× (1 œ DBOOST)
)
2
(18)
where
•
•
•
•
IMAXOUT(BOOST) = maximum deliverable current through inductor by the converter
DBOOST = maximum duty cycle for boost mode
IPEAK(BOOST) = boost switch peak current limit from from Electrical Characteristics table
ΔIL_MAX(BOOST) = Ripple current through the inductor calculated in 方程式 17.
Buck Operation
表 10-6 provides the tabulated ΔIL_BUCK(MAX) and ISW_BUCK(MAX) for the conditions below.
•
•
•
•
η = 0.95
VIN(MAX) = 18 V
VOUT(MIN) = 3.3 V
DBUCK(MIN) = 0.193
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表 10-6. Buck Calculation Results (L = 4.7 µH), IBUS = 3 A
fSW
(kHz)
IOUT
(A)
ΔIL_BUCK(MAX)
(A)
ISW_BUCK(MAX)
(A)
300
400
450
300
400
450
3.00
3.00
3.00
3.00
3.00
3.00
2.87
2.15
1.91
2.01
1.51
1.34
4.44
4.08
3.96
4.01
3.76
3.67
Boost Operation
表 10-7 provides the tabulated ΔIL_BOOST(MAX), ISW_BOOST(MAX), suggested GUI IPEAK(BOOST) (MIN) settings for
the maximum output power conditions shown below.
If ISW_BOOST(MAX) > IPEAK(BOOST) (MIN) → VBUS dropout likely.
If ISW_BOOST(MAX) < IPEAK(BOOST) (MIN) → VBUS regulates normally.
•
•
•
•
η = 0.95
VIN(MIN) = 5.5 V to 9 V
VOUT(MAX) = 21 V
IOUT = 3 A
To be noted, the calculation here uses 21V 3 A instead of 20 V 3.25A because 21 V 3A has bigger inductor peak
current.
表 10-7. Boost Calculation Results (L = 4.7 µH), IBUS = 3 A
GUI (1)
IPEAK(BOOST)
(A)
fSW
(kHz)
VIN(MIN)
(V)
ΔIL_BOOST(MAX)
(A)
ISW_BOOST(MAX)
(A)
DBOOST(MAX)
5.5
6
0.751
0.729
0.706
0.683
0.661
0.638
0.615
0.593
0.751
0.729
0.706
0.683
0.661
0.638
0.615
0.593
2.93
3.10
3.25
3.39
3.52
3.62
3.71
3.79
2.20
2.33
2.44
2.54
2.64
2.71
2.78
2.84
13.51
12.62
11.83
11.16
10.61
10.10
9.65
12.3
12.3
12.3
12.3
10.8
10.8
10.8
9.3
6.5
7
300
7.5
8
8.5
9
9.27
5.5
6
13.15
12.24
11.42
10.73
10.17
9.64
12.3
12.3
12.3
10.8
10.8
10.8
9.3
6.5
7
400
7.5
8
8.5
9
9.18
8.79
9.3
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表 10-7. Boost Calculation Results (L = 4.7 µH), IBUS = 3 A (continued)
GUI (1)
IPEAK(BOOST)
(A)
fSW
(kHz)
VIN(MIN)
(V)
ΔIL_BOOST(MAX)
(A)
ISW_BOOST(MAX)
(A)
DBOOST(MAX)
5.5
6
0.751
0.729
0.706
0.683
0.661
0.638
0.615
0.593
1.95
2.07
2.17
2.26
2.34
2.41
2.47
2.51
13.02
12.11
11.29
10.59
10.02
9.49
12.3
12.3
12.3
10.8
10.8
9.3
6.5
7
450
7.5
8
8.5
9
9.03
9.3
8.63
9.3
(1) MIN value of boost peak ILIM shown. See electrical characteristics table for MIN, TYP, MAX values.
10.2.2.6 Output Capacitor
In the boost mode, the output capacitor conducts high ripple current. The output capacitor RMS ripple current is
given by 方程式 19 where the minimum VIN corresponds to the maximum capacitor current.
VOUT
ICOUT(RMS) = IOUT
ì
-1
V
IN
(19)
In this example the maximum output ripple RMS current is ICOUT(RMS) = 3.18 A. A 5-mΩ output capacitor ESR
causes an output ripple voltage of 34 mV as given by:
IOUT ì VOUT
DVRIPPLE(ESR)
=
ìESR
V
IN(MIN)
(20)
(21)
A 140 µF output capacitor (COUT + CBUS) causes a capacitive ripple voltage of 26 mV as given by:
V
≈
’
÷
◊
IN(MIN)
IOUT ì 1-
∆
VOUT
«
DVRIPPLE(COUT)
=
COUT ìF
sw
Typically a combination of ceramic and bulk capacitors is needed to provide low ESR and high ripple current
capacity. The complete schematic in Typical Application section provides COUT and CBUS recommendations
suitable for most applications.
10.2.2.7 Input Capacitor
In the buck mode, the input capacitor supplies high ripple current. The RMS current in the input capacitor is
given by:
ICIN(RMS) = IOUT Dì(1-D)
(22)
The maximum RMS current occurs at D = 0.5, which gives ICIN(RMS) = IOUT/2 = 1.5 A. A combination of ceramic
and bulk capacitors should be used to provide short path for high di/dt current and to reduce the output voltage
ripple. 表 10-1 in the Typical Application section is a good starting point for CIN selection.
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10.2.3 Application Curves
VOUT = 5 V
100
80
60
VIN = 7 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 18 V
40
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
3
IBUS (A)
L = 4.7 μH
L = 4.7 μH
图 10-6. Efficiency vs Output Current (IOUT), VOUT
=
图 10-7. Efficiency vs Output Current (IOUT), VOUT =
5 V
9 V
VOUT = 15 V
100
80
60
VIN = 7 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 18 V
40
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
IBUS (A)
3
L = 4.7 μH
L = 4.7 μH
图 10-8. Efficiency vs Output Current (IOUT), VOUT
=
图 10-9. Efficiency vs Output Current (IOUT), VOUT =
12 V
15 V
IBUS = 3 A
L = 4.7 μH
L = 4.7 μH
图 10-11. Efficiency vs Input Voltage
图 10-10. Efficiency vs Output Current (IOUT), VOUT
= 20 V
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VIN = 13.5 V
VBUS = 0 V to 5 V
IBUS = 0 A
VIN = 13.5 V
VBUS = 5 V to 0 V
IBUS = 0 A
图 10-12. Type-C Attach
图 10-13. Type-C Detach
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VIN = 7 V
VBUS = 20 V
IBUS = 0 A
VIN = 18 V
VBUS = 5 V
IBUS = 0 A
图 10-14. Boost Mode: Low VIN, No Load
图 10-15. Buck Mode: High VIN, No Load
VIN = 7 V
VBUS = 20 V
IBUS = 3 A
VIN = 18 V
VBUS = 5 V
IBUS = 3 A
图 10-16. Boost Mode: Low VIN, 3 A Load
图 10-17. Buck Mode: High VIN, 3 A load
VIN = 12 V
VBUS = 5 V
IBUS = 0 A
VIN = 12 V
VBUS = 20 V
IBUS = 0 A
图 10-19. Buck Mode: Nominal VIN, No Load
图 10-18. Boost Mode: Nominal VIN, No Load
VIN = 12 V
VBUS = 5 V
IBUS = 3 A
VIN = 12 V
VBUS = 13 V
IBUS = 0 A
图 10-20. Buck Mode: nominal VIN, 3 A Load
图 10-21. Buck-Boost Mode: VIN ≨ VBUS, No Load
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VIN = 12 V
VBUS = 12 V
IBUS = 0 A
VIN = 12 V
VBUS = 11 V
IBUS = 0 A
图 10-22. Buck-Boost Mode: VIN = VBUS, No Load
图 10-23. Buck-Boost Mode: VIN ≩ VBUS, No Load
VIN = 12 V
VBUS = 12 V
IBUS = 3 A
VIN = 12 V
VBUS = 15 V
IBUS = 0 A
图 10-24. Buck-Boost Mode: VIN = VBUS, 3 A Load
图 10-25. Buck-Boost Mode: Nominal VIN, No Load
VIN = 12 V
VBUS = 15 V
IBUS = 3 A
VIN 12 V ➔ 20 V
图 10-26. Buck-Boost Mode: Nominal VIN, 3 A Load
图 10-27. VIN(OVP) Entry
VIN 20 V ➔ 12 V
VIN 12 V ➔ 20 V
VBUS = 0 V
IBUS = 0 A
图 10-28. VIN(OVP) Recovery
图 10-29. VIN(OVP) Showing VBUS Discharge
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VIN = 13.5V
VBUS = 9 V
IBUS 0 A ➔ 3 A
VIN = 13.5V
VBUS = 5 V
IBUS 0 A ➔ 3 A
图 10-31. Load Transient (Buck): VBUS = 9 V
图 10-30. Load Transient (Buck): VBUS = 5 V
VIN
650 mV/div
VIN
650 mV/div
VBUS
650 mV/div
VBUS
650 mV/div
I_IN
1.1 A/div
I_IN
1.48 A/div
IBUS
558 mA/div
IBUS
577 mA/div
SW1
1.77 V/div
SW1
650 mV/div
SW2
1.93 V/div
SW2
2.45 V/div
VIN = 13.5V
VBUS = 15 V
IBUS 0 A ➔ 3 A
VIN = 13.5V
VBUS = 20 V
IBUS 0 A ➔ 3 A
图 10-32. Load Transient (Buck-Boost): VBUS = 15 V
图 10-33. Load Transient (Boost): VBUS = 20 V
VIN
1.62 V/div
VBUS
650 mV/div
IBUS
98.3 mA/div
7
ꢀ
6.9
ꢀ
6.8
ꢀ
6.7
ꢀ
6.6
ꢀ
6.5
ꢀ
6.4
ꢀ
6.3
ꢀ
6.2
ꢀ
6.1
ꢀ
6 ꢀ
SW1
2.72 V/div
VIN 12 V
VBUS = 20 V
ILIMIT = 3.1 A
图 10-34. Current Limit: Stepped Resistive Load
SW2
3.01 V/div
VIN 7 V ➔ 18 V
VBUS = 20 V
IBUS = 3 A
图 10-35. Line Transient: VBUS = 20 V
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VIN
1.59 V/div
VIN
1.61 V/div
VBUS
317 mV/div
VBUS
650 mV/div
IBUS
79.6 mA/div
IBUS
86.1 mA/div
SW1
2.69 V/div
SW1
2.63 V/div
SW2
1.56 V/div
SW2
2.32 V/div
VIN 7 V ➔ 18 V
VBUS = 9 V
IBUS = 3 A
VIN 7 V ➔ 18 V
VBUS = 15 V
IBUS = 3 A
图 10-37. Line Transient: VBUS = 9 V
图 10-36. Line Transient: VBUS = 15 V
VIN
1.6 V/div
VBUS
330 mV/div
IBUS
99.6 mA/div
SW1
2.68 V/div
SW2
433 mV/div
VIN 7 V ➔ 18 V
VBUS = 5 V
IBUS = 3 A
图 10-38. Line Transient: VBUS = 5 V
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11 Power Supply Recommendations
The TPS25762-Q1 is a power management device typically operated from an automotive battery, though the
power supply for the device can be any dc voltage source within the specified VIN input range. The supply should
be capable of supplying sufficient current based on the maximum inductor current in boost mode operation. The
input supply should be bypassed with bulk capacitors at the input of the application board to avoid ringing due to
parasitic impedance of the connecting cables. A typical choice is an aluminum electrolytic capacitor of 47 to 100
μF.
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12 Layout
12.1 Layout Guidelines
The basic PCB board layout requires separation of sensitive signal and power paths. This checklist must be
followed to get good performance for a well designed board.
•
Use a combination of bulk capacitors and smaller ceramic capacitors with low series impedance for the IN,
OUT, and VBUS capacitors. Place the smaller capacitors closer to the IC to provide a low impedance path for
high di/dt switching currents.
•
Refer to 表 10-1 for suggested CIN values. Place the input bypass capacitors, CIN and CIN_HF, as close to
the IN and PGND pins as possible to minimize the loop area for input switching current in buck operation.
The CIN_HF capacitors should be as close as possible - see 图 10-4. The IN and PGND pins transverse the
package and it is highly recommended to split CIN and CIN_HF such that capacitors can be placed on either
side.
•
•
Place the output filter capacitors, COUT and COUT_HF, as close to the OUT and PGND pins as possible to
minimize the loop area for output switching current in boost operation. Refer to 表 10-1 for suggested COUT
and COUT_HF values.
Place the current sense resistor and filter components. RSNS, RCSP, RCSN, and CFLT. Place the filter capacitor
for the current sense signal as close to the IC CSP and CSN/BUS as possible. Use Kelvin connections
between RSNS through the CSP and CSN resistors and to the CSP and CSN/BUS pins to avoid creating
offsets in the current sense amplifier. Avoid crossing noisy areas such as SW1 and SW2 nodes. The
recommended values in 表 10-2 provide a good starting point but may require some fine adjustment to
meet PPS current limit accuracy requirements. When deviating from recommended values, RCSP must not be
larger than 10 ohms. RCSN must be 0 ohms. CFLT should not be larger than 0.33 μF.
Place CBUS between the RSNS and the USB Type-C connector. See 表 10-1 for suggested CBUS values. .
Place the CIN, COUT, and CBUS ground connections as close as possible to the IC with thick ground trace
and/or planes on multiple layers.
•
•
•
•
Minimize the SW1 and SW2 loop areas as these are high dv/dt nodes.
Place the LDO_5V bypass capacitors, C5V and C5V_HF close to the IC pin, between the LDO_5V and PGND
pins. A 4.7 µF and 0.1 µF ceramic capacitors are typically used. LDO_5V supplies LDO_3V3 and LDO_1V5
as well as the low side buck and boost MOSFETs.
•
•
Place the LDO_3V3 bypass capacitors, C3V3 and C3V3_HF close to the IC pin, between the LDO_3V3 and
AGND pins. A 4.7 µF and 0.1 µF ceramic capacitors are typically used. LDO_3V3 supplies the analog IO
circuits.
Place the LDO_1V5 bypass capacitors, C1V5 and C1V5_HF close to the IC pin, between the LDO_1V5 and
AGND pins. A 4.7 µF and 0.1 µF ceramic capacitors are typically used. LDO_3V3 supplies the Cortex M0
and digital circuits.
•
•
•
Place the BOOT1 bootstrap capacitor close to the IC and connect directly to the BOOT1 to SW1 pins. For
EMI mittigation, a series resistor RBOOT1 may be added.
Place the BOOT2 bootstrap capacitor close to the IC and connect directly to the BOOT2 to SW2 pins. For
EMI mittigation, a series resistor RBOOT2 may be added.
Bypass the TVSP pin to PGND with a low ESR ceramic capacitor, CTVSP located close to the IC. A 0.1 µF
ceramic capacitor is typically used. RTVSP_DAMP and CTVSP_DAMP should be added in parallel close to CTVSP
10 Ω and 0.47 μF are recommended values.
.
•
•
Use care to separate the power and signal paths so that no power or switching current flows through the
AGND connections which can either corrupt the USB PD modem or GPIO signals. The PGND and AGND
traces can be connected near the AGND pin.
USB data lines, DP and DM should be differentially routed between the IC pins and USB connector.
Impedance control is based on the PCB stack-up. 90 Ω differential is recommended. Route the DP and
DM USB signals using a minimum of vias and corners which will reduce signal reflections and impedance
changes. When a via must be used, increase the clearance size around it to minimize its capacitance.
Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up
interference from the other layers of the board. Be careful when designing test points on twisted pair lines;
through-hole pins are not recommended. When it becomes necessary to turn 90°, use two 45° turns or an arc
instead of making a single 90° turn. This reduces reflections on the signal traces by minimizing impedance
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discontinuities. Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is
unavoidable, then the stub should be less than 200 mm.
•
•
CC lines should be routed with a 10-mil trace to ensure the needed current for supporting powered Type-C
cables through VCONN. For more information on VCONN refer to the Type-C specifications. For the 330 pF
CC capacitor GND pins use a 16-mil trace if possible.
GPIO signals can be fanned out on the top or bottom layer using either a 8-mil or 10-mil trace.
12.2 Layout Example
图 12-1. TPS25762-Q1 Power Stage Layout
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
Please visit TI homepage for latest technical document including application notes, user guides, and reference
designs.
IC Package Thermal Metrics application report, Semiconductor and IC Package Thermal Metrics.
13.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI
的《使用条款》。
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
USB Type-C® is a registered trademark of USB Implementers Forum.
ARM® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
所有商标均为其各自所有者的财产。
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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16-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS25762CQRQLRQ1
ACTIVE
VQFN-HR
RQL
29
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS25762
C
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
RQL 29
5 x 6, 0.5 mm pitch
VQFN-HR - 1 mm max height
VERY THIN QUAD FLATPACK-HotRod
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225475/A
www.ti.com
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
RQL0029A
PLASTIC QUAD FLATPACK-NO LEAD
A
6.1
5.9
B
0.100
MIN
PIN 1 INDEX AREA
5.1
4.9
(0.13)
SECTION A-A
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
5
30X 0.5
PKG
1.75
1.55
12X
(0.2)
4X (0.375) TYP
4X (0.625) TYP
17
9
8
18
(0.16)
0.3
33X
0.2
3.5 PKG
0.1
C A B
0.05
C
0.975
0.775
4X
C0.15
25
1
29
26
0.6
4X
0.725
0.525
4X
0.4
0.65
4X
0.45
4225332/A 10/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RQL0029A
12X (1.85)
4X (0.825)
PKG
4X (1.075)
29
26
1
25
4.7
PKG
4.65
4.325
18
8
9
17
4X (0.7)
(R0.05) TYP
30X (0.5)
33X (0.25)
4X (0.75)
4.55
5.575
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.05 MIN
0.05 MAX
ALL AROUND
ALL AROUND
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225332/A 10/2019
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RQL0029A
24X (0.825)
4X (0.825)
PKG
20X (1.2)
4X (1.075)
29
26
1
25
2X
(1.4)
2X
(0.7)
4.7
PKG
4.65
4.325
METAL TYP
18
8
9
17
4X (0.7)
(R0.05) TYP
30X (0.5)
60X (0.25)
4X (0.75)
3.525
5.575
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PADS 2-7 & 19-24: 89%
PADS 11-15: 88%
SCALE: 15X
4225332/A 10/2019
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
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Copyright © 2023，德州仪器 (TI) 公司
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