TPS2848PWPG4 [TI]

4.4A HALF BRDG BASED MOSFET DRIVER, PDSO14, 5.10 X 6.60 MM, GREEN, PLASTIC, HTSSOP-14;


型号：	TPS2848PWPG4
厂家：	TEXAS INSTRUMENTS
描述：	4.4A HALF BRDG BASED MOSFET DRIVER, PDSO14, 5.10 X 6.60 MM, GREEN, PLASTIC, HTSSOP-14 驱动光电二极管接口集成电路驱动器
文件：	总27页 (文件大小：623K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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SLVS367A − MARCH 2001 − REVISED JUNE 2001

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Inverting and Noninverting Options

FEATURES

TSSOP PowerPad Package for Excellent

Thermal Performance

Integrated Drive Regulator (4 V to 14 V)

Adjustable/Adaptive Dead-Time Control

4-A Peak current at VDRV of 14 V

10-V to 15-V Supply Voltage Range

TTL-Compatible Inputs

APPLICATIONS

Single or Multiphase Synchronous-Buck

Power Supplies

High-Current DC/DC Power Modules

Internal Schottky Diode Reduces Part Count

Synchronous or Nonsynchronous Operation

The devices feature VDRV to PGND shoot-

through protection with adaptive/adjustable

deadtime control. The deadtime, for turning on the

high-side FET from LOWDR transitioning low, is

adjustable with an external capacitor on the

DELAY pin. This allows compensation for the

effect the gate resistor has on the synchronous

FET turn off. The adaptive deadtime prevents the

turning on of the low-side FET until the voltage on

the BOOTLO pin falls below a threshold after the

high-side FET stops conducting. The high-side

drive can be configured as a ground referenced

driver or a floating bootstrap driver. The internal

Schottky diode minimizes the size and number of

external components needed for the bootstrap

driver circuit. Only one external ceramic capacitor

is required to configure the bootstrap driver.

DESCRIPTION

The TPS2838/39/48/49 devices are MOSFET

drivers designed for high-performance

synchronous power supplies. The drivers can

source and sink up to 4-A peak current at a 14-V

drive voltage. These are ideal devices to use with

power supply controllers that do not have on-chip

drivers. The low-side driver is capable of driving

loads of 3.3 nF in 10-ns rise/fall times and has

40-ns propagation delays at room temperature.

The MOSFET drivers have an integrated 150-mA

regulator, so the gate drive voltage can be

optimized for specific MOSFETs. The TPS2848

and TPS2849 have a fixed 8-V drive regulator,

while the TPS2838/39 allow the drive regulator to

be adjusted from 4 V to 14 V by selection of two

external resistors.

TPS2838, TPS2839

PWP PACKAGE

(TOP VIEW)

TPS2848, TPS2849

PWP PACKAGE

(TOP VIEW)

ENABLE

PWRRDY

DELAY

BOOT

HIGHDR

BOOTLO

BOOT

HIGHDR

BOOTLO

ACTUAL SIZE

(5,1 mm x 6,6 mm)

PWRRDY

DELAY

SYNC

ADJ

Thermal

Pad

Thermal

Pad

VDRV

LOWDR

VDRV

LOWDR

PGND

AGND

ACTUAL SIZE

(5,1 mm x 6,6 mm)

AGND

PGND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

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SLVS367A − MARCH 2001 − REVISED JUNE 2001

description (continued)

The SYNC pin can be used regardless of load to disable the synchronous FET driver and operate the power

supply nonsynchronously.

A power ready/undervoltage lockout function outputs the status of the V -pin voltage and driver regulator

output on the open-drain PWRRDY pin. This feature can be used to enable a controller’s output once the V

voltage reaches the threshold and the regulator output is stable. This function ensures both FET drivers are off

when the V voltage is below the voltage threshold.

The TPS2838/39/48/49 devices are offered in the thermally enhanced 14-pin and 16-pin PowerPAD TSSOP

package. The PowerPAD package features an exposed leadframe on the bottom that can be soldered to the

printed-circuit board to improve thermal efficiency. The TPS2838/48 are noninverting control logic while the

TPS2839/49 drivers are inverting control logic.

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ꢉ

SLVS367A − MARCH 2001 − REVISED JUNE 2001

functional block diagram (TPS2838, TPS2839)

ADJ

VDRV

Vr1

0.9 × Vref

REFERENCES

POR

SYS_UVLO

Vref

0.9 × Vref

SHUTDOWN

Vr1

PWRRDY

AGND

THERMAL

SHUTDOWN

DRIVE

REGULATOR

BOOT

SHUTDOWN

HIGHDR

BOOTLO

INVERTING OPTION

TPS2839 ONLY

VDRV

LOWDR

SYNC

SYS_UVLO

DEADTIME

PGND

ENABLE

CONTROL

DELAY

functional block diagram (TPS2848, TPS2849)

VDRV

Vr1

0.9 × Vref

REFERENCES

POR

SYS_UVLO

Vref

0.9 × Vref

SHUTDOWN

Vr1

PWRRDY

AGND

THERMAL

SHUTDOWN

DRIVE

REGULATOR

BOOT

SHUTDOWN

HIGHDR

BOOTLO

INVERTING OPTION

TPS2849 ONLY

VDRV

LOWDR

SYS_UVLO

DEADTIME

CONTROL

PGND

ENABLE

DELAY

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SLVS367A − MARCH 2001 − REVISED JUNE 2001

Terminal Functions

TERMINAL

NO.

NAME

DESCRIPTION

TPS283x TPS284x

ADJ

—

Adjust. The adjust pin is the feedback pin for the drive regulator (TPS283X only)

Analog ground

AGND

BOOT

Bootstrap. A capacitor is connected between the BOOT and BOOTLO pins to develop the floating

bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1 µF and 1 µF.

BOOTLO

DELAY

Boot low. This pin connects to the junction of the high-side and low-side MOSFETs.

Delay. Connecting a capacitor between this pin and ground adjusts the deadtime for high-side driver

Deadtime control. Connect DT to the junction of the high-side and low-side MOSFETs

Enable. If ENABLE is low, both drivers are off.

ENABLE

HIGHDR

High drive. This pin is the output drive for the high-side power MOSFET.

Input. This pin is the input signal to the MOSFET drivers.

LOWDR

Low drive. This pin is the output drive for the low-side power MOSFET.

No internal connection

PGND

PWRRDY

SYNC

Power ground. This pin is connected to the FET power ground.

Power ready. This open-drain pin indicates a power good for VDRV and V .

—

Synchronous rectifier enable. If SYNC is low, the low-side driver is always off; if SYNC is high, the

low-side driver provides gate drive to the low-side MOSFET.

Input power supply. It is recommended that a capacitor (minimum 1 µF) be connected from V to

PGND. Note that V

must be 2 V higher than VDRV.

VDRV

Drive regulator output voltage. It is recommended that a capacitor (minimum 1 µF) be connected from

VDRV to PGND. Note that V must be 2 V higher than VDRV.

detailed description

low-side driver

The low-side driver is designed to drive low r

source and sink.

N-channel MOSFETs. The current rating of the driver is 4 A,

N-channel MOSFETs. The current rating of the driver is 4 A

DS(on)

high-side driver

The high-side driver is designed to drive low r

DS(on)

minimum, source and sink. The high-side driver can be configured as a GND-reference driver or as a

floating-bootstrap driver. The internal bootstrap diode is a Schottky, for improved drive efficiency. The maximum

voltage that can be applied from BOOT to ground is 30 V.

dead-time (DT) control

Dead-time control prevents shoot-through current from flowing through the main power FETs during switching

transitions by controlling the turnon times of the MOSFET drivers. The high-side driver is not allowed to turn

on until the gate drive voltage to the low-side FET is low, and the low-side driver is not allowed to turn on until

the voltage at the junction of the power FETs (BOOTLO) is low. The TTL-compatible DT terminal connects to

the junction of the power FETs.

ENABLE

The ENABLE terminal enables the drivers. When enable is low, the output drivers are low. ENABLE is a

TTL-compatible digital terminal.

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SLVS367A − MARCH 2001 − REVISED JUNE 2001

detailed description (continued)

The IN terminal is a TTL-compatible digital terminal that is the input control signal for the drivers. The

TPS2838/48 have noninverting inputs; the TPS2839/49 have inverting inputs. On the TPS2838 and TPS2848,

a high on IN results in a high on HIGHDR. On the TPS2839 and TPS2849, a high on IN results in a low on

HIGHDR.

SYNC (TPS283x only)

The SYNC terminal controls whether the drivers operate in synchronous or nonsynchronous mode. In

synchronous mode, the low-side FET is operated as a synchronous rectifier. In nonsynchronous mode, the

low-side FET is always off. SYNC is a TTL-compatible digital terminal.

PWRRDY

Depicts the status of the V

pin voltage and the driver regulator output on the open-drain PWRRDY pin.

DELAY

Adjustable high-side turnon delay from from when the low-side FET is turned off.

ADJ (TPS283x only)

Input for adjusting the driver regulator output. See the application information section for the adjustment formula.

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V

Input voltage range:ADJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V

BOOT to PGND (high-side driver ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 30 V

BOOTLO to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V

BOOT to BOOTLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V

ENABLE, IN, and SYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V

VDRV, PWRRDY, and DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V

DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V

Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C

Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: Unless otherwise specified, all voltages are with respect to PGND.

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SLVS367A − MARCH 2001 − REVISED JUNE 2001

DISSIPATION RATING TABLE

PACKAGE

≤ 25°C

DERATING FACTOR

26.68 mW/°C

= 70°C

T = 85°C

‡

14-pin PWP with solder

2668

1467

563

1067

409

‡

14-pin PWP without solder

1024

2739

1108

10.24 mW/°C

‡

16-pin PWP with solder

27.39 mW/°C

1506

609

1095

443

‡

16-pin PWP without solder

11.08 mW/°C

JUNCTION-CASE THERMAL RESISTANCE TABLE

14-pin PWP

16-pin PWP

Junction-case thermal resistance

2.07 °C/W

‡

Test Board Conditions:

1. Thickness: 0.062I

2. 3I × 3I (for packages < 27 mm long)

3. 4I × 4I (for packages > 27 mm long)

4. 2-oz copper traces located on the top of the board (0,071 mm thick)

5. Copper areas located on the top and bottom of the PCB for soldering

6. Power and ground planes, 1-oz copper (0,036 mm thick)

7. Thermal vias, 0,33 mm diameter, 1,5 mm pitch

8. Thermal isolation of power plane

For more information, refer to TI technical brief literature number SLMA002.

recommended operating conditions

MIN NOM

MAX

UNIT

Supply voltage, V

Input voltage, V BOOT to PGND

electrical characteristics over recommended operating virtual junction temperature range,

= 12 V, ENABLE = High, C = 3.3 nF (unless otherwise noted)

supply current

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

425

UNIT

µA

= Low,

= High,

= 13 V

(ENABLE)

Quiescent current

(ENABLE)

NOTE 2: Ensured by design, not production tested.

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SLVS367A − MARCH 2001 − REVISED JUNE 2001

electrical characteristics over recommended operating virtual junction temperature range,

= 12 V, ENABLE = High, C = 3.3 nF (unless otherwise noted) (continued)

dead-time control

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LOWDR high-level input voltage

LOWDR low-level input voltage

DT high-level input voltage

DT low-level input voltage

Deadtime delay

Over full VDRV range

See Note 2

%VDRV

IH(LOWDR)

IL(LOWDR)

IH(DT)

Over full V

range

Over full V

1.5

IL(DT)

= 4 V to 14 V

See Note 2

0.5

ns/pF

(VDRV)

= 4.5 V, T = 25°C, See Note 2

150

100

Driver nonoverlap time (DT to LOWDR)

= 14.5 V, T = 25°C, See Note 2

= 4.5 V,

= 50 pF

L(Delay)

See Note 2

180

125

100

T = 25°C,

Driver nonoverlap time (LOWDR to

HIGHDR)

= 14.5 V, C

= 50 pF

L(Delay)

(VDRV)

T = 25°C,

See Note 2

= 4.5 V,

= 0 pF

(VDRV)

T = 25°C,

L(Delay)

See Note 2

Driver nonoverlap time (LOWDR to

HIGHDR)

= 14.5 V, C

= 0 pF

L(Delay)

(VDRV)

T = 25°C,

See Note 2

NOTE 2: Ensured by design, not production tested.

high-side driver

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

= 0.5 V (src)

= 4 V (sink)

= 0.5 V (src)

= 8 V (sink)

= 0.5 V (src)

= 14 V (sink)

= 4 V (src)

1.3

2.4

3.3

3.9

4.4

−V

= 4 V,

(HIGHDR)

(BOOT) (BOOTLO)

See Note 2

−V

= 8 V,

(BOOT) (BOOTLO)

See Note 2

Peak output current

−V

= 14 V,

= 4.5 V

= 7.5 V,

= 11.5 V,

(BOOT) (BOOTLO)

See Note 2

−V

(BOOT) (BOOTLO)

T = 25°C

= 0.5 V (sink)

= 7 V (src)

−V

(BOOT) (BOOTLO)

Output resistance

Ω

T = 25°C

= 0.5 V (sink)

= 11 V (src)

= 0.5 V (sink)

−V

(BOOT) (BOOTLO)

T = 25°C

HIGHDRV-to-BOOTLO resistor

250

kΩ

= 4 V

(BOOT)

= 3.3 nF,

= GND,

(BOOTLO)

= 8 V

T = 125°C

= 14 V

= 4 V

Rise and fall time

(see Notes 2 and 3)

t /t

r f

170

= 10 nF, V

(BOOTLO)

= 8 V

140

100

120

T = 125°C

= 14 V

= 4 V

Propagation delay time,

HIGHDR going low

(excluding deadtime)

= GND, T = 125°C,

(BOOTLO)

See Notes 2 and 3

= 8 V

100

PHL

= 14 V

NOTES: 2: Ensured by design, not production tested.

3. The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the

combined current from the bipolar and MOSFET transistors. The output resistance is the r of the MOSFET transistor when

DS(on)

the voltage on the driver output is less than the saturation voltage of the bipolar transistor.

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ꢉ

SLVS367A − MARCH 2001 − REVISED JUNE 2001

electrical characteristics over recommended operating virtual junction temperature range,

= 12 V, ENABLE = High, C = 3.3 nF (unless otherwise noted) (continued)

low-side driver

PARAMETER

TEST CONDITIONS

MIN

TYP

1.6

2.4

3.3

3.9

4.4

MAX

UNIT

= 0.5 V (src)

= 4 V (sink)

= 0.5 V (src)

= 8 V (sink)

= 0.5 V (src)

= 14 V (sink)

= 4 V (src)

= 4 V,

(LOWDR)

(HIGHDR)

(LOWDR)

(VDRV)

T = 25°C,

See Note 2

= 8 V,

(VDRV)

T = 25°C,

Peak output current

See Note 2

= 14 V (src),

(VDRV)

T = 25°C,

See Note 2

= 4.5 V,

(VDRV)

T = 25°C

= 0.5 V (sink)

= 7 V (src)

= 7.5 V,

(VDRV)

T = 25°C

Output resistance

Ω

= 0.5 V (sink)

= 11 V (src)

= 0.5 V (sink)

= 11.5 V,

(VDRV)

T = 25°C

LOWDR-to-PGND resistor

250

kΩ

= 4 V

(VDRV)

= 3.3 nF, T = 125°C,

= 8 V

See Note 2

= 14 V

= 4 V

t /t

r f

Rise and fall time

110

100

= 10 nF,

T = 125°C,

= 8 V

See Note 2

= 14 V

= 4 V

110

Propagation delay time, LOWDR

going high (excluding deadtime)

T = 125°C,

See Notes 2 and 3

= 8 V

PLH

= 14 V

NOTES: 2: Ensured by design, not production tested.

3: The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the

combined current from the bipolar and MOSFET transistors. The output resistance is the r of the MOSFET transistor when

DS(on)

the voltage on the driver output is less than the saturation voltage of the bipolar transistor.

undervoltage lockout

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Start threshold voltage

10.3

Stop threshold voltage

Hysteresis voltage

7.5

hys

1.5

Propagation delay time

Falling-edge delay time

50-mV overdrive, See Note 2

See Note 2

300

1000

NOTE 2: Ensured by design, not production tested.

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SLVS367A − MARCH 2001 − REVISED JUNE 2001

electrical characteristics over recommended operating virtual junction temperature range,

= 12 V, ENABLE = High, C = 3.3 nF (unless otherwise noted) (continued)

digital control (IN, ENABLE, SYNC)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Over full V

range

High-level input voltage

Low-level input voltage

ENABLE, SYNC

2.2

ENABLE, SYNC

ENABLE propagation delay time

See Note 2

µs

NOTE 2: Ensured by design, not production tested.

thermal shutdown

PARAMETER

TEST CONDITIONS

MIN

155

TYP

MAX

185

UNIT

Thermal shutdown

See Note 2

170

Falling edge delay time

µs

NOTE 2: Ensured by design, not production tested.

drive regulator

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Recommended output voltage

Output voltage

= 10 V to 15 V,

= 10 V to 15 V

= 10 V,

= 5 mA to 150 mA

= 150 mA

−2

%nom

ref

Reference voltage

1.235

1000

Dropout voltage

1100

See Note 2

Line regulation

= 10 V to 15 V,

= 10 V,

= 5 mA

0.2

%/V

Load regulation

= 5 mA to 150 mA

Current limit

= 8 V

0.5

0.6

0.8

PWRRDY saturation voltage

Leakage current

= 5 mA

= 4.5 V

µA

lkg

I(PWRRDY)

drive regulator undervoltage lockout

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Start threshold voltage

See Note 2

85 %Vref

%Vref

Stop threshold voltage

hys

Hysteresis voltage

2.5

%Vref

Propagation delay time

Falling-edge delay time

Power on reset time

50-mV overdrive,

See Note 2

300

1000

µs

See Note 2

100

1000

NOTE 2: Ensured by design, not production tested.

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SLVS367A − MARCH 2001 − REVISED JUNE 2001

PARAMETER MEASUREMENT INFORMATION

Rising Edge

Falling Edge

50%

(EN, SYNC, IN)

off

50%

(LOWDRV, HIGHDR)

50%

(LOWDRV, HIGHDR)

High-Side and Low-Side Drive

90%

10%

90%

10%

(LOWDRV, HIGHDR)

Figure 1. Voltage Waveforms

TYPICAL CHARACTERISTICS

FALL TIME

INPUT VOLTAGE (VDRV)

RISE TIME

INPUT VOLTAGE (VDRV)

= 3.3 nF

= 25°C

= 3.3 nF

= 25°C

High Side

Low Side

High Side

Low Side

10 11 12 13 14 15

V − Input Voltage (VDRV) − V

Figure 2

Figure 3

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SLVS367A − MARCH 2001 − REVISED JUNE 2001

TYPICAL CHARACTERISTICS

RISE TIME

FALL TIME

JUNCTION TEMPERATURE

VDRV = 8 V

= 3.3 nF

VDRV = 8 V

= 3.3 nF

High Side

Low Side

−50

−25

100

125

100

125

−50

−25

− Junction Temperature − °C

Figure 4

Figure 5

HIGH-TO-LOW PROPAGATION DELAY TIME

LOW-TO-HIGH PROPAGATION DELAY TIME

INPUT VOLTAGE (VDRV)

200

180

140

120

= 3.3 nF

= 25°C

= 3.3 nF

= 25°C

160

100

140

120

High Side

100

High Side

Low Side

10 11 12 13 14 15

V − Input Voltage (VDRV) − V

Figure 6

Figure 7

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ꢉ

SLVS367A − MARCH 2001 − REVISED JUNE 2001

TYPICAL CHARACTERISTICS

LOW-TO-HIGH PROPAGATION DELAY TIME

HIGH-TO-LOW PROPAGATION DELAY TIME

JUNCTION TEMPERATURE

180

160

VDRV = 8 V

= 3.3 nF

VDRV = 8 V

= 3.3 nF

High Side

140

120

High Side

100

Low Side

−50

−25

100

125

−50

−25

100

125

− Junction Temperature − °C

Figure 8

Figure 9

DRIVER-OUTPUT FALL TIME

DRIVER-OUTPUT RISE TIME

LOAD CAPACITANCE

1000

VDRV = 8 V

= 25°C

VDRV = 8 V

T = 25°C

100

High Side

Low Side

0.01

0.1

100

0.01

0.1

100

− Load Capacitance − nF

Figure 10

Figure 11

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SLVS367A − MARCH 2001 − REVISED JUNE 2001

TYPICAL CHARACTERISTICS

SUPPLY CURRENT

INPUT VOLTAGE (VDRV)

= 50 pF

= 25°C

= 50 pF

= 25°C

22.5

17.5

500 kHz

100 kHz

300 kHz

200 kHz

2 MHz

50 kHz

25 kHz

12.5

7.5

1 MHz

2.5

10 11 12 13 14 15

V − Input Voltage (VDRV) − V

Figure 12

Figure 13

PEAK SOURCE CURRENT

PEAK SINK CURRENT

INPUT VOLTAGE (VDRV)

4.5

= 25°C

4.5

3.5

High Side

Low Side

3.5

2.5

Low Side

2.5

High Side

1.5

0.5

10 11 12 13 14 15

V − Input Voltage (VDRV) − V

Figure 14

Figure 15

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ꢉ

SLVS367A − MARCH 2001 − REVISED JUNE 2001

TYPICAL CHARACTERISTICS

BOOTSTRAP SCHOTTKY DIODE

INPUT CURRENT

START/STOP V

UNDERVOLTAGE LOCKOUT

OUTPUT VOLTAGE

JUNCTION TEMPERATURE

1200

1000

800

= 25°C

9.8

Start

9.6

9.4

9.2

600

400

8.8

8.6

Stop

200

8.4

8.2

0.25 0.5 0.75

1.25 1.5 1.75

−50

−25

100

125

− Junction Temperature − °C

− Output Voltage − V

Figure 16

Figure 17

DELAY TIME

DELAY TIME (DEAD TIME)

JUNCTION TEMPERATURE

INPUT VOLTAGE (VDRV)

200

180

160

200

180

VDRV = 8 V

= 25°C

50 pF

160

10 pF

50 pF

20 pF

5 pF

10 pF

5 pF

20 pF

140

120

140

120

50 pF

100

1 pF

0 pF

1 pF

10 11 12 13 14 15

−50

−25

100

125

V − Input Voltage (VDRV) − V

− Junction Temperature − °C

Figure 18

Figure 19

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SLVS367A − MARCH 2001 − REVISED JUNE 2001

TYPICAL CHARACTERISTICS

VDRV LOAD REGULATION

VDRV LINE REGULATION

8.062

8.061

8.115

= 1 µF

L(VDRV)

= 25°C

L(VDRV)

= 25°C

8.11

8.06

8.105

8.059

8.1

8.058

8.057

8.095

8.09

8.056

8.055

8.085

−10

110 130 150

− Supply Voltage − V

I − Input Current − mA

Figure 20

Figure 21

APPLICATION INFORMATION

Figure 22 shows the circuit schematic of a 100-kHz synchronous-buck converter implemented with a TL5001ACD

pulse-width-modulation (PWM) controller and a TPS2838 driver. The converter operates over an input range from

4.5 V to 12 V and has a 3.3-V output. The circuit can supply 3-A continuous load. The converter achieves an efficiency

of 94% for V = 5 V, I =1 A, and 93% for V = 5 V, I = 3 A.

VDRV

Voltage

(V)

(kΩ)

ADJ

165

261

322

14.5

To set the regulator voltage (TPS2838/39) use the following equation:

_{R2 +}ǒ _VDRVǓ_* R1

1.235

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SLVS367A − MARCH 2001 − REVISED JUNE 2001

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SLVS367A − MARCH 2001 − REVISED JUNE 2001

APPLICATION INFORMATION

Great care should be taken when laying out the PC board. The power-processing section is the most critical

and will generate large amounts of EMI if not properly configured. The junction of Q1, Q2, and L1 should be very

tight. The connection from Q1 drain to the positive sides of C5, C10, and C11 and the connection from Q2 source

to the negative sides of C5, C10, and C11 should be as short as possible. The negative terminals of C7 and

C12 should also be connected to Q2 source.

Next, the traces from the MOSFET driver to the power switches should be considered. The BOOTLO signal from

the junction of Q1 and Q2 carries the large gate drive current pulses and should be as heavy as the gate drive

traces. The bypass capacitor (C14) should be tied directly across V

and PGND.

The next most sensitive node is the FB node on the controller (terminal 4 on the TL5001A). This node is very

sensitive to noise pickup and should be isolated from the high-current power stage and be as short as possible.

The ground around the controller and low-level circuitry should be tied to the power ground as the output. If these

three areas are properly laid out, the rest of the circuit should not have other EMI problems and the power supply

will be relatively free of noise.

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PACKAGE OPTION ADDENDUM

www.ti.com

24-Jan-2013

PACKAGING INFORMATION

Orderable Device

TPS2838PWP

Status Package Type Package Pins Package Qty

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

(1)

(2)

(3)

(4)

ACTIVE

HTSSOP

PWP

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

TPS2838

TPS2838PWPG4

TPS2839PWP

ACTIVE

PWP

Green (RoHS

& no Sb/Br)

TPS2838

TPS2839

TPS2848

TPS2849

Green (RoHS

& no Sb/Br)

TPS2839PWPG4

TPS2848PWP

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TPS2848PWPG4

TPS2849PWP

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TPS2849PWPG4

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

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24-Jan-2013

⁽⁴⁾Only one of markings shown within the brackets will appear on the physical device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

IMPORTANT NOTICE

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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

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TPS2848PWPG4 [TI]

相关型号：

TPS2848PWPR

TPS2848PWPRG4

TPS2848_15

TPS2849

TPS2849PWP

TPS2849PWPG4

TPS2849PWPR

TPS2849PWPRG4

TPS2901

TPS2H000-Q1

TPS2H000AQPWPRQ1

TPS2H000BQPWPRQ1