TPS2849PWPR_技术文档

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SLVS367A – MARCH 2001 – REVISED JUNE 2001

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D

Inverting and Noninverting Options

FEATURES

D

TSSOP PowerPad Package for Excellent

Thermal Performance

D

Integrated Drive Regulator (4 V to 14 V)

Adjustable/Adaptive Dead-Time Control

4-A Peak current at VDRV of 14 V

10-V to 15-V Supply Voltage Range

TTL-Compatible Inputs

APPLICATIONS

D

Single or Multiphase Synchronous-Buck

Power Supplies

High-Current DC/DC Power Modules

Internal Schottky Diode Reduces Part Count

Synchronous or Nonsynchronous Operation

The devices feature VDRV to PGND shoot-

through protection with adaptive/adjustable

deadtime control. The deadtime, for turning on the

high-side FET from LOWDR transitioning low, is

adjustable with an external capacitor on the

DELAY pin. This allows compensation for the

effect the gate resistor has on the synchronous

FET turn off. The adaptive deadtime prevents the

turning on of the low-side FET until the voltage on

the BOOTLO pin falls below a threshold after the

high-side FET stops conducting. The high-side

drive can be configured as a ground referenced

driver or a floating bootstrap driver. The internal

Schottky diode minimizes the size and number of

external components needed for the bootstrap

driver circuit. Only one external ceramic capacitor

is required to configure the bootstrap driver.

DESCRIPTION

The TPS2838/39/48/49 devices are MOSFET

drivers designed for high-performance

synchronous power supplies. The drivers can

source and sink up to 4-A peak current at a 14-V

drive voltage. These are ideal devices to use with

power supply controllers that do not have on-chip

drivers. The low-side driver is capable of driving

loads of 3.3 nF in 10-ns rise/fall times and has

40-ns propagation delays at room temperature.

The MOSFET drivers have an integrated 150-mA

regulator, so the gate drive voltage can be

optimized for specific MOSFETs. The TPS2848

and TPS2849 have a fixed 8-V drive regulator,

while the TPS2838/39 allow the drive regulator to

be adjusted from 4 V to 14 V by selection of two

external resistors.

TPS2838, TPS2839

PWP PACKAGE

(TOP VIEW)

TPS2848, TPS2849

PWP PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

ENABLE

IN

PWRRDY

DELAY

NC

BOOT

HIGHDR

BOOTLO

BOOT

HIGHDR

BOOTLO

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

ACTUAL SIZE

(5,1 mm x 6,6 mm)

IN

PWRRDY

DELAY

SYNC

ADJ

Thermal

Pad

V

Thermal

Pad

CC

VDRV

LOWDR

NC

VDRV

LOWDR

PGND

DT

AGND

ACTUAL SIZE

(5,1 mm x 6,6 mm)

DT

AGND

8

PGND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

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1

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SLVS367A – MARCH 2001 – REVISED JUNE 2001

description (continued)

The SYNC pin can be used regardless of load to disable the synchronous FET driver and operate the power

supply nonsynchronously.

A power ready/undervoltage lockout function outputs the status of the V -pin voltage and driver regulator

CC

output on the open-drain PWRRDY pin. This feature can be used to enable a controller’s output once the V

CC

voltage reaches the threshold and the regulator output is stable. This function ensures both FET drivers are off

when the V voltage is below the voltage threshold.

CC

The TPS2838/39/48/49 devices are offered in the thermally enhanced 14-pin and 16-pin PowerPAD TSSOP

package. The PowerPAD package features an exposed leadframe on the bottom that can be soldered to the

printed-circuit board to improve thermal efficiency. The TPS2838/48 are noninverting control logic while the

TPS2839/49 drivers are inverting control logic.

2

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SLVS367A – MARCH 2001 – REVISED JUNE 2001

functional block diagram (TPS2838, TPS2839)

V

CC

ADJ

VDRV

Vr1

V

CC

0.9 × Vref

REFERENCES

POR

SYS_UVLO

Vref

0.9 × Vref

SHUTDOWN

Vr1

PWRRDY

AGND

THERMAL

SHUTDOWN

DRIVE

REGULATOR

BOOT

SHUTDOWN

HIGHDR

BOOTLO

IN

INVERTING OPTION

TPS2839 ONLY

VDRV

LOWDR

SYNC

DT

SYS_UVLO

DEADTIME

PGND

ENABLE

CONTROL

DELAY

functional block diagram (TPS2848, TPS2849)

V

CC

VDRV

Vr1

V

CC

0.9 × Vref

REFERENCES

POR

SYS_UVLO

Vref

0.9 × Vref

SHUTDOWN

Vr1

PWRRDY

AGND

THERMAL

SHUTDOWN

DRIVE

REGULATOR

BOOT

SHUTDOWN

HIGHDR

BOOTLO

IN

INVERTING OPTION

TPS2849 ONLY

VDRV

LOWDR

SYS_UVLO

DEADTIME

CONTROL

DT

PGND

ENABLE

DELAY

3

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SLVS367A – MARCH 2001 – REVISED JUNE 2001

Terminal Functions

TERMINAL

NO.

NAME

DESCRIPTION

TPS283x TPS284x

ADJ

6

8

—

7

Adjust. The adjust pin is the feedback pin for the drive regulator (TPS283X only)

Analog ground

AGND

BOOT

16

14

Bootstrap. A capacitor is connected between the BOOT and BOOTLO pins to develop the floating

bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1 µF and 1 µF.

BOOTLO

DELAY

DT

14

4

12

4

Boot low. This pin connects to the junction of the high-side and low-side MOSFETs.

Delay. Connecting a capacitor between this pin and ground adjusts the deadtime for high-side driver

Deadtime control. Connect DT to the junction of the high-side and low-side MOSFETs

Enable. If ENABLE is low, both drivers are off.

7

6

ENABLE

HIGHDR

IN

1

15

2

13

2

High drive. This pin is the output drive for the high-side power MOSFET.

Input. This pin is the input signal to the MOSFET drivers.

LOWDR

NC

11

10

9

Low drive. This pin is the output drive for the low-side power MOSFET.

No internal connection

5

PGND

PWRRDY

SYNC

8

Power ground. This pin is connected to the FET power ground.

3

Power ready. This open-drain pin indicates a power good for VDRV and V .

CC

5

—

Synchronous rectifier enable. If SYNC is low, the low-side driver is always off; if SYNC is high, the

low-side driver provides gate drive to the low-side MOSFET.

V

13

12

11

10

Input power supply. It is recommended that a capacitor (minimum 1 µF) be connected from V to

CC

PGND. Note that V

must be 2 V higher than VDRV.

CC

VDRV

Drive regulator output voltage. It is recommended that a capacitor (minimum 1 µF) be connected from

VDRV to PGND. Note that V must be 2 V higher than VDRV.

CC

detailed description

low-side driver

The low-side driver is designed to drive low r

source and sink.

N-channel MOSFETs. The current rating of the driver is 4 A,

N-channel MOSFETs. The current rating of the driver is 4 A

DS(on)

high-side driver

The high-side driver is designed to drive low r

DS(on)

minimum, source and sink. The high-side driver can be configured as a GND-reference driver or as a

floating-bootstrap driver. The internal bootstrap diode is a Schottky, for improved drive efficiency. The maximum

voltage that can be applied from BOOT to ground is 30 V.

dead-time (DT) control

Dead-time control prevents shoot-through current from flowing through the main power FETs during switching

transitions by controlling the turnon times of the MOSFET drivers. The high-side driver is not allowed to turn

on until the gate drive voltage to the low-side FET is low, and the low-side driver is not allowed to turn on until

the voltage at the junction of the power FETs (BOOTLO) is low. The TTL-compatible DT terminal connects to

the junction of the power FETs.

ENABLE

The ENABLE terminal enables the drivers. When enable is low, the output drivers are low. ENABLE is a

TTL-compatible digital terminal.

4

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SLVS367A – MARCH 2001 – REVISED JUNE 2001

detailed description (continued)

IN

The IN terminal is a TTL-compatible digital terminal that is the input control signal for the drivers. The

TPS2838/48 have noninverting inputs; the TPS2839/49 have inverting inputs. On the TPS2838 and TPS2848,

a high on IN results in a high on HIGHDR. On the TPS2839 and TPS2849, a high on IN results in a low on

HIGHDR.

SYNC (TPS283x only)

The SYNC terminal controls whether the drivers operate in synchronous or nonsynchronous mode. In

synchronous mode, the low-side FET is operated as a synchronous rectifier. In nonsynchronous mode, the

low-side FET is always off. SYNC is a TTL-compatible digital terminal.

PWRRDY

Depicts the status of the V

pin voltage and the driver regulator output on the open-drain PWRRDY pin.

CC

DELAY

Adjustable high-side turnon delay from from when the low-side FET is turned off.

ADJ (TPS283x only)

Input for adjusting the driver regulator output. See the application information section for the adjustment formula.

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 16 V

CC

Input voltage range:ADJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V

BOOT to PGND (high-side driver ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 30 V

BOOTLO to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 16 V

BOOT to BOOTLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 16 V

ENABLE, IN, and SYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 16 V

VDRV, PWRRDY, and DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 16 V

DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 16 V

Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C

J

Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: Unless otherwise specified, all voltages are with respect to PGND.

5

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SLVS367A – MARCH 2001 – REVISED JUNE 2001

DISSIPATION RATING TABLE

PACKAGE

T

A

≤ 25°C

DERATING FACTOR

26.68 mW/°C

T

A

= 70°C

T = 85°C

A

‡

14-pin PWP with solder

14-pin PWP without solder

2668

1467

563

1067

409

‡

1024

2739

1108

10.24 mW/°C

‡

16-pin PWP with solder

27.39 mW/°C

1506

609

1095

443

‡

16-pin PWP without solder

11.08 mW/°C

JUNCTION-CASE THERMAL RESISTANCE TABLE

14-pin PWP

16-pin PWP

Junction-case thermal resistance

2.07 °C/W

‡

Test Board Conditions:

1. Thickness: 0.062I

2. 3I × 3I (for packages < 27 mm long)

3. 4I × 4I (for packages > 27 mm long)

4. 2-oz copper traces located on the top of the board (0,071 mm thick)

5. Copper areas located on the top and bottom of the PCB for soldering

6. Power and ground planes, 1-oz copper (0,036 mm thick)

7. Thermal vias, 0,33 mm diameter, 1,5 mm pitch

8. Thermal isolation of power plane

For more information, refer to TI technical brief literature number SLMA002.

recommended operating conditions

MIN NOM

MAX

15

UNIT

V

Supply voltage, V

CC

10

Input voltage, V BOOT to PGND

29

V

I

electrical characteristics over recommended operating virtual junction temperature range,

= 12 V, ENABLE = High, C = 3.3 nF (unless otherwise noted)

V

CC

L

supply current

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

425

1

UNIT

µA

V

= Low,

= High,

V

= 13 V

(ENABLE)

CC

I

Quiescent current

CC

mA

(ENABLE)

CC

NOTE 2: Ensured by design, not production tested.

6

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SLVS367A – MARCH 2001 – REVISED JUNE 2001

electrical characteristics over recommended operating virtual junction temperature range,

V

= 12 V, ENABLE = High, C = 3.3 nF (unless otherwise noted) (continued)

CC

L

dead-time control

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

LOWDR high-level input voltage

LOWDR low-level input voltage

DT high-level input voltage

DT low-level input voltage

Deadtime delay

Over full VDRV range

See Note 2

50

%VDRV

IH(LOWDR)

IL(LOWDR)

IH(DT)

1

V

Over full V

range

2

CC

Over full V

1

1.5

V

IL(DT)

V

= 4 V to 14 V

See Note 2

0.5

30

1

ns/pF

ns

(VDRV)

= 4.5 V,

T

J

= 25°C, See Note 2

150

100

Driver nonoverlap time (DT to LOWDR)

= 14.5 V, T = 25°C, See Note 2

ns

J

= 4.5 V,

= 25°C,

C

= 50 pF

L(Delay)

See Note 2

75

58

50

30

180

125

100

T

J

Driver nonoverlap time (LOWDR to

HIGHDR)

ns

V

= 14.5 V, C

= 50 pF

L(Delay)

(VDRV)

= 25°C,

T

J

See Note 2

V

= 4.5 V,

C

= 0 pF

(VDRV)

= 25°C,

L(Delay)

See Note 2

T

J

Driver nonoverlap time (LOWDR to

HIGHDR)

V

= 14.5 V, C

= 0 pF

L(Delay)

(VDRV)

= 25°C,

T

J

See Note 2

NOTE 2: Ensured by design, not production tested.

high-side driver

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V

= 0.5 V (src)

= 4 V (sink)

= 0.5 V (src)

= 8 V (sink)

= 0.5 V (src)

= 14 V (sink)

= 4 V (src)

1

2

1.3

2.4

3.3

3.9

4.4

V

–V

= 4 V,

(HIGHDR)

(BOOT) (BOOTLO)

See Note 2

V

–V

= 8 V,

(BOOT) (BOOTLO)

See Note 2

Peak output current

A

V

–V

= 14 V,

= 4.5 V

= 7.5 V,

= 11.5 V,

(BOOT) (BOOTLO)

See Note 2

45

6

V

T

–V

= 25°C

(BOOT) (BOOTLO)

J

= 0.5 V (sink)

= 7 V (src)

26

V

–V

= 25°C

(BOOT) (BOOTLO)

r

Output resistance

Ω

o

T

J

= 0.5 V (sink)

= 11 V (src)

= 0.5 V (sink)

5

20

4

V

T

–V

= 25°C

(BOOT) (BOOTLO)

J

HIGHDRV-to-BOOTLO resistor

250

kΩ

85

70

65

V

= 4 V

(BOOT)

C

T

= 3.3 nF,

= 125°C

V

= GND,

L

J

(BOOTLO)

= 8 V

= 14 V

= 4 V

Rise and fall time

(see Notes 2 and 3)

t /t

r f

ns

170

C

= 10 nF, V

(BOOTLO)

= 125°C

L

J

= 8 V

140

100

120

T

= 14 V

= 4 V

Propagation delay time,

HIGHDR going low

(excluding deadtime)

V

= GND,

T

J

= 125°C,

(BOOTLO)

= 8 V

100

ns

t

PHL

See Notes 2 and 3

= 14 V

80

NOTES: 2: Ensured by design, not production tested.

3. The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the

combined current from the bipolar and MOSFET transistors. The output resistance is the r of the MOSFET transistor when

DS(on)

the voltage on the driver output is less than the saturation voltage of the bipolar transistor.

7

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SLVS367A – MARCH 2001 – REVISED JUNE 2001

electrical characteristics over recommended operating virtual junction temperature range,

V

= 12 V, ENABLE = High, C = 3.3 nF (unless otherwise noted) (continued)

CC

L

low-side driver

PARAMETER

TEST CONDITIONS

MIN

1

TYP

1.6

2.4

3.3

3.9

4.4

MAX

UNIT

V

= 0.5 V (src)

= 4 V (sink)

= 0.5 V (src)

= 8 V (sink)

= 0.5 V (src)

= 14 V (sink)

= 4 V (src)

V

T

= 4 V,

(LOWDR)

(HIGHDR)

(LOWDR)

(VDRV)

= 25°C,

See Note 2

2

J

2

V

T

= 8 V,

= 25°C,

(VDRV)

J

Peak output current

A

See Note 2

2

V

= 14 V (src),

(VDRV)

T

J

= 25°C,

See Note 2

2

30

8

V

T

= 4.5 V,

= 25°C

(VDRV)

J

= 0.5 V (sink)

= 7 V (src)

25

7

V

= 7.5 V,

= 25°C

(VDRV)

r

Output resistance

Ω

o

T

J

= 0.5 V (sink)

= 11 V (src)

= 0.5 V (sink)

22

6

V

T

= 11.5 V,

= 25°C

(VDRV)

J

LOWDR-to-PGND resistor

250

kΩ

V

= 4 V

60

50

(VDRV)

C

= 3.3 nF,

T

= 125°C,

L

J

= 8 V

See Note 2

= 14 V

= 4 V

40

t /t

r f

Rise and fall time

ns

110

100

80

C

= 10 nF,

L

J

= 8 V

See Note 2

= 14 V

= 4 V

110

90

ns

Propagation delay time, LOWDR

going high (excluding deadtime)

T = 125°C,

J

See Notes 2 and 3

= 8 V

t

PLH

= 14 V

80

NOTES: 2: Ensured by design, not production tested.

3: The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the

combined current from the bipolar and MOSFET transistors. The output resistance is the r of the MOSFET transistor when

DS(on)

the voltage on the driver output is less than the saturation voltage of the bipolar transistor.

V

undervoltage lockout

CC

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

Start threshold voltage

Stop threshold voltage

Hysteresis voltage

10.3

7.5

1

V

hys

1.5

V

t

Propagation delay time

Falling-edge delay time

50-mV overdrive, See Note 2

See Note 2

300

1000

5

ns

us

pd

2

d

NOTE 2: Ensured by design, not production tested.

8

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SLVS367A – MARCH 2001 – REVISED JUNE 2001

electrical characteristics over recommended operating virtual junction temperature range,

V

= 12 V, ENABLE = High, C = 3.3 nF (unless otherwise noted) (continued)

CC

L

digital control (IN, ENABLE, SYNC)

PARAMETER

TEST CONDITIONS

MIN

2

TYP

MAX

UNIT

V

IN

Over full V

range

CC

V

High-level input voltage

Low-level input voltage

IH

ENABLE, SYNC

IN

2.2

V

1

7

V

IL

ENABLE, SYNC

V

ENABLE propagation delay time

See Note 2

2

µs

NOTE 2: Ensured by design, not production tested.

thermal shutdown

PARAMETER

TEST CONDITIONS

MIN

155

10

TYP

MAX

185

20

UNIT

_C

Thermal shutdown

See Note 2

170

t

d

Falling edge delay time

µs

NOTE 2: Ensured by design, not production tested.

drive regulator

PARAMETER

TEST CONDITIONS

MIN

4

TYP

MAX

14

UNIT

V

Recommended output voltage

V

Output voltage

V

= 10 V to 15 V,

= 10 V to 15 V

= 10 V,

I

= 5 mA to 150 mA

= 150 mA

–2

2

%nom

V

O

CC

O

V

ref

Reference voltage

1.235

1000

O

Dropout voltage

1100

mV

See Note 2

Line regulation

V

= 10 V to 15 V,

= 10 V,

I

= 5 mA

0.2

2

%/V

%

CC

O

Load regulation

= 5 mA to 150 mA

O

Current limit

= 8 V

0.5

0.6

0.8

1

A

PWRRDY saturation voltage

Leakage current

I

O

= 5 mA

V

I

V

= 4.5 V

µA

lkg

I(PWRRDY)

drive regulator undervoltage lockout

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Start threshold voltage

See Note 2

85 %Vref

%Vref

Stop threshold voltage

80

V

hys

Hysteresis voltage

2.5

5

%Vref

t

pd

Propagation delay time

Falling-edge delay time

Power on reset time

50-mV overdrive,

See Note 2

300

1000

ns

µs

2

5

See Note 2

100

1000

NOTE 2: Ensured by design, not production tested.

9

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SLVS367A – MARCH 2001 – REVISED JUNE 2001

PARAMETER MEASUREMENT INFORMATION

Rising Edge

Falling Edge

50%

V

I

50%

(EN, SYNC, IN)

V

I

(EN, SYNC, IN)

t

off

on

t

off

on

V

O

50%

V

O

(LOWDRV, HIGHDR)

50%

(LOWDRV, HIGHDR)

High-Side and Low-Side Drive

t

f

r

V

O

90%

10%

90%

10%

(LOWDRV, HIGHDR)

Figure 1. Voltage Waveforms

TYPICAL CHARACTERISTICS

FALL TIME

vs

INPUT VOLTAGE (VDRV)

RISE TIME

vs

INPUT VOLTAGE (VDRV)

70

60

35

30

C

T

= 3.3 nF

= 25°C

L

J

C

T

= 3.3 nF

= 25°C

L

J

50

40

25

20

High Side

Low Side

High Side

30

20

15

10

Low Side

10

0

5

0

4

5

6

7

8

9

10 11 12 13 14 15

4

5

6

7

8

9

10 11 12 13 14 15

V – Input Voltage (VDRV) – V

I

V – Input Voltage (VDRV) – V

I

Figure 2

Figure 3

10

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SLVS367A – MARCH 2001 – REVISED JUNE 2001

TYPICAL CHARACTERISTICS

RISE TIME

vs

FALL TIME

vs

JUNCTION TEMPERATURE

60

35

30

VDRV = 8 V

= 3.3 nF

VDRV = 8 V

C

= 3.3 nF

L

50

40

High Side

25

20

30

20

15

10

Low Side

10

0

5

0

–50

–25

0

25

50

75

100

125

0

25

50

75

100

125

–50

–25

T

J

– Junction Temperature – °C

T

J

– Junction Temperature – °C

Figure 4

Figure 5

HIGH-TO-LOW PROPAGATION DELAY TIME

LOW-TO-HIGH PROPAGATION DELAY TIME

vs

INPUT VOLTAGE (VDRV)

200

180

140

120

C

T

= 3.3 nF

= 25°C

L

J

C

T

= 3.3 nF

= 25°C

L

J

160

100

80

140

120

High Side

100

80

High Side

Low Side

60

40

60

40

Low Side

20

0

20

0

4

5

6

7

8

9

10 11 12 13 14 15

4

5

6

7

8

9

10 11 12 13 14 15

V – Input Voltage (VDRV) – V

I

V – Input Voltage (VDRV) – V

I

Figure 6

Figure 7

11

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SLVS367A – MARCH 2001 – REVISED JUNE 2001

TYPICAL CHARACTERISTICS

LOW-TO-HIGH PROPAGATION DELAY TIME

HIGH-TO-LOW PROPAGATION DELAY TIME

vs

JUNCTION TEMPERATURE

180

160

80

VDRV = 8 V

= 3.3 nF

C

= 3.3 nF

L

C

L

70

60

High Side

140

120

High Side

50

40

100

80

Low Side

30

20

60

40

Low Side

10

0

20

0

–50

–25

0

25

50

75

100

125

–50

–25

0

25

50

75

100

125

T

J

– Junction Temperature – °C

T

J

– Junction Temperature – °C

Figure 8

Figure 9

DRIVER-OUTPUT FALL TIME

vs

DRIVER-OUTPUT RISE TIME

vs

LOAD CAPACITANCE

1000

VDRV = 8 V

= 25°C

VDRV = 8 V

T = 25°C

J

T

J

100

10

100

10

High Side

Low Side

1

0.01

0.1

1

10

100

0.01

0.1

1

10

100

C

– Load Capacitance – nF

C

– Load Capacitance – nF

L

Figure 10

Figure 11

12

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SLVS367A – MARCH 2001 – REVISED JUNE 2001

TYPICAL CHARACTERISTICS

SUPPLY CURRENT

vs

INPUT VOLTAGE (VDRV)

10

25

C

T

= 50 pF

= 25°C

C

T

= 50 pF

= 25°C

L

J

L

J

9

8

22.5

20

7

6

5

4

3

2

17.5

15

500 kHz

100 kHz

300 kHz

200 kHz

2 MHz

50 kHz

25 kHz

12.5

10

7.5

5

1 MHz

1

0

2.5

0

4

5

6

7

8

9

10 11 12 13 14 15

4

5

6

7

8

9

10 11 12 13 14 15

V – Input Voltage (VDRV) – V

I

V – Input Voltage (VDRV) – V

I

Figure 12

Figure 13

PEAK SOURCE CURRENT

vs

PEAK SINK CURRENT

vs

INPUT VOLTAGE (VDRV)

5

4.5

4

T

J

= 25°C

T

J

= 25°C

4.5

4

3.5

3

High Side

Low Side

3.5

3

2.5

2

Low Side

2.5

2

High Side

1.5

1

1.5

1

0.5

0

0.5

0

4

5

6

7

8

9

10 11 12 13 14 15

4

5

6

7

8

9

10 11 12 13 14 15

V – Input Voltage (VDRV) – V

I

V – Input Voltage (VDRV) – V

I

Figure 14

Figure 15

13

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ꢉ

SLVS367A – MARCH 2001 – REVISED JUNE 2001

TYPICAL CHARACTERISTICS

BOOTSTRAP SCHOTTKY DIODE

INPUT CURRENT

vs

START/STOP V

UNDERVOLTAGE LOCKOUT

CC

vs

OUTPUT VOLTAGE

JUNCTION TEMPERATURE

10

1200

1000

800

T

J

= 25°C

9.8

Start

9.6

9.4

9.2

9

600

400

8.8

8.6

Stop

200

0

8.4

8.2

0

0.25 0.5 0.75

1

1.25 1.5 1.75

2

–50

–25

0

25

50

75

100

125

T

J

– Junction Temperature – °C

V

O

– Output Voltage – V

Figure 16

Figure 17

DELAY TIME

vs

DELAY TIME (DEAD TIME)

vs

JUNCTION TEMPERATURE

INPUT VOLTAGE (VDRV)

200

180

160

200

180

VDRV = 8 V

T

J

= 25°C

50 pF

160

10 pF

50 pF

20 pF

5 pF

10 pF

5 pF

20 pF

140

120

140

120

50 pF

100

80

100

80

60

40

60

1 pF

40

0 pF

1 pF

20

0

20

0

4

5

6

7

8

9

10 11 12 13 14 15

–50

–25

0

25

50

75

100

125

V – Input Voltage (VDRV) – V

I

T

J

– Junction Temperature – °C

Figure 18

Figure 19

14

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SLVS367A – MARCH 2001 – REVISED JUNE 2001

TYPICAL CHARACTERISTICS

VDRV LOAD REGULATION

VDRV LINE REGULATION

8.062

8.061

8.115

C

T

= 1 µF

C

T

= 1 µF

L(VDRV)

= 25°C

J

8.11

8.06

8.105

8.059

8.1

8.058

8.057

8.095

8.09

8.056

8.055

8.085

10

11

12

13

14

15

–10

10

30

50

70

90

110 130 150

V

CC

– Supply Voltage – V

I – Input Current – mA

I

Figure 20

Figure 21

APPLICATION INFORMATION

Figure 22 shows the circuit schematic of a 100-kHz synchronous-buck converter implemented with a TL5001ACD

pulse-width-modulation (PWM) controller and a TPS2838 driver. The converter operates over an input range from

4.5 V to 12 V and has a 3.3-V output. The circuit can supply 3-A continuous load. The converter achieves an efficiency

of 94% for V = 5 V, I =1 A, and 93% for V = 5 V, I = 3 A.

IN

L

IN

L

VDRV

Voltage

(V)

R1

(kΩ)

R2

(kΩ)

R2

R1

30

67

91

4

5

ADJ

165

261

322

8

12

14.5

To set the regulator voltage (TPS2838/39) use the following equation:

R1

_{R2 +}ǒ _VDRVǓ_* R1

1.235

15

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SLVS367A – MARCH 2001 – REVISED JUNE 2001

APPLICATION INFORMATION

Great care should be taken when laying out the PC board. The power-processing section is the most critical

and will generate large amounts of EMI if not properly configured. The junction of Q1, Q2, and L1 should be very

tight. The connection from Q1 drain to the positive sides of C5, C10, and C11 and the connection from Q2 source

to the negative sides of C5, C10, and C11 should be as short as possible. The negative terminals of C7 and

C12 should also be connected to Q2 source.

Next, the traces from the MOSFET driver to the power switches should be considered. The BOOTLO signal from

the junction of Q1 and Q2 carries the large gate drive current pulses and should be as heavy as the gate drive

traces. The bypass capacitor (C14) should be tied directly across V

and PGND.

CC

The next most sensitive node is the FB node on the controller (terminal 4 on the TL5001A). This node is very

sensitive to noise pickup and should be isolated from the high-current power stage and be as short as possible.

The ground around the controller and low-level circuitry should be tied to the power ground as the output. If these

three areas are properly laid out, the rest of the circuit should not have other EMI problems and the power supply

will be relatively free of noise.

17

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SLVS367A – MARCH 2001 – REVISED JUNE 2001

MECHANICAL DATA

PWP (R-PDSO-G**)

PowerPAD PLASTIC SMALL-OUTLINE PACKAGE

20-PIN SHOWN

0,30

0,19

0,65

20

M

0,10

11

Thermal Pad

(See Note D)

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

1

10

0,25

A

0°–ā8°

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

14

16

20

24

28

DIM

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

A MAX

A MIN

4073225/E 03/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusions.

D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically

and thermally connected to the backside of the die and possibly selected leads.

E. Falls within JEDEC MO-153

18

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PACKAGE OPTION ADDENDUM

www.ti.com

8-Mar-2005

PACKAGING INFORMATION

Orderable Device

TPS2838PWP

TPS2838PWPR

TPS2839PWP

TPS2839PWPR

TPS2848PWP

TPS2848PWPR

TPS2849PWP

TPS2849PWPR

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

HTSSOP

PWP

16

14

90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

HTSSOP

PWP

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,

including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process

in which TI products or services are used. Information published by TI regarding third-party products or services

does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.

Use of such information may require a license from a third party under the patents or other intellectual property

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Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

product or service voids all express and any implied warranties for the associated TI product or service and

is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	TPS2849PWPR
厂家：	TEXAS INSTRUMENTS
描述：	SYNCHRONOUS BUCK MOSFET DRIVERS WITH DRIVE REGULATOR 同步降压MOSFET驱动器与驱动器稳压器驱动器 MOSFET驱动器稳压器驱动程序和接口接口集成电路光电二极管
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