TPS3610U18_技术文档

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SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002

features

typical applications

D

Supply Current of 40 µA (Max)

D

Fax Machines

Battery Supply Current of 100 nA (Max)

D

Set-Top Boxes

Precision Supply-Voltage Monitor,

1.8 V, 5 V; Other Options on Request

Advanced Voice Mail Systems

Portable Battery-Powered Equipment

Computer Equipment

Watchdog Timer With 800-ms Time-Out

Backup-Battery Voltage Can Exceed V

DD

Advanced Modems

Power-On Reset Generator With Fixed

100-ms Reset Delay Time

Automotive Systems

Portable Long-Time Monitoring Equipment

Point of Sale Equipment

D

Battery-OK Output

D

Voltage Monitor for Power-Fail or

Low-Battery Monitoring

TPS3610

TSSOP (PW) Package

(TOP VIEW)

D

Manual Switchover to Battery-Backup

Mode

1

2

3

4

5

6

7

14

13

12

11

10

9

V

BAT

RESET

OUT

Chip-Enable Gating . . . 3 ns (at V

Max Propagation Delay

= 5 V)

DD

V

DD

GND

MSWITCH

CEIN

WDI

LOWLINE

CEOUT

BATTOK

PFO

Battery-Freshness Seal

14-pin TSSOP Package

BATTON

PFI

8

Temperature Range . . . –40°C to 85°C

ACTUAL SIZE

(5,10mm x 6,60mm)

typical operating circuit

Address

Decoder

Power

Supply

0.1 µF

External

CEIN

CE

CMOS

RAM

CE

CMOS

RAM

CEOUT

Address Bus

Real-

Time

Clock

Backup

Battery

Source

V

BAT

DD

TPS3610

R

x

y

uC

V

CC

PFI

8

RESET

WDI

I/O

Data Bus

16

I/O

PFO

BATTOK

BATTON

LOWLINE

Switchover

Capacitor

MSWITCH

V

OUT

V

CC

0.1 µF

GND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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1

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SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002

description

The TPS3610 family of supervisory circuits monitors and controls processor activity by providing backup-battery

switchover for data retention of CMOS RAM. Other features include an additional power-fail comparator,

low-line indication, watchdog function, battery-status indicator, manual switchover, and write protection for

CMOS RAM.

The TPS3610 family allow usage of 3-V or 3.6-V lithium batteries as the backup supply in systems with, e.g.,

V

= 1.8 V. During power-on, RESET is asserted when the supply voltage (V

or V

) becomes higher than

DD

BAT

1.1 V. Thereafter, the supply-voltage supervisor monitors V

remains below the threshold voltage V . An internal timer delays the return of the output to the inactive state

(high) to ensure proper system reset. The delay time starts after V

When the supply voltage drops below the threshold voltage V , the output becomes active (low) again.

and keeps RESET output active as long as V

DD

IT

has risen above the threshold voltage V .

DD

IT

The product spectrum is designed for supply voltages of 1.8 V and 5 V. The circuits are available in a 14-pin

TSSOP package. TPS3610 devices are characterized for operation over a temperature range of –40°C to 85°C.

standard and application-specific versions (see Note 1)

TPS3610U 18

PW

R

Tape and Reel

TI Package Designator

Nominal Supply Voltage

Nominal Battok Threshold Voltage

APPLICATION-SPECIFIC VERSIONS,

NOMINAL SUPPLY AND BATTOK VOLTAGE

NOMINAL SUPPLY

NOMINAL BATTOK

THRESHOLD VOLTAGE,

PACKAGED DEVICES

T

A

VOLTAGE, V

(V)

DD(NOM)

†

TSSOP (PW)

V

(V)

IT(BOK)

1.8

5

1.6

TPS3610U18PWR

TPS3610T50PWR

–40°C to 85°C

2.4

†

The PW package is only available taped and reeled (indicated by the R suffix on the device type).

NOTE 1: For other NOMINAL and BATTOK voltage versions, contact your local TI sales office for availability and order lead time.

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SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002

TRUTH TABLES

INPUTS

OUTPUTS

V

DD

> V

V

DD

> V

IT

V

DD

> V

MSWITCH

V

OUT

BATTON

LOWLINE

RESET

CEOUT

LL

BAT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

V

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DIS

EN

DIS

EN

DIS

EN

DIS

EN

DIS

EN

BAT

DD

0

1

V

BAT

DD

V

BAT

DD

V

BAT

DD

V

DIS

EN

DIS

EN

DIS

EN

BAT

DD

V

BAT

V

BAT

BATTOK

POWER-FAIL

CHIP-ENABLE

CEOUT

V

BAT

> V

BATTOK

PFI > V

(PFI)

PFO

CEIN

BOK

0

1

0

1

0

1

0

1

0

1

0

1

Condition: V

DD

> V

IT

Condition: V

DD

> V min

DD

Condition: Enabled

3

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SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002

functional block diagram

MSWITCH

V

BAT

+

_

Switch

Control

V

OUT

Internal

Power Supply

V

DD

BATTON

BATTOK

+

_

Reference

Voltage

of 1.15 V

_

+

RESET

Logic

+

GND

RESET

Timer

+

_

LOWLINE

Oscillator

_

+

PFO

PFI

V

OUT

Transition

Detector

Watchdog

Logic + Control

WDI

40 kΩ

CEOUT

CEIN

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SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002

timing diagram

V

BAT

V

LL

IT

V

BOK

V

DD

t

V

OUT

V

BAT

BATTOK

1

0

RESET

t

d

t

BATTON

LOWLINE

t

†

MSWITCH = 0

Timing diagram shown under operation, not in freshness seal mode.

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SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

BATTOK

NO.

9

O

I

Battery status output

BATTON

CEIN

6

Logic output/external bypass switch driver output

Chip-enable input

5

CEOUT

10

O

Chip-enable output

GND

3

11

4

I

O

I

Ground

LOWLINE

MSWITCH

Early power-fail warning output

Manual switch to force device into battery-backup mode

Supply output

V

OUT

1

O

I

PFI

7

Power-fail comparator input

Power-fail comparator output

Active-low reset output

Backup-battery input

PFO

8

O

I

RESET

13

14

2

V

BAT

I

Input supply voltage

DD

WDI

12

I

Watchdog timer input

detailed description

battery freshness seal

The battery freshness seal of the TPS3610 family disconnects the backup battery from internal circuitry until

it is needed. This function ensures that the backup battery connected to V is fresh when the final product

BAT

is put to use. The following steps explain how to enable the freshness seal mode:

1. Connect V (V > V min)

BAT BAT

BAT

2. Ground PFO

3. Connect PFI to V

(PFI = V

)

DD

4. Connect V

to power supply (V

> V ) and keep connected for 5 ms < t < 35 ms

DD

DD IT

The battery freshness seal mode is disabled by the positive-going edge of RESET when V

is applied.

DD

BATTOK output

BATTOK is a logic feedback of the device to indicate the status of the backup battery. The supervisor checks

the battery voltage every 200 ms with a voltage divider load of approximately 100 kΩ and a measurement cycle

on-time of 25 µs. The measurement cycle starts after the reset is released. If the battery voltage V

is below

BAT

the negative-going threshold voltage V

, the indicator BATTOK does a high-to-low transition. Otherwise

IT(BOK)

it retains its status to V

level.

DD

I

BAT

25 µs

200 ms

100 µA

t

Figure 1. BATTOK Timing

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SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002

detailed description (continued)

chip-enable signal gating

The internal gating of chip-enable signals, CE, prevents erroneous data from corrupting CMOS RAM during an

undervoltage condition. The TPS3610 use a series transmission gate from CEIN to CEOUT. During normal

operation (reset not asserted), the CE transmission gate is enabled and passes all CE transitions. When reset

is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The short

CE propagation delay from CEIN to CEOUT enables TPS3610 devices to be used with most processors.

The CE transmission gate is disabled and CEIN is high-impedance (disable mode) while reset is asserted.

During a power-down sequence, when V

crosses the reset threshold, the CE transmission gate is disabled

DD

and CEIN immediately becomes high impedance if the voltage at CEIN is high. If CEIN is low while reset is

asserted, the CE transmission gate is disabled at the same time CEIN goes high, or 15 µs after RESET asserts,

whichever occurs first. This allows the current write cycle to complete during power-down. When the CE

transmission gate is enabled, the impedance of CEIN appears as a resistor in series with the load at CEOUT.

The overall device propagation delay through the CE transmission gate depends on V

, the source

OUT

impedance of the device connected to CEIN and the load at CEOUT. To achieve minimum propagation delay,

the capacitive load at CEOUT should be minimized, and a low-output-impedance driver should be used.

During disable mode, the transmission gate is off and an active pullup connects CEOUT to V

turns off when the transmission gate is enabled.

. The pullup

OUT

CEIN

t

CEOUT

15 µs

t

RESET

t

Figure 2. Chip-Enable Timing

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SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002

detailed description (continued)

power-fail comparator (PFI and PFO)

An additional comparator is provided to monitor voltages other than the nominal supply voltage. The

power-fail-input (PFI) is compared with an internal voltage reference of 1.15 V. If the input voltage falls below

the power-fail threshold V

of typical 1.15 V, the power-fail output (PFO) goes low. If V

goes above

IT(PFI)

V

, plus about 12-mV hysteresis, the output returns to high. By connecting two external resistors, it is

(PFI)

possible to supervise any voltages above V

. The sum of both resistors should be about 1 MΩ, to minimize

(PFI)

power consumption and also to assure that the current in the PFI pin can be neglected compared with the current

through the resistor network. The tolerance of the external resistors should be not more than 1% to ensure

minimal variation of sensed voltage. If the power-fail comparator is unused, PFI should be connected to ground

and PFO left unconnected.

LOWLINE

The lowline comparator monitors V with a threshold voltage typically 2% above the reset threshold (V ). For

DD

IT

normal operation (V above the reset threshold), LOWLINE is pulled to V . LOWLINE can be used to provide

DD

a nonmaskable interrupt (NMI) to the processor when power begins to fall. In most battery-operated portable

systems, reserve energy in the battery provides enough time to complete the shutdown routine once the low-line

warning is encountered and before reset asserts. If the system must also contend with a more rapid V

fall

DD

time, such as when the main battery is disconnected or a high-side switch is opened during normal operation,

a capacitor can be used on the V line to provide enough time for executing the shutdown routine. First, the

DD

worst-case settling time (t ) required for the system to perform its shutdown routine needs to be defined. Then,

sd

using the worst-case load current (I ) that can be drained from the capacitor, and the minimum reset threshold

L

voltage (V min), the capacitor value (C ) can be calculated as follows:

IT

H

I t

L

sd

C

+

H

V min 0.012

IT

BATTON

Most often BATTON is used as a gate drive for an external pass transistor for high-current applications. In

addition, it can be used as a logic output to indicate the battery switchover status. BATTON is high when V

OUT

is connected to V

.

BAT

BATTON can be connected directly to the gate of a PMOS transistor (see Figure 3). No current-limiting resistor

is required. If a PMOS transistor is used, it must be connected in the reverse of the traditional method (see

Figure 3), which orients the body diode from V

through the FET when its gate is high.

to V

and prevents the backup battery from discharging

DD

OUT

PMOS FET

Body Diode

D

S

G

V

DD

BATTON V

OUT

TPS3610

GND

Figure 3. Driving an External MOSFET Transistor With BATTON

8

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SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002

detailed description (continued)

backup-battery switchover

In case of a brownout or power failure, it may be necessary to preserve the contents of RAM. If a backup-battery

is installed at V , the device automatically switches the connected RAM to backup power when V fails. In

BAT

DD

order to allow the backup-battery (e.g., a 3.6-V lithium cell) to have a higher voltage than V , these supervisors

DD

do not connect V

to V

when V

is greater than V . V

only connects to V

(through a 15-Ω switch)

BAT

OUT

BAT

DD BAT

OUT

when V

falls below V and V

is greater than V . When V

recovers, switchover is deferred either until

DD

IT

BAT

DD

V

crosses V

, or until V

rises above the reset threshold V . V

connects to V

through a 1-Ω (max)

DD

BAT

DD

IT OUT

DD

PMOS switch when V

crosses the reset threshold.

DD

FUNCTION TABLE

V

DD

> V

1

V

DD

> V

IT

V

OUT

BAT

1

V

DD

1

0

1

0

V

0

V

0

V

BAT

V

DD

Mode

V

IT

Hysteresis

V

BAT

Mode

VBSW Hysteresis

Undefined

V

BAT

– Backup-Battery Supply Voltage – V

Figure 4. Normal Supply Voltage vs Backup-Battery Supply Voltage

9

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SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002

detailed description (continued)

manual switchover (MSWITCH)

While operating in the normal mode from V , the device can be forced manually to operate in battery-backup

DD

mode by connecting MSWITCH to V . Refer to Table 1 for different switchover modes.

DD

Table 1. Switchover Modes

MSWITCH

STATUS

GND

V

mode

DD

V

mode

DD

V

DD

GND

Switch to battery-backup mode

Battery-backup mode

V

DD

Battery-backup mode

If the manual switchover feature is not used, MSWITCH must be connected to ground.

watchdog

In a microprocessor- or DSP-based system, it is important not only to supervise the supply voltage, but also to

ensure correct program execution. The task of a watchdog is to ensure that the program is not stalled in an

indefinite loop. The microprocessor, microcontroller or DSP has to toggle the watchdog input within typically

0.8 s to avoid the occurence of a time-out. Either a low-to-high or a high-to-low transition resets the internal

watchdog timer. If the input is unconnected, the watchdog is disabled and is retriggered internally.

saving current while using the watchdog

The watchdog input is internally driven low during the first 7/8 of the watchdog time-out period, then the input

momentarily pulses high, resetting the watchdog counter. For minimum watchdog input current (minimum

overall power consumption), WDI should be left low for the majority of the watchdog time-out period, and pulsed

low-high-low once within 7/8 of the watchdog time-out period to reset the watchdog timer. If instead WDI is

externally driven high for the majority of the timeout period, a current of, e.g., 5 V/40 kΩ ≈ 125 µA, can flow into

WDI.

V

OUT

V

IT

WDI

t

(tout)

RESET

t

d

Undefined

Figure 5. Watchdog Timing

10

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SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage, V

(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

DD

All other pins (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V

Continuous output current at V , I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA

OUT O(VOUT)

Continuous output current (all other pins) I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA

O

Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

Operating free-air temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

A

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 2: All voltage values are with respect to GND. For reliable operation the device must not be operated at 7 V for more than t=1000h

continuously.

DISSIPATION RATING TABLE

T

≤ 25°C

DERATING FACTOR

T

= 70°C

T = 85°C

A

PACKAGE

POWER RATING

ABOVE T = 25°C

POWER RATING POWER RATING

A

PW

700 mW

5.6 mW/°C

448 mW 364 mW

recommended operating conditions

MIN

MAX

5.5

UNIT

V

Supply voltage, V

DD

1.65

1.5

0

Battery supply voltage, V

BAT

5.5

V

Input voltage, V

V

+0.3

V

I

DD

High-level input voltage, V

IH

0.7xV

V

DD

Low-level input voltage, V

IL

0.3×V

DD

V

Continuous output current at V

, I

300

100

1

mA

ns/V

V/µs

°C

OUT O

Input transition rise and fall rate at WDI, MSWITCH, ∆t/∆V

Slew rate at V or V

DD BAT

Operating free-air temperature range, T

–40

85

A

11

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SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

= 1.8 V,

= 3.3 V,

= 5 V,

I

= –400 µA

= –2 mA

= –3 mA

= –400 µA

= –2 mA

= –3 mA

= –20 µA

= –80 µA,

= –120 µA

= –1 mA

= –2 mA

= –5 mA

V

–0.2 V

DD

OH

DD

RESET,

BATTOK

DD

–0.4 V

–0.2 V

DD

= 1.8 V,

= 3.3 V,

= 5 V,

V

OUT

BATTON

–0.4 V

–0.3 V

OUT

= 1.8 V,

= 3.3 V,

= 5 V,

V

DD

V

High-level output voltage

V

OH

LOWLINE,

PFO

DD

–0.4 V

–0.2 V

DD

= 1.8 V,

= 3.3 V,

= 5 V,

V

OUT

CEOUT,

Enable mode,

CEIN = V

V

–0.3 V

–0.4 V

OUT

CEOUT,

Disable mode

V

OUT

= 3.3 V,

I

= –0.5 mA

V

OUT

OH

V

= 1.8 V,

= 3.3 V,

= 5 V,

I

= 400 µA

= 2 mA

= 3 mA

= 500 µA

= 3 mA

= 5 mA

= 1 mA

= 2 mA

= 5 mA

0.2

DD

OL

RESET, PFO,

BATTOK,

LOWLINE

DD

0.4

0.2

DD

= 1.8 V,

= 3.3 V,

= 5 V,

OUT

Low-level output voltage

BATTON

V

OL

0.4

0.2

= 1.8 V,

= 3.3 V,

= 5 V,

CEOUT,

Enable mode,

CEIN = 0 V

0.3

0.4

V

> 1.1 V,

BAT

OR

Power-up reset voltage (see Note 3)

I

= 20 µA,

OL

V

> 1.1 V,

DD

= 8.5 mA,

= 1.8 V,

O

DD

V

DD

–50 mV

V

= 0 V

BAT

= 125 mA,

I

V

= 3.3 V,

= 5 V,

= 0 V,

O

DD

V

–150 mV

–200 mV

Normal mode

DD

= 0 V

BAT

= 200 mA,

I

V

O

V

OUT

= 0 V

BAT

= 0.5 mA,

I

V

O

V

–20 mV

BAT

= 1.5 V

BAT

Battery-backup mode

I

V

= 7.5 mA,

O

V

–113 mV

BAT

= 3.3 V

BAT

NOTE 3: The lowest supply voltage at which RESET becomes active. t

V

≥ 15 µs/V

r, DD

12

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SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (continued)

PARAMETER

TEST CONDITIONS

MIN

1.68

TYP

1.71

4.55

1.15

2.4

1.6

+2%

20

MAX

1.74

UNIT

TPS3610U18

TPS3610T50

PFI

V

IT

4.46

4.64

1.13

1.17

T

= –40°C to 85°C

V

Negative-going input threshold

voltage (see Note 4)

(PFI)

(BOK)

(LL)

A

TPS3610T50

TPS3610U18

LOWLINE

2.33

2.47

1.55

1.65

V

IT

+1.2%

V

IT

V +2.8%

IT

1.65 V < V < 2.5 V

IT

2.5 V < V < 3.5 V

IT

40

V

IT

3.5 V < V < 5.5 V

IT

60

1.65 V < V

< 2.5 V

20

(LL)

2.5 V < V

< 3.5 V

< 5.5 V

40

LOWLINE

(LL)

3.5 V < V

(LL)

60

V

hys

Hysteresis

mV

1.65 V < V

< 2.5 V

20

(BOK)

2.5 V < V

< 3.5 V

< 5.5 V

40

BATTOK

PFI

(BOK)

3.5 V < V

(BOK)

60

12

V

BSW

V

DD

= 1.8 V

55

(see Note 5)

I

IH

High-level input current

Low-level input current

WDI = V

= 5 V

150

WDI

(see Note 6)

DD

µA

I

IL

WDI = 0 V,

V

DD

= 5 V

–150

PFI,

MSWITCH

I

Input current

–25

25

nA

V

= 1.8 V

= 3.3 V

= 5 V

–0.3

–1.1

DD

I

Short-circuit output current

PFO

PFO = 0 V

mA

OS

DD

–2.4

V

OUT

V

OUT

V

OUT

V

OUT

= V

40

DD

Supply current at V

µA

DD

40

0.1

0.5

±1

BAT

DD

–0.1

I

µA

BAT

Leakage current at CEIN

Disable mode,

V < V

I DD

lkg

V

to V

OUT

on-resistance

V

= 5 V

0.6

8

1

DD

r

Ω

DS(on)

to V

OUT

= 3.3 V

15

BAT

C

Input capacitance

V = 0 V to 5 V

I

5

pF

i

NOTES: 4. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near to the supply terminals.

5. For V < 1.6 V, V switches to V regardless of V

DD OUT BAT BAT

6. For details on how to optimize current consumption when using WDI. Refer to detailed description section, watchdog.

13

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SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002

timing requirements at R = 1 MΩ, C = 50 pF, T = –40°C to 85°C

L

A

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

µs

At V

DD

V

= V + 0.2 V,

IT

V

IL

V

= V –0.2 V

IT

6

IH

t

w

Pulse width

At WDI

= V + 0.2 V,

IT

= 0.3 × V

DD

,

V

= 0.7 × V

100

ns

DD

IL

IH DD

switching characteristics at R = 1 MΩ, C = 50 pF, T =–40°C to 85°C

L

A

PARAMETER

TEST CONDITIONS

MIN

60

TYP

100

0.8

MAX

140

UNIT

ms

s

t

Delay time

d

V

> V +0.2 V

DD

IT

(see timing diagram

Watchdog timeout

0.48

1.12

(tout)

Propagation (delay) time, low-to-

high-level output

t

15

µs

50% RESET to 50% CEOUT

50% CEIN to 50% CEOUT,

PLH

V

= 1.8 V

= 3.3 V

= 5 V

5

1.6

1

15

5

DD

ns

C

= 50 pF only (see Note 7)

L

3

Propagation (delay) time, high-to-

low-level output

t

PHL

V

= V –0.2 V,

IT

IL

IH

V

DD

to RESET

2

3

5

= V +0.2 V

IT

µs

V

= V –0.2 V,

(PFI)

IL

IH

PFI to PFO

= V

+0.2 V

(PFI)

V

= V

+ 200 mV,

IH

IL

BAT

t

Transition time

V

DD

to BATTON

= V – 200 mV,

BAT

3

< V

IT

NOTE 7: Specified by design

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

Static drain-source on-state resistance (V

Static drain-source on-state resistance

Supply current

to V

)

6

DD

OUT

vs Output current

to V

)

7

8

r

BAT

OUT

DS(on)

vs Input voltage at CEIN

vs Supply voltage

I

9

DD

V

Normalized threshold at RESET

High-level output voltage at RESET

High-level output voltage at PFO

High-level output voltage at CEOUT

Low-level output voltage at RESET

Low-level output voltage at CEOUT

Low-level output voltage at BATTON

vs Free-air temperature

10

IT

11, 12

13, 14

15, 16, 17, 18

19, 20

21, 22

23, 24

25

V

OH

vs High-level output current

V

OL

vs Low-level output current

vs Threshold overdrive at V

t

Minimum Pulse Duration at V

DD

p(min)

DD

Minimum Pulse Duration at PFI

vs Threshold overdrive at PFI

26

p(min)

14

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SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

STATIC DRAIN-SOURCE ON-STATE RESISTANCE

(V

to V

vs

)

(V

to V

vs

)

DD

OUT

BAT

OUT

OUTPUT CURRENT

1000

900

800

700

20

V

= 3.3 V

DD

V

= 3.3 V

BAT

MSWITCH = GND

= GND

MSWITCH = GND

BAT

17.5

15

T

A

= 85°C

T

A

= 85°C

12.5

10

T

A

= 25°C

T

A

= 25°C

T

A

= 0°C

T

A

= 0°C

T

= –40°C

A

600

500

7.5

5

T

A

= –40°C

50

75

100

125

150

175

200

2.5

4.5

6.5

8.5

10.5

12.5

14.5

I

O

– Output Current – mA

I

O

– Output Current – mA

Figure 6

Figure 7

STATIC DRAIN-SOURCE ON-STATE RESISTANCE

SUPPLY CURRENT

vs

SUPPLY VOLTAGE

(CEIN to CEOUT)

vs

INPUT VOLTAGE AT CEIN

40

30

25

20

15

10

5

V

Mode

= 2.6 V

V

Mode

DD

BAT

35

V

BAT

= GND

or

T

= 85°C

A

MSWITCH = GND

T

= 25°C

A

30

25

T

A

= 0°C

T

= 25°C

A

T

= 85°C

A

20

15

10

T

A

= 0°C

T

= –40°C

A

T

= –40°C

A

I

V

= 5 mA

CEOUT

= 5 V

DD

MSWITCH = GND

5

0

1

2

3

4

5

0

1

2

3

4

5

6

V

– Input Voltage at CEIN – V

I(CEIN)

V

DD

– Supply Voltage – V

Figure 8

Figure 9

15

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SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

TPS3610T50

NORMALIZED THRESHOLD AT RESET

vs

FREE-AIR TEMPERATURE

1.001

1

0.999

0.998

0.997

0.996

0.995

–40 –30 –20 –10

0 10 20 30 40 50 60 70 80

T

A

– Free-Air Temperature – °C

Figure 10

HIGH-LEVEL OUTPUT VOLTAGE AT RESET

vs

HIGH-LEVEL OUTPUT CURRENT

5.1

5

6

5

4

3

2

1

0

V

= 5 V

DD

Expanded View

= GND

BAT

MSWITCH = GND

T

= –40°C

A

T

A

= –40°C

T

= 25°C

A

4.9

T

A

= 25°C

T

A

= 0°C

T

A

= 0°C

4.8

4.7

T

A

= 85°C

T

A

= 85°C

V

= 5 V

= GND

MSWITCH = GND

DD

BAT

4.6

4.5

0

–0.5 –1 –1.5 –2 –2.5 –3 –3.5 –4 –4.5 –5

0

–5

–10

–15

–20

–25

–30

–35

I – High-Level Output Current – mA

OH

I

– High-Level Output Current – mA

OH

Figure 11

Figure 12

16

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SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

HIGH-LEVEL OUTPUT VOLTAGE AT PFO

vs

HIGH-LEVEL OUTPUT CURRENT

5.55

5.50

5.45

5.40

5.35

5.30

5.25

5.20

6

5

4

3

2

Expanded View

T

= –40°C

A

T

= –40°C

A

T

A

= 25°C

T

A

= 25°C

T

A

= 0°C

T

A

= 0°C

T

A

= 85°C

T

= 85°C

A

V

= 5.5 V

DD

PFI = 1.4 V

= GND

V

= 5.5 V

DD

PFI = 1.4 V

= GND

1

0

V

BAT

MSWITCH = GND

5.15

5.10

V

BAT

MSWITCH = GND

0

–20 –40 –60 –80 –100 –120 –140 –160 –180 –200

0

–0.5 –1

–1.5

–2

–2.5

I – High-Level Output Current – µA

OH

I

– High-Level Output Current – mA

OH

Figure 13

Figure 14

HIGH-LEVEL OUTPUT VOLTAGE AT CEOUT

vs

HIGH-LEVEL OUTPUT CURRENT

3.35

3.30

3.25

3.20

3.5

V

= 3.3 V

Expanded View

Enable Mode

V

= 3.3 V

(CEIN)

= 5 V

DD

Enable Mode

V

DD

= 5 V

MSWITCH = GND

3

2.5

2

MSWITCH = GND

T

A

= –40°C

T

= –40°C

A

T

A

= 25°C

T

A

= 0°C

T

A

= 25°C

T

= 0°C

A

1.5

1

T

A

= 85°C

T

A

= 85°C

3.15

3.10

0.5

0

–0.5 –1 –1.5 –2 –2.5 –3 –3.5 –4 –4.5 –5

–10

–30

–50 –70 –90 –110 –130 –150

I – High-Level Output Current – mA

OH

I

– High-Level Output Current – mA

OH

Figure 15

Figure 16

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SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

HIGH-LEVEL OUTPUT VOLTAGE AT CEOUT

vs

HIGH-LEVEL OUTPUT CURRENT

3.5

3.4

3.3

3.2

3.1

3.5

V

= open

Expanded View

Disable Mode

(CEIN)

= 1.65 V

DD

MSWITCH = GND

3

T

A

= –40°C

T = –40°C

A

2.5

T

A

= 25°C

T

A

= 25°C

T

A

= 0°C

2

T

A

= 0°C

1.5

T

= 85°C

A

3

2.9

2.8

2.7

T

= 85°C

A

1

0.5

0

Disable Mode

V

= open

(CEIN)

= 1.65 V

DD

MSWITCH = GND

0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 –0.8 –0.9 –1

0

–0.5 –1 –1.5 –2 –2.5 –3 –3.5 –4 –4.5

I – High-Level Output Current – mA

OH

I

– High-Level Output Current – mA

OH

Figure 17

Figure 18

LOW-LEVEL OUTPUT VOLTAGE AT RESET

vs

LOW-LEVEL OUTPUT CURRENT

500

3.5

3

Expanded View

V

= 3.3 V

= GND

DD

BAT

T = 85°C

A

V

= 3.3 V

DD

MSWITCH = GND

400

300

200

100

0

= GND

BAT

MSWITCH = GND

2.5

2

T

= 25°C

A

T

= 0°C

A

T

A

= 0°C

T

= 25°C

A

1.5

1

T

= 85°C

A

T

A

= –40°C

T

= –40°C

A

0.5

0

1

2

3

4

5

0

5

10

15

20

25

I – Low-Level Output Current – mA

OL

I

– Low-Level Output Current – mA

OL

Figure 19

Figure 20

18

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ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢅꢈ ꢉ ꢀ ꢁ ꢂꢃ ꢄꢅ ꢆꢀꢊ ꢆ

ꢋ ꢌꢀ ꢀꢍ ꢎꢏꢐꢋꢌꢑ ꢒꢇꢁ ꢂꢇ ꢁꢍꢎꢓꢔ ꢂꢕ ꢎꢂ ꢖ ꢕꢎ ꢎꢌꢗ ꢎꢍꢀ ꢍꢘ ꢀꢔ ꢕ ꢘ

SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

LOW-LEVEL OUTPUT VOLTAGE AT CEOUT

vs

LOW-LEVEL OUTPUT CURRENT

140

120

3.5

3

V

= GND

Enable Mode

Expanded View

(CEIN)

= 5 V

Enable Mode

DD

V

= GND

MSWITCH = GND

(CEIN)

= 5 V

DD

T

A

= 85°C

MSWITCH = GND

2.5

2

100

80

T

= 85°C

A

T

= 25°C

A

T

A

= 25°C

T

A

= 0°C

T

A

= 0°C

60

1.5

1

T

A

= –40°C

T

A

= –40°C

40

20

0

0.5

0

1

2

3

4

5

10 20 30 40 50 60 70 80 90 100

0

I – Low-Level Output Current – mA

OL

I

– Low-Level Output Current – mA

OL

Figure 21

Figure 22

LOW-LEVEL OUTPUT VOLTAGE AT BATTON

vs

LOW-LEVEL OUTPUT CURRENT

3.5

3

400

350

300

250

200

150

100

Enable Mode

V

= 3.3 V

Enable Mode

Expanded View

DD

V

= 3.3 V

DD

= GND

BAT

= GND

BAT

MSWITCH = GND

T

A

= 85°C

2.5

2

T

= 85°C

A

T

= 25°C

A

T

= 0°C

A

T

A

= 0°C

T

A

= 25°C

1.5

1

T

A

= –40°C

T

A

= –40°C

0.5

0

50

0

5

10

15

20

25

30

0

1

2

3

4

5

I

– Low-Level Output Current – mA

OL

I

– Low-Level Output Current – mA

OL

Figure 23

Figure 24

19

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ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢅ ꢈꢉ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢀꢊ ꢆ

ꢋ ꢌꢀ ꢀ ꢍꢎꢏꢐꢋ ꢌ ꢑꢒ ꢇꢁ ꢂ ꢇꢁ ꢍꢎꢓ ꢔ ꢂꢕ ꢎꢂ ꢖꢕ ꢎ ꢎꢌꢗ ꢎꢍ ꢀꢍ ꢘꢀꢔ ꢕ ꢘ

SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

TPS3610T50

MINIMUM PULSE DURATION AT V

vs

DD

THRESHOLD OVERDRIVE AT V

DD

10

9

8

7

6

5

4

3

2

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1

Threshold Overdrive at V

– V

DD

Figure 25

TPS3610T50

MINIMUM PULSE DURATION AT PFI

vs

THRESHOLD OVERDRIVE AT PFI

5

4.6

4.2

3.8

3.4

3

V

DD

= 1.65 V

2.6

2.2

1.8

1.4

1

0.6

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Threshold Overdrive at PFI – V

Figure 26

20

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ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢅꢈ ꢉ ꢀ ꢁ ꢂꢃ ꢄꢅ ꢆꢀꢊ ꢆ

ꢌꢀ ꢀꢍ ꢎꢏꢐꢋꢌꢑ ꢒꢇꢁ ꢂꢇ ꢁꢍꢎꢓꢔ ꢂꢕ ꢎꢂ ꢖ ꢕꢎ ꢎꢌꢗ ꢎꢍꢀ ꢍꢘ ꢀꢔ ꢕ ꢘ

ꢋ

SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002

MECHANICAL DATA

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–ā8°

0,75

0,50

A

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

A MAX

A MIN

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

21

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IMPORTANT NOTICE

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in

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型号：	TPS3610U18
厂家：	TEXAS INSTRUMENTS
描述：	BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION 电池备份监事RAM保持电池
文件：	总22页 (文件大小：454K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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