TPS3710DSER [TI]
宽输入电压电压检测器 | DSE | 6 | -40 to 125;
| 型号： | TPS3710DSER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 宽输入电压电压检测器 | DSE | 6 | -40 to 125 光电二极管 |
| 文件： | 总26页 (文件大小：959K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS3710
ZHCSE85 –OCTOBER 2015
TPS3710 宽 VIN 电压检测器
1 特性
3 说明
TPS3710 宽电源电压检测器在 1.8V 至 18V 的电压范
围内运行。 此器件具有一个内部基准电压为 400mV
的高精度比较器和一个额定电压为 18V 的开漏输出，
用于实现精确的电压检测。 可以使用外部电阻设置监
视电压。
1
•
•
•
宽电源电压范围：1.8V 至 18V
可调节阈值：低至 400mV
高阈值精度：
–
–
在温度范围内为 1.0%
0.25%（典型值）
当 SENSE 引脚上的电压下降至低于 (VIT–) 时，OUT
引脚被驱动至低电平，而当电压返回到对应阈值 (VIT+
)
•
•
•
•
•
低静态电流：5.5μA（典型值）
漏极开路输出
之上时，OUT 引脚变为高电平。 TPS3701 的比较器
均内置有滞后特性，可抑制短小毛刺脉冲，从而确保输
出操作稳定而无错误触发。
内部滞后：5.5mV（典型值）
温度范围：-40°C 至 +125°C
封装：
TPS3710 提供 SOT-6 封装和 1.5mm × 1.5mm
WSON-6 封装，额定工作结温范围为 –40°C 至 +125°
C。
–
–
小外形尺寸晶体管 (SOT)-6 封装
1.5mm × 1.5mm 晶圆级小外形无引线
(WSON)-6 封装
器件信息 (1)
部件号
TPS3710
封装
封装尺寸（标称值）
2.90mm x 1.60mm
1.50mm x 1.50mm
SOT (6)
WSON (6)
2 应用
•
•
•
•
工业控制系统
(1) 要了解所有可用封装，请见数据表末尾的封装选项附录。
车载系统
嵌入式计算模块
数字信号处理器 (DSP)、微控制器、或者微处理器
应用
•
•
•
笔记本和台式计算机
便携式和电池供电类产品
现场可编程门阵列 (FPGA) 和专用集成电路 (ASIC)
应用
简化电路原理图
上升输入阈值电压 (VIT+) 与温度间的关系
401
VMON
1.8 V to 18 V
VDD = 1.8 V
VDD = 5 V
VDD = 12 V
VDD = 18 V
0.01 ꢀF
400.6
VPULLUP
Up to 18 V
400.2
R1
VDD
SENSE
RP
399.8
399.4
399
To a reset or enable
input of the system.
OUT
R2
GND
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBVS271
TPS3710
ZHCSE85 –OCTOBER 2015
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 10
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application .................................................. 13
8.3 Do's and Don'ts....................................................... 14
Power-Supply Recommendations...................... 15
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 6
6.7 Switching Characteristics.......................................... 6
6.8 Typical Characteristics.............................................. 7
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................. 10
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 15
11 器件和文档支持 ..................................................... 16
11.1 器件支持................................................................ 16
11.2 文档支持................................................................ 16
11.3 社区资源................................................................ 16
11.4 Trademarks........................................................... 16
11.5 Electrostatic Discharge Caution............................ 16
11.6 Glossary................................................................ 16
12 机械、封装和可订购信息....................................... 16
7
4 修订历史记录
日期
修订版本
注释
2015 年 10 月
*
最初发布版本
2
Copyright © 2015, Texas Instruments Incorporated
TPS3710
www.ti.com.cn
ZHCSE85 –OCTOBER 2015
5 Pin Configuration and Functions
DDC Package
6-Pin SOT
Top View
DSE Package
6-Pin WSON
Top View
OUT
GND
1
2
3
6
5
4
GND
VDD
GND
GND
VDD
1
2
6
5
4
OUT
GND
GND
3
SENSE
SENSE
Pin Functions
PIN
I/O
DESCRIPTION
NAME
GND
DDC
DSE
2, 4, 6
1, 3, 5
—
Connect all three pins to ground.
SENSE comparator open-drain output. OUT is driven low when the voltage at this
comparator is below (VIT-). The output goes high when the sense voltage returns above
the respective threshold (VIT+).
OUT
1
6
O
This pin is connected to the voltage to be monitored with the use of an external resistor
divider. When the voltage at this pin drops below the threshold voltage (VIT-), OUT is
driven low.
SENSE
VDD
3
5
4
2
I
I
Supply voltage input. Connect a 1.8-V to 18-V supply to VDD to power the device. Good
analog design practice is to place a 0.1-µF ceramic capacitor close to this pin.
Copyright © 2015, Texas Instruments Incorporated
3
TPS3710
ZHCSE85 –OCTOBER 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
20
UNIT
VDD
Voltage(2)
OUT
20
V
SENSE
7
Current
OUT (output sink current)
Operating junction, TJ
Storage, Tstg
40
mA
°C
–40
–65
125
150
Temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network ground pin.
6.2 ESD Ratings
VALUE
±2500
±1000
UNIT
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins
V(ESD)
Electrostatic discharge
V
(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating temperature range (unless otherwise noted)
MIN
1.8
0
NOM
MAX UNIT
VDD
VI
Supply voltage
Input voltage
Output voltage
18
6.5
18
V
V
V
SENSE
OUT
VO
0
6.4 Thermal Information
TPS3710
(1)
THERMAL METRIC
DDC (SOT)
6 PINS
204.6
50.5
DSE (WSON)
6 PINS
194.9
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
128.9
54.3
153.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.8
11.9
ψJB
52.8
157.4
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2015, Texas Instruments Incorporated
TPS3710
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ZHCSE85 –OCTOBER 2015
6.5 Electrical Characteristics
Over the operating temperature range of TJ = –40°C to +125°C, and 1.8 V < VDD < 18 V (unless otherwise noted).
Typical values are at TJ = 25°C and VDD = 5 V.
PARAMETER
TEST CONDITIONS
VOLmax = 0.2 V, output sink current = 15 µA
VDD = 1.8 V
MIN
TYP
MAX UNIT
(1)
V(POR)
VIT+
Power-on reset voltage
0.8
404
404
400
400
12
V
396
396
387
387
400
400
Positive-going input threshold voltage
Negative-going input threshold voltage
mV
VDD = 18 V
VDD = 1.8 V
394.5
394.5
5.5
VIT–
Vhys
mV
VDD = 18 V
Hysteresis voltage (hys = VIT+ – VIT–
)
mV
nA
I(SENSE) Input current (at the SENSE pin)
VDD = 1.8 V and 18 V, VI = 6.5 V
VDD = 1.3 V, output sink current = 0.4 mA
VDD = 1.8 V, output sink current = 3 mA
VDD = 5 V, output sink current = 5 mA
VDD = 1.8 V and 18 V, VO = VDD
VDD = 1.8 V, VO = 18 V
VDD = 1.8 V, no load
–25
1
25
250
250
250
300
300
11
VOL
Low-level output voltage
mV
nA
Ilkg(OD)
Open-drain output leakage-current
5.5
6
VDD = 5 V
13
IDD
Supply current
µA
V
VDD = 12 V
6
13
VDD = 18 V
7
13
(2)
UVLO
Undervoltage lockout
VDD falling
1.3
1.7
(1) The lowest supply voltage (VDD) at which output is active; tr(VDD) > 15 µs/V. Below V(POR), the output cannot be determined.
(2) When VDD falls below UVLO, OUT is driven low. The output cannot be determined below V(POR)
.
Copyright © 2015, Texas Instruments Incorporated
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ZHCSE85 –OCTOBER 2015
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6.6 Timing Requirements
over operating temperature range (unless otherwise noted)
MIN
NOM
MAX UNIT
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV,
see Figure 1
(1)
(1)
tpd(HL)
High-to-low propagation delay
Low-to-high propagation delay
18
µs
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV,
see Figure 1
tpd(LH)
td(start)
29
µs
µs
(2)
Start-up delay
150
(1) High-to-low and low-to-high refers to the transition at the input pin (SENSE).
(2) During power on, VDD must exceed 1.8 V for at least 150 µs before the output is in a correct state.
6.7 Switching Characteristics
over operating temperature range (unless otherwise noted)
PARAMETER
Output rise time
Output fall time
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VO = (0.1 to 0.9) × VDD
tr
tf
2.2
µs
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VO = (0.1 to 0.9) × VDD
0.22
µs
VDD
V(POR)
VIT+
VITœ
VHYS
SENSE
OUT
tpd(LH)
tpd(HL)
tpd(LH)
t d(start)
Figure 1. Timing Diagram
6
Copyright © 2015, Texas Instruments Incorporated
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ZHCSE85 –OCTOBER 2015
6.8 Typical Characteristics
at TJ = 25°C and VDD = 5 V (unless otherwise noted)
401
400.6
400.2
399.8
399.4
399
10
9
VDD = 1.8 V
VDD = 5 V
VDD = 12 V
VDD = 18 V
8
7
6
5
4
3
2
1
0
TJ = -40°C
TJ = 0°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
0
2
4
6
8
10
12
14
16
18
-40 -25 -10
5
20 35 50 65 80 95 110 125
Supply Voltage (V)
Temperature (èC)
Figure 2. Supply Current (IDD) vs Supply Voltage (VDD
)
Figure 3. Rising Input Threshold Voltage (VIT+) vs
Temperature
25
23
21
19
17
15
13
11
9
9
VDD = 1.8 V
VDD = 18 V
8
7
6
5
4
3
VDD = 1.8 V
VDD = 5 V
VDD = 12 V
VDD = 18 V
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
Temperature (èC)
Figure 5. Propagation Delay vs Temperature
(High-to-Low Transition at Sense)
Figure 4. Hysteresis (Vhys) vs Temperature
30
28
26
24
22
20
18
16
14
16
14
12
10
8
6
4
VDD = 1.8 V
VDD = 18 V
2
0
2.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
4
5.5
7
8.5
10
11.5
13
14.5
Temperature (èC)
Positive-Going Input Threshold Overdrive (%)
SENSE = negative spike below VIT–
Figure 6. Propagation Delay vs Temperature
(Low-to-High Transition at Sense)
Figure 7. Minimum Pulse Width vs
Threshold Overdrive Voltage
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ZHCSE85 –OCTOBER 2015
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Typical Characteristics (continued)
at TJ = 25°C and VDD = 5 V (unless otherwise noted)
2000
1800
1600
1400
1200
1000
800
12
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
10
8
6
4
600
TJ = -40°C
TJ = 0°C
400
TJ = +25°C
TJ = +85°C
TJ = +125°C
2
0
200
0
0
4
8
12
16
20
24
28
32
36
40
0
4
8
12
16
20
24
28
32
36
40
Output Sink Current (mA)
Output Sink Current (mA)
Figure 9. Output Voltage Low (VOL) vs
Output Sink Current (–40°C)
Figure 8. Supply Current (IDD) vs
Output Sink Current
2000
1800
1600
1400
1200
1000
800
2000
1800
1600
1400
1200
1000
800
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
600
600
400
400
200
200
0
0
0
4
8
12
16
20
24
28
32
36
40
0
4
8
12
16
20
24
28
32
36
40
Output Sink Current (mA)
Output Sink Current (mA)
Figure 10. Output Voltage Low (VOL) vs
Output Sink Current (0°C)
Figure 11. Output Voltage Low (VOL) vs
Output Sink Current (25°C)
2000
1800
1600
1400
1200
1000
800
2000
1800
1600
1400
1200
1000
800
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
600
600
400
400
200
200
0
0
0
4
8
12
16
20
24
28
32
36
40
0
4
8
12
16
20
24
28
32
36
40
Output Sink Current (mA)
Output Sink Current (mA)
Figure 12. Output Voltage Low (VOL) vs
Output Sink Current (85°C)
Figure 13. Output Voltage Low (VOL) vs
Output Sink Current (125°C)
8
Copyright © 2015, Texas Instruments Incorporated
TPS3710
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ZHCSE85 –OCTOBER 2015
7 Detailed Description
7.1 Overview
The TPS3710 provides precision voltage detection. The TPS3710 is a wide-supply voltage range (1.8 V to 18 V)
device with a high-accuracy rising input threshold of 400 mV (1% over temperature) and built-in hysteresis. The
output is also rated to 18 V, and can sink up to 40 mA.
The TPS3710 asserts the output signal, as shown in Table 1. To monitor any voltage above 0.4 V, set the input
using an external resistor divider network. Broad voltage thresholds are supported that enable the device for use
in a wide array of applications.
Table 1. TPS3710 Truth Table
CONDITION
SENSE > VIT+
SENSE < VIT–
OUTPUT
OUT high
OUT low
STATUS
Output not asserted
Output asserted
7.2 Functional Block Diagram
VDD
SENSE
OUT
VIT+
GND
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7.3 Feature Description
7.3.1 Input (SENSE)
The TPS3710 comparator has two inputs: one external input, and one input connected to the internal reference.
The comparator rising threshold is trimmed to be equal to the reference voltage (400 mV). The comparator also
has a built-in falling hysteresis that makes the device less sensitive to supply-rail noise and provides stable
operation.
The comparator input (SENSE) is able to swing from ground to 6.5 V, regardless of the device supply voltage.
Although not required in most cases, in order to reduce sensitivity to transients and layout parasitics for
extremely noisy applications, place a 1-nF to 10-nF bypass capacitor at the comparator input.
OUT is driven to logic low when the input SENSE voltage drops below (VIT-). When the voltage exceeds VIT+, the
output (OUT) goes to a high-impedance state; see Figure 1.
7.3.2 Output (OUT)
In a typical TPS3710 application, the output is connected to a reset or enable input of the processor (such as a
digital signal processor [DSP], central processing unit [CPU], field-programmable gate array [FPGA], or
application-specific integrated circuit [ASIC]) or the output is connected to the enable input of a voltage regulator
(such as a dc-dc converter or low-dropout regulator [LDO]).
The TPS3710 device provides an open-drain output (OUT). Use a pullup resistor to hold this line high when the
output goes to high impedance (not asserted). To connect the output to another device at the correct interface-
voltage level, connect a pullup resistor to the proper voltage rail. The TPS3710 output can be pulled up to 18 V,
independent of the device supply voltage.
Table 1 and the Input (SENSE) section describe how the output is asserted or deasserted. See Figure 1 for a
timing diagram that describes the relationship between threshold voltage and the respective output.
7.3.3 Immunity to Input-Pin Voltage Transients
The TPS3710 is relatively immune to short voltage transient spikes on the sense pin. Sensitivity to transients
depends on both transient duration and amplitude; see Figure 7, Minimum Pulse Width vs Threshold Overdrive
Voltage.
7.4 Device Functional Modes
7.4.1 Normal Operation (VDD > UVLO)
When the voltage on VDD is greater than 1.8 V for at least 150 µs, the OUT signal correspond to the voltage on
SENSE as listed in Table 1.
7.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
When the voltage on VDD is less than the device UVLO voltage, and greater than the power-on reset voltage,
V(POR), the OUT signal is asserted regardless of the voltage on SENSE.
7.4.3 Power-On Reset (VDD < V(POR)
)
When the voltage on VDD is lower than the required voltage to internally pull the asserted output to GND (V(POR)),
SENSE is in a high-impedance state.
10
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ZHCSE85 –OCTOBER 2015
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS3710 device is a wide-supply voltage comparator that operates over a VDD range of 1.8 V to
18 V. The device has a high-accuracy comparator with an internal 400-mV reference and an open-drain output
rated to 18 V for precision voltage detection. The device can be used as a voltage monitor. The monitored
voltage are set with the use of external resistors.
8.1.1 VPULLUP to a Voltage Other Than VDD
The output is often tied to VDD through a resistor. However, some applications may require the output to be
pulled up to a higher or lower voltage than VDD to correctly interface with the reset and enable pins of other
devices.
VMON
1.8 V to 18 V
0.01 ꢀF
VPULLUP
Up to 18 V
R1
VDD
RP
To a reset or enable
input of the system.
SENSE
OUT
R2
GND
Figure 14. Interfacing to a Voltage Other Than VDD
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ZHCSE85 –OCTOBER 2015
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Application Information (continued)
8.1.2 Monitoring VDD
Many applications monitor the same rail that is powering VDD. In these applications the resistor divider is simply
connected to the VDD rail.
1.8 V to 18 V
0.01 ꢀF
VPULLUP
Up to 18 V
R1
R2
VDD
SENSE
RP
To a reset or enable
input of the system.
OUT
GND
Figure 15. Monitoring the Same Voltage as VDD
8.1.3 Monitoring a Voltage Other Than VDD
Some applications monitor rails other than the one that is powering VDD. In these types of applications the
resistor divider used to set the desired threshold is connected to the rail that is being monitored.
VMON
1.8 V to 18 V
0.01 ꢀF
VPULLUP
Up to 18 V
R1
VDD
RP
To a reset or enable
input of the system.
SENSE
OUT
R2
GND
NOTE: The input can monitor a voltage greater than maximum VDD with the use of an external resistor divider
network.
Figure 16. Monitoring a Voltage Other Than VDD
12
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ZHCSE85 –OCTOBER 2015
8.2 Typical Application
The TPS3710 device is a wide-supply voltage comparator that operates over a VDD range of 1.8 to 18 V. The
monitored voltage is set with the use of external resistors, so the device can be used either as a precision
voltage monitor.
VMON
1.8 V to 18 V
0.01 ꢀF
VPULLUP
Up to 18 V
R1
2.21 MΩ
RP
VDD
SENSE
49.9 kΩ
To a reset or enable
input of the system.
OUT
R2
83.5 kΩ
GND
Figure 17. Wide VIN Voltage Monitor
8.2.1 Design Requirements
For this design example, use the values summarized in Table 2 as the input parameters.
Table 2. Design Parameters
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
12-V nominal rail with maximum falling
threshold of 10%
Monitored voltage
VMON(UV)= 10.99 V (8.33%)
8.2.2 Detailed Design Procedure
8.2.2.1 Resistor Divider Selection
The resistor divider values and target threshold voltage can be calculated by using Equation 1 to determine
VMON(UV)
.
R1
R2
≈
’
VMON(UV) = 1 +
× V
IT-
∆
÷
◊
«
(1)
where
•
•
R1 and R2 are the resistor values for the resistor divider on the SENSEx pins
VMON(UV) is the target voltage at which an undervoltage condition is detected
Choose RTOTAL ( = R1 + R2) so that the current through the divider is approximately 100 times higher than the
input current at the SENSE pin. The resistors can have high values to minimize current consumption as a result
of low input bias current without adding significant error to the resistive divider. For details on sizing input
resistors, refer to application report SLVA450, Optimizing Resistor Dividers at a Comparator Input, available for
download from www.ti.com.
Copyright © 2015, Texas Instruments Incorporated
13
TPS3710
ZHCSE85 –OCTOBER 2015
www.ti.com.cn
8.2.2.2 Pullup Resistor Selection
To ensure the proper voltage level, the pullup resistor value is selected by ensuring that the pullup voltage
divided by the resistor does not exceed the sink-current capability of the device. This confirmation is calculated
by verifying that the pullup voltage minus the output-leakage current (Ilkg(OD)) multiplied by the resistor is greater
than the desired logic-high voltage. These values are specified in the Electrical Characteristics .
Use Equation 2 to calculate the value of the pullup resistor.
(VHI - VPU)
VPU
IO
³ RPU
³
Ilkg(OD)
(2)
8.2.2.3 Input Supply Capacitor
Although an input capacitor is not required for stability, for good analog design practice, connect a 0.1-μF low
equivalent series resistance (ESR) capacitor across the VDD and GND pins. A higher-value capacitor may be
necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the power
source.
8.2.2.4 Sense Capacitor
Although not required in most cases, for extremely noisy applications, place a 1-nF to 10-nF bypass capacitor
from the comparator input (SENSE) to the GND pin for good analog design practice. This capacitor placement
reduces device sensitivity to transients.
8.2.3 Application Curves
401
VDD = 1.8 V
VDD = 5 V
VDD = 12 V
VDD = 18 V
400.6
400.2
399.8
399.4
399
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
Figure 18. Rising Input Threshold Voltage (VIT+) vs Temperature
8.3 Do's and Don'ts
Do connect a 0.1-µF decoupling capacitor from VDD to GND for best system performance.
If the monitored rail is noisy, do connect a decoupling capacitor from the comparator input (sense) to GND.
Don't use resistors for the voltage divider that cause the current through them to be less than 100 times the input
current of the comparator without also accounting for the effect to the accuracy.
Don't use a pullup resistor that is too small, because the larger current sunk by the output then exceeds the
desired low-level output voltage (VOL).
14
Copyright © 2015, Texas Instruments Incorporated
TPS3710
www.ti.com
ZHCSE85 –OCTOBER 2015
9 Power-Supply Recommendations
These devices operate from an input voltage supply range between 1.8 V and 18 V.
10 Layout
10.1 Layout Guidelines
Placing a 0.1-µF capacitor close to the VDD pin to reduce the input impedance to the device is good analog
design practice.
10.2 Layout Example
Pullup
Voltage
RP1
Output
Flag
6
5
1
CVDD
Input
Supply
2
3
4
R1
R2
Monitored
Voltage
Figure 19. Layout Example
Copyright © 2015, Texas Instruments Incorporated
15
TPS3710
ZHCSE85 –OCTOBER 2015
www.ti.com
11 器件和文档支持
11.1 器件支持
11.1.1 器件命名规则
Table 3. 器件命名规则
产品
说明
yyy 为封装标识符
z 为封装数量
TPS3710yyyz
11.2 文档支持
11.2.1 相关文档ꢀ
相关文档如下：
•
优化比较器输入上的电阻分压器，SLVA450
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
16
Copyright © 2015, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS3710DDCR
TPS3710DDCT
TPS3710DSER
TPS3710DSET
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDC
DDC
DSE
DSE
6
6
6
6
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
11AO
11AO
1A
NIPDAU
NIPDAU
NIPDAU
ACTIVE
ACTIVE
WSON
WSON
1A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
DSE0006A
WSON - 0.8 mm max height
SCALE 6.000
PLASTIC SMALL OUTLINE - NO LEAD
1.55
1.45
A
B
1.55
1.45
PIN 1 INDEX AREA
0.8 MAX
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
0.6
0.4
5X
3
4
2X 1
4X 0.5
6
1
0.3
6X
0.7
0.5
0.2
0.1
0.05
PIN 1 ID
C A B
C
4220552/A 04/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DSE0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
PKG
(0.8)
5X (0.7)
1
6
6X (0.25)
SYMM
4X 0.5
4
3
(R0.05) TYP
(1.6)
LAND PATTERN EXAMPLE
SCALE:40X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
PADS 4-6
NON SOLDER MASK
DEFINED
PADS 1-3
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220552/A 04/2021
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DSE0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
PKG
5X (0.7)
(0.8)
6X (0.25)
1
6
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:40X
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DDC0006A
SOT-23 - 1.1 max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
3.05
2.55
1.1
0.7
1.75
1.45
0.1 C
B
A
PIN 1
INDEX AREA
1
6
4X 0.95
1.9
3.05
2.75
4
3
0.5
0.3
0.1
6X
TYP
0.0
0.2
C A B
C
0 -8 TYP
0.25
GAGE PLANE
SEATING PLANE
0.20
0.12
TYP
0.6
0.3
TYP
4214841/C 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
www.ti.com
EXAMPLE BOARD LAYOUT
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X (0.95)
4
3
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4214841/C 04/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214841/C 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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