TPS3711 [TI]
36V 电压检测器;
| 型号： | TPS3711 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 36V 电压检测器 |
| 文件： | 总24页 (文件大小：1356K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS3711
ZHCSED3A –NOVEMBER 2015–REVISED SEPTEMBER 2018
TPS3711 36V 电压检测器
1 特性
3 说明
1
•
•
•
•
•
宽电源电压范围：1.8V 至 36V
可调节阈值：低至 400mV
针对欠压检测的开漏输出
低静态电流：7μA（典型值）
高阈值精度：
TPS3711 宽电源电压比较器在 1.8V 至 36V 的电压范
围内运行。该器件具有一个内部基准电压为 400mV 的
高精度比较器以及一个额定电压为 25V 的开漏输出，
用于实现欠压检测。监视电压可使用外部电阻进行设
置。
–
–
0.75%（整个温度范围内）
0.25%（典型值）
当 SENSE 引脚的电压降至负向阈值以下时，OUT 被
驱动为低电平；当 SENSE 引脚的电压升至正向阈值以
上时，OUT 被驱动为高电平。TPS3711 的比较器内置
实现噪声抑制的滞后特性，可避免触发错误，从而确保
输出稳定运行。
•
•
•
内部滞后：5.5mV（典型值）
温度范围：-40°C 至 +125°C
封装：小外形尺寸晶体管 (SOT)-6
TPS3711 采用 SOT-6 封装，额定工作结温范围为
–40°C 至 +125°C。
2 应用
•
•
•
•
•
•
工业控制系统
嵌入式计算模块
器件信息 (1)
数字信号处理器 (DSP)、微控制器和微处理器
笔记本和台式计算机
器件型号
TPS3711
封装
封装尺寸（标称值）
SOT (6)
2.90mm x 1.60mm
便携式和电池供电类产品
(1) 要了解所有可用封装，请见数据表末尾的封装选项附录。
现场可编程门阵列 (FPGA) 和专用集成电路 (ASIC)
系统
典型应用
典型误差与结温之间的关系
1.8 V to 36 V
400
399.9
399.8
399.7
399.6
399.5
399.4
399.3
VMON
0.01 ꢀF
VPULLUP
0 V to 25 V
RP
VDD
R1
To a reset or
enable input
of the system
SENSE
OUT
399.2
VDD = 1.8 V
VDD = 12 V
VDD = 36 V
R2
399.1
399
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
GND
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBVS272
TPS3711
ZHCSED3A –NOVEMBER 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
目录
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 10
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application ................................................. 12
Power Supply Recommendations...................... 14
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 6
6.7 Typical Characteristics.............................................. 7
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
8
9
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 15
11 器件和文档支持 ..................................................... 16
11.1 文档支持 ............................................................... 16
11.2 社区资源................................................................ 16
11.3 商标....................................................................... 16
11.4 静电放电警告......................................................... 16
11.5 术语表 ................................................................... 16
12 机械、封装和可订购信息....................................... 16
7
4 修订历史记录
Changes from Original (November 2015) to Revision A
Page
•
•
Changed input pin voltage maximum value from 1.7 V to 6.5 V............................................................................................ 4
Added tablenote .................................................................................................................................................................... 4
2
Copyright © 2015–2018, Texas Instruments Incorporated
TPS3711
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ZHCSED3A –NOVEMBER 2015–REVISED SEPTEMBER 2018
5 Pin Configuration and Functions
DDC Package
6-Pin SOT
Top View
OUT
GND
1
2
3
6
5
4
GND
VDD
GND
SENSE
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
GND
2, 4, 6
—
Ground. Connect all three pins to ground.
Comparator open-drain output. This pin is driven low when the voltage at this comparator is
OUT
SENSE
VDD
1
3
5
O
less than VIT–. The output goes high when the sense voltage rises above VIT+
.
Comparator input. This pin is connected to the voltage to be monitored with the use of an
external resistor divider. When the voltage at this pin drops below the threshold voltage VIT–
OUT is driven low.
I
,
Supply-voltage input. Connect a 1.8-V to 36-V supply to VDD to power the device. It is good
analog design practice to place a 0.1-µF ceramic capacitor close to this pin.
I
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3
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ZHCSED3A –NOVEMBER 2015–REVISED SEPTEMBER 2018
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6 Specifications
(1)
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)
MIN
–0.3
–0.3
–0.3
MAX
UNIT
VDD
40
28
(2)
Voltage
VOUT
V
VSENSE
7
Current
Output pin current
Operating junction, TJ
Storage, Tstg
40
mA
°C
–40
-40
125
125
Temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
1.8
0
NOM
MAX
36
6.5(1)
UNIT
VDD
Supply pin voltage
Input pin voltage
Output pin voltage
Pullup voltage
V
V
VSENSE
VOUT
VPULLUP
IOUT
0
25
V
0
25
V
Output pin current
Junction temperature
0
10
mA
°C
TJ
–40
25
125
(1) Operating Vsense at 1.7 V or higher and at 125°C continuously for 10 years or more would cause a degradation of accuracy spec to 1.5%
maximum.
6.4 Thermal Information
TPS3711
(1)
THERMAL METRIC
DDC (SOT)
6 PINS
201.6
47.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
51.2
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.7
ψJB
50.8
RθJC(bot)
N/A
(1) 有关传统和新热指标的更多信息，请参见应用报告《半导体和 IC 封装热指标》（文献编号：SPRA953）。
4
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TPS3711
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ZHCSED3A –NOVEMBER 2015–REVISED SEPTEMBER 2018
6.5 Electrical Characteristics
Over the operating temperature range of TJ = –40°C to +125°C, 1.8 V ≤ VDD < 36 V, and pullup resistor RP = 100 kΩ (unless
otherwise noted). Typical values are at TJ = 25°C and VDD = 12 V.
PARAMETER
Power-on reset voltage(1)
TEST CONDITIONS
VOL ≤ 0.2 V
MIN
TYP
MAX UNIT
V(POR)
VIT–
0.8
403
413
V
SENSE pin negative input threshold voltage VDD = 1.8 V to 36 V
397
400
400
mV
mV
VIT+
SENSE pin positive input threshold voltage
SENSE pin hysteresis voltage
VDD = 1.8 V to 36 V
405.5
VHYS
VOL
2
5.5
12
mV
mV
(HYS = VIT+ – VIT–
)
VDD = 1.8 V, IOUT = 3 mA
VDD = 5 V, IOUT = 5 mA
130
150
+1
+1
10
250
250
+25
+15
300
11
Low-level output voltage
VDD = 1.8 V and 36 V, VSENSE = 6.5 V
VDD = 1.8 V and 36 V, VSENSE = 0.1 V
VDD = 1.8 V and 36 V, VOUT = 25 V
VDD = 1.8 V – 36 V
–25
–15
IIN
Input current (at SENSE pin)
nA
ID(leak)
IDD
Open-drain leakage current
Supply current
Undervoltage lockout(2)
nA
µA
V
8
UVLO
VDD falling
1.3
1.5
1.7
(1) The lowest supply voltage (VDD) at which output is active; tr(VDD) > 15 µs/V. If less than V(POR), the output is undetermined.
(2) When VDD falls below UVLO, OUT is driven low. The output cannot be determined if less than V(POR)
.
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6.6 Timing Requirements
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
VDD = 24 V, ±10-mV input overdrive,
RL = 100 kΩ, VOH = 0.9 × VDD, VOL = 250 mV
tpd(HL)
High-to-low propagation delay(1)
9.9
µs
VDD = 24 V, ±10-mV input overdrive,
RL = 100 kΩ, VOH = 0.9 × VDD, VOL = 250 mV
tpd(LH)
td(start)
tr
Low-to-high propagation delay(1)
Startup delay
28.1
155
2.7
µs
µs
µs
(2)
VDD = 5 V
VDD = 12 V, 10-mV input overdrive,
RL = 100 kΩ, CL = 10 pF, VO = (0.1 to 0.9) × VDD
Output rise time
VDD = 12 V, 10-mV input overdrive,
RL = 100 kΩ, CL = 10 pF, VO = (0.9 to 0.1) × VDD
tf
Output fall time
0.12
µs
(1) High-to-low and low-to-high refers to the transition at the input pin (SENSE).
(2) During power on, VDD must exceed 1.8 V for at least 150 µs (typ) before the output state reflects the input condition.
VDD
V(POR)
VIT+
VHYS
SENSE
OUT
VITœ
tpd(LH)
tpd(HL)
tpd(LH)
t d(start)
图 1. Timing Diagram
6
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ZHCSED3A –NOVEMBER 2015–REVISED SEPTEMBER 2018
6.7 Typical Characteristics
at TJ = 25°C and VDD = 12 V (unless otherwise noted)
10
9
10
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
0
4
8
12
16
20
24
28
32
36
0
5
10
15
20
25
30
35
40
45
50
Supply Voltage (V)
Overdrive (%)
VDD = 24 V, minimum pulse duration required to trigger output
high-to-low transition, SENSE = negative spike below VIT–
图 3. Minimum Pulse Duration vs
Threshold Overdrive Voltage
图 2. Supply Current vs Supply Voltage
409
408.5
408
400
399.9
399.8
399.7
399.6
399.5
399.4
399.3
VDD = 1.8 V
VDD = 12 V
VDD = 36 V
407.5
407
406.5
406
405.5
405
399.2
VDD = 1.8 V
VDD = 12 V
VDD = 36 V
404.5
399.1
404
399
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
Temperature (èC)
图 4. SENSE Positive Input Threshold Voltage (VIT+) vs
图 5. SENSE Negative Input Threshold Voltage (VIT–) vs
Temperature
Temperature
3500
4500
4000
3500
3000
2500
2000
1500
1000
500
3000
2500
2000
1500
1000
500
0
0
VIT+ Threshold (mV)
VIT- Threshold (mV)
VDD = 1.8 V
VDD = 1.8 V
图 6. SENSE Positive Input Threshold Voltage (VIT+
)
图 7. SENSE Negative Input Threshold Voltage (VIT–)
Distribution
Distribution
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Typical Characteristics (接下页)
at TJ = 25°C and VDD = 12 V (unless otherwise noted)
12
3
2.5
2
VDD = 1.8 V
VDD = 36 V
10
8
1.5
1
6
0.5
0
VDD = 1.8V
VDD = 36 V
4
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
Input step ±200 mV
Input step ±200 mV
图 8. Propagation Delay vs Temperature
图 9. Propagation Delay vs Temperature
(High-to-Low Transition at SENSE)
(Low-to-High Transition at SENSE)
0.6
0.5
0.4
0.3
0.2
0.1
0
0.6
0.5
0.4
0.3
0.2
0.1
0
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Output Sink Current (mA)
Output Sink Current (mA)
VDD = 1.8 V
VDD = 12 V
图 10. Output Voltage Low vs Output Sink Current
图 11. Output Voltage Low vs Output Sink Current
195
180
165
150
135
120
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
VDD = 5 V
图 12. Startup Delay vs Temperature
8
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TPS3711
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ZHCSED3A –NOVEMBER 2015–REVISED SEPTEMBER 2018
7 Detailed Description
7.1 Overview
The TPS3711 combines a comparator and a precision reference for undervoltage detection. The TPS3711
features a wide supply voltage range (1.8 V to 36 V) and a high-accuracy threshold voltage of 400 mV (0.75%
over temperature) with built-in hysteresis. The output is rated to 25 V and can sink up to 10 mA.
Set the input pin (SENSE) to monitor any voltage above 0.4 V by using an external resistor divider network.
SENSE has very low input leakage current, allowing the use of a large resistor divider without sacrificing system
accuracy. The relationship between the input and the output is shown in 表 1. Broad voltage thresholds are
supported that enable the device to be used in a wide array of applications.
表 1. Truth Table
CONDITION
SENSE > VIT+
SENSE < VIT–
OUTPUT
OUT high
OUT low
STATUS
Output high impedance
Output asserted
7.2 Functional Block Diagram
VDD
SENSE
OUT
VIT-
GND
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7.3 Feature Description
7.3.1 Input Pin (SENSE)
The TPS3711 combines a comparator with a precision reference voltage. The comparator has one external input
and one internal input connected to the internal reference. The falling threshold on SENSE is designed and
trimmed to be equal to the reference voltage (400 mV). This configuration optimizes the device accuracy. The
comparator also has built-in hysteresis that proves immunity to noise and ensures stable operation.
The comparator input swings from ground to 6.5 V (7.0 V absolute maximum), regardless of the device supply
voltage used. Although not required in most cases, it is good analog design practice to place a 1-nF to 10-nF
bypass capacitor at the comparator input for noisy applications in order to reduce sensitivity to transient voltage
changes on the monitored signal.
For the comparator, the output (OUT) is driven to logic low when the input SENSE voltage drops below VIT–
.
When the voltage exceeds VIT+, OUT goes to a high-impedance state; see 图 1.
7.3.2 Output Pin (OUT)
In a typical TPS3711 application, the output is connected to a reset or enable input of the processor [such as a
digital signal processor (DSP), application-specific integrated circuit (ASIC), or other processor type] or the output
is connected to the enable input of a voltage regulator [such as a dc-dc converter or low-dropout regulator
(LDO)].
The TPS3711 provides an open-drain output (OUT); use a pullup resistor to hold the line high when the output
goes to a high-impedance state. Connect this pullup resistor to a voltage rail that meets the logic requirements of
the downstream device. The TPS3711 output can be pulled up to 25 V, independent of the device supply
voltage. To ensure the proper voltage level, give some consideration when choosing the pullup resistor value.
The pullup resistor value is determined by VOL, output capacitive loading, and the open-drain leakage current
(ID(leak)). These values are specified in the Electrical Characteristics table.
表 1 and the Input Pin (SENSE) section describe how the output is asserted or high impedance. See 图 1 for a
timing diagram that describes the relationship between threshold voltage and the respective output.
7.4 Device Functional Modes
7.4.1 Normal Operation (VDD > UVLO)
When the voltage on VDD is greater than 1.8 V for at least 155 µs, the OUT signal corresponds to the voltage on
SENSE, as listed in 表 1.
7.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
When the voltage on VDD is less than the device UVLO voltage, and greater than the power-on reset voltage,
V(POR), the OUT signal is asserted regardless of the voltage on SENSE.
7.4.3 Power On Reset (VDD < V(POR)
)
When the voltage on VDD is lower than the required voltage to internally pull the asserted output to GND
(V(POR)), OUT is in a high-impedance state.
10
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS3711 is used as a precision voltage supervisor in several different configurations. The monitored voltage
(VMON), VDD voltage, and output pullup voltage can be independent voltages or connected in any configuration.
The following sections show the connection configurations and the voltage limitations for each configuration.
8.1.1 Input and Output Configurations
图 13 to 图 14 show examples of the various input and output configurations.
1.8 V to 25 V
0.01 ꢀF
RP
VDD
SENSE
R1
To a reset or
enable input
OUT
of the system
R2
GND
图 13. Monitoring the Same Voltage as VDD
1.8 V to 36 V
VMON
0.01 ꢀF
VPULLUP
0 V to 25 V
RP
VDD
R1
To a reset or
enable input
of the system
SENSE
OUT
R2
GND
NOTE: The input can monitor a voltage higher than VDD (max) with the use of an external resistor divider network.
图 14. Monitoring a Voltage Other than VDD
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Application Information (接下页)
8.1.2 Immunity to Input Pin Voltage Transients
The TPS3711 is immune to short voltage transient spikes on the input pin. Sensitivity to transients depends on
both transient duration and amplitude; see 图 3, Minimum Pulse Duration vs Threshold Overdrive Voltage.
8.2 Typical Application
VMON
24 V
0.01 ꢀF
VPULLUP
+
3.3 V
œ
100 kΩ
VDD
2 MΩ
To a reset or
enable input
SENSE
OUT
of the system
37.4 kΩ
GND
图 15. 24-V, 10% Comparator
表 2. Design Parameters
8.2.1 Design Requirements
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
24-V nominal, falling (VMON(UV)
threshold
)
Monitored voltage
VMON(UV) = 21.8 V ±2.7%
10% nominal (21.6 V)
Output logic voltage
3.3-V CMOS
30 µA
3.3-V CMOS
24 µA
Maximum current consumption
8.2.2 Detailed Design Procedure
8.2.2.1 Resistor Divider Selection
The resistor divider values and target threshold voltage can be calculated by using 公式 1 to determine VMON(UV)
.
R1
R2
≈
’
VMON(UV) = 1 +
× V
IT-
∆
÷
◊
«
where
•
•
R1 and R2 are the resistor values for the resistor divider on the SENSE pin
VMON(UV) is the target voltage at which an undervoltage condition is detected
(1)
Choose an RTOTAL ( = R1 + R2) so that the current through the divider is approximately 100 times higher than the
input current at the SENSE pin. Use resistors with high values to minimize current consumption (as a result of
low input bias current) without adding significant error to the resistive divider. For details on sizing input resistors,
refer to application report SLVA450, Optimizing Resistor Dividers at a Comparator Input, available for download
from www.ti.com.
12
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8.2.2.2 Pullup Resistor Selection
To ensure the proper logic-high voltage level (VHI), select a pullup resistor value where the pullup voltage divided
by the pullup resistor value does not exceed the sink-current capability of the device. Confirm this voltage level
by verifying that the pullup voltage minus the open-drain leakage current (ID(leak) ) multiplied by the resistor is
greater than the desired VHI. These values are specified in the Electrical Characteristics .
Use 公式 2 to calculate the value of the pullup resistor.
VHI - Vpullup
Vpullup
Ç RP Ç
ID(leak)
IOUT
(2)
8.2.2.3 Input Supply Capacitor
Although an input capacitor is not required for stability, for good analog design practice, connect a 0.1-μF low
equivalent series resistance (ESR) capacitor across the VDD and GND pins. A higher-value capacitor may be
necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the power
source.
8.2.3 Application Curves
10
9
8
7
6
5
4
3
2
1
0
0
5
10
15
20
25
30
35
40
45
50
Overdrive (%)
图 16. 24-V Window Monitor Output Response
版权 © 2015–2018, Texas Instruments Incorporated
13
TPS3711
ZHCSED3A –NOVEMBER 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
9 Power Supply Recommendations
The TPS3711 has a 40-V absolute maximum rating on the VDD pin, with a recommended maximum operating
condition of 36 V. If the voltage supply that provides power to VDD is susceptible to any large voltage transient
that may exceed 40 V, or if the supply exhibits high voltage slew rates greater than 1 V/µs, then place an RC
filter between the supply and VDD to filter any high-frequency transient surges on the VDD pin. In these cases, a
100-Ω resistor and 0.01-µF capacitor are required, as shown in 图 17.
100 Ω
0.01 ꢀF
+
œ
VPULLUP
VDD
SENSE
R1
To a reset or
enable input
OUT
of the system
R2
GND
图 17. Using an RC Filter to Remove High-Frequency Disturbances on VDD
14
版权 © 2015–2018, Texas Instruments Incorporated
TPS3711
www.ti.com.cn
ZHCSED3A –NOVEMBER 2015–REVISED SEPTEMBER 2018
10 Layout
10.1 Layout Guidelines
•
•
•
Place R1 and R2 close to the device to minimize noise coupling into the SENSE node.
Place the VDD decoupling capacitor close to the device.
Avoid using long traces for the VDD supply node. The VDD capacitor (CVDD), along with parasitic inductance
from the supply to the capacitor, might form an LC tank and create ringing with peak voltages above the
maximum VDD voltage. If long traces are unavoidable, see 图 17 for an example of filtering VDD.
10.2 Layout Example
Pullup
Voltage
RP1
Output
Flag
6
5
1
CVDD
Input
Supply
2
3
4
R1
R2
Monitored
Voltage
图 18. Recommended Layout
版权 © 2015–2018, Texas Instruments Incorporated
15
TPS3711
ZHCSED3A –NOVEMBER 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
如需相关文档，请参见下列应用报告（可从 TI 网站 www.ti.com 获取）：
•
优化比较器输入上的电阻分压器，SLVA450
11.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
16
版权 © 2015–2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS3711DDCR
TPS3711DDCT
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDC
DDC
6
6
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
11BO
11BO
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS3711DDCR
TPS3711DDCT
SOT-
23-THIN
DDC
DDC
6
6
3000
250
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
SOT-
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
23-THIN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS3711DDCR
TPS3711DDCT
SOT-23-THIN
SOT-23-THIN
DDC
DDC
6
6
3000
250
213.0
213.0
191.0
191.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DDC0006A
SOT-23 - 1.1 max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
3.05
2.55
1.1
0.7
1.75
1.45
0.1 C
B
A
PIN 1
INDEX AREA
1
6
4X 0.95
1.9
3.05
2.75
4
3
0.5
0.3
0.1
6X
TYP
0.0
0.2
C A B
C
0 -8 TYP
0.25
GAGE PLANE
SEATING PLANE
0.20
0.12
TYP
0.6
0.3
TYP
4214841/C 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
www.ti.com
EXAMPLE BOARD LAYOUT
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X (0.95)
4
3
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4214841/C 04/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214841/C 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2022，德州仪器 (TI) 公司
相关型号：
TPS3779ADBVR
Push-pull, low-power, dual-voltage detector in a small µSON package 6-SOT-23 -40 to 125
TI
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