TPS3808 [TI]
Low Quiescent Current, Programmable-Delay Supervisory Circuit; 低静态电流可编程延迟监控电路
| 型号： | TPS3808 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Low Quiescent Current, Programmable-Delay Supervisory Circuit |
| 文件： | 总15页 (文件大小：412K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS3808
www.ti.com
SBVS050E–MAY 2004–REVISED OCTOBER 2005
Low Quiescent Current, Programmable-Delay
Supervisory Circuit
FEATURES
DESCRIPTION
•
Power-On Reset Generator with Adjustable
Delay Time: 1.25ms to 10s
The
TPS3808xxx
family
of
microprocessor
supervisory circuits monitor system voltages from
0.4V to 5.0V, asserting an open drain RESET signal
when the SENSE voltage drops below a preset
threshold or when the manual reset (MR) pin drops to
a logic low. The RESET output remains low for the
user adjustable delay time after the SENSE voltage
and manual reset (MR) return above their thresholds.
•
•
•
Very Low Quiescent Current: 2.4µA typ
High Threshold Accuracy: 0.5% typ
Fixed Threshold Voltages for Standard
Voltage Rails from 0.9V to 5V and Adjustable
Voltage Down to 0.4V Are Available
•
•
•
•
Manual Reset (MR) Input
Open-Drain RESET Output
The TPS3808 uses a precision reference to achieve
0.5% threshold accuracy for VIT ≤ 3.3V. The reset
delay time can be set to 20ms by disconnecting the
CT pin, 300ms by connecting the CT pin to VDD using
a resistor, or can be user-adjusted between 1.25ms
and 10s by connecting the CT pin to an external
capacitor. The TPS3808 has a very low typical
quiescent current of 2.4µA so it is well-suited to
battery-powered applications. It is available in a small
Temperature Range: –40°C to +125°C
Small SOT23 and 2mm × 2mm QFN Packages
APPLICATIONS
•
•
•
•
•
DSP or Microcontroller Applications
Notebook/Desktop Computers
PDAs/Hand-Held Products
Portable/Battery-Powered Products
FPGA/ASIC Applications
SOT23 and an ultra-small 2mm
× 2mm QFN
PowerPAD™ package and is fully specified over a
temperature range of –40°C to +125°C (TJ).
DBV PACKAGE
SOT23
1.2V
3.3V
(TOP VIEW)
6
5
4
1
2
3
RESET
GND
MR
VDD
SENSE
CT
V
V
CORE
SENSE
V
SENSE V
DD
I/O
DD
TPS3808G12
TPS3808G33
DSP
RESET
MR
RESET
GPIO
GND
CT
CT
GND
GND
DRV PACKAGE
2mm x 2mm QFN
(TOP VIEW)
VDD
1
2
3
6
5
4
RESET
Power
PAD
Typical Application Circuit
SENSE
CT
GND
MR
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2005, Texas Instruments Incorporated
TPS3808
www.ti.com
SBVS050E–MAY 2004–REVISED OCTOBER 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT
TPS3808G01
TPS3808G09
TPS3808G12
TPS3808G15
TPS3808G18
TPS3808G25
TPS3808G30
TPS3808G33
TPS3808G50
NOMINAL SUPPLY VOLTAGE(2)
THRESHOLD VOLTAGE (VIT)
Adjustable
0.9V
0.405V
0.84V
1.12V
1.40V
1.67V
2.33V
2.79V
3.07V
4.65V
1.2V
1.5V
1.8V
2.5V
3.0V
3.3V
5.0V
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Custom threshold voltages from 0.82V to 3.3V, 4.4V to 5.0V are available through the use of factory EEPROM programming. Minimum
order quantities apply. Contact factory for details and availability.
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range (unless otherwise noted)(1)
TPS3808
–0.3 to 7.0
–0.3 to VDD + 0.3
–0.3 to 7
5
UNIT
V
Input voltage range, VDD
CT voltage range, VCT
V
Other voltage ranges: VRESET, VMR, VSENSE
V
RESET pin current
mA
°C
°C
kV
V
(2)
Operating junction temperature range, TJ
–40 to +150
–65 to +150
2
Storage temperature range, TSTG
ESD rating, HBM
ESD rating, CDM
500
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) Due to the low dissipated power in this device, it is assumed that TJ = TA.
2
TPS3808
www.ti.com
SBVS050E–MAY 2004–REVISED OCTOBER 2005
ELECTRICAL CHARACTERISTICS
1.8V ≤ VDD ≤ 6.5V, RLRESET = 100kΩ, CLRESET = 50pF, over operating temperature range (TJ = –40°C to +125°C), unless
otherwise noted. Typical values are at TJ = +25°C.
PARAMETER
Input supply range
TEST CONDITIONS
MIN
TYP
MAX UNIT
VDD
1.8
6.5
V
VDD = 3.3V, RESET not asserted
MR, RESET, CT open
2.4
2.7
5.0
µA
IDD
Supply current (current into VDD pin)
VDD = 6.5V, RESET not asserted
MR, RESET, CT open
6.0
µA
1.3V ≤ VDD < 1.8V, IOL = 0.4mA
1.8V ≤ VDD ≤ 6.5V, IOL = 1.0mA
VOL (max) = 0.2V, IRESET = 15µA
0.3
0.4
V
V
V
VOL
Low-level output voltage
Power-up reset voltage(1)
0.8
TPS3808G01
–2.0
–1.5
±1.0
±0.5
±1.0
±0.5
±0.5
1.5
+2.0
+1.5
+2.0
+1.25
+1.5
3.0
VIT ≤ 3.3V
Negative-going
input threshold
accuracy
VIT
3.3V < VIT ≤ 5.0V
VIT ≤ 3.3V
–2.0
%
–40°C < TJ < +85°C
–1.25
–1.5
3.3V < VIT ≤ 5.0V –40°C < TJ < +85°C
TPS3808G01
VHYS
RMR
ISENSE
IOH
Hysteresis on VIT pin
%VIT
Fixed versions
1.0
2.5
MR Internal pull-up resistance
70
90
kΩ
nA
µA
nA
TPS3808G01
VSENSE = VIT
–25
25
Input current at
SENSE pin
Fixed versions
VSENSE = 6.5V
1.7
RESET leakage current
VRESET = 6.5V, RESET not asserted
VIN = 0V to VDD
300
CT pin
5
5
Input capacitance,
any pin
CIN
pF
V
Other pins
VIN = 0V to 6.5V
VIL
VIH
MR logic low input
MR logic high input
0.3 VDD
0.7 VDD
SENSE
VIH = 1.05VIT, VIL = 0.95VIT
VIH = 0.7VDD, VIL = 0.3VDD
20
0.001
20
Maximum transient
duration
tw
µs
MR
CT = Open
CT = VDD
CT = 100pF
CT = 180nF
MR to RESET
12
180
0.75
0.7
28
420
1.75
1.7
ms
ms
ms
s
300
1.25
1.2
td
RESET delay time
Propagation delay
See timing diagram
VIH = 0.7VDD, VIL = 0.3VDD
150
ns
tpHL
High to low level
RESET delay
SENSE to RESET VIH = 1.05VIT, VIL = 0.95VIT
20
µs
θJA
Thermal resistance, junction-to-ambient
290
°C/W
(1) The lowest supply voltage (VDD) at which RESET becomes active. Trise(VDD) ≥ 15µs/V.
3
TPS3808
www.ti.com
SBVS050E–MAY 2004–REVISED OCTOBER 2005
FUNCTIONAL BLOCK DIAGRAMS
VDD
VDD
VDD
TPS3808G01
VDD
Adjustable Voltage
90k
90k
RESET
RESET
MR
MR
SENSE
Reset
Logic
Timer
Reset
Logic
Timer
R1
−
−
SENSE
CT
CT
+
+
R2
0.4V
VREF
0.4V
VREF
Ω
R1 + R2 = 4M
GND
GND
Fixed Voltage Version
Adjustable Voltage Version
Figure 1. Adjustable and Fixed Voltage Versions
PIN ASSIGNMENTS
DBV PACKAGE
SOT23
DRV PACKAGE
2mm x 2mm QFN
(TOP VIEW)
(TOP VIEW)
6
5
4
1
2
3
RESET
GND
MR
VDD
VDD
SENSE
CT
1
2
3
6
5
4
RESET
GND
MR
Power
PAD
SENSE
CT
TERMINAL FUNCTIONS
TERMINAL
SOT23 (DBV)
PIN NO.
NAME
DESCRIPTION
RESET
1
RESET is an open drain output that is driven to a low impedance state when RESET is asserted (either the
SENSE input is lower than the threshold voltage (VIT) or the MR pin is set to a logic low). RESET will remain
low (asserted) for the reset period after both SENSE is above VIT and MR is set to a logic high. A pull-up
resistor from 10kΩ to 1MΩ should be used on this pin, and allows the reset pin to attain voltages higher than
VDD
.
GND
MR
2
3
Ground
Driving the manual reset pin (MR) low asserts RESET. MR is internally tied to VDD by a 90kΩ pull-up
resistor.
CT
4
Reset period programming pin. Connecting this pin to VDD through a 40kΩ to 200kΩ resistor or leaving it
open results in fixed delay times (see Electrical Characteristics). Connecting this pin to a ground referenced
capacitor ≥ 100pF gives a user-programmable delay time. See Selecting The Reset Delay Time in the
Device Operation section for more information.
SENSE
5
6
This pin is connected to the voltage to be monitored. If the voltage at this terminal drops below the threshold
voltage VIT, then RESET is asserted.
VDD
Supply voltage. It is good analog design practice to place a 0.1µF ceramic capacitor close to this pin.
PowerPAD
PowerPAD. Connect to ground plane to enhance thermal performance of package.
4
TPS3808
www.ti.com
SBVS050E–MAY 2004–REVISED OCTOBER 2005
TIMING DIAGRAM
VDD
0.8V
0.0V
RESET
SENSE
tD = Reset Delay
= Undefined State
tD
tD
tD
VIT + VHYS
VIT
MR
0.7VDD
0.3VDD
Time
Figure 2. TPS3808 Timing Diagram Showing MR and SENSE Reset Timing
TRUTH TABLE
MR
L
SENSE > VIT
RESET
0
1
0
1
L
L
L
H
L
H
H
5
TPS3808
www.ti.com
SBVS050E–MAY 2004–REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS
At TJ = +25°C, VDD = 3.3V, RLRESET = 100kΩ, and CLRESET = 50pF, unless otherwise noted.
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
RESET TIMEOUT PERIOD
vs
CT
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
100
10
_
+125 C
_
+85 C
−40°C, +25°C, +125°C
1
_
+25 C
0.1
0.01
0.001
_
−40 C
0
1
2
3
4
5
6
7
0.0001
0.001
0.01
0.1
1
10
V
DD
(V)
µ
CT ( F)
Figure 3.
Figure 4.
NORMALIZED RESET TIMEOUT PERIOD
vs
MAXIMUM TRANSIENT DURATION AT SENSE
TEMPERATURE
vs
(CT = OPEN, CT = VDD, CT = Any)
SENSE THRESHOLD OVERDRIVE VOLTAGE
100
10
1
10
8
6
4
RESET OCCURS
ABOVE THE CURVE
2
0
−2
−4
−6
−8
−10
0
5
10
15
20
25 30
35
45
40
50
10
30
50
70
90 110 130
−50 −30 −10
Overdrive (%VIT)
Temperature (°C)
Figure 5.
Figure 6.
6
TPS3808
www.ti.com
SBVS050E–MAY 2004–REVISED OCTOBER 2005
At TJ = +25°C, VDD = 3.3V, RLRESET = 100kΩ, and CLRESET = 50pF, unless otherwise noted.
NORMALIZED SENSE THRESHOLD VOLTAGE (VIT)
LOW-LEVEL RESET VOLTAGE
vs
vs
TEMPERATURE
RESET CURRENT
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
VDD = 1.8V
−0.8
−1.0
10
30
50
70
90 110 130
−50 −30 −10
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
RESET Current (mA)
Temperature (°C)
Figure 7.
Figure 8.
LOW-LEVEL RESET VOLTAGE
vs
RESET CURRENT
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VDD = 3.3V
VDD = 6.5V
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
RESET Current (mA)
Figure 9.
7
TPS3808
www.ti.com
SBVS050E–MAY 2004–REVISED OCTOBER 2005
DEVICE OPERATION
supply line can be used to allow the reset signal for
the microprocessor to have a voltage higher than VDD
(up to 6.5V). The pull-up resistor should be no
smaller than 10kΩ as a result of the finite impedance
of the RESET line.
The TPS3808 microprocessor supervisory product
family is designed to assert a RESET signal when
either the SENSE pin voltage drops below VIT or the
manual reset (MR) is driven low. The RESET output
remains asserted for a user-adjustable time after both
the manual reset (MR) and SENSE voltages return
above their thresholds. A broad range of voltage
threshold and reset delay time adjustments are
available, allowing these devices to be used in a wide
array of applications. Reset threshold voltages can be
factory-set from 0.82V to 3.3V or from 4.4V to 5.0V,
while the TPS3808G01 can be set to any voltage
above 0.405V using an external resistor divider. Two
preset delay times are also user-selectable:
connecting the CT pin to VDD results in a 300ms reset
delay, while leaving the CT pin open yields a 20ms
reset delay. In addition, connecting a capacitor
between CT and GND allows the designer to select
any reset delay period from 1.25ms to 10s.
SENSE INPUT
The SENSE input provides a terminal at which any
system voltage can be monitored. If the voltage on
this pin drops below VIT, then RESET is asserted.
The comparator has a built-in hysteresis to ensure
smooth RESET assertions and de-assertions. It is
good analog design practice to put a 1nF to 10nF
bypass capacitor on the SENSE input to reduce
sensitivity to transients and layout parasitics.
The TPS3808G01 can be used to monitor any
voltage rail down to 0.405V using the circuit shown in
Figure 11.
VIN
VOUT
RESET OUTPUT
VDD
R1
R2
VIT
′
= (1 +
)0.405
A typical application of the TPS3808G25 used with
the OMAP1510 processor is shown in Figure 10. The
open drain RESET output is typically connected to
the RESET input of a microprocessor. A pull-up
resistor must be used to hold this line high when
RESET is not asserted. The RESET output is
undefined for voltage below 0.8V, but this is normally
not a problem since most microprocessors do not
function below this voltage. RESET remains high
(unasserted) as long as SENSE is above its threshold
(VIT) and the manual reset (MR) is logic high. If either
SENSE falls below VIT or MR is driven low, RESET is
asserted, driving the RESET pin to a low impedance.
R1
TPS3808G01
SENSE
RESET
GND
R2
1nF
Figure 11. Using the TPS3808G01 to Monitor a
User-Defined Threshold Voltage
MANUAL RESET (MR) INPUT
2.5V
The manual reset (MR) input allows a processor or
other logic circuits to initiate a reset. A logic low
(0.3VDD) on MR causes RESET to assert. After MR
returns to a logic high and SENSE is above its reset
threshold, RESET is de-asserted after the user
defined reset delay expires. Note that MR is internally
tied to VDD using a 90kΩ resistor so this pin can be
left unconnected if MR will not be used.
V
SENSE
V
DD
DDSHV 1, 3, 6, 7, 9
Ω
1M
TPS3808G25
OMAP1510
MR
RESET
RESPWRON
GND
CT
GND
See Figure 12 for how MR can be used to monitor
multiple system voltages. Note that if the logic signal
driving MR does not go fully to VDD, there will be
some additional current draw into VDD as a result of
the internal pull-up resistor on MR. To minimize
current draw, a logic-level FET can be used as
illustrated in Figure 13.
Figure 10. Typical Application of the TPS3808
with an OMAP Processor
Once MR is again logic high and SENSE is above VIT
+ VHYS (the threshold hysteresis), a delay circuit is
enabled which holds RESET low for a specified reset
delay period. Once the reset delay has expired, the
RESET pin goes to a high impedance state. The
pull-up resistor from the open drain RESET to the
8
TPS3808
www.ti.com
SBVS050E–MAY 2004–REVISED OCTOBER 2005
by the choice of resistor. Figure 14b shows a fixed
20ms delay time by leaving the CT pin open.
Figure 14c shows a ground referenced capacitor
connected to CT for a user-defined program time
between 1.25ms and 10s.
1.2V
3.3V
V
V
CORE
SENSE
V
SENSE V
DD
I/O
DD
The capacitor CT should be ≥ 100pF nominal value in
order for the TPS3808xxx to recognize that the
capacitor is present. The capacitor value for a given
delay time can be calculated using the following
equation:
TPS3808G12
TPS3808G33
DSP
RESET
MR
RESET
GPIO
GND
CT
CT
GND
GND
*3
ƪ
ƫ
CT (nF) + tD (s)*0.5 10 (s) 175
(1)
The reset delay time is determined by the time it
takes an on-chip precision 220nA current source to
charge the external capacitor to 1.23V. When a
RESET is asserted the capacitor is discharged. When
the RESET conditions are cleared, the internal
current source is enabled and begins to charge the
external capacitor. When the voltage on this capacitor
reaches 1.23V, RESET is de-asserted. Note that a
low leakage type capacitor such as a ceramic should
be used, and that stray capacitance around this pin
may cause errors in the reset delay time.
Figure 12. Using MR to Monitor Multiple System
Voltages
3.3V
V
SENSE
DD
Ω
90k
CT
TPS3808xxx
IMMUNITY TO SENSE PIN VOLTAGE
TRANSIENTS
GND
The TPS3808 is relatively immune to short negative
transients on the SENSE pin. Sensitivity to transients
is dependent on threshold overdrive, as shown in the
Maximum Transient Duration at Sense vs Sense
Threshold Overdrive Voltage graph (Figure 6) in the
Typical Characteristics section.
Figure 13. Using an External MOSFET to Minimize
IDD When MR Signal Does Not Go to VDD
SELECTING THE RESET DELAY TIME
The TPS3808 has three options for setting the
RESET delay time as shown in Figure 14. Figure 14a
shows the configuration for a fixed 300ms typical
delay time by tying CT to VDD; a resistor from 40kΩ to
200kΩ must be used. Supply current is not affected
3.3V
3.3V
3.3V
SENSE VDD
SENSE VDD
SENSE VDD
Ω
50k
TPS3808G33
TPS3808G33
TPS3808G33
RESET
CT RESET
CT RESET
CT
CT
−3
Delay (s) = C (nF) + 0.5 x 10 (s)
T
300ms Delay
20ms Delay
175
(b)
(a)
(c)
Figure 14. Configuration Used to Set the RESET Delay Time
9
PACKAGE OPTION ADDENDUM
www.ti.com
26-Oct-2005
PACKAGING INFORMATION
Orderable Device
TPS3808G01DBVR
TPS3808G01DBVRG4
TPS3808G01DBVT
TPS3808G01DBVTG4
TPS3808G09DBVR
TPS3808G09DBVT
TPS3808G09DBVTG4
TPS3808G12DBVR
TPS3808G12DBVRG4
TPS3808G12DBVT
TPS3808G12DBVTG4
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-23
DBV
6
6
6
6
6
6
6
6
6
6
6
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS3808G12DRVR
TPS3808G12DRVT
TPS3808G15DBVR
PREVIEW
PREVIEW
ACTIVE
SON
SON
DRV
DRV
DBV
6
6
6
3000
250
TBD
TBD
Call TI
Call TI
Call TI
Call TI
SOT-23
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS3808G15DBVRG4
TPS3808G15DBVT
TPS3808G15DBVTG4
TPS3808G18DBVR
TPS3808G18DBVRG4
TPS3808G18DBVT
TPS3808G18DBVTG4
TPS3808G25DBVR
TPS3808G25DBVRG4
TPS3808G25DBVT
TPS3808G25DBVTG4
TPS3808G30DBVR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
6
6
6
6
6
6
6
6
6
6
6
6
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Oct-2005
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
no Sb/Br)
TPS3808G30DBVRG4
TPS3808G30DBVT
TPS3808G30DBVTG4
TPS3808G33DBVR
TPS3808G33DBVRG4
TPS3808G33DBVT
TPS3808G33DBVTG4
TPS3808G50DBVR
TPS3808G50DBVRG4
TPS3808G50DBVT
TPS3808G50DBVTG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
6
6
6
6
6
6
6
6
6
6
6
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
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www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
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