TPS386060RGPR_技术文档

TPS386000, TPS386020

TPS386040, TPS386060

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Quad Supply Voltage Supervisors

with Programmable Delay and Watchdog Timer

Check for Samples: TPS386000 TPS386020 TPS386040 TPS386060

1

FEATURES

DESCRIPTION

2

•

4 Complete SVS Modules on 1 Silicon Platform

Programmable Delay Time: 1.4ms to 10s

Very Low Quiescent Current: 12μA typ

Threshold Accuracy: 0.25% typ

The TPS3860x0 family of voltage supervisors can

monitor four power rails that are greater than 0.4V

with a 0.25% (typical) threshold accuracy. Each of the

four supervisory circuits (SVS-n) assert a RESETn or

RESETn output signal when the SENSEm input

voltage drops below the programmed threshold. With

external resistors, the threshold of each SVS-n can

be programmed (where n = 1, 2, 3, 4 and m = 1, 2, 3,

4L, 4H).

•

Adjustable Threshold Down to 0.4V

SVS-1: Manual Reset (MR) Input

SVS-4: Window Comparator or Low-Voltage

Sensing with VREF (1.2V) Pin

Each SVS-n has a programmable delay before

releasing RESETn or RESETn, and the delay time

can be set from 1.4ms to 10s through the CTn pin

connection. Only SVS-1 has an active-low manual

reset (MR) input; a logic-low input to MR asserts

RESET1 or RESET1.

•

Watchdog Timer with Dedicated Output

Well-Controlled RESETn Output During

Power-Up

•

TPS386000: Open-Drain RESETn and WDO

TPS386020: Open-Drain RESETn and WDO

TPS386040: Push-Pull RESETn and WDO

TPS386060: Push-Pull RESETn and WDO

Package: 4mm x 4mm, 20-pin QFN

SVS-4 monitors the threshold window using two

comparators. The extra comparator can be

configured as a fifth SVS to monitor negative voltage

with voltage reference output VREF.

The TPS3860x0 has a very low quiescent current of

12μA (typical) and is available in a small, 4mm x

4mm, QFN-20 package.

APPLICATIONS

•

Analog Sequencing

All DSP and Microcontroller Applications

All FPGA/ASIC Applications

Sequence: VIN

VCC41(positive)&VCC42(neagtive)

VCC3

VCC42

VCC2

VCC1

VCC-

AMP

VCC+

VCC41

EN4 DC-DC

LDO

VCC3

VCC2

VCC1

EN3 DC-DC

LDO

RP5 RP4 RP3 RP2 RP1

VCC

Sub CPU

MSP430

MR

VREF

WDO

VCC1

VCC2

VCC3

CLK

EN2 DC-DC

LDO

WDI

RS3H

RS2H

RS1H

DSP

CPU

FPGA

SENSE1

RESET1

RESET2

RESET3

RESET4

RESET

SENSE2

SENSE3

SENSE4L

TPS386000

Pos

and

VIN

RS41H

Neg

DC-DC

SENSE4H

CT1

CT2

CT3

CT4

GND

RS42L

CT1

CT2

CT3

CT4

RS42H

RS41L

RS3L

RS2L

RS1L

Figure 1. TPS386000 Typical Application Circuit

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS386000, TPS386020

TPS386040, TPS386060

SBVS105 –SEPTEMBER 2009......................................................................................................................................................................................... www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION⁽¹⁾

PRODUCT

DESCRIPTION

TPS3860x0yyy z

x is device configuration option

xx x = 0: Open-drain, active low

xx x = 2: Open-drain, active high

xx x = 4: Push-pull, active low

xx x = 6: Push-pull, active high

yyy is package designator

z is package quantity

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating junction temperature range, unless otherwise noted.

TPS3860x0

–0.3 to 7.0

UNIT

V

Input voltage range, V_VCC

CT pin voltage range, V_CT1, V_CT2, V_CT3, V_CT4

–0.3 to V_VCC+ 0.3

V

Other voltage ranges: V_RESET1, V_RESET2, V_RESET3, V_RESET4, V_MR, V_SENSE1

V_SENSE2, V_SENSE3, V_SENSE4L, V_SENSE4H, V_WDI, V_WDO

,

–0.3 to 7.0

V

RESETn , RESETn, WDO, WDO, VREF pin current

Continuous total power dissipation

5

mA

See Dissipation Ratings Table

(2)

Operating virtual junction temperature range, T_J

–40 to +150

–40 to +125

–65 to +150

2

°C

kV

V

Operating ambient temperature range

Storage temperature range, T_STG

Human body model (HBM)

ESD rating

Charged device model (CDM)

500

(1) Stresses beyond those listed under the Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the recommended

operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

(2) As a result of the low dissipated power in this device, it is assumed that T_J= T_A.

DISSIPATION RATINGS

T_A< +25°C

DERATING FACTOR

ABOVE T_A> +25°C

T_A= +70°C

POWER RATING

T_A= +85°C

POWER RATING

PACKAGE

POWER RATING

RGP

2.86W

28.6mW/°C

1.57W

1.24W

2

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ELECTRICAL CHARACTERISTICS

Over the operating temperature range of T_J= –40°C to +125°C, 1.8V < V_VCC< 6.5V, R_RESETn(n = 1, 2, 3, 4) = 100kΩ to V_VCC

(TPS386000, TPS386020 only), C_RESETn(n = 1, 2, 3, 4L, 4H) = 50pF to GND, R_WDO= 100kΩ to V_VCC, C_WDO= 50pF to GND,

V_MR= 100kΩ to V_VCC, WDI = GND, and CTn (n = 1, 2, 3, 4) = open, unless otherwise noted. Typical values are at T_J= +25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_VCC

Input supply range

1.8

6.5

V

V_VCC= 3.3V, RESETn or RESETn not

asserted, WDI toggling⁽¹⁾, no output load,

and VREF open

11

13

19

μA

I_VCC

Supply current (current into VCC pin)

V_VCC= 6.5V, RESETn or RESETn not

asserted, WDI toggling⁽¹⁾, no output load,

and VREF open

22

μA

Power-up reset

voltage^{(2) (3)}

TPS386000,

TPS386040

V_OL(max) = 0.2V, I_RESETn= 15μA

0.9

V

V_ITN

Negative-going input threshold voltage SENSE1, SENSE2, SENSE3, SENSE4L

Positive-going input threshold voltage SENSE4H

396

400

3.5

404

mV

nA

V

V_ITP

V_HYSN

V_HYSP

I_SENSE

Hysteresis (positive-going) on V_ITN

Hysteresis (negative-going) on V_ITP

Input current at SENSEm pin

SENSE1, SENSE2, SENSE3, SENSE4L

SENSE4H

10

3.5

10

VSENSEm = 0.42V

–25

245

1

+25

CT1

C_CT1> 220pF, V_CT1= 0.5V⁽⁴⁾

300

1.238

355

CTn pin charging

current

I_CT

CT2, CT3, CT4 C_CTn> 220pF, V_CTn= 0.5V⁽⁴⁾

235

365

V_TH(CTn)CTn pin threshold

C_CTn> 220pF

1.180

0

1.299

0.3V_VCC

V_IL

V_IH

MR and WDI logic low input

MR and WDI logic high input

V

0.7V_VCC

V

All

I_OL= 1mA

0.4

0.3

0.4

0.3

V

Low-level RESETn

or RESETn output

voltage

TPS386000,

TPS386040

SENSEn = 0V, 1.3V < V_VCC< 1.8V,

I_OL= 0.4mA⁽²⁾

V

V_OL

All

I_OL= 1mA

Low-level WDO

output voltage

TPS386020,

TPS386060

SENSEn = 0V, 1.3V < V_VCC< 1.8V,

I_OL= 0.4mA⁽²⁾

TPS386040,

TPS386060

I_OL= –1mA

V_VCC– 0.4

V_VCC– 0.3

V_VCC– 0.4

V_VCC– 0.3

V

High-level RESETn

or RESETn output

voltage

SENSEn = 0V, 1.3V < V_VCC< 1.8V,

I_OL= –0.4mA⁽²⁾

TPS386060

V_OH

TPS386040,

TPS386060

I_OL= –1mA

High-level WDO

output voltage

SENSEn = 0V, 1.3V < V_VCC< 1.8V,

I_OL= –0.4mA⁽²⁾

TPS386040

RESETn, RESETn,

WDO, and WDO

leakage current

TPS386000,

TPS386020

V_RESETn= 6.5V, RESETn, RESETn, WDO,

and WDO are logic high

I_LKG

–300

1.18

300

nA

V_REF

C_IN

Reference voltage output

Input pin capacitance

1μA < I_VREF< 0.2mA (source only, no sink)

1.20

5

1.22

V

CTn: 0V to V_VCC, other pins: 0V to 6.5V

pF

SENSEm: 1.05V_ITN→ 0.95V_ITNor

0.95V_ITP→ 1.05V_ITP

4

μs

Input pulse width to SENSEm and MR

pins

t_W

MR: 0.7V_CC→ 0.3V_VCC

CTn = open

1

20

ns

ms

14

24

t_D

RESETn or RESETn delay time

Watchdog timer timeout period

CTn = V_VCC

225

300

375

Start from RESET1 or RESET1 release or

last WDI transition

t_WDT

450

600

750

ms

(1) Toggling WDI for a period less than t_WDTnegatively affects I_VCC

.

(2) These specifications are beyond the recommended V_VCCrange, and only define RESETn or RESETn output performance during VCC

ramp up.

(3) The lowest supply voltage (V_VCC) at which RESETn or RESETn becomes active; t_RISE(VCC) ≥ 15μs/V.

(4) CTn (where n = 1, 2, 3, or 4) are constant current charging sources working from a range of 0V to V_TH(CTn), and the device is tested at

V_CTn= 0.5V. For I_CTperformance between 0V and V_TH(CTn), see Figure 26 .

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TPS386000, TPS386020

TPS386040, TPS386060

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FUNCTIONAL BLOCK DIAGRAMS

VCC

WDO

WDI

WDT

VREF

RESET1

SENSE1

Delay

0.4V

MR

CT1

RESET2

SENSE2

Delay

0.4V

CT2

RESET3

SENSE3

Delay

0.4V

CT3

RESET4

SENSE4L

Delay

0.4V

SENSE4H

CT4

GND

Figure 2. TPS386000 Block Diagram

4

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VCC

WDO

WDI

WDT

VREF

RESET1

SENSE1

Delay

0.4V

MR

CT1

RESET2

SENSE2

Delay

0.4V

CT2

RESET3

SENSE3

Delay

0.4V

CT3

RESET4

SENSE4L

Delay

0.4V

SENSE4H

CT4

GND

Figure 3. TPS386020 Block Diagram

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VCC

WDO

WDI

WDT

VREF

SENSE1

Delay

RESET1

0.4V

MR

CT1

SENSE2

Delay

RESET2

0.4V

CT2

SENSE3

Delay

RESET3

0.4V

CT3

SENSE4L

Delay

RESET4

0.4V

SENSE4H

CT4

GND

Figure 4. TPS386040 Block Diagram

6

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VCC

WDO

WDI

WDT

VREF

SENSE1

Delay

RESET1

0.4V

MR

CT1

SENSE2

Delay

RESET2

0.4V

CT2

SENSE3

Delay

RESET3

0.4V

CT3

SENSE4L

Delay

RESET4

0.4V

SENSE4H

CT4

GND

Figure 5. TPS386060 Block Diagram

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PIN CONFIGURATIONS

RGP PACKAGE

QFN-20

(TOP VIEW)

1

2

3

4

5

15

14

13

12

11

MR

CT4

CT3

CT2

CT1

RESET1

VCC

1

2

3

4

5

15

14

13

12

11

MR

CT4

CT3

CT2

CT1

RESET1

VCC

TPS386000

TPS386040

TPS386020

TPS386060

VREF

GND

VREF

GND

(Thermal Pad)

NC

PIN ASSIGNMENTS

NAME

NO.

DESCRIPTION

VCC

GND

14

12

Supply voltage. Connecting a 0.1μF ceramic capacitor close to this pin is recommended.

Ground

When the voltage at this terminal drops below the

threshold voltage (V_ITN), RESET1 is asserted.

SENSE1

SENSE2

SENSE3

SENSE4L

10

9

Monitor voltage input to SVS-1

Monitor voltage input to SVS-2

Monitor voltage input to SVS-3

When the voltage at this terminal drops below the

threshold voltage (V_ITN), RESET2 is asserted.

When the voltage at this terminal drops below the

threshold voltage (V_ITN), RESET3 is asserted.

8

Falling monitor voltage input to SVS-4. When the voltage at this terminal drops below the threshold

voltage (V_ITN), RESET4 or RESET4 is asserted.

7

Rising monitor voltage input to SVS-4. When the voltage at this terminal exceeds the threshold voltage

(V_ITP), RESET4 or RESET4 is asserted. This pin can also be used to monitor the negative voltage rail

in combination with VREF pin.

SENSE4H

6

CT1

CT2

CT3

5

4

3

Reset delay programming pin for SVS-1

Reset delay programming pin for SVS-2

Reset delay programming pin for SVS-3

Connecting this pin to VCC through a 40kΩ to

200kΩ resistor, or leaving it open, selects a fixed

delay time (see the Electrical Characteristics).

Connecting a capacitor > 220pF between this pin

and GND selects the programmable delay time

(see the Reset Delay Time section).

CT4

2

Reset delay programming pin for SVS-4

Reference voltage output. By connecting a resistor network between this pin and the negative power

rail, SENSE4H can monitor the negative power rail. This pin is intended to only source current into

resistor(s). Do not connect only capacitors and do not connect resistor(s) to a higher voltage than this

pin.

VREF

13

MR

1

Manual reset input for SVS-1. Logic low level of this pin asserts RESET1 or RESET1.

Watchdog timer (WDT) trigger input. Inputting either a positive or negative logic edge every 610ms (typ)

prevents WDT time out at the WDO or WDO pin. Timer starts from releasing event of RESET1 or

RESET1.

WDI

20

NC

11

Not connected. It is recommended to connect this pin to the GND pin (pin 12), which is next to this pin.

This is the IC substrate. This pad must be connected only to GND or to the floating thermal pattern on

the printed circuit board (PCB).

(Thermal Pad)

(PAD)

8

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PIN ASSIGNMENTS (continued)

NAME

TPS386000

RESET1

NO.

DESCRIPTION

15

16

17

18

Active low reset output of SVS-1

Active low reset output of SVS-2

Active low reset output of SVS-3

Active low reset output of SVS-4

RESETn is an open-drain output pin. When

RESETn is asserted, this pin remains in a

low-impedance state. When RESETn is released,

this pin goes to a high-impedance state after the

delay time programmed by CTn.

RESET2

RESET3

RESET4

Watchdog timer output. This is an open-drain output pin. When WDT times out, this pin goes to a

low-impedance state to GND. If there is no WDT timeout, this pin stays in a high-impedance state.

WDO

19

TPS386020

RESET1

RESET2

RESET3

RESET4

15

16

17

18

Active high reset output of SVS-1

Active high reset output of SVS-2

Active high reset output of SVS-3

Active high reset output of SVS-4

RESETn is open-drain output pin. When RESETn

is asserted, this pin remains in a high impedance

state. When RESETn is released, this pin goes to

a low-impedance state after the delay time

programmed by CTn.

Watchdog timer output. This is an open-drain output pin. When WDT times out, this pin goes to a

high-impedance state. If there is no WDT timeout, this pin stays in a low-impedance state to GND.

WDO

19

TPS386040

RESET1

RESET2

RESET3

RESET4

15

16

17

18

Active low reset output of SVS-1

Active low reset output of SVS-2

Active low reset output of SVS-3

Active low reset output of SVS-4

RESETn is a push-pull logic buffer output pin.

When RESETn is asserted, this pin remains logic

low. When RESETn is released, this pin goes to

logic high after the delay time programmed by

CTn.

Watchdog timer output. This is a push-pull output pin. When WDT times out, this pin goes to logic low.

If there is no WDT timeout, this pin stays in logic high.

WDO

19

TPS386060

RESET1

RESET2

RESET3

RESET4

15

16

17

18

Active high reset output of SVS-1

RESETn is a push-pull logic buffer output pin.

Active high reset output of SVS-2

Active high reset output of SVS-3

Active high reset output of SVS-4

When RESETn is asserted, this pin remains logic

high. When RESETn is released, this pin goes to

logic low after the delay time programmed by CTn.

Watchdog timer output. This is a push-pull output pin. When WDT times out, this pin goes to logic high.

If there is no WDT timeout, this pin stays in logic low.

WDO

19

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TYPICAL CHARACTERISTICS

At T_A= +25°C, and V_CC= 3.3V, with all four options (TPS386000, TPS386020, TPS386040, and TPS386060) having the

same characteristics, unless otherwise noted.

TPS386040

SUPPLY CURRENT vs SUPPLY VOLTAGE

RESETn TIMEOUT Period vs CTn

10000

1000

100

10

20

18

16

14

12

10

8

+125°C

+85°C

+105°C

+85°C

+25°C

0°C

+125°C

-40°C

6

4

-40°C

2

NOTE: UVLO released at approximately 1.5V.

1

0

0.0001

0.001

0.01

CT (mF)

0.1

1

0

1

2

3

4

5

6

7

V_CC(V)

Figure 6.

Figure 7.

TPS386040

RESETn TIMEOUT PERIOD vs TEMPERATURE (CTn = Open)

RESETn TIMEOUT PERIOD vs TEMPERATURE (CTn = V_CC)

25

360

CT1

CT3

340

320

20

15

10

5

CT2

CT4

CT1

CT3

300

280

260

240

CT2

CT4

0

-50 -30 -10

10

30

50

70

90

110 130

-50 -30 -10

10

30

50

70

90

110 130

Temperature (°C)

Figure 8.

Figure 9.

TPS386040

RESETn TIMEOUT PERIOD vs TEMPERATURE (CTn = 0.1µF)

WDO TIMEOUT PERIOD vs TEMPERATURE

550

700

680

660

640

620

600

580

560

540

520

500

450

V_CC= 1.8V

V_CC= 3.3V

CT3

CT4

400

350

300

250

CT1

CT2

V_CC= 6.5V

NOTE: These curves contain variance of capacitor values.

-50 -30 -10

10

30

50

70

90

110 130

-50 -30 -10

10

30

50

70

90

110 130

Temperature (°C)

Figure 10.

Figure 11.

10

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, and V_CC= 3.3V, with all four options (TPS386000, TPS386020, TPS386040, and TPS386060) having the

same characteristics, unless otherwise noted.

TPS386040

SENSEn MINIMUM PULSE WIDTH

TPS386040

vs SENSEn THRESHOLD OVERDRIVE VOLTAGE

SENSE1 THRESHOLD VOLTAGE vs TEMPERATURE

100

408

2mV » 0.5%

406

V_ITN+ V_HYSN, V_CC= 6.5V

SENSE4H

10

404

SENSE4L

V_ITN+ V_HYSN, V_CC= 1.8V

402

SENSE2

SENSE1

SENSE3

V_ITN+ V_HYSN, V_CC= 3.3V

V_ITN, V_CC= 6.5V

1

400

V_ITN, V_CC= 1.8V

V_ITN, V_CC= 3.3V

398

396

NOTE: See Figure 27 for the measurement technique.

0.1

1

10

100

-50 -30 -10

10

30

50

70

90

110 130

Overdrive (%)

Temperature (°C)

Figure 12.

Figure 13.

TPS386040

SENSE2 THRESHOLD VOLTAGE vs TEMPERATURE

SENSE3 THRESHOLD VOLTAGE vs TEMPERATURE

408

2mV » 0.5%

406

V_ITN+ V_HYSN, V_CC= 6.5V

V_ITN+ V_HYSN, V_CC= 3.3V

V_ITN+ V_HYSN, V_CC= 6.5V

404

V_ITN+ V_HYSN, V_CC= 1.8V

V_ITN, V_CC= 3.3V

402

V_ITN+ V_HYSN, V_CC= 3.3V

400

V_ITN, V_CC= 1.8V

V_ITN, V_CC= 6.5V

V_ITN, V_CC= 3.3V

V_ITN, V_CC= 6.5V

398

396

398

V_ITN, V_CC= 1.8V

396

-50 -30 -10

10

30

50

70

90

110 130

-50 -30 -10

10

30

50

70

90

110 130

Temperature (°C)

Figure 14.

Figure 15.

TPS386040

SENSE4L THRESHOLD VOLTAGE vs TEMPERATURE

SENSE4H THRESHOLD VOLTAGE vs TEMPERATURE

408

404

2mV » 0.5%

406

402

V_ITP+ V_HYSP, V_CC= 3.3V

V_ITP+ V_HYSP, V_CC= 6.5V

V_ITN+ V_HYSN, V_CC= 6.5V

V_ITN+ V_HYSN, V_CC= 3.3V

404

400

V_ITN+ V_HYSN, V_CC= 1.8V

V_ITP, V_CC= 1.8V

V_ITP+ V_HYSP, V_CC= 1.8V

402

398

396

394

392

V_ITN, V_CC= 1.8V

400

V_ITP, V_CC= 6.5V

V_ITN, V_CC= 6.5V

V_ITN, V_CC= 3.3V

398

396

V_ITP, V_CC= 6.5V

70 90 110 130

-50 -30 -10

10

30

50

70

90

110 130

-50 -30 -10

10

30

50

Temperature (°C)

Figure 16.

Figure 17.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, and V_CC= 3.3V, with all four options (TPS386000, TPS386020, TPS386040, and TPS386060) having the

same characteristics, unless otherwise noted.

OUTPUT VOLTAGE LOW vs OUTPUT CURRENT

OUTPUT VOLTAGE LOW AT 1mA vs TEMPERATURE

0.200

All RESETn, RESETn, WDO, and WDO

0.180

0.160

0.140

0.120

0.100

0.080

0.060

0.040

0.020

0

0.180

0.160

V_CC= 1.8V

0.140

V_CC= 1.8V, +25°C

V_CC= 3.3V

0.120

0.100

0.080

V_CC= 3.3V, +25°C

0.060

V_CC= 6.5V

0.040

0.020

0

V_CC= 6.5V, +25°C

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Output Sink Current (mA)

-50 -30 -10

10

30

50

70

90

110 130

Temperature (°C)

Figure 18.

Figure 19.

OUTPUT VOLTAGE HIGH vs OUTPUT CURRENT

OUTPUT VOLTAGE HIGH AT 1mA vs TEMPERATURE

0

V_CC= 6.5V, +25°C

All RESETn, RESETn, WDO, and WDO

V_CC= 6.5V

-0.050

V_CC= 1.8V, +25°C

V_CC= 3.3V, +25°C

-0.100

-0.150

-0.200

-0.250

-0.100

V_CC= 3.3V

-0.150

V_CC= 1.8V

-0.200

All RESETn, RESETn, WDO, and WDO

-0.250

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Output Source Current (mA)

-50 -30 -10

10

30

50

70

90

110 130

Temperature (°C)

Figure 20.

Figure 21.

TPS386040

V_REFOUTPUT LOAD REGULATION (V_CC= 1.8V)

V_REFOUTPUT LOAD REGULATION (V_CC= 3.3V)

1.200

0°C

1.198

1.196

1.194

1.192

1.190

1.188

1.198

1.196

1.194

1.192

1.190

1.188

0°C

+25°C

+85°C

-40°C

+85°C

-40°C

+105°C

+125°C

+105°C

+125°C

NOTE: Y-Axis (1.188V to 1.2V) is 1% of 1.2V.

0

50

100

150

200

250

300

350

400

0

50

100

150

200

250

300

350

400

Load (mA)

Figure 22.

Figure 23.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, and V_CC= 3.3V, with all four options (TPS386000, TPS386020, TPS386040, and TPS386060) having the

same characteristics, unless otherwise noted.

TPS386040

V_REFOUTPUT LOAD REGULATION (V_CC= 6.5V)

V_REFAT 0µA vs TEMPERATURE

1.207

1.205

1.203

1.201

1.199

1.197

1.195

NOTE: Y-Axis (1.195V to 1.207V) is 1% of 1.2V.

V_CC= 6.5V

1.205

1.203

1.201

1.199

1.197

1.195

0°C

V_CC= 3.3V

-40°C

+25°C

+85°C

V_CC= 1.8V

+105°C

+125°C

0

50

100

150

200

Load (mA)

250

300

350

400

-50 -30 -10

10

30

50

70

90

110 130

Temperature (°C)

Figure 24.

Figure 25.

TPS386040

CT1 TO CT4 PIN CHARGING CURRENT vs TEMPERATURE OVER CT PIN VOLTAGE

0.33

0.32

0.1V

0.31

0V

0.3V

0.5V

0.30

0.29

0.28

0.27

1.1V

0.9V

0.7V

NOTE: Min and max values of Y-axis are 10% of 0.3mA.

-50 -30 -10

10

30

50

70

90

110 130

Temperature (°C)

Figure 26.

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PARAMETRIC MEASUREMENT INFORMATION

TEST CIRCUIT

Z₁

X₁

X₂

=

´ 100 (%)

V_ITN= 0.42V

V_ITN= 0.4V

0.4

Z₂

0.4

Y₁

Y₂

Z₁

X₁and X₂are overdrive (%) values calculated

from actual SENSEn voltage amplitudes

measured as Z₁and Z₂.

Z₂

Y_Nis the minimum pulse width that gives

RESETn or RESETn transition.

Greater Z_Nproduces shorter Y_N.

For SENSE4H, this graph should be inverted

180 degrees on the voltage axis.

Time

Figure 27.

GENERAL DESCRIPTION

The TPS3860x0 multi-channel supervisory device

family combines four complete SVS function sets into

one IC. The design of each SVS channel is based on

the single-channel supervisory device series,

TPS3808. The TPS3860x0 is designed to assert

RESETn or RESETn signals, as shown in Table 1,

Table 2, Table 3, and Table 4. The RESETn or

user-configurable delay time after the event of reset

release (see the Reset Delay Time section). Each

SENSEm (m = 1, 2, 3, 4L, 4H) pin can be set to any

voltage threshold above 0.4V using an external

resistor divider. A broad range of voltage threshold

and reset delay time adjustments can be supported,

allowing these devices to be used in a wide array of

applications.

RESETn outputs remain asserted during

a

Table 1. SVS-1 Truth Table

OUTPUT

TPS386000

TPS386040

TPS386020

TPS386060

CONDITION

STATUS

MR = Low

MR = High

SENSE1 < V_ITN

SENSE1 > V_ITN

SENSE1 < V_ITN

RESET1 = Low

RESET1 = High

Reset asserted

Reset released after

delay

MR = High

SENSE1 > V_ITN

RESET1 = High

RESET1 = Low

Table 2. SVS-2 Truth Table

OUTPUT

TPS386000

TPS386020

CONDITION

SENSE2 < V_ITN

SENSE2 > V_ITN

TPS386040

RESET2 = Low

RESET2 = High

TPS386060

RESET2 = High

RESET2 = Low

STATUS

Reset asserted

Reset released after delay

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Table 3. SVS-3 Truth Table

OUTPUT

TPS386000

TPS386040

TPS386020

TPS386060

CONDITION

SENSE3 < V_ITN

SENSE3 > V_ITN

STATUS

RESET3 = Low

RESET3 = High

RESET3 = Low

Reset asserted

Reset released after delay

Table 4. SVS-4 Truth Table

OUTPUT

TPS386000

TPS386040

TPS386020

TPS386060

CONDITION

SENSE4H > V_ITP

STATUS

SENSE4L < V_ITN

SENSE4L > V_ITN

RESET4 = Low

RESET4 = High

Reset asserted

SENSE4H < V_ITP

SENSE4H > V_ITP

Reset released after

delay

SENSE4L > V_ITN

SENSE4H < V_ITP

RESET4 = High

RESET4 = Low

Table 5. Watchdog Timer (WDT) Truth Table

CONDITION

OUTPUT

RESET1 OR

RESET1

TPS386000

TPS386040

TPS386020

TPS386060

WDO

WDI PULSE INPUT

STATUS

Remains in WDT

timeout

Low

High

Asserted

Released

Toggling

WDO = low

WDO = high

Remains in WDT

timeout

Low

610ms after last WDI↑ or WDI↓

WDO = high

Remains in WDT

timeout

Toggling

Remains in WDT

timeout

610ms after last WDI↑ or WDI↓

WDO = low

WDO = high

High

Low

Asserted

Released

Toggling

WDO = low

WDO = high

Normal operation

Enters WDT timeout

610ms after last WDI↑ or WDI↓ WDO = high

Toggling

WDO = high

WDO = low

610ms after last WDI↑ or WDI↓

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RESET OUTPUT

VCC

In a typical TPS3860x0 application, RESETn or

RESETn outputs are connected to the reset input of a

processor (DSP, CPU, FPGA, ASIC, etc.), or

0.9V

connected to the enable input of a voltage regulator

(DC-DC, LDO, etc.)

t

The TPS386000 and TPS386020 provide open-drain

reset outputs. Pull-up resistors must be used to hold

SENSE1

these lines high when RESETn is not asserted, or

when RESETn is asserted. By connecting pull-up

resistors to the proper voltage rails (up to 6.5V),

V_HYSN

RESETn or RESETn output nodes can be connected

V_ITN

to the other devices at the correct interface voltage

levels. The pull-up resistor should be no smaller than

10kΩ because of the safe operation of the output

t

transistors. By using wired-OR logic, any combination

of RESETn can be merged into one logic signal.

MR

The TPS386040 and TPS386060 provide push-pull

reset outputs. The logic high level of the outputs is

determined by the VCC voltage. With this

configuration, pull-up resistors are not required and

some board area can be saved. However, all the

interface logic levels should be examined. All

t

RESETn or RESETn connections must be compatible

with the VCC logic level.

RESET1

The RESETn or RESETn outputs are defined for

VCC voltage higher than 0.9V. To ensure that the

target processor(s) are properly reset, the VCC

t_D

supply input should be fed by the available power rail

as early as possible in application circuits. Table 1,

Table 2, Table 3, and Table 4 are truth tables that

describe how the outputs are asserted or released.

Figure 28, Figure 29, Figure 30, and Figure 31 show

the SVS-n timing diagrams. When the condition(s)

are met, the device changes the state of SVS-n from

asserted to released after a user-configurable delay

time. However, the transitions from released-state to

asserted-state are performed almost immediately with

minimal propagation delay. Figure 30 describes

relationship between threshold voltages (V_ITNand

V_HYSN) and SENSEm voltage; and all SVS-1, SVS-2,

SVS-3, and SVS-4 have the same behavior of

Figure 30.

t

NOTE: The TPS386000 or TPS386040 is shown here using

RESETn. The TPS386020 and TPS386060 use RESETn;

therefore, the diagram of RESETn should be read as RESETn with

the opposite polarity.

Figure 28. SVS-1 Timing Diagram

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VCC

0.9V

t

SENSE2

SENSE3

V_HYSN

V_ITN

t

RESET2

RESET3

t_D

t

NOTE: The TPS386000 or TPS386040 is shown here using

RESETn. The TPS386020 and TPS386060 use RESETn;

therefore, the diagram of RESETn should be read as RESETn with

the opposite polarity.

NOTE: The TPS386000 or TPS386040 is shown here using

RESETn. The TPS386020 and TPS386060 use RESETn;

therefore, the diagram of RESETn should be read as RESETn with

the opposite polarity.

Figure 29. SVS-2 Timing Diagram

Figure 30. SVS-3 Timing Diagram

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VCC

MR

t

0.9V

RESET1

t

SENSE4L

t

WDI

V_HYSN

V_ITN

t

(Internal timer)

Timeout

t_WDT

SENSE4H

Zero

V_ITP

V_HYSP

t

WDO

t

RESET4

NOTE: The TPS386000 or TPS386040 is shown here using

RESETn and WDO. The TPS386020 and TPS386060 use

RESETn and WDO; therefore, the diagrams of RESETn and WDO

should be read as RESETn and WDO with the opposite polarities.

Figure 32. WDT Timing Diagram

t_D

NOTE: The TPS386000 or TPS386040 is shown here using

RESETn. The TPS386020 and TPS386060 use RESETn;

therefore, the diagram of RESETn should be read as RESETn with

the opposite polarity.

Figure 31. SVS-4 Timing Diagram

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SENSE INPUT

WINDOW COMPARATOR

The SENSEm inputs are pins that allow any system

voltages to be monitored. If the voltage at the

SENSE1, SENSE2, SENSE3, or SENSE4L pins

drops below V_ITN, then the corresponding reset

outputs are asserted. If the voltage at the SENSE4H

pin exceeds V_ITP, then RESET4 or RESET4 is

asserted. The comparators have a built-in hysteresis

to ensure smooth reset output assertions and

deassertions. Although not required in most cases,

for extremely noise applications, it is good analog

design practice to place a 1nF to 10nF bypass

capacitor at the SENSEm input in order to reduce

sensitivity to transients, layout parasitics, and

interference between power rails monitored by this

device. A typical connection of resistor dividers are

shown in Figure 33. All the SENSEm pins can be

used to monitor voltage rails down to 0.4V. Threshold

voltages can be calculated by following equations:

The comparator at the SENSE4H pin has the

opposite comparison polarity to the other SENSEm

pins. In the configuration shown in Figure 33, this

comparator monitors overvoltage of the VCC4 node;

combined with the comparator at SENSE4L, SVS-4

forms a window comparator.

NEGATIVE VOLTAGE SENSING

By using voltage reference output VREF, the SVS-4

comparator can monitor negative voltage or positive

voltage lower than 0.4V. Figure 1 shows this usage in

an application circuit. SVS-4 monitors the positive

and negative voltage power rail (for example, +15V

and –15V supply to an op amp) and the RESET4 or

RESET4 output status continues to be as described

in Table 4. Note that R_S42His located at higher

voltage position than R_S42L. The threshold voltage

calculations are shown in the following equations:

VCC1_target = (1 + R_S1H/R_S1L) × 0.4 (V)

VCC2_target = (1 + R_S2H/R_S2L) × 0.4 (V)

VCC3_target = (1 + R_S3H/R_S3L) × 0.4 (V)

VCC4_target1 = {1+ R_S4H/(R_S4M+ R_S4L)} × 0.4 (V)

VCC4_target2 = {1+ (R_S4H+ R_S4M)/R_S4L} × 0.4 (V)

VCC41_target = (1 + R_S41H/R_S41L) × 0.4 (V)

VCC42_target = (1 + R_S42L/R_S42H) × 0.4 – R_S42L/R_S42H

V_REF

×

= 0.4 – R_S42L/R_S42H× 0.8 (V)

Where VCC4_target1 is the undervoltage threshold,

and VCC4_target2 is the overvoltage threshold.

Sequence: VIN

VCC4

VCC3

VCC2

VCC1

VIN

VCC4

DC-DC

LDO

VCC3

VCC2

VCC1

EN4 DC-DC

LDO

RP5 RP4 RP3 RP2 RP1

VCC

EN3 DC-DC

LDO

MR

VREF

VCC1 VCC2 VCC3 VCC4

WDI

WDO

RESET1

RESET2

RESET3

RESET4

DSP

CPU

FPGA

RS4H

RS3H

RS2H

RS1H

SENSE1

CLK

RESET

EN2 DC-DC

LDO

SENSE2

SENSE3

SENSE4L

TPS386000

SENSE4H

CT1

CT2

CT3

CT4

GND

RS4M

RS4L

CT1

RS3L

RS2L

RS1L

Figure 33. Typical Application Circuit (SVS-4: Window Comparator)

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RESET DELAY TIME

logic high and SENSE1 is above its reset threshold,

RESET1 or RESET1 is released after the

user-configured reset delay time. Note that unlike the

TPS3808 series, the TPS3860x0 does not integrate

an internal pull-up resistor between MR and VCC.

Each of the SVS-n channels can be configured

independently in one of three modes. Table 6

describes the delay time settings.

Table 6. Delay Timing Selection

To control the MR function from more than one logic

signal, the logic signals can be combined by

wired-OR into the MR pin using multiple NMOS

transistors and one pull-up resistor.

CTn CONNECTION

Pull-up to VCC

Open

DELAY TIME

300ms (typ)

20 ms (typ)

Capacitor to GND

Programmable

WATCHDOG TIMER

The TPS3860x0 provides a watchdog timer with a

dedicated watchdog error output, WDO or WDO. The

WDO or WDO output enables application board

designers to easily detect and resolve the hang-up

status of a processor. As with MR, the watchdog

timer function of the device is also tied to SVS-1.

Figure 32 shows the timing diagram of the WDT

function. Once RESET1 or RESET1 is released, the

internal watchdog timer starts its countdown. Inputting

a logic level transition at WDI resets the internal timer

count and the timer restarts the countdown. If the

TPS3860x0 fails to receive any WDI rising or falling

edge within the WDT period, the WDT times out and

asserts WDO or WDO. After WDO or WDO is

asserted, the device holds the status with the internal

latch circuit. To clear this timeout status, a reset

assertion of RESET1 or RESET is required. That is, a

negative pulse to MR, a SENSE1 voltage less than

V_ITN, or a VCC power-down is required.

To select the 300ms fixed delay time, the CTn pin

should be pulled up to VCC using a resistor from

40kΩ to 200kΩ. Please note that there is a pulldown

transistor from CTn to GND that turns on every time

the device powers on to determine and confirm CTn

pin status; therefore, a direct connection of CTn to

VCC causes a large current flow. To select the 20ms

fixed delay time, the CTn pin should be left open. To

program a user-defined adjustable delay time, an

external capacitor must be connected between CTn

and GND. The adjustable delay time can be

calculated by the following equation:

C_CT(nF) = [t_DELAY(ms) – 0.5(ms)] × 0.242

Using this equation, a delay time can be set to

between 1.4ms to 10s. The external capacitor should

be greater than 220pF (nominal) so that the

TPS3860x0 can distinguish it from an open CT pin.

The reset delay time is determined by the time it

takes an on-chip, precision 300nA current source to

charge the external capacitor to 1.24V. When the

RESETn or RESETn outputs are asserted, the

corresponding capacitors are discharged. When the

condition to release RESETn or RESETn occurs, the

internal current sources are enabled and begin to

charge the external capacitors. When the CTn

To reset the processor by WDT timeout, WDO can be

combined with RESET1 by using the wired-OR with

the TPS386000 option.

For legacy applications where the watchdog timer

timout causes RESET1 to assert, connect WDO to

MR; see Figure 33 for the connections and see

Figure 34 and Figure 35 for the timing diagram. This

legacy support configuration is available with the

TPS386000 and TPS386040.

voltage on

a

capacitor reaches 1.24V, the

corresponding RESETn or RESETn pins are

released. Note that a low leakage type capacitor

(such as ceramic) should be used, and that stray

capacitance around this pin may cause errors in the

reset delay time.

IMMUNITY TO SENSEn VOLTAGE

TRANSIENTS

The TPS3860x0 is relatively immune to short

negative transients on the SENSEn pin. Sensitivity to

transients depends on threshold overdrive, as shown

in the typical performance graph TPS386040

SENSEn Minimum Pulse Width vs SENSEn

Threshold Overdrive Voltage (Figure 12).

MANUAL RESET

The manual reset (MR) input allows external logic

signal from other processors, logic circuits, and/or

discrete sensors to initiate a device reset. Because

MR is connected to SVS-1, the RESET1 or RESET1

pin is intended to be connected to processor(s) as a

primary reset source. A logic low at MR causes

RESET1 or RESET1 to assert. After MR returns to a

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Event 1

Event 2

Event 3

WDI

Event 1

t

RESET1

t

MR = WDO

t_D

MR = WDO

t_WDT

(Internal timer)

NOTE: This configuration (connecting WDO and MR) is available

only with the TPS386000 and TPS386040.

NOTE: This configuration (connecting WDO and MR) is available

only with the TPS386000 and TPS386040.

Figure 34. Legacy WDT Configuration Timing

Diagram

Figure 35. Enlarged View of Event 1 from

Figure 34

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PACKAGE OPTION ADDENDUM

www.ti.com

28-Sep-2009

PACKAGING INFORMATION

Orderable Device

TPS386000RGPR

TPS386000RGPT

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

QFN

RGP

20

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

QFN

RGP

20

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TPS386020RGPR

TPS386020RGPT

TPS386040RGPR

PREVIEW

ACTIVE

QFN

RGP

20

3000

250

TBD

Call TI

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TPS386040RGPT

ACTIVE

QFN

RGP

20

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TPS386060RGPR

TPS386060RGPT

PREVIEW

QFN

RGP

20

3000

250

TBD

Call TI

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

25-Sep-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS386000RGPR

TPS386000RGPT

TPS386040RGPR

TPS386040RGPT

QFN

RGP

20

3000

250

330.0

180.0

330.0

180.0

12.4

4.25

1.15

8.0

12.0

Q2

3000

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

25-Sep-2009

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS386000RGPR

TPS386000RGPT

TPS386040RGPR

TPS386040RGPT

QFN

RGP

20

3000

250

346.0

190.5

346.0

190.5

346.0

212.7

346.0

212.7

29.0

31.8

29.0

31.8

3000

250

Pack Materials-Page 2

IMPORTANT NOTICE

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and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should provide

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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Amplifiers

Applications

Audio

Automotive

Broadband

Digital Control

Medical

Military

Optical Networking

Security

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

www.ti.com/audio

Data Converters

DLP® Products

DSP

Clocks and Timers

Interface

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/medical

www.ti.com/military

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

dsp.ti.com

www.ti.com/clocks

interface.ti.com

logic.ti.com

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

Logic

Power Mgmt

Microcontrollers

RFID

Telephony

Video & Imaging

Wireless

RF/IF and ZigBee® Solutions www.ti.com/lprf

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS386060RGPR
厂家：	TEXAS INSTRUMENTS
描述：	Quad Supply Voltage Supervisors with Programmable Delay and Watchdog Timer 四路电源电压监控器，具有可编程延迟和看门狗定时器监控
文件：	总28页 (文件大小：899K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS386060RGPR [TI]

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