TPS38700-Q1 [TI]
支持 I²C 和多达 12 个通道的汽车电源序列发生器;型号: | TPS38700-Q1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 支持 I²C 和多达 12 个通道的汽车电源序列发生器 |
文件: | 总78页 (文件大小:4407K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS38700-Q1
ZHCSQB8C –JULY 2021 –REVISED DECEMBER 2022
TPS38700-Q1 支持I2C 和多达12 个通道的电源序列发生器
• I2C 可编程序列
• RTC 时钟报警功能
1 特性
• 符合汽车应用要求
• 具有符合AEC-Q100 标准的下列特性:
2 应用
• 高级驾驶辅助系统(ADAS)
– 器件温度等级1:–40°C 至+125°C
– 器件HBM ESD 分类等级2
– 器件CDM ESD 分类等级C7B
• 符合功能安全标准
3 说明
TPS38700-Q1 器件是一款集成了窗口看门狗和可编程
I2C 的多通道电压序列发生器,采用 24 引脚 4mm x
4mm VQFN 封装。
– 专为功能安全应用开发
– 在发布量产版本时将会提供有助于进行ISO
26262 系统设计的文档
这种多通道电压序列发生器非常适合需要精确上电和/
或断电时序的系统,并且可以与多通道电压监控器连
接。该器件默认采用预编程的 OTP 选项,但 I2C 可对
上电和断电时序控制、看门狗设置和序列时序选项(如
需要)重新编程。
– 系统可满足ASIL D 级要求
– 硬件可满足ASIL B 要求
• 输入电压范围:2.2V 至5.5V
• 欠压锁定(UVLO):2.0V
• 低静态电流:35µA(典型值)
• 窗口看门狗
得益于灵活且可编程的电压轨时序功能、低静态电流和
小尺寸等优势,该器件能够满足大多数应用要求。
• 独立RESET
• 独立NIRQ
• NVM 误差校验
器件信息
封装(1)
封装尺寸(标称值)
器件型号
– 1 位误差校正
– 2 位错误检测
• 在寄存器映射上进行CRC 错误检查
• 备用电池
• 晶体振荡器选项
TPS38700-Q1
VQFN (24)
4mm x 4mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
Vo
BUCK1
BUCK5
EN6
EN1
EN5
EN
Vo
EN
Vo
BUCK6
EN2
BUCK2
EN
EN
Vo
Vo
BUCK7
EN8
BUCK3
EN7
EN3
EN
EN
Vo
EN4
Vo
BUCK8
EN
BUCK4
EN
Vo
SOC
CLK32K
SLEEP
NRST
VDD
EN12
EN11
XOUT
XIN
TPS38700-Q1
Voltage Monitor
NEM_PD
EN9
VDD
VBBAT
VDD
CLK32K
VDD
GND
GND
GND
GND
2
2
ACT
I2C
Safety
Micro
NIRQ
多通道电压序列发生器和监视器
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SNVSBT6
TPS38700-Q1
ZHCSQB8C –JULY 2021 –REVISED DECEMBER 2022
www.ti.com.cn
Table of Contents
8.3 Feature Description...................................................14
8.4 Register Map Table...................................................31
9 Application and Implementation..................................58
9.1 Application Information............................................. 58
9.2 Typical Application.................................................... 59
10 Power Supply Recommendations..............................63
10.1 Power Supply Guidelines........................................63
11 Layout...........................................................................64
11.1 Layout Guidelines................................................... 64
11.2 Layout Example...................................................... 64
12 Device and Documentation Support..........................65
12.1 Device Nomenclature..............................................65
12.2 Receiving Notification of Documentation Updates..66
12.3 支持资源..................................................................66
12.4 Trademarks.............................................................66
12.5 Electrostatic Discharge Caution..............................66
12.6 术语表..................................................................... 66
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison.........................................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................7
7.5 Electrical Characteristics.............................................7
7.6 Timing Requirements..................................................8
7.7 Typical Characteristics.............................................. 11
8 Detailed Description......................................................13
8.1 Overview...................................................................13
8.2 Functional Block Diagram.........................................13
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision B (October 2022) to Revision C (December 2022)
Page
• Updated Electrical Characteristics .....................................................................................................................7
• Added various orderables for I2C logic levels ................................................................................................... 7
Changes from Revision A (July 2021) to Revision B (October 2022)
Page
• 量产数据发布...................................................................................................................................................... 1
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5 Device Comparison
图 5-1 shows the device nomenclature of the TPS38700-Q1 device. See 表 12-2 for more information regarding
device ordering codes. Contact TI sales representatives or on TI's E2E forum for details and availability of other
options; minimum order quantities apply.
TPS 38700 X ZZZ RGE RQ1
Sequencer Channel Count
C: 11 channel sequencer
Ordering Code
ZZZ: Device Op on
Package
RGE: VQFN (24-pin)
图5-1. TPS38700-Q1 Device Nomenclature
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6 Pin Configuration and Functions
24
21 20 19
23 22
VBBAT
NIRQ
18
1
NRST
2
VDD
GND
17
16
15
14
13
SLEEP
3
GND
ACT
4
XIN
SCL
5
XOUT
CLK32K
SDA
6
10 11 12
7
9
8
图6-1. RGE Package
24-Pin VQFN
TPS38700-Q1 Top View
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表6-1. Pin Functions
PIN
TPS38700-Q1
NAME
I / O
DESCRIPTION
NO.
1
2
3
4
5
6
7
8
9
NIRQ
O
O
Interrupt Pin (open-drain, active-low)
Reset Pin (open-drain, active-low)
NRST
SLEEP
I
Sleep Pin (Logic high exits Sleep, logic low enters Sleep)
ACT pin (logic high starts power up SEQ, logic low starts power down SEQ)
I2C clock pin
ACT
I
SCL
I
SDA
I / O
O
I2C data pin
EN7 / GPO7
EN8 / GPO8
EN9 / GPO9
Enable 7 (open-drain / push-pull) / GPO7
Enable 8 (open-drain / push-pull) / GPO8
Enable 9 (open-drain/push-pull) / GPO9
Enable 10 (open-drain / push-pull) / Emergency Power Down (open-drain) / GPO10
Enable 11 (open-drain / push-pull) / Reset In (open-drain) / GPO11
Enable 12 (open-drain / push-pull) / Power Button (open-drain) / GPO12
32.768kHZ clock output
O
I / O
I / O
I / O
I / O
O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
EN10 / NEM_PD / GPO10
EN11 / NRST_IN / GPO11
EN12 / NPWR_BTN / GPO12
CLK32K
XOUT
O
Crystal oscillator output
XIN
I
Crystal oscillator input
GND
-
Ground
VDD
-
Power supply
VBBAT
-
Backup battery supply
EN1 / GPO1
EN2 / GPO2
EN3 / GPO3
EN4 / GPO4
EN5 / GPO5
EN6 / GPO6
O
Enable 1 (open-drain / push-pull) / GPO1
Enable 2 (open-drain / push-pull) / GPO2
Enable 3 (open-drain / push-pull) / GPO3
Enable 4 (open-drain / push-pull) / GPO4
Enable 5 (open-drain / push-pull) / GPO5
Enable 6 (open-drain / push-pull) / GPO6
O
O
O
O
O
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX UNIT
Voltage
Voltage
VDD, VBBAT
6
6
V
V
–0.3
NIRQ, NRST, SLEEP, ACT, ENx,
SDA, SCL
–0.3
Voltage
Voltage
Voltage
Voltage
NEM_PD, NRST_IN, NPWR_BTN
XIN, XOUT, CLK32K
-0.3
6
2
V
V
V
V
–0.3
SCL, SDA (OTP=1.2V, 1.8V)
SCL, SDA (OTP=3.3V, 5.0V)
Continuous total power dissipation
Operating junction temperature, TJ
Operating free-air temperature, TA
Storage temperature, Tstg
-0.3
2.2
5.5
-0.3
See the Thermal Information
-40
-40
-65
150
125
150
°C
°C
°C
Temperature (2)
(1) Stresses beyond values listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) As a result of the low dissipated power in this device, it is assumed that TJ = TA.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
Electrostatic
discharge
V(ESD)
All pins
V
Charged-device model (CDM), per AEC
Q100-011
Corner pins
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification
7.3 Recommended Operating Conditions
MIN
2.2
NOM
MAX
5.5
UNIT
V
VDD
Supply pin voltage
Battery back up
VBBAT
1.8
5.5
V
NIRQ, NRST,
ENx, SLEEP, Pin voltage
ACT
0
5.5
V
INRST, INIRQ, IE
Pin Currents
0
0
0
±1
2
mA
V
Nx
XIN, XOUT
CLK32K
Crystal pins
Clock output
2
V
NEM_PD,
NRST_IN,
NPWR_BTN
Pin voltage
0
5.5
V
SCL, SDA
SCL, SDA
RUP
Pin Voltage (OTP=3.3V, 5.0V)
0
0
5.5
2.0
V
V
Pin Voltage (OTP=1.2V, 1.8V)
Pull-up resistor (Open Drain configuration)
Junction temperature (free-air temperature)
10
-40
100
125
kΩ
℃
TJ
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7.4 Thermal Information
TPS38700x-Q1
THERMAL METRIC(1)
RGE (VQFN)
PINS
53.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
51.4
17.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ΨJT
20.7
ΨJB
RθJC(bot)
3.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
At 2.2 V ≤ VDD ≤5.5 V, NRST/NIRQ Voltage = 10 kΩto VDD, NRST/NIRQ load = 10 pF, and over the operating free-air
temperature range of –40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C, typical conditions at
VDD= 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Common Parameters
VDD
Input supply voltage
2.2
5.5
5.5
2.2
2
V
V
V
V
V
VBBAT
Backup battery voltage range
1.85
UVLO_VDDR UVLO VDD
Rising threshold
UVLO_VDDF UVLO VDD
Falling threshold/switch over to VBBAT
Falling threshold
1.90
UVLO_VBBAT UVLO Battery backup
1.85
Power ON reset voltage, all outputs
POR
IDD
guaranteed to be stable above this
value
Falling threshold
1.39
75
V
Supply current into VDD pin
ACT=High, SLEEP=High, RTC=active
VDD ≤5.5 V, power up sequence
complete
45
µA
µA
VDD ≤5.5 V ,power down sequence
complete
Supply current into VDD pin
ACT=Low, SLEEP=Low, RTC=active
IDD
35
35
60
IBBAT
Supply current from VBBAT
Output leakage current (NRST)
Output leakage current (NIRQ)
Logic Low input
60
300
300
0.36
µA
nA
nA
V
V
BBAT ≤5.5 V
ILKG_NRST
ILKG_NIRQ
ACT_L
VDD=VNRST = 5.5 V
VDD=VNIRQ = 5.5 V
VDD -
0.2
ACT_H
Logic high input
Logic Low input
Logic high input
0.84
0.84
V
V
V
SLEEP_L
SLEEP_H
0.36
VDD -
0.2
ACT
Internal Pull down
Internal Pull down
Output High
100
100
kΩ
kΩ
V
SLEEP
Push-Pull configuration, Io=1mA
VDD-0.2
ENx
Push-Pull or Open-Drain (10 kΩ pull
up)
Output Low
0.1
V
R_ENx
NRST
Enable Output resistance
Output Low
Push-Pull config
200
0.1
Ω
V
Open-Drain (10 kΩ pull up)
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7.5 Electrical Characteristics (continued)
At 2.2 V ≤ VDD ≤5.5 V, NRST/NIRQ Voltage = 10 kΩto VDD, NRST/NIRQ load = 10 pF, and over the operating free-air
temperature range of –40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C, typical conditions at
VDD= 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
NIRQ
Output Low
0.1
V
Open-Drain (10 kΩ pull up)
Open-Drain,4.7 kΩ pull up to 1.8V,
Leakage test
Output Low
100
0.1
nA
V
10pF capacitive load
CLK32K
Open-Drain, Io = -1mA, pull up to 1.8V,
10pF
capacitive load
Accuracy Early Boot
t < 50ms, VDD > VDDmin
t > 1s, VDD > VDDmin
-10
-100
-10
-5
10
100
10
%
ppm
%
Acc_CLK32K
Accuracy Operating
XTAL Fault
OSC
Crystal Frequency fault detection
Internal oscillator tolerance
Leakge current from VBBAT
Thermal Shutdown
5
%
Ilkg(BBAT)
TSD
VBBAT > 1.85V
300
nA
℃
165
25
TSD
Hysterisis
Thermal Shutdown Hysteresis
℃
VIH_ALT
VIL_ALT
NEM_PD, NRST_IN, NPWR_BTN
NEM_PD, NRST_IN, NPWR_BTN
Pin 10,11,12 Active Low, Open-Drain
Pin 10,11,12 Active Low, Open-Drain
1.1
V
V
0.36
I2C Electrical Specifications
CB
Capacitive load for SDA and SCL
400
pF
V
V
V
V
V
V
V
V
V
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA
Low Threshold, OTP = 1.2 V
High Threshold, OTP = 1.2 V
Low Threshold, OTP = 1.8 V
High Threshold, OTP = 1.8 V
Low Threshold, OTP = 3.3 V
Low Threshold, OTP = 3.3 V
Low Threshold, OTP = 5V
0.36
0.84
1.26
2.31
3.5
0.54
0.84
1.5
production variant
production variant
High Threshold, OTP = 5V
Output Low with 3 mA sink current
0.2
7.6 Timing Requirements
At 2 V ≤VDD ≤5.5 V, NIRQ/NRST Voltage = 10 kΩto VDD, NIRQ/NRST load = 10 pF, and over the operating free-air
temperature range of –40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C, typical conditions at VDD =
3.3 V.
MIN
NOM
MAX UNIT
Common parameters
From start of time
slot
tD_ENx
ENx toggle delay from start of time slot
CLK32K toggle delay from start of time slot
10
10
µs
µs
Hz
%
From start of time
slot
tD_CLK32K
Capacitive load =
12pF
F_CLK32K Frequency
32768
50
Capacitive load =
12pF
D_CLK32K Duty cycle
Trf_CLK32
40
60
Capacitive load =
12pF
50
1
ns
Rise and fall time of CLK32K (Rpullup = 4.7 kΩ)
K
tD_ENx,y
tNRST_EN
Delay between 2 subsequent EN in same time slot
ENx delay from NRST in Emergency Shutdown
µs
ns
Sequence 2 and 9
200
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7.6 Timing Requirements (continued)
At 2 V ≤VDD ≤5.5 V, NIRQ/NRST Voltage = 10 kΩto VDD, NIRQ/NRST load = 10 pF, and over the operating free-air
temperature range of –40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C, typical conditions at VDD =
3.3 V.
MIN
NOM
MAX UNIT
NRST assertion latency from falling edge of ACT pin below
VIL or falling edge of VDD pin below VDDmin
tD_NRST
tD_NIRQ
tBIST
25
25
15
µs
µs
Fault detection to NIRQ assertion latency
POR to ready with BIST
including OTP load
with ECC
ms
including OTP load
with ECC
tNo_BIST
POR to ready without BIST
2.5
12.5
50
ms
ms
ms
ms
BIST time
tStartup_CLK3
Clock 32k startup from UVLO at power ON
2K
Freq_fault Crystal frequency fault detection time
1
I2C Timing Characteristics
fSCL
Serial clock frequency (1)
Standard mode
Fast mode
100
400
1
kHz
kHz
MHz
µs
µs
µs
µs
µs
µs
ns
fSCL
Serial clock frequency (1)
fSCL
Serial clock frequency (1)
Fast mode +
Standard mode
Fast mode
tLOW
SCL low time (1)
4.7
1.3
0.5
4
tLOW
SCL low time (1)
tLOW
SCL low time (1)
Fast mode +
Standard mode
Fast Mode
tHIGH
SCL high time (1)
tHIGH
SCL high time (1)
1
tHIGH
SCL high time (1)
Fast mode +
Standard mode
Fast mode
0.26
250
100
50
tSU_DAT
tSU_DAT
tSU_DAT
tHD_DAT
tHD_DAT
tHD_DAT
tSU_STA
tSU_STA
tSU_STA
tHD_STA
tHD_STA
tHD_STA
tBUF
Data setup time (1)
Data setup time (1)
ns
Data setup time (1)
Fast mode +
Standard mode
Fast mode
ns
Data hold time (1)
10
3450
900
ns
Data hold time (1)
10
ns
Data hold time (1)
Fast mode +
Standard mode
Fast mode
10
ns
Setup time for a Start or Repeated Start condition (1)
Setup time for a Start or Repeated Start condition (1)
Setup time for a Start or Repeated Start condition (1)
Hold time for a Start or Repeated Start condition (1)
Hold time for a Start or Repeated Start condition (1)
Hold time for a Start or Repeated Start condition (1)
Bus free time between a STOP and START condition (1)
Bus free time between a STOP and START condition (1)
Bus free time between a STOP and START condition (1)
Setup time for a Stop condition (1)
Setup time for a Stop condition (1)
Setup time for a Stop condition (1)
Rise time of SDA signal (1)
4.7
0.6
0.26
4
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
Fast mode +
Standard mode
Fast mode
0.6
0.26
4.7
1.3
0.5
4
Fast mode +
Standard mode
Fast mode
tBUF
tBUF
Fast mode +
Standard mode
Fast mode
tSU_STO
tSU_STO
tSU_STO
trDA
0.6
0.26
Fast mode +
Standard mode
Fast mode
1000
300
120
300
300
trDA
Rise time of SDA signal (1)
20
ns
ns
ns
ns
trDA
Rise time of SDA signal (1)
Fast mode +
Standard mode
Fast mode
tfDA
Fall time of SDA signal (1)
tfDA
Fall time of SDA signal (1)
1.4
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7.6 Timing Requirements (continued)
At 2 V ≤VDD ≤5.5 V, NIRQ/NRST Voltage = 10 kΩto VDD, NIRQ/NRST load = 10 pF, and over the operating free-air
temperature range of –40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C, typical conditions at VDD =
3.3 V.
MIN
NOM
MAX UNIT
tfDA
trCL
trCL
trCL
tfCL
tfCL
tfCL
Fall time of SDA signal (1)
Rise time of SCL signal (1)
Rise time of SCL signal (1)
Rise time of SCL signal (1)
Fall time of SCL signal (1)
Fall time of SCL signal (1)
Fall time of SCL signal (1)
Fast mode +
Standard mode
Fast mode
6.5
120
1000
300
120
300
300
120
ns
ns
ns
ns
ns
ns
ns
20
Fast mode +
Standard mode
Fast mode
6.5
6.5
Fast mode +
Standard mode,
Fast mode and Fast
mode +
tSP
Pulse width of SCL and SDA spikes that are suppressed (1)
50
ns
(1) Guaranteed by design
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7.7 Typical Characteristics
At TA = 25°C, VDD = 3.3 V, and RPU = 10 kΩ, unless otherwise noted.
0.70
0.70
0.70
0.69
0.68
0.68
0.68
0.67
0.66
0.66
0.66
0.65
0.64
0.64
0.583
0.580
0.578
0.575
0.573
0.570
0.568
0.565
0.563
0.560
0.558
0.555
0.553
-60 -40 -20
0
20
40
60
80 100 120 140
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (oC)
Temperature (oC)
图7-2. ACT Logic Low Threshold Voltage vs. Temperature
图7-1. ACT Logic High Threshold Voltage vs. Temperature
46
41.5
39.5
37.5
35.5
33.5
31.5
29.5
27.5
44
42
40
38
36
34
32
-60 -40 -20
0
20
40
60
80 100 120 140
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (oC)
Temperature (oC)
图7-4. IDD Shutdown Current vs. Temperature
图7-3. IBBAT vs. Temperature
1.5528
1.552
0.705
0.700
0.695
0.690
0.685
0.680
0.675
0.670
0.665
0.660
0.655
0.650
0.645
0.640
1.5512
1.5504
1.5496
1.5488
1.548
1.5472
1.5464
1.5456
1.5448
1.544
-60
-30
0
30
60
90
120
150
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (oC)
Temperature (oC)
图7-5. VPOR vs. Temperature
图7-6. SLEEP Logic High Threshold Voltage vs. Temperature
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7.7 Typical Characteristics (continued)
At TA = 25°C, VDD = 3.3 V, and RPU = 10 kΩ, unless otherwise noted.
0.572
0.570
0.568
0.565
0.562
0.560
0.558
0.555
0.552
0.550
0.548
2.145
EN1
EN3
EN7
EN12
2.140
2.135
2.130
2.125
2.120
2.115
2.110
2.105
2.100
2.095
-60 -40 -20
0
20
40
60
80 100 120 140
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (oC)
Temperature (oC)
图7-7. SLEEP Logic Low Threshold Voltage vs. Temperature
图7-8. ENx Logic High Output Voltage vs. Temperature
0.012
EN1
0.012
EN3
EN7
EN12
0.011
0.010
0.010
0.010
0.009
0.008
0.008
0.008
0.007
0.007
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (oC)
图7-9. ENx Logic Low Output Voltage vs. Temperature
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8 Detailed Description
8.1 Overview
TPS38700-Q1 is a versatile part that can be configured for multiple configurations. The part can be ordered as a
pure sequencer, pure GPIO expander, or combination sequencer & GPIO outputs. The outputs can be factory
configured as push-pull or open-drain. Sequencing outputs can be assigned to ACT pin and/or SLEEP pin.
These sequencing outputs can be factory configured for default values and subsequently changed via I2C on
power-up before sending ACT pin high. The device also features a Built in Self-Test (BIST) function which runs
automatically on power up.
TPS38700-Q1 features a precise Real Time Clock (RTC) CLK32K output with the aide of an external crystal
(XTAL). It also has an RTC alarm feature and a window watchdog, all of which can be configured via I2C. The
TPS38700-Q1 is capable of various I2C logic levels. A full featured Graphical User Interface (GUI) is available
for download in the product folder. Contact a Texas Instruments representative for custom configured part
queries.
TPS38700-Q1 can be configured to have up to twelve channels and has an emergency power down (NEM_PD)
function that is activated once VDD falls below the UVLO threshold of the device. Once in the emergency power
down sequence, the TPS38700-Q1 will either turn off or enter into Backup state. If a voltage on VBBAT is present
and greater than 1.85 V, then the TPS38700-Q1 will enter into Backup state and the power supply for the device
will switch to VBBAT
.
The TPS38700-Q1 is AEC-Q100 qualified for automotive applications and has been characterized from
-40ºC to +125ºC.
8.2 Functional Block Diagram
EN1
VDD
Data Register
EN2
VBBAT
EN3
SCL
EN4
I2C Interface/
WDI/RTC
SDA
EN5
CLK32K
EN6
Sequence
XIN
Outputs
EN7
BIST/Crystal
XOUT
EN8
EN9
NRST
RESET Signal
NIRQ
NEM_PD
图8-1. TPS38700-Q1 Block Diagram
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8.3 Feature Description
8.3.1 Device State Diagram
The TPS38700-Q1 state diagrams shown in 图8-2 and 图8-3 show the flow of operation.
VDD>POR&UVLO
ACT=LOW
OFF
VDD<UVLO&
VBBATT<1.85
VDD<UVLO&
VBBATT>1.85
1
Fail
VBBATT<1.85
AT_POR
0
FAIL SAFE
FS
VDD>UVLO
BACKUP
Fail
BIST
ECC on OTP load
Pass
Pass
1
0
AT_SHDN
ACT=LOW
SHDN1
SHDN2
ACT si ng at Logic High
ACT=HIGH
00
SEQ2:
EMERGENCY
POWER
FORCE_SHDN=01
FORCE_SHDN=11
& RTC Alarm
SEQ1:
POWER UP
01/10/11
FORCE_SHDN
VDD<UVLO
DOWN
Set FORCE_ACT=1 &
FORCE_SHDN=0
FORCE_SHDN=10 &
1 second expired
ACT=LOW
SEQ5:
POWER
DOWN
ACTIVE
FORCE_SHDN=01/10/11
SLEEP=LOW&
FORCE_ACT=0
SEQ9:
FAILSAFE
POWER
DOWN
F_LDO=1
F_TSD=1
F_EN=1
FS
SEQ3:
SLEEP
ENTRY
SEQ4:
SLEEP EXIT
SLEEP=HIGH OR
FORCE_ACT=1
(RTC Alarm)
SEQ6:
POWER
DOWN
from
SLEEP
ACT=LOW
FORCE_SHDN=01/10/11
SLEEP
图8-2. TPS38700-Q1 State Diagram
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VDD>POR&UVLO
ACT=LOW
SLEEP=HIGH
VDD<UVLO
OFF
Fail
FAILSAFE
FS
Fail
BIST
ECC on OTP load
Pass
Pass
SHDN
ACT=HIGH
SEQ2:
EMERGENCY
POWER
DOWN
SEQ1:
POWER UP
VDD<UVLO
SEQ9:
FAILSAFE
POWER
DOWN
ACT=LOW
SEQ5:
POWER
DOWN
F_LDO=1
F_TSD=1
FS
ACTIVE
F_EN=1
图8-3. TPS38700-Q1 Simple Use Case
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8.3.2 Built-In Self Test and Configuration Load
Built-In Self Test (BIST) is performed:
• AT POR, if TEST_CFG_AT_POR = 1
• When exiting Sequence 5 or Sequence 6, if TEST_CFG_AT_SHDN = 1 and the power down is not initiated
by CTL_1. FORCE_SHDN[1:0] being set to 01b, 10b, or 11b.
Configuration load from OTP is assisted by ECC (supporting SEC-DED). This is to protect against data integrity
issues and to maximize sysetem availability.
During BIST, NIRQ is de-asserted (asserted in case of failure), NRST is held low, ENx pins are held low
(including pins with alternate functions), CLK32K is held low, input pins are ignored, and the I2C block is inactive
with SDA and SCL de-asserted. Once BIST is completed without failure, I2C is immediately active and the
device enters SHDN1 state after loading the configuration data from OTP. If BIST fails and/or ECC reports
Double-Error Detection (DED), NIRQ is asserted, the device enters the FAILSAFE state (inputs are ignored), and
a best effort attempt is made to active I2C. TEST_STAT register may provide additional information on the test
results.
8.3.3 CLK32K
The TPS38700-Q1 is designed to give an accurate CLK32K output and it is used internally for setting the RTC
time and alarms. TPS38700-Q1 is configured to be used with a 32.768 kHz crystal oscillator. To achieve a well-
defined frequency of oscillations, all crystals oscillators are tuned at specific capacitive load such as 6.5 pF, 12
pF, or 20 pF (during manufacturing stage), which becomes a part of the crystal specification. The task of a
designer is to design within the crystal's specifications to achieve the correct specified frequency.
For these crystal oscillators, the need for loading capacitors are required because the capacitive load is
effectively split between the output and input capacitance in a typical Pierce Oscillator scheme. These capacitors
are essentially connected in series with the crystal oscillator. Therefore, if a chosen crystal oscillator has a
capacitive load that is specified for 12.5 pF load, then the need for two 12.5 pF capacitors are required for proper
frequency output from the crystal oscillator.
The TPS38700-Q1 is configured to be used without the need of loading capacitors, as long as the 6.5 pF version
of the external crystal oscillator is selected. External crystal oscillators will typically specify their internal
capacitance such as 6.5 pF, 9 pF, 12.5 pF etc. If the external crystal oscillator has load capacitance specification
requirement not equal to 6.5 pF, please contact the TI factory for an OTP (one time programming) configuration
for the correct external capacitor loading.
The CLK32K signal can start as late as 50 ms from when the input voltage VDD exits out of UVLO. The
accuracy of CLK32K is within ±100 ppm after one second of initial operation. If the frequency of CLK32K
deviates for more than ±10%, a fault interrupt is asserted. The accuracy of the CLK32K will also depend on the
choice of external crystal oscillator and its temperature rating.
8.3.4 BACKUP State
In the BACKUP state only the battery is supplying power to the device, however the device must have gone
through a VDD supplied state (and loaded configuration data) in order to enter this state. If no VDD supplied
state has occurred, then the TPS38700-Q1 stays in the "OFF or Battery Installed" state, from which it will exit
only with a valid VDD supply.
When in BACKUP state, the TPS38700-Q1 pins are in the following state:
• ENx = Low (de-asserted)
• CLK32K = Low (output disabled)
• NRST = Low (asserted)
• ACT and SLEEP inputs are ignored.
Crystal oscillator and RTC remain active with Acc_CLK32K accuracy, but the crystal oscillator fault monitor is not
active. RTC_T[31:0], interrupt, and status registers are maintained and updated. Registers configuration is
maintained as set before entering the BACKUP state. PROT1 and PROT2 registers are cleared. All remaining
blocks are inactive.
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Upon exiting from the BACKUP state, the last configuration is active and the device enters the SHDN1 state.
8.3.5 FAILSAFE State
When in FAILSAFE state, ENx, CLK32K, NRST, NIRQ are all held Low, and a best effort attempt is made to
keep I2C active. ACT and SLEEP inputs are ignored.
In order to exit from FAILSAFE state, VDD has to be removed. Depending on VBBAT, the TPS38700-Q1 will enter
BACKUP or OFF state.
8.3.6 Transitioning Sequences
The sequences of the device are described here with timing diagrams showing the main signals involved in each
sequence.
8.3.6.1 Sequence 1: Power Up
When NPWR_BTN is not enabled, power-up is controlled by ACT, shown in 图8-4.
When ACT is high, the ENx output sequence starts and NRST is de-asserted RST_DLY[3:0] time after the last
ENx. The power-up sequence is defined by PWR_ENx registers, for more information see 表8-31.
ACT(in)
FORCE_ACT (bit)
FORCE_SHDN (bit)
ENx (out)
00b
Sequence defined by PWR_Enx and PWR_CLK32OE registers
CLK32K (out)
RST_DLY
NRST (out)
SHDN1
SEQUENCE 1
ACTIVE
TPS38700x-Q1 State
图8-4. Power Up with NPWR_BTN Disabled - ACT controlled
When NPWR_BTN is enabled, ACT is used as AUTO/BUTTON power-on strap option. With ACT strapped to
VDD, a short push on NPWR_BTN will start the power-up sequence; with ACT strapped to GND, the power-up
sequence will automatically start once VDD is valid. From SHDN2 state a short push on NPWR_BTN is always
required to start the power-up sequence. See 图 8-5 for details. When power-up is triggered, the ENx output
sequence starts and NRST is de-asserted CTL_2.RST_DLY[3:0] time after the last ENx.
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ACT(in)
NPWR_BTN (in)
ACT(in)
ACT high
NPWR_BTN triggers SEQUENCE 1
ACT low
NPWR_BTN (in)
VDD
AUTO POWER ON
VDD triggers SEQUENCE 1
Any ACT
ACT(in)
NPWR_BTN (in)
NPWR_BTN triggers SEQUENCE 1
FORCE_ACT (bit)
00b
FORCE_SHDN (bit)
ENx (out)
Sequence defined by PWR_Enx and PWR_CLK32OE registers
CLK32K (out)
NRST (out)
RST_DLY
TPS38700x-Q1 State
SHDNx
SEQUENCE 1
ACTIVE
图8-5. Power Up with NPWR_BTN Enabled
0 sec if FORCE_SHDN=01b
1 sec if FORCE_SHDN=10b
ACT(in)
RTC_WAKE if FORCE_SHDN=11b
FORCE_SHDN (bit)
ENx (out)
01/10/11b
00b
00b
Sequence defined by PWR_Enx and PWR_CLK32OE registers
CLK32K (out)
NRST (out)
RST_DLY
tNRST
ACTIVE
SLEEP
SEQUENCE 5
SEQUENCE 6
SHDN2
TPS38700x-Q1 State
SEQUENCE 1
ACTIVE
图8-6. Power Up from SHDN2 - Software Shutdown with FORCE_SHDN ≠00b
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8.3.6.2 Sequence 2: Emergency Power Down
In case of emergency power down (VDD drops below UVLO), a best effort approach is taken to assert NRST
before pulling ENx, CLK32K, and NIRQ down.
UVLOFALL
VDD
tNRST_EN
ENx (out)
CLK32K (out)
NIRQ (out)
NRST (out)
NRST could be asserted earlier (other system detection of power drop)
tNRST
TPS38700x-Q1 State
SEQUENCE 2
OFF/BACKUP
Any state
图8-7. Emergency Power Down
8.3.6.3 Sequence 3: Sleep Entry
Sleep entry is controlled by SLEEP going low. This triggers the ENx pins to de-assert as per the configuration in
SLP_ENx registers, 表 8-33 contains more information on SLP_ENx registers. See 图 8-8 for timing diagram
details.
ACT(in)
SLEEP (in)
FORCE_ACT (bit)
FORCE_SHDN (bit)
Sequence defined by SLP_Enx and SLP_CLK32OE registers
ENx (out)
CLK32K (out)
SEQUENCE 3
SLEEP
TPS38700x-Q1 State
ACTIVE
图8-8. Sleep Entry
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8.3.6.4 Sequence 4: Sleep Exit
Sleep exit is controlled by SLEEP going high or by FORCE_ACT being set to 1 by an RTC alarm. This triggers
the ENx pins to assert as per the configuration in SLP_ENx registers, consult 表 8-33 for more information on
SLP_ENx registers.
In case of RTC alarm wake, the host will see the interrupt and it will assert SLEEP and clear FORCE_ACT. See
图8-9, 图8-10, and 图8-11 for signal details.
SLEEP (in)
FORCE_ACT (bit)
NIRQ (out)
ACT(in)
FORCE_SHDN (bit)
Sequence defined by SLP_Enx and SLP_CLK32OE registers
ENx (out)
CLK32K (out)
TPS38700x-Q1 State
SLEEP
SEQUENCE 4
ACTIVE
图8-9. Sleep Exit SLEEP Triggered
RTC_T == RTC_A
RTC_T
INT_SRC1.RTC
INT_SRC1.RTC=1
I2C Wr
HOST I2C
I2C Rd
Host asserts SLEEP when detecting NIRQ
SLEEP (in)
FORCE_ACT (bit)
NIRQ (out)
ACT(in)
FORCE_SHDN (bit)
ENx (out)
Sequence defined by SLP_Enx and SLP_CLK32OE registers
CLK32K (out)
Sequence 4
TPS38700x-Q1 State
SLEEP
ACTIVE
图8-10. Sleep Exit RTC Triggered - SLEEP Sequencing
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RTC_T == RTC_A
RTC_T
INT_SRC1.RTC INT_SRC1.RTC=1 CTL_1.FORCE_ACT=0
I2C Rd I2C Wr I2C Wr
HOST I2C
SLEEP (in)
Host asserts SLEEP before clearing FORCE_ACT
FORCE_ACT (bit)
NIRQ (out)
ACT(in)
FORCE_SHDN (bit)
ENx (out)
Sequence defined by SLP_Enx and SLP_CLK32OE registers
CLK32K (out)
SEQUENCE 4
ACTIVE
TPS38700x-Q1 State
SLEEP
图8-11. Sleep Exit RTC Triggered - Autonomous Sequencing
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8.3.6.5 Sequence 5 & 6: Power Down from Active and Sleep States
The power-down sequence can be triggered as depicted in 图 8-12. In all cases, NRST is asserted in the first
sequencing slot, while ENx are de-asserted as per the configuration in PWR_ENx registers, see 表8-31. In case
of NPWR_BTN enabled, the "t long press" is determined as per register LP_TTSHLD shown in
表8-21.
Power-down from sleep differs from power-down from active as some ENx might be already de-asserted as part
of the sleep entry sequence. In the power-down from sleep sequence, the remaining ENx are de-asserted as per
the configuration in PWR_ENx registers.
ACT(in)
FORCE_SHDN (bit)
01/10/11b
NPWR_BTN (in)
NEM_PD (in)
ACT(in)
FORCE_SHDN (bit)
00b
NPWR_BTN (in)
NEM_PD (in)
0 or 1 (not changing)
ACT(in)
FORCE_SHDN (bit)
00b
> t long press
NPWR_BTN (in)
NEM_PD (in)
ACT(in)
FORCE_SHDN (bit)
00b
NPWR_BTN (in)
NEM_PD (in)
Sequence defined by PWR_Enx and PWR_CLK32OE registers
ENx (out)
CLK32K (out)
NRST (out)
tNRST
ACTIVE
SLEEP
SEQUENCE 5
SEQUENCE 6
SHDN2
TPS38700x-Q1 State
图8-12. Power Down from Active and Sleep
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8.3.6.6 Sequence 7: Sleep Exit Due to NRST_IN
If NRST_IN pin is enabled, it may be asserted while TPS38700-Q1 is in SLEEP state. To ensure proper power
state synchronization with the rest of the system, TPS38700-Q1 will assert NRST while executing the Sleep exit
sequence. The NRST signal is de-asserted when both RST_DLY delay time has passed since last ENx, and the
NRST_IN signal is de-asserted (or the connected button is released).
It should be noted that although not depicted in the TPS38700-Q1 State Diagram, 图 8-2, for clarity, this
sequence applies also in case of WDT-initiated reset.
ACT(in)
SLEEP (in)
NRST_IN (in)
Host asserts SLEEP when receiving NRST
FORCE_ACT (bit)
FORCE_SHDN (bit)
00b
Sequence defined by SLP_Enx and SLP_CLK32OE registers
ENx (out)
CLK32K (out)
NRST (out)
RST_DLY
SEQUENCE 7
ACTIVE
TPS38700x-Q1 State
SLEEP
图8-13. Sleep Exit due to NRST_IN
8.3.6.7 Sequence 8: RESET Due to NRST_IN
It is noted that although not depicted in the TPS38700-Q1 State Diagram,图 8-2, for clarity, this sequence
applies also in case of WDT-initiated reset.
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ACT(in)
NRST_IN (in)
FORCE_ACT (bit)
FORCE_SHDN (bit)
00b
ENx (out)
CLK32K (out)
NRST (out)
No Change
RST_DLY
TPS38700x-Q1 State
ACTIVE
SEQUENCE 8
ACTIVE
图8-14. RESET due to NRST_IN
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8.3.6.8 Sequence 9: Failsafe Power Down
F_TSD and F_LDO faults will cause the TPS38700-Q1 to move to FAILSAFE State. The transition to FAILSAFE
State is essentially the same as Sequence 2, with the trigger being the fault instead of the loss of VDD. A best
effort approach is taken to assert NRST before pulling ENx, CLK32K, and NIRQ down.
F_TSD or F_LDO
tNRST_EN
ENx (out)
CLK32K (out)
NIRQ (out)
NRST (out)
tNRST
TPS38700x-Q1 State
Any state
SEQUENCE 9
FAILSAFE
图8-15. Failsafe Power Down
8.3.6.9 Output Sequencing
Output sequencing can be triggered by hardware or software through ACT, SLEEP, RTC wake, FORCE_SHDN,
NPWR_BTN (if enabled), NEM_PD (if enabled), and NRST_IN (if enabled).
Such events start sequencing the outputs (ENx and CLK32K) according to the settings in registers 表 8-27, 表
8-30, 表8-31, 表8-32, 表8-33, and 表8-34.
In those registers, Slot 1 is the earliest slot that can be selected and it indicates that the ENx (or CLK32K) will
toggle in the first time slot after the triggering event. The example timing diagram in 图 8-16 shows the time
delays specified in 节7.6 .
ACT(in)
EN1 (out)
EN2 (out)
EN3 (out)
RST_DLY
CLK32K (out)
tSL_EN
tSL_EN
tSL_EN
NRST
Slot 2
Slot 3
Slot 1
Time Slot
tslot1
tEN_EN
图8-16. Output Sequencing Example
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8.3.7 I2C
Refer to 表 8-1 for the I2C register map overview. Note that "PSEQ" refers to TPS38700-Q1 and is used
enhance table readability.
表8-1. I2C Register Categories and Associated Details
WHO ELSE
CAN WRITE AFFECTED DUE
TO THEM?
None
WHAT GETS
RANGE / FUNCTION WHO TOGGLES
TYPE
BITS
DESCRIPTION
OR STATUS
THEM?
TO THIS BIT?
None
VENDORID[7:0]
MODEL_REV[7:0]
TARGET_ID[7:0]
TI defined
TI defined
TI defined
TI defined
TI defined
TI defined
OTP option
OTP option
OTP option
OTP bits R
None
None
None
I2C
Any of the
interrupts
generated;
Can be
No internal fault /
Internal fault detected
F_INTERR
Internal fault
Interrupt
NIRQ
cleared by
writing 1
No emergency PD /
shutdown caused by
emergency PD
Emergency Power
down
EM_PD (1)
WDT
PSEQ
PSEQ; SOC
WD; SOC
NRST; NIRQ
NIRQ; NRST
(depends on if set
in configuration
register)
Watchdog violation Did not occur / occurred
Watchdog
Packet Error
checking (PEC)
PEC miscompare did not
occur / occurred
F_PEC
RTC
I2C
I2C; SOC
RTC; SOC
PSEQ; SOC
NIRQ
NIRQ
has not triggered /
triggered
RTC alarm
RTC
Enable output pin
fault
No faults detected / fault EN readback-
F_EN
NIRQ; NRST
detected
PSEQ
Interrupt info
bits RW1C
Frequency
detector;
SOC
No faults detected / fault
detected
Frequency
detector
F_OSC
Crystal oscillator fault
NIRQ
Reset or Interrupt pin No faults detected / fault Reset readback-
F_NRSTIRQ
F_BIST
PSEQ; SOC
BIST; SOC
BIST; SOC
TSD; SOC
SOC
NIRQ
fault
detected
PSEQ
No faults detected / fault
detected
Built-In self test fault
BIST
NIRQ; NRST
NIRQ; NRST
NIRQ; NRST
NIRQ
No faults detected / fault
detected
F_LDO
LDO fault
BIST
TSD
CRC
Thermal shutdown No faults detected / fault
F_TSD
fault
detected
Runtime CRC
register fault
No faults detected / fault
detected
F_RT_CRC
ECC double error
deduction on OTP
load
NVM_ECC;
REG_CRC;
SOC
No ECC DED / ECC
DED on OTP load
NVM_ECC;
REG_CRC
F_ECC_DED
F_PBSB (1)
NIRQ; NRST
NRST; NIRQ
NPWR_BTN short
press
No short pulse / short
pulse
PSEQ
PSEQ; SOC
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TYPE
表8-1. I2C Register Categories and Associated Details (continued)
WHO ELSE
WHAT GETS
CAN WRITE AFFECTED DUE
RANGE / FUNCTION WHO TOGGLES
BITS
DESCRIPTION
OR STATUS
THEM?
TO THEM?
TO THIS BIT?
Current state of
NIRQ output
NIRQ asserted / not
asserted
ST_NIRQ
ST_NRST
Interrupt
None
None
Interrupt;
NRSTstate
change
Current state of
NRST output
NRST asserted / not
asserted
None
None
Current state of
SLEEP input
SLEEP pin driven Low
or High
ST_ACTSLP
PSEQ
PSEQ
None
None
None
None
Current state of ACT ACT pin driven Low or
ST_ACTSHDN
input
High
SHDNx, Power Up,
Power Down, Sleep,
Sleep entry, Sleep exit,
invalid, Active
Current state of
PSEQ
ST_PSEQ[1:0]
PSEQ
None
None
Current drive state of Sequencer is driving EN
EN12 to EN9 Low or High
STDR1
STDR2
OPEN
PSEQ
PSEQ
WD
None
None
None
None
None
None
None
None
None
None
Current drive state of Sequencer is driving EN
EN8 to EN1
Low or High
Watchdog Open
Window
Watchdog update
Window closed / open
Status bits
R
Watchdog Update
Violation
No violation / WD
updated too early
WDUV
WDEXP
WD
Watchdog close timer
expired
WDT not expired /
expired
WD
BIST not complete or
executed / BIST
complete
BIST_C
ECC_SEC
BIST_VM
BIST state
BIST
None
None
None
None
None
None
Status of ECC single
error correction
No error correction
applied / SEC applied
NVM_ECC
REG_CRC
Status of volatile
memory test output
from BIST
Volatile memory test
pass / fail
Status of non-volatile
memory test output
from BIST
Non-Volatile memory
test pass / fail
BIST_NVM
OTP covered
None
None
Status of Logic test
ouput from BIST
BIST_L
BIST_A
Logic test pass / fail
Analog test pass / fail
Disabled/ Enabled
BIST
None
None
None
None
None
None
None
None
NIRQ/ NRST
NIRQ/ NRST
PSEQ
Status of Analog test
ouput from BIST
BIST
Enable AF for EN12,
EN11, EN10, EN9
EN_AF[12:9]
AFIO[12:9]
PP_EN[12:1]
XTAL_LOAD
XTAL_EN
OTP option
OTP option
OTP option
OTP option
OTP option
OTP option
Select AF for EN12,
EN11, EN10, EN9
GPO or NPWR_BTN /
NRST_IN/ NEM_PD
PSEQ
ENx pin driver
configuration
Open drain/ Push-Pull
External/ Internal
IO
OTP bits R
Crystal oscillator load
capacitance
XTAL
Crystal oscillator
Enable
Crystal driver disabled/
enabled
XTAL
CLK32K pin driver
configuration
PP_CLK32K
Open drain/ Push-Pull
XTAL
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表8-1. I2C Register Categories and Associated Details (continued)
WHO ELSE
CAN WRITE AFFECTED DUE
TO THEM?
WHAT GETS
RANGE / FUNCTION WHO TOGGLES
TYPE
BITS
DESCRIPTION
OR STATUS
Open drain / Push-Pull
5 ms to 80 ms
THEM?
SOC
TO THIS BIT?
General purpose
input / outputs
GPIO[12:9]
Debounce[3:0]
None
PSEQ
Debounce value for
AF input pins
SOC
None
None
None
PSEQ
PSEQ
PSEQ
Enable debounce for
AF input pins
Debouce disabled /
enabled
EN_DEB[12:9]
SOC
NPWR_BTN long
press time threshold
LP_TIME_TSHLD[7:0]
100 ms to 25.6 s
SOC
Reload or do not Reload
when SEQ5 / 6 is
complete
RELOAD
Reload OTP
SOC
SOC
SOC
SOC
OTP Register
NRST
NIRQ contolled by
faults / register
FORCE_INT
FORCE_ACT
Force NIRQ low
SOC can
clear it; but
not set it
Force PSEQ Active SLEEP pin controls exit /
PSEQ
PSEQ
state
entry or is ignored
CONTROL
R/W
ACT pin control or Force
SHDN and resume ACT
pin control after delay
Force PSEQ
Shutdown state
FORCE_SHDN[1:0]
SOC
SOC; WDT
PSEQ
RST_DLY[3:0]
RTC_WAKE
Reset Delay
0.1 ms to 128 ms
Disabled / Enabled
SOC
SOC
None
None
PSEQ
RTC
Autonomous wake
alarm enable
Autonomous RTC
power up from
SHDN2 to ACTIVE
RTC_PU
Disabled / Enabled
SOC
SOC
None
None
RTC
I2C
Require PEC byte (if Missing PEC is treated
REQ_PEC
EN_PEC = 1)
as good / bad
Packet Error
checking (PEC)
EN_PEC
AT_POR
AT_SHDN
PEC disabled / enabled
Skip / run BIST at POR
Default to not run BIST
SOC
SOC
SOC
None
None
None
I2C
Run BIST at POR
BIST
BIST
Run BIST when
exiting SEQ5 / 6
Power Up / Sleep
Exit time slots
USLOT[3:0]
SOC
None
PSEQ
125 μs / 2.5 s
Power down / Sleep
Entry time slots
DSLOT[3:0]
SSTEP
SOC
SOC
SOC
None
None
None
PSEQ
PSEQ
PSEQ
125 μs / 2.5 s
Slot step multiplier
250 μs / 1000 μs
ENx not mapped / ENx
mapped
PU[3:0][12:1]
Power Up Sequence
PSEQ
Power Down
Sequence
ENx not mapped / ENx
mapped
PD[3:0][12:1]
SOC
SOC
SOC
None
None
None
PSEQ
PSEQ
PSEQ
ENx not mapped / ENx
mapped
SLP_EXT[3:0][12:1] Sleep Exit Sequence
SLP_ENTRY[3:0]
[12:1]
Sleep Entry
Sequence
ENx not mapped / ENx
mapped
XTAL; internal
oscillator
RTC_T[31:0]
RTC_A[31:0]
RTC time setting
RTC alarm setting
1 sec to 136 years
1 sec to 136 years
None
None
RTC
RTC
RTC (2)
SOC
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TYPE
表8-1. I2C Register Categories and Associated Details (continued)
WHO ELSE
WHAT GETS
CAN WRITE AFFECTED DUE
RANGE / FUNCTION WHO TOGGLES
BITS
DESCRIPTION
OR STATUS
THEM?
SOC
TO THEM?
TO THIS BIT?
Watchdog
configuration
WDT_EN[1:0]
SLP_EN
Disabled / Enabled
None
WDT
Automatic disable in
Sleep mode
Watchdog disabled /
enabled in Sleep
SOC
None
None
WDT
WDT
Delay in number of
Watchdog periods
WDT_DLY[2:0]
1 or 8 WDT period
Value written to
SOC
Power down mode
WDT
PDMD[1:0]
CLOSE[7:0]
for WDT force power CTL_1.FORCE_SHDN
SOC
SOC
None
None
PSEQ
WDT
down
on WDT power down
WDT close window
configuration
1 ms to 864 ms
WDT open window
configuration
OPEN[7:0]
KEY[7:0]
1 ms to 864 ms
0 / 1
SOC
SOC
None
None
WDT
WDT
WDT key to reset
Write function to
those register
groups
WRK
SEQS
SEQP
SEQC
Work set register lock
0 / 1
0 / 1
0 / 1
0 / 1
SOC only 1
SOC only 1
SOC only 1
SOC only 1
None
None
None
None
Write function to
those register
groups
SEQS set register
lock
Write function to
those register
groups
SEQP set register
lock
PROT
Write function to
those register
groups
SEQC set register
lock
Write function to
those reg groups
WDT
RTC
CTL
WDT set register lock
RTC set register lock
CTL set register lock
0 / 1
0 / 1
0 / 1
SOC only 1
SOC only 1
SOC only 1
None
None
None
Write function to
those reg groups
Write function to
those reg groups
(1) Presence of fault reporting functionality dependent on part configuration.
(2) Register RTC_T must be written to before writing a value in register RTC_A.
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From I2C Principal to I2C Agent
From I2C Agent to I2C Principal
Data Byte to Register
Device(Agent) Address
Register Address
R7 R6 R5 R4 R3 R2 R1 R0
S
A6 A5 A4 A3 A2 A1 A0
0
A
A
D7 D6 D5 D4 D3 D2 D1 D0
A
P
START
ACK
ACK
STOP
‘0’(write)ACK
图8-17. I2C Single Byte Write
From I2C Principal to I2C Agent
From I2C Agent to I2C Principal
Register Address
R7 R6 R5 R4 R3 R2 R1 R0
Data Byte from Register
Device(Agent) Address
Device(Agent) Address
S
A6 A5 A4 A3 A2 A1 A0
0
A
A
Sr A6 A5 A4 A3 A2 A1 A0
1
A
D7 D6 D5 D4 D3 D2 D1 D0 NA
P
START
‘0’(writeA) CK
ACK
Repeated Start
NACK
STOP
‘1’(read)ACK
图8-18. I2C Single Byte Read
From I2C Principal to I2C Agent
Device(Agent) Address
From I2C Agent to I2C Principal
Data Byte to Register
D7 D6 D5 D4 D3 D2 D1 D0
Data Byte to Register
Register Address
R7 R6 R5 R4 R3 R2 R1 R0
S
A6 A5 A4 A3 A2 A1 A0
0
A
A
A
D7 D6 D5 D4 D3 D2 D1 D0
A
P
START
‘0’(writeA) CK
ACK
ACK
ACK STOP
图8-19. I2C Sequencial Write
From I2C Principal to I2C Agent
From I2C Agent to I2C Principal
Data Byte from Register
Device(Agent) Address
Data Byte from Register
D7 D6 D5 D4 D3 D2 D1 D0
Device(Agent) Address
Register Address
S
A6 A5 A4 A3 A2 A1 A0
0
A
R7 R6 R5 R4 R3 R2 R1 R0
A
Sr A6 A5 A4 A3 A2 A1 A0
1
A
A
D7 D6 D5 D4 D3 D2 D1 D0 NA
P
START
‘0’(writeA)CK
ACK Repeated Start
NACK
‘1’(readA) CK
ACK
STOP
图8-20. I2C Sequential Read
From I2C Principal to I2C Agent
Device(Agent) Address
From I2C Agent to I2C Principal
Register Address
Data Byte to Register
PEC Byte
S
A6 A5 A4 A3 A2 A1 A0
0
A
R7 R6 R5 R4 R3 R2 R1 R0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
P
START
‘0’(write)ACK
ACK
ACK
ACK STOP
图8-21. I2C Single Byte Write with PEC
From I2C Principal to I2C Agent
Device(Agent) Address
From I2C Agent to I2C Principal
Register Address
R7 R6 R5 R4 R3 R2 R1 R0
Device(Agent) Address
Data Byte from Register
D7 D6 D5 D4 D3 D2 D1 D0
PEC Byte
S
A6 A5 A4 A3 A2 A1 A0
0
A
A
Sr A6 A5 A4 A3 A2 A1 A0
1
A
A
D7 D6 D5 D4 D3 D2 D1 D0 NA
P
ACK
‘0’(write)
ACK Repeated Start
START
‘1’(read)
ACK
ACK
NACK STOP
图8-22. I2C Single Byte Read with PEC
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8.4 Register Map Table
表8-2. Register Map Table
RSVD = Reserved
ADDR
NAME
R/W
MSB
6
5
4
3
2
1
LSB
DEFAULT
GROUP
0x00 - 0x0F: Vendor info and vendor usage registers
Vendor ID (Bits 0-2)
0x00
0x01
Model Rev
Revision
RSVD
R
R
Device Model (Bits 3-7)
Silicon_Rev
OTP_Rev
Vendor defined or other IC information
0x02 …
0x0F
0x10 - 0x1F: Interrupts and Status registers
0x10
0x11
0x12
0x13
INT_SRC1
INT_SRC2
RW1C F_INTERNAL
EM_PD
RSVD
WDT
F_PEC
F_BIST
RTC
F_EN
F_OSC
F_NRSTIRQ
F_PBSP
0x00
0x00
0x00
0x00
RW1C
RW1C
R
F_VENDOR
RSVD
F_RT_CRC
F_LDO
F_TSD
F_ECC_DED
INT_VENDOR
CTL_STAT
Vendor specific internal fault flags
ST_VBBAT
ST_NIRQ
ST_NRST
ST_ACTSLP ST_ACTSHD
N
ST_PSEQ[1:0]
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
EN_STDR1
EN_STDR2
EN_STRD1
EN_STRD2
WDT_STAT
TEST_STAT
LAST_RST
R
R
R
R
R
R
R
RSVD
STDR_EN8 STDR_EN7 STDR_EN6 STDR_EN5 STDR_EN4 STDR_EN3 STDR_EN2 STDR_EN1
RSVD STRD_EN12 STRD_EN11 STRD_EN10 STRD_EN9
STRD_EN8 STRD_EN7 STRD_EN6 STRD_EN5 STRD_EN4 STRD_EN3 STRD_EN2 STRD_EN1
STDR_EN12 STDR_EN11 STDR_EN10 STDR_EN9
0x00
0x00
0x00
0x00
0x00
0x00
0x00
RSVD
ECC_SEC
OPEN
RSVD
WDUV
BIST_L
WDEXP
BIST_A
RSVD
BIST_C
RSVD
BIST_VM
BIST_NVM
NRST_IN
WDT_RST LP_NPWR_B
TN
NEM_PD
ACTSHDN WDT_SHDN
FORCE_SHDN[1:0]
RSVD
RSVD
0x1B …
0x1F
0x20 - 0x2F: Configuration registers
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
EN_ALT_F
AF_IN_OUT
EN_CFG1
EN_CFG2
CLK_CFG
GP_OUT
R
R
RSVD
RSVD
RSVD
EN_AF12
EN_AF11
AFIO11
EN_AF10
EN_AF9
AFIO9
NVM
NVM
NVM
NVM
NVM
NVM
NVM
NVM
NVM
AFIO12
PP_EN12
PP_EN4
AFIO10
PP_EN10
PP_EN2
R
PP_EN11
PP_EN3
PP_EN9
PP_EN1
R
PP_EN8
PP_EN7
PP_EN6
RSVD
PP_EN5
R
XTAL_LOAD
XTAL_EN
PP_CLK32K
RSVD
R/W
R/W
R/W
R/W
RSVD
GPO12
GPO11
GPO10
GPO9
RSVD
WRK
CTL
DEB_IN
DEBOUNCE[3:0]
EN_DEB12
EN_DEB11
EN_DEB10
LP_TTSHLD
CTL_1
LP_TIME_TSHLD[7:0]
FORCE_INT FORCE_ACT
CTL
RSVD
FORCE_SHDN[1:0]
WRK
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表8-2. Register Map Table (continued)
RSVD = Reserved
ADDR
NAME
R/W
R/W
R/W
R/W
MSB
6
5
4
3
2
1
LSB
DEFAULT
NVM
GROUP
CTL
0x29
CTL_2
RST_DLY[3:0]
RSVD
RTC_WAKE
RTC_PU
AT_SHDN
REQ_PEC
EN_PEC
0x2A
0x2B
TEST_CFG
IEN_VENDOR
RSVD
AT_POR[1:0]
NCM
CTL
Vendor specifc internal fault enables
RSVD
NVM
CTL
0x2C …
0x2F
0x30 - 0x6F: Sequencing registers
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
SEQ_CFG
SEQ_USLOT
SEQ_DSLOT
PWR_EN1
PWR_EN2
PWR_EN3
PWR_EN4
PWR_EN5
PWR_EN6
PWR_EN7
PWR_EN8
PWR_EN9
PWR_EN10
PWR_EN11
PWR_EN12
PWR_CLK32OE
RSVD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RSVD
SSTEP
NVM
NVM
NVM
NVM
NVM
NVM
NVM
NVM
NVM
NVM
NVM
NVM
NVM
NVM
NVM
NVM
SEQC
SEQC
SEQC
SEQP
SEQP
SEQP
SEQP
SEQP
SEQP
SEQP
SEQP
SEQP
SEQP
SEQP
SEQP
SEQP
TIME[7:0]
TIME[7:0]
PU[3:0]
PU[3:0]
PU[3:0]
PU[3:0]
PU[3:0]
PU[3:0]
PU[3:0]
PU[3:0]
PU[3:0]
PU[3:0]
PU[3:0]
PU[3:0]
PU[3:0]
PD[3:0]
PD[3:0]
PD[3:0]
PD[3:0]
PD[3:0]
PD[3:0]
PD[3:0]
PD[3:0]
PD[3:0]
PD[3:0]
PD[3:0]
PD[3:0]
PD[3:0]
RSVD
RSVD
0x40 …
0x4F
RSVD
0x50 …
0x52
0x53
0x54
0x55
0x56
0x57
0x58
SLP_EN1
SLP_EN2
SLP_EN3
SLP_EN4
SLP_EN5
SLP_EN6
R/W
R/W
R/W
R/W
R/W
R/W
SLP_EXIT[3:0]
SLP_EXIT[3:0]
SLP_EXIT[3:0]
SLP_EXIT[3:0]
SLP_EXIT[3:0]
SLP_EXIT[3:0]
SLP_ENTRY[3:0]
SLP_ENTRY[3:0]
SLP_ENTRY[3:0]
SLP_ENTRY[3:0]
SLP_ENTRY[3:0]
SLP_ENTRY[3:0]
NVM
NVM
NVM
NVM
NVM
NVM
SEQS
SEQS
SEQS
SEQS
SEQS
SEQS
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表8-2. Register Map Table (continued)
RSVD = Reserved
ADDR
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
NAME
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MSB
6
5
4
3
2
1
LSB
DEFAULT
NVM
GROUP
SEQS
SEQS
SEQS
SEQS
SEQS
SEQS
SEQS
SLP_EN7
SLP_EN8
SLP_EXIT[3:0]
SLP_ENTRY[3:0]
SLP_ENTRY[3:0]
SLP_ENTRY[3:0]
SLP_ENTRY[3:0]
SLP_ENTRY[3:0]
SLP_ENTRY[3:0]
SLP_ENTRY[3:0]
SLP_EXIT[3:0]
SLP_EXIT[3:0]
SLP_EXIT[3:0]
SLP_EXIT[3:0]
SLP_EXIT[3:0]
SLP_EXIT[3:0]
NVM
SLP_EN9
NVM
SLP_EN10
SLP_EN11
SLP_EN12
SLP_CLK32OE
RSVD
NVM
NVM
NVM
NVM
RSVD
0x60 …
0x6F
0x70 - 0x7F: Real Time Clock (RTC) registers
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
RTC_T3
RTC_T2
RTC_T1
RTC_T0
RTC_A3
RTC_A2
RTC_A1
RTC_A0
RSVD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RTC_T[31:24]
RTC_T[23:16]
RTC_T[15:8]
RTC_T[7:0]
RTC_A[31:24]
RTC_A[23:16]
RTC_A[15:8]
RTC_A[7:0]
RSVD
0x00
0x00
0x00
0x00
0xFF
0xFF
0xFF
0xFF
RTC
RTC
RTC
RTC
RTC
RTC
RTC
RTC
0x78 …
0x7F
0x80 - 0x8F: Watchdog Timer (WDT) registers
0x80
0x81
0x82
0x83
WDT_CFG
WDT_CLOSE
WDT_OPEN
WDTKEY
R/W
R/W
R/W
R/W
WDTEN[1:0]
SLP_EN
WDTDLY[2:0]
PDMD[1:0]
0x00
0x00
0x00
0x00
WDT
WDT
WDT
None
CLOSE[7:0]
OPEN[7:0]
KEY[7:0]
RSVD
RSVD
0x84 …
0x8F
Unused
Unused
0x90 …
0xEF
0xF0 - 0xFF: Protection registers
0xF0
0xF1
PROT1
PROT2
R/W
R/W
RSVD
RSVD
WRK
WRK
SEQS
SEQS
SEQP
SEQP
SEQC
SEQC
WDT
WDT
RTC
RTC
CTL
CTL
0x00
0x00
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GROUP
表8-2. Register Map Table (continued)
RSVD = Reserved
ADDR
NAME
R/W
MSB
6
5
4
3
2
1
LSB
DEFAULT
RSVD
RSVD
0xF2 …
0xF8
0xF9
0xFA
I2CADDR
DEV_CFG
RSVD
R
R
RSVD
ADDR_NVM[6:0]
NVM
NVM
RSVD
SOC_IF[1:0]
RSVD
0xFB …
0xFF
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8.4.1 Register Descriptions
表8-3. INT_SRC1
Address: 0x10
Description: Interrupt Source register. If F_INTERNAL, then INT_SRC2 register provides further information.
POR Value: 0x00
Access: Read and write 1 to clear. Writing 0 has no effect; writing 1 to a bit which is already at 0 has no effect.
Back to Register Map Table.
BIT
NAME
DESCRIPTION
7
F_INTERNAL
Internal Fault (ORed value of all bits in INT_SRC2): 0 = No internal fault detected
1 = Internal fault detected. Further detail flagged in INT_SRC2. This bit is cleared by
clearing the bits in INT_SRC2.
6
EM_PD
Emergency Power Down:
0 = No emergency power-down event
1 = Shutdown caused by emergency power-down (Sequence 2).
Write-1-to-clear will clear the bit. The bit will be set again on next emergency power-
down.
5
4
WDT
PEC
0 = WDT violation did not occur (or WDT_CFG.WDTEN[1:0] = 00b). 1 = WDT violation
occurred.
This bit is valid only if WDT_CFG.WDTEN[1:0] is enabled.
Write-1-to-clear will clear the bit. The bit will be set again on next WDT violation.
Packet Error Checking:
0 = PEC miscompare has not occurred (or CTL_2.EN_PEC = 0). 1 = PEC miscompare
has occurred.
This bit is valid only if CTL_2.EN_PEC is enabled.
Write-1-to-clear will clear the bit. The bit will be set again on next PEC miscompare.
3
RTC
0 = RTC alarm has not triggered (or alarm function is disabled). 1 = RTC alarm has
triggered.
This bit is invalid if the alarm function is disabled (CTL_2.RTC_WAKE and
CTL_2.RTC_PU are both clear, and RTC_A[31:0] is set to 0xFFFFFFFF.)
Write-1-to-clear will clear the bit. The bit will be set again on next RTC alarm.
2
1
F_EN
Enable Output Pin Fault:
0 = No short to supply or ground detected. 1 = Short to supply or ground detected.
Write-1-to-clear will clear the bit only if the fault condition is also removed.
F_OSC
Crystal Oscillator Fault:
0 = No fault detected on Crystal Oscillator (or CLK_CFG.XTAL_EN = 0, disabled). 1 =
Fault detected on Crystal Oscillator.
Write-1-to-clear will clear the bit only if the fault condition is also removed.
0
F_NRSTIRQ
Reset or Interrupt Pin Fault:
0 = No fault detected on NRST or NIRQ.
1 = Low resistance path to supply detected on either NRST or NIRQ.
Write-1-to-clear will clear the bit only if the fault condition is also removed.
INT_SRC1 represents the reason that NIRQ was asserted. When the host processor receives NIRQ, it may read
this register to quickly determine the source of the interrupt. If this register is clear, then TPS38700-Q1 did not
assert NIRQ.
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表8-4. INT_SRC2
Address: 0x11
Description: Interrupt Source register for internal errors.
POR Value: 0x00
Access: Read and write 1 to clear. Writing 0 has no effect; writing 1 to a bit which is already at 0 has no effect.
Back to Register Map Table.
BIT
NAME
DESCRIPTION
7
F_VENDOR
Vendor specific internal fault. Details reported in INT_VENDOR. This bit represents the
ORed value of all bits in INT_VENDOR.
0 = No fault reported in INT_VENDOR 1 = Fault reported in INT_VENDOR
This bit is cleared by clearing the bits in INT_VENDOR.
6
5
RSVD
Reserved
F_RT_CRC
Runtime register CRC Fault:
0 = No fault detected.
1 = Register CRC fault detected.
Write-1-to-clear will clear the bit. The bit will be set again during next register CRC
check if a fault is detected.
4
3
F_BIST
F_LDO
Built-In Self Test Fault:
0 = No fault detected.
1 = BIST fault detected.
Note that clearing this bit does not clear the results in TEST_STAT register.
Write-1-to-clear will clear the bit. The bit will be set again during next BIST execution if
a fault is detected.
LDO Fault:
0 = No LDO fault detected. 1 = LDO fault detected.
If internal LDO is used, this flag is to indicate fault.
If internal LDO is not used, this flag must be reserved.
Write-1-to-clear will clear the bit only if the fault condition is also removed.
2
1
0
F_TSD
F_ECC_DED
F_PBSP
Thermal Shutdown:
0 = No thermal shutdown.
1 = Thermal shutdown occurred since last read.
Write-1-to-clear will clear the bit only if the fault condition is also removed.
ECC Double-Error Detection on OTP configuration load:
0 = No ECC-DED on OTP load. 1 = ECC-DED on OTP load.
Write-1-to-clear will clear the bit. The bit will be set again during next OTP configuration
load if a fault is detected.
NPWR_BTN Short Pulse:
0 = No short pulse on NPWR_BTN (or NPWR_BTN is not enabled). 1 = Short pulse
detected on NPWR_BTN.
This bit is valid only if NPWR_BTN is enabled through EN_AF12 and AFIO12 bits.
Write-1-to-clear will clear the bit. The bit will be set again during next short pulse
detected on NPWR_BTN.
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表8-5. INT_VENDOR
Address: 0x12
Description: Vendor Specific Internal Interrupt Status register.
POR Value: 0x00
Access: Read and write 1 to clear. Writing 0 has no effect; writing 1 to a bit which is already at 0 has no effect.
Back to Register Map Table.
BIT
NAME
DESCRIPTION
7:0
FAULTS[7:0]
Vendor specific internal faults flags.
表8-6. CTL_STAT
Address: 0x13
Description: TPS38700-Q1 Status register for control pins and internal state.
POR Value: 0x00
Access: Read only.
Back to Register Map Table.
BIT
7:6
5
NAME
RSVD
DESCRIPTION
Reserved
ST_NIRQ
Current state of NIRQ Output:
0 = NIRQ pin asserted low by TPS38700-Q1.
1 = NIRQ pin not asserted low by TPS38700-Q1.
4
3
ST_NRST
ST_ACTSLP
ST_ACTSHDN
ST_PSEQ[1:0]
Current state of NRST Output:
0 = NRST pin asserted low by TPS38700-Q1.
1 = NRST pin not asserted low by TPS38700-Q1.
Current state of SLEEP input:
0 = SLEEP pin driven low (Sleep) by system. 1 = SLEEP pin driven high (Active) by
system.
2
Current state of ACT input:
0 = ACT pin driven low (Shutdown) by system. 1 = ACT pin driven high (Active) by
system.
1:0
00b: SHDNx, Power Up, Power Down
01b: SLEEP, Sleep Entry, Sleep Exit
10b: Invalid combination
11b: ACTIVE
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表8-7. EN_STDR1
Address: 0x14
Description: Current drive status of Enable Pins.
POR Value: 0x00
Access: Read only.
Back to Register Map Table.
BIT
7:4
3:0
NAME
RSVD
DESCRIPTION
Reserved
STDR_EN[12:9]
Current drive state of EN[X]:
0 = TPS38700-Q1 is driving EN[X] Low.
1 = TPS38700-Q1 is driving or allowing to float EN[X] High
表8-8. EN_STDR2
Address: 0x15
Description: Current drive status of Enable Pins.
POR Value: 0x00
Access: Read only.
Back to Register Map Table.
BIT
NAME
DESCRIPTION
7:0
STDR_EN[8:1]
Current drive state of EN[X]:
0 = TPS38700-Q1 is driving EN[X] Low.
1 = TPS38700-Q1 is driving or allowing to float EN[X] High
表8-9. EN_STRD1
Address: 0x16
Description: Current read status of Enable Pins.
POR Value: 0x00
Access: Read only.
Back to Register Map Table.
BIT
7:4
3:0
NAME
RSVD
DESCRIPTION
Reserved
STRD_EN[12:9]
Current read state of EN[X]:
0 = TPS38700-Q1 is reading EN[X] Low.
1 = TPS38700-Q1 is reading EN[X] High
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表8-10. EN_STRD2
Address: 0x17
Description: Current read status of Enable Pins.
POR Value: 0x00
Access: Read only.
Back to Register Map Table.
BIT
NAME
DESCRIPTION
7:0
STRD_EN[8:1]
Current read state of EN[X]:
0 = TPS38700-Q1 is reading EN[X] Low.
1 = TPS38700-Q1 is reading EN[X] High
表8-11. WDT_STAT
Address: 0x18
Description: WDT status register.
POR Value: 0x00
Access: Read only.
Back to Register Map Table.
BIT
NAME
RSVD
OPEN
DESCRIPTION
7:4
3
Reserved
Watchdog Open Window:
0 = Watchdog update window closed.
1 = Watchdog update window open.
2
1
RSVD
WDUV
Reserved
Watchdog Update Violation. Clear on read.
0 = No violation detected.
1 = Watchdog updated too early.
0
WDEXP
Watchdog close timer expired without update to WDKEY. Clear on read.
0 = WDT Not Expired.
1 = WDT Expired.
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表8-12. TEST_STAT
Address: 0x19
Description: Internal Self-Test and ECC status register.
POR Value: 0x00
Access: Read only.
Back to Register Map Table.
BIT
NAME
RSVD
DESCRIPTION
Reserved
7
6
BIST_C
BIST state:
0 = BIST running or not executed since last POR. Check also
TEST_CFG register.
1 = BIST complete.
5
ECC_SEC
Status of ECC Single-Error Correction on OTP configuration load.
0 = no error correction applied.
1 = Single-Error Correction applied.
4
3
RSVD
Reserved
BIST_VM
Status of Volatile Memory test output from BIST.
0 = Volatile Memory test pass.
1 = Volatile Memory test fail.
2
1
0
BIST_NVM
BIST_L
Status of Non-Volatile Memory test output from BIST.
0 = Non-Volatile Memory test pass.
1 = Non-Volatile Memory test fail.
Status of Logic test output from BIST.
0 = Logic test pass.
1 = Logic test fail.
BIST_A
Status of Analog test output from BIST.
0 = Analog test pass.
1 = Analog test fail.
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表8-13. LAST_RST
Address: 0x1A
Description: Reason of last NRST assertion or shutdown. NRST assertion and shutdown occur in Sequence 2,
Sequence 5, Sequence 6, Sequence 7, and Sequence 8.
The register is maintained as long as VDD and/or VBBAT is present. An emergency shutdown triggering
Sequence 2 is already recorded in INT_SRC1.EM_PD register bit, so it does not need to be stored in this
register. The host is expected to read this register as part of the first actions taken upon power ON.
The register is overwritten with new relevant data on next NRST assertion or shutdown.
POR Value: 0x00
Access: Read Only.
Back to Register Map Table.
BIT
NAME
DESCRIPTION
7
NRST_IN
NRST assertion due to NRST_IN (if enabled in EN_ALT_F and
AF_IN_OUT registers).
0 = Last NRST assertion was not due to NRST_IN.
1 = Last NRST assertion was due to NRST_IN.
6
WDT_RST
NRST assertion due to WDT (see also 表8-37).
0 = Last NSRT assertion was not due to WDT.
1 = Last NSRT assertion was due to WDT.
5
4
RSVD
Reserved
NEM_PD
NRST/Shutdown due to NEM_PD (if enabled in EN_ALT_F and
AF_IN_OUT registers).
0 = Last NRST/Shutdown assertion was not due to NEM_PD.
1 = Last NRST/Shutdown assertion was due to NEM_PD.
3
2
ACTSHDN
NRST/Shutdown due to ACT asserted Low (shutdown).
0 = Last NRST/Shutdown assertion was not due to ACT Low.
1 = Last NRST/Shutdown assertion was due to ACT Low.
WDT_SHDN
NRST/Shutdown due to WDT (see also 表8-37).
0 = Last NRST/Shutdown assertion was not due to ACT/ SHDN
Low.
1 = Last NRST/Shutdown assertion was due to ACT/ SHDN Low.
If this bit is set, LAST_RST.FORCE_SHDN[1:0] contains
WDT_CFG.PDMD[1:0] value.
1:0
FORCE_SHDN[1:0]
NRST/Shutdown due to CTL_1.FORCE_SHDN[1:0] ≠00b.
Value is the same as CTL_1.FORCE_SHDN[1:0] that initiated the
last NRST/Shutdown. If WDT_SHDN bit is set, this bitfield contains
WDT_CFG.PDMD[1:0] value.
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表8-14. EN_ALT_F
Address: 0x20
Description: Enable Alternate Function for sequencing pins EN[12:9] (AF is selected in AF_IN_OUT register).
POR Value: Loaded from NVM
Access: Read only once loaded from NVM
Back to Register Map Table.
BIT
7:4
3
NAME
RSVD
DESCRIPTION
Reserved
EN_AF12
Enable alternate function of EN[12]:
0 = Disabled.
1 = AF Enabled (GPO12 or NPWR_BTN).
2
1
0
EN_AF11
EN_AF10
EN_AF9
Enable alternate function of EN[11]:
0 = Disabled.
1 = AF Enabled (GPO11 or NRST_IN).
Enable alternate function of EN[10]:
0 = Disabled.
1 = AF Enabled (GPO10 or NEM_PD).
Enable alternate function of EN[9]:
0 = Disabled.
1 = AF Enabled (GPO9).
The alternate function can be enabled only if the corresponding PU/ PD/ SLP_EXIT/ SLP_ENTRY registers
fields are all set to 0. If any of those bit fields are non-zero, the corresponding pin is locked to EN[X] sequencing
function.
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表8-15. AF_IN_OUT
Address: 0x21
Description: Select Alternate Function for sequencing pins EN[12:9] (AF is enabled in EN_ALT_F register).
POR Value: Loaded from NVM.
Access: Read only once loaded from NVM.
Back to Register Map Table.
BIT
7:4
3
NAME
RSVD
DESCRIPTION
Reserved
AFIO12
Select alternate function of EN12:
0 = General Purpose Output (GPO) - GPO12.
1 = AF NPWR_BTN (power button input).
2
1
0
AFIO11
AFIO10
AFIO9
Select alternate function of EN11:
0 = GPO11.
1 = AF NRST_IN (reset input).
Select alternate function of EN10:
0 = GPO10.
1 = AF NEM_PD (emergency power-down input).
Select alternate function of EN9:
0 = GPO9.
1 = Invalid.
EN9 can only be selected as GPO9 through
EN_ALT_F.EN_AF9, and does not have an al- ternate function.
Therefore, this bit is always read-only and should always read
0.
表8-16. EN_CFG1
Address: 0x22
Description: Drive mode configuration for EN[12:9]
POR Value: Loaded from NVM.
Access: Read only once loaded from NVM
Back to Register Map Table.
BIT
7:4
3:0
NAME
RSVD
DESCRIPTION
Reserved
PP_EN[12:9]
ENx pin driver configuration:
0 = Open drain.
1 = Push pull.
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表8-17. EN_CFG2
Address: 0x23
Description: Drive mode configuration for EN[8:1].
POR Value: Loaded from NVM.
Access: Read only once loaded from NVM.
Back to Register Map Table.
BIT
NAME
DESCRIPTION
ENx pin driver configuration:
7:0
PP_EN[8:1]
0 = Open drain.
1 = Push pull.
表8-18. CLK_CFG
Address: 0x24
Description: Oscillator configuration.
POR Value: Loaded from NVM.
Access: Read only once loaded from NVM.
Back to Register Map Table.
BIT
NAME
DESCRIPTION
7
XTAL_LOAD
Crystal oscillator load capacitance:
0 = external.
1 = internal (value specified by the vendor).
6
XTAL_EN
Crystal oscillator enable:
0 = Crystal driver disabled.
1 = Crystal driver enabled.
5
4
RSVD
Reserved
PP_CLK32K
CLK32K pin driver configuration:
0 = Open drain.
1 = Push pull.
Note that Push-Pull configuration for CLK32K output is
optional and not a requirement.
3:0
RSVD
Reserved
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表8-19. GP_OUT
Address: 0x25
Description: Set General Purpose Output state for sequencing pins EN[12:9]. GPO is enabled through
AF_IN_OUT and EN_ALT_F registers.
POR Value: Loaded from NVM.
Access: Read/Write. Read-only if CTL group is protected.
Back to Register Map Table.
BIT
7:4
3
NAME
RSVD
DESCRIPTION
Reserved
GPO12
EN12 General Purpose Output. Only used when both
PWR_EN12 and SLP_EN12 are clear.
0 = EN12 pin driven low.
1 = EN12 pin driven high.
2
1
0
GPO11
GPO10
GPO9
EN11 General Purpose Output. Only used when both
PWR_EN11 and SLP_EN11 are clear.
0 = EN11 pin driven low.
1 = EN11 pin driven high.
EN10 General Purpose Output. Only used when both
PWR_EN10 and SLP_EN10 are clear.
0 = EN10 pin driven low.
1 = EN10 pin driven high.
EN9 General Purpose Output. Only used when both
PWR_EN9 and SLP_EN9 are clear.
0 = EN9 pin driven low.
1 = EN9 pin driven high.
表8-20. DEB_IN
Address: 0x26
Description: Debounce configuration for AF input pins.
POR Value: Loaded from NVM.
Access: Read/Write. Read-only if CTL group is protected.
Back to Register Map Table.
BIT
NAME
DESCRIPTION
7:4
DEBOUNCE[3:0]
Debounce value for AF input pins:
0000b = 5 ms
0001b = 10 ms
0010b = 15 ms
0011b = 20 ms
nnnnb = 5(N+1) ms
1111b = 80 ms
3:1
0
EN_DEB[12:10]
RSVD
Enable debounce for AF input pins:
0 = debounce disabled.
1 = debounce enabled.
Reserved
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表8-21. LP_TTSHLD
Address: 0x27
Description: NPWR_BTN Long Press time threshold configuration.
POR Value: Loaded from NVM.
Access: Read/Write. Read-only if CTL group is protected.
Back to Register Map Table.
BIT
NAME
DESCRIPTION
7:0
LP_TIME_TSHLD
If NPWR_BTN is enabled, this value, in 100 ms
increments, determines the minimum duration of the
NPWR_BTN pulse to be detected as "Long Press"
(shorter is detected as "Short Press")
00h = 100 ms
01h = 200 ms
...
FEh = 25.5 s
FFh = 25.6 s
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表8-22. CTL_1
Address: 0x28
Description: Interrupt and State SW control.
POR Value: Loaded from NVM.
Access: Read/Write. Read-only if CTL group is protected.
Back to Register Map Table.
BIT
7:4
3
NAME
RSVD
DESCRIPTION
Reserved
FORCE_INT (1)
Force NIRQ low:
0 = NIRQ pin controlled by INT_SRCx register faults.
1 = NIRQ pin forced low.
2
FORCE_ACT (2)
Force TPS38700-Q1 active state:
0 (cleared only by I2C writes) = SLEEP pin controls
sleep entry/ exit.
1 (set only by HW) = SLEEP is ignored.
1:0
FORCE_SHDN[1:0]
Force TPS38700-Q1 to shutdown state.
With NPWR_BTN disabled (EN_ALT_F.EN_AF12 = 0):
00b = Normal ACT pin control.
01b = Force power-down sequence, then resume
normal ACT pin control immediately.
10b = Force power-down sequence, then resume
normal ACT pin control after 1 second delay.
11b = Force power-down sequence, then resume
normal ACT pin control when ACT = Low or when
RTC alarm occurs as per configuration in registers
CTL_2, RTC_T, and RTC_A.
With NPWR_BTN enabled (EN_ALT_F.EN_AF12 = 1):
00b = Normal NPWR_BTN pin control.
01b = Force power-down sequence, then move to
Sequence 1 immediately (proceed as if ACT = High).
10b = Force power-down sequence, then move to
Sequence 1 after 1 second (proceed as if ACT =
High). If NPWR_BTN is pressed before 1 second
expires, then the TPS38700-Q1 will move to
Sequence 1 at that time.
11b = Force power-down sequence, then move to
Sequence 1 when RTC alarm occurs as per
configuration in registers CTL_2, RTC_T, and RTC_A
(proceed as if
ACT = High). If NPWR_BTN is pressed before the
RTC alarm, then the TPS38700-Q1 will move to
Sequence 1 at that time.
(1) FORCE_INT is used by software for periodic check for internal or external short to VDD on NIRQ pin.
(2) FORCE_ACT is automatically set by HW when entering the Power Up sequence (SEQUENCE 1). As the TPS38700-Q1 performs the
power-up sequence, ACT may be undefined. FORCE_ACT being set prevents a bad ACT level from causing a transition directly into
SLEEP before the application processor has booted. I2C commands are allowed to clear this bit but not set it.
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表8-23. CTL_2
Address: 0x29
Description: Miscellaneous configuration.
POR Value: Loaded from NVM.
Access: Read/Write. Read-only if CTL group is protected.
Back to Register Map Table.
BIT
NAME
DESCRIPTION
7:4
RST_DLY[3:0]
Power up sequence: NRST remains asserted until RST_DLY[3:0] after
last ENx assert.
0000b = 0.1 ms
0001b = 0.2 ms
0010b = 0.4 ms
0011b = 0.8 ms
0100b = 1.6 ms
0101b = 3.2 ms
0110b = 6.4 ms
0111b = 12.8 ms
1000b = 1 ms
1001b = 2 ms
1010b = 4 ms
1011b = 8 ms
1100b = 16 ms
1101b = 32 ms
1110b = 64 ms
1111b = 128 ms
Power down sequence: NRST asserted within tNRST of ACT= Low.
3
RTC_WAKE
Autonomous RTC wake alarm enable:
0 = Disabled (CTL_1.FORCE_ACT = 0 on RTC alarm).
1 = Enabled (CTL_1.FORCE_ACT = 1 on RTC alarm).
If RTC_T == RTC_A, a wake event is generated which sets
INT_SRC1.RTC.
If this bit is enabled, then also CTL_1.FORCE_ACT is set to 1, triggering
the automatic exit from SLEEP state to ACTIVE.
2
RTC_PU
Autonomous RTC Power Up from SHDN2 to ACTIVE:
0 = Disabled.
1 = Enabled.
If RTC_T == RTC_A, a power-up event is generated.
1
0
REQ_PEC
EN_PEC
Require PEC byte (valid only if EN_PEC is 1):
0 = missing PEC byte is treated as good PEC.
1 = missing PEC byte is treated as bad PEC, triggering a fault.
Packet Error Checking (PEC):
0 = PEC disabled (Default).
1 = PEC Enabled. Disables support for register address auto-increment.
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表8-24. TEST_CFG
Address: 0x2A
Description: Built-In Self Test (BIST) execution configuration.
Default: Loaded from NVM (only AT_POR[1:0])
Access: Read/Write. Read-only if CTL group is protected.
Back to Register Map Table.
BIT
7:3
2
NAME
DESCRIPTION
RSVD
Reserved
AT_SHDN
0 = Do not run BIST when exiting Sequence 5 or
Sequence 6.
1 = Run BIST when exiting Sequence 5 or Sequence
6 if CTL_1.FORCE_SHDN[1:0] = 00b.
Device ready after tCFG_WB
.
This bit cannot be set in OTP.
Always defaults to 0 when loading configuration from
OTP.
1:0
AT_POR[1:0]
Run BIST at POR. Device ready after tCFG_WB.
00b = Valid OTP configuration, skip BIST at POR
01b = Corrupt OTP configuration, run BIST at POR.
10b = Corrupt OTP configuration, run BIST at POR.
11b = Valid OTP configuration, run BIST at POR.
表8-25. IEN_VENDOR
Address: 0x2B
Description: Vendor Specific Internal Interrupt Enable register.
POR Value: 0x00 or load from NVM.
Access: Read/Write. Read-only if CTL group is protected.
Back to Register Map Table.
BIT
NAME
DESCRIPTION
7:0
FAULTS[7:0]
Vendor specific internal faults enables.
表8-26. SEQ_CFG
Address: 0x30
Description: Sequencing configuration.
POR Value: Loaded from NVM.
Access: Read/Write. Read-only if SEQ group is protected.
Back to Register Map Table.
BIT
7:1
0
NAME
RSVD
DESCRIPTION
Reserved
SSTEP
Sequencing time slot step size selection for
SEQ_USLOT and SEQ_DSLOT:
0 = Time slot step size tSSTEP = 250 μs
1 = Time slot step size tSSTEP= 1000 μs
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表8-27. SEQ_USLOT
Address: 0x31
Description: Power Up / Sleep Exit sequencing time slot configuration.
POR Value: Loaded from NVM.
Access: Read/Write. Read only if SEQ group is protected.
Back to Register Map Table.
BIT
NAME
DESCRIPTION
7:0
TIME[7:0]
Sets time slot between sequencing points on power-up /
sleep-exit:
tUSLOT = SEQ_USLOT.TIME[7:0] × tSSTEP + tSMIN
with tSSTEP set by SEQ_CFG.SSTEP and tSMIN = tSSTEP/2
For the case where SEQ_CFG.SSTEP = 0, refer to 表
8-28.
For the case where SEQ_CFG.SSTEP = 1, refer to 表
8-29.
表8-28. SEQ_CFG.SSTEP = 0
PARAMETER
Slot step size
SYMBOL
tSSTEP
tSMIN
MIN (-6%)
TYPICAL
MAX (+6%)
265
UNIT
μs
235
250
Min slot time (0x00)
Max slot time (0xFF)
117.5
125
132.5
μs
tSMAX
60042.5
63875
67707.5
μs
表8-29. SEQ_CFG.SSTEP = 1
PARAMETER
Slot step size
SYMBOL
tSSTEP
tSMIN
MIN (-6%)
TYPICAL
MAX (+6%)
1060
UNIT
μs
940
1000
Min slot time (0x00)
Max slot time (0xFF)
470
500
530
μs
tSMAX
240170
255500
270830
μs
表8-30. SEQ_DSLOT
Address: 0x32
Description: Power Down / Sleep Entry sequencing time slot configuration.
POR Value: Loaded from NVM.
Access: Read/Write. Read-only if SEQ group is protected.
Back to Register Map Table.
BIT
NAME
DESCRIPTION
7:0
TIME[7:0]
Sets time slot between sequencing points on power-down /
sleep-entry:
tDSLOT = SEQ_DSLOT.TIME[7:0] × tSSTEP + tSMIN
with tSSTEP set by SEQ_CFG.SSTEP and tSMIN = tSSTEP/2
See 表8-27 for setting details.
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表8-31. PWR_EN[12:1]
Address: PWR_EN1 (0x33) - PWR_EN12 (0x3E) (Twelve 8-bit registers).
Description: Power Up/ Down sequence definition by assignment of EN[12:1] to one of fifteen time slots.
Slot=1 is the earliest slot that can be selected and it indicates that the ENx pin will toggle in the first
SEQ_USLOT.TIME or SEQ_DSLOT.TIME after the triggering event. See 节8.3.6.9.
POR Value: Loaded from NVM.
Access: Read/Write. Read-only if SEQ group is protected.
Back to Register Map Table.
BIT
NAME
DESCRIPTION
7:4
PU[3:0]
Power Up Sequence:
0 = ENx pin not mapped to sequence. ENx maintains
previous state, unless entering BACKUP or FAILSAFE
state (ENx is pulled low in those states).
1 = ENx pin mapped to first time slot (first up).
15 = ENx pin mapped to last time slot (last up).
3:0
PD[3:0]
Power Down Sequence:
0 = ENx pin not mapped to sequence. ENx maintains
previous state, unless entering BACKUP or FAILSAFE
state (ENx is pulled low in those states).
1 = ENx pin mapped to first time slot (first down).
15 = ENx pin mapped to last time slot (last down).
表8-32. PWR_CLK32OE
Address: 0x3Fh
Description: Power Up/ Down (PU/ PD) sequence assignment of 32 kHz clock output to one of fifteen time slots.
POR Value: Loaded from NVM.
Access: Read/Write. Read-only if SEQ group is protected.
Back to Register Map Table.
BIT
NAME
DESCRIPTION
7:4
PU[3:0]
0 = CLK32 not mapped to PU sequence. CLK32 maintains
previous state, unless entering BACKUP or FAILSAFE state
(CLK32 is pulled low in those states).
1 = Enable CLK32 on first PU time slot.
15 = Enable CLK32 on last PU time slot.
3:0
PD[3:0]
0 = CLK32 not mapped to PD sequence. CLK32 maintains
previous state, unless entering BACKUP or FAILSAFE state
(CLK32 is pulled low in those states).
1 = Disable CLK32 on first PD time slot.
15 = Disable CLK32 on last PD time slot.
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表8-33. SLP_EN[12:1]
Address: SLP_EN1 (0x53) - SLP_EN12 (0x5E) (Twelve 8-bit registers).
Description: Sleep Exit/Entry sequence definition by assignment of EN[12:1] to one of fifteen time slots.
Slot=1 is the earliest slot that can be selected and it indicates that the ENx pin will toggle in the first
SEQ_USLOT.TIME or SEQ_DSLOT.TIME after the triggering event. See 节8.3.6.9.
POR Value: Loaded from NVM.
Access: Read/Write. Read-only if SEQ group is protected.
Back to Register Map Table.
BIT
NAME
DESCRIPTION
Sleep Exit Sequence:
7:4
SLP_EXIT[3:0]
0 = ENx pin not mapped to sequence. ENx maintains
previous state, unless entering BACKUP or FAILSAFE
state (ENx is pulled low in those states).
1 = ENx pin mapped to first time slot (first up).
15 = ENx pin mapped to last time slot (last up).
3:0
SLP_ENTRY[3:0]
Sleep Entry Sequence:
0 = ENx pin not mapped to sequence. ENx maintains
previous state, unless entering BACKUP or FAILSAFE
state (ENx is pulled low in those states).
1 = ENx pin mapped to first time slot (first down).
15 = ENx pin mapped to last time slot (last down).
表8-34. SLP_CLK32OE
Address: 0x5F
Description: Sleep Exit/Entry sequence assignment of 32 kHz clock output to one of fifteen time slots.
POR Value: Loaded from NVM.
Access: Read/Write. Read-only if SEQ group is protected.
Back to Register Map Table.
BIT
NAME
DESCRIPTION
7:4
SLP_EXIT[3:0]
0 = CLK32 not mapped to Sleep Exit sequence. CLK32
maintains previous state, unless entering BACKUP or
FAILSAFE state (CLK32 is pulled low in those states).
1 = Enable CLK32 on first Sleep Exit time slot.
15 = Enable CLK32 on last Sleep Exit time slot.
3:0
SLP_ENTRY[3:0]
0 = CLK32 not mapped to Sleep Entry sequence. CLK32
maintains previous state, unless entering BACKUP or
FAILSAFE state (CLK32 is pulled low in those states).
1 = Disable CLK32 on first Sleep Entry time slot.
15 = Disable CLK32 on last Sleep Entry time slot.
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表8-35. RTC_T[31:0]
Address: RTC_T[31:24] (0x70) - RTC_T[7:0] (0x73) (Four 8-bit registers).
Description: RTC time setting. Although no provision is specified to maintain data coherency across the four
registers, it is expected that accessing these registers in a single transaction will guarantee data coherency.
RTC_T register values should be written prior to RTC_A values.
POR Value: 0x00000000
Access: Read/Write. Read-only if RTC group is protected.
Back to Register Map Table.
BIT
31:24
23:16
15:8
7:0
NAME
RTC_T3
RTC_T2
RTC_T1
RTC_T0
DESCRIPTION
RTC Time Byte 3 Address 0x70
RTC Time Byte 2 Address 0x71
RTC Time Byte 1 Address 0x72
RTC Time Byte 0 Address 0x73
32-bit unsigned value representing 136 years of 1 second ticks since power-on. Can be used to keep POSIX
time. Must be set with correct value on each power-up
表8-36. RTC_A[31:0]
Address: RTC_A[31:24] (0x74) - RTC_A[7:0] (0x77) (Four 8-bit registers).
Description: RTC alarm setting. Although no provision is specified to maintain data coherency across the four
registers, it is expected that accessing these registers in a single transaction will guarantee data coherency.
POR Value: 0xFFFFFFFF
Access: Read/Write. Read-only if RTC group is protected.
Back to Register Map Table.
BIT
31:24
23:16
15:8
7:0
NAME
DESCRIPTION
RTC Alarm Byte 3 Address 0x74
RTC_A3
RTC_A2
RTC_A1
RTC_A0
RTC Alarm Byte 2 Address 0x75
RTC Alarm Byte 1 Address 0x76
RTC Alarm Byte 0 Address 0x77
Assert Alarm when RTC_T[31:0]==RTC_A[31:0]. See CTL_2.RTC_WAKE and CTL_2.RTC_PU for wake events.
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表8-37. WDT_CFG
Address: 0x80
Description: WDT configuration.
POR Value: Loaded from NVM.
Access: Read/Write. Read-only if WDT group is protected.
Back to Register Map Table.
BIT
NAME
DESCRIPTION
00b = Watchdog disabled.
7:6
WDTEN[1:0]
01b = On successive expires, first interrupt, then reset,
then power-down according to WDT_CFG.PDMD.
10b = On successive expires, first reset, then power-
down according to WDT_CFG.PDMD.
11b = Power-down according to WDT_CFG.PDMD on
expire.
5
SLP_EN
Automatic disable in sleep mode:
0 = Watchdog disabled automatically in sleep mode.
1 = Watchdog enabled in sleep mode.
4:2
WDTDLY[2:0]
Delay, in number of WDT periods (WDT_CLOSE +
WDT_OPEN), from de-assertion of NRST (if exiting
SHDN1 or SHDN2 states), or from value written to
WDT_CFG.WDTEN[1:0], or from Sleep state exit (if
WDT_CFG.SLP_EN=0), to first close window.
000b = 1 WDT period.
111b = 8 WDT periods.
1:0
PDMD[1:0]
Power Down Mode for WDT force power-down.
Value written to CTL_1.FORCE_SHDN[1:0] on WDT
power-down event.
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表8-38. WDT_CLOSE
Address: 0x81
Description: WDT close window configuration.
POR Value: Loaded from NVM.
Access: Read/Write. Read-only if WDT group is protected.
Back to Register Map Table.
BIT
NAME
DESCRIPTION
7:0
CLOSE[7:0]
WDT close window duration:
LSB increment value
1 ms (00h-1Fh)
2 ms (20h-3Fh)
4 ms (40h-FFh)
00h = 1 ms
01h = 2 ms
02h = 3 ms
03h = 4 ms
04h = 5 ms
...
20h = 34 ms
21h = 36 ms
22h = 38 ms
23h = 40 ms
24h = 42 ms
...
40h = 100 ms
41h = 104 ms
42h = 108 ms
43h = 112 ms
44h = 116 ms
...
1Dh = 30 ms
1Eh = 31 ms
1Fh = 32 ms
3Dh = 92 ms
3Eh = 94 ms
3Fh = 96 ms
FDh = 856 ms
FEh = 860 ms
FFh = 864 ms
表8-39. WDT_OPEN
Address: 0x82
Description: WDT open window configuration.
POR Value: Loaded from NVM.
Access: Read/Write. Read-only if WDT group is protected.
Back to Register Map Table.
BIT
NAME
DESCRIPTION
7:0
OPEN[7:0]
WDT open window duration:
LSB increment value
1 ms (00h-1Fh)
2 ms (20h-3Fh)
4 ms (40h-FFh)
00h = 1 ms
01h = 2 ms
02h = 3 ms
03h = 4 ms
04h = 5 ms
...
20h = 34 ms
21h = 36 ms
22h = 38 ms
23h = 40 ms
24h = 42 ms
...
40h = 100 ms
41h = 104 ms
42h = 108 ms
43h = 112 ms
44h = 116 ms
...
1Dh = 30 ms
1Eh = 31 ms
1Fh = 32 ms
3Dh = 92 ms
3Eh = 94 ms
3Fh = 96 ms
FDh = 856 ms
FEh = 860 ms
FFh = 864 ms
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表8-40. WDTKEY
Address: 0x83
Description: WDT key to reset.
POR Value: 0x00
Access: Read/Write.
Back to Register Map Table.
BIT
NAME
DESCRIPTION
Watchdog key register.
7:0
KEY[7:0]
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表8-41. PROT1, PROT2
Address: 0xF0, 0xF1
Description: Protection selection registers. In order to write-protect a register group, the host must set the
relevant bit in both registers.
POR Value: 0x00
Access: Read/Write.
For security, these registers need to have POR value=0x00 and become read-only once set until power cycle.
Once set to 1, they cannot be cleared to 0 by the host; a power cycle (VDD=0) is required to write different
registers configurations.
These registers are cleared also if BIST is executed on exiting Sequence 5 or Sequence 6
(TEST_CFG.AT_SHDN=1).
Back to Register Map Table.
BIT
NAME
RSVD
WRK
DESCRIPTION
7
Reserved
6
0 = Working registers are writable.
1 = Writes to working registers are ignored.
5
4
3
SEQS
SEQP
SEQC
0 = Sleep Sequence registers are writable.
1 = Writes to Sleep Sequence registers are
ignored.
0 = Power Sequence registers are writable.
1 = Writes to Power Sequence registers are
ignored.
0 = Sequence slot configuration registers are
writable.
1 = Writes to Sequence slot configuration
registers are ignored.
2
1
0
WDT
RTC
CTL
0 = WDT registers are writable.
1 = Writes to WDT registers are ignored.
0 = RTC registers are writable.
1 = Writes to RTC registers are ignored.
0 = Control registers are writable.
1 = Writes to control registers are ignored.
表8-42. I2CADDR
Address: 0xF9
Description: I2C address.
POR Value: Loaded from NVM.
Access: Read-Only.
Back to Register Map Table.
BIT
NAME
RSVD
DESCRIPTION
Reserved
7
6:0
ADDR_NVM[6:0]
I2C target device address. Set in NVM.
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
Modern SOC and FPGA devices typically have multiple power rails to provide power to the different blocks within
the IC. Accurate voltage level and timing requirements are common and must be met in order to ensure proper
operation of these devices. By utilizing TPS38700-Q1 along with a multichannel voltage supervisor, the power
up and power down sequencing requirements as well as the core voltage requirements of the target SOC or
FPGA device can be met. This design focuses on meeting the timing requirements for an SOC by using the
TPS38700-Q1.
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9.2 Typical Application
9.2.1 Automotive Multichannel Sequencer and Monitor
A typical application for the TPS38700-Q1 is shown in 图 9-1. TPS38700-Q1 is used to provide the proper
voltage sequencing for the target SOC device by providing enable signals to the DC/DC converters shown.
These DC/DC converters are used to generate the appropriate voltage rails for the SOC. A mulitchannel voltage
monitor is used to monitor the voltage rails as these rails power up and power down to ensure that the correct
sequence occurs in both occasions. A safety microcontroller is also used to provide ACT, NIRQ, and I2C
commands to the TPS38700-Q1 and the multichannel voltage monitor. The ACT signal from the safety
microcontroller determines when the TPS38700-Q1 enters into ACTIVE or SHDN states while the NIRQ pin of
the TPS38700-Q1 acts as an interrupt pin that is set when a fault has occurred. For instance, if an external
device pulls the NRST pin low, then the TPS38700-Q1 will trigger an interrupt through the NIRQ pin. I2C is used
to communicate the type of fault to the host microcontroller. The host microcontroller can clear the fault by writing
1 to the affected register. The power rails for the safety microcontroller are not shown in 图9-1 for simplicity.
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VDD
BUCK1
EN
Vo
VDD VBBAT
EN1
BUCK2
EN
Vo
ACT
EN2
BUCK3
Vo
EN
EN3
NIRQ
BUCK4
Vo
EN
EN4
TPS38700-Q1
BUCK5
Vo
NRST
EN5
EN
EN6
BUCK6
Vo
SLEEP
EN
I2C
EN7
BUCK7
Vo
EN
EN8
GND
BUCK8
Vo
EN
VDD
MON1
MON2
MON3
MON4
NIRQ
Voltage Monitor
MON5
ACT
MON6
SLEEP
ADDR
I2C
RS_1/2
SYNC
GND
SOC
SLEEP
NRST
CLK32K
ACT
Safety Micro
I2C
NIRQ
2
图9-1. TPS38700-Q1 Voltage Sequencer Design Block Diagram
9.2.2 Design Requirements
• Eight different voltage rails supplied by DC/DC converters need to be properly sequenced in this design. The
sequence order and timing requirements are outlined in 表9-1 and 表9-2.
• Emergency power down functionality is optional.
• Backup battery power supply required. This must be stepped down to a maximum value of 5.5 V in order to
comply with the absolute maximum ratings of the VBBAT pin.
• All detected failures in sequencing should be reported via an external hardware interrupt signal.
• All detected failures should be logged in internal registers and be accessible to an external processor via I2C.
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表9-1. Power Up and Power Down Sequence Requirement
ENABLE CHANNEL
POWER UP SEQUENCE
POSITION
POWER DOWN
TIME BETWEEN POWER TIME BETWEEN POWER
SEQUENCE POSITION
UP SIGNALS (μs)
DOWN SIGNALS (μs)
EN1
EN2
EN3
EN4
EN5
EN6
EN7
EN8
1
1
2
2
4
6
1
2
5
1
4
4
2
1
1
4
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
表9-2. Sleep Entry and Sleep Exit Sequence Requirement
ENABLE CHANNEL
SLEEP EXIT SEQUENCE
POSITION
SLEEP ENTRY
TIME BETWEEN SLEEP TIME BETWEEN SLEEP
SEQUENCE POSITION
EXIT SIGNALS (μs)
ENTRY SIGNALS (μs)
EN1
EN2
EN3
EN4
EN5
EN6
EN7
EN8
0
1
3
0
0
2
1
3
0
3
2
0
0
1
3
2
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
9.2.3 Detailed Design Procedure
• TPS38700-Q1 device comes preprogrammed with the power up, power down, sleep entry, and sleep exit
sequences shown in 表9-1 and 表9-2.
• NIRQ and NRST pins both require a pull up resistor in the range of 10 kΩto 100 kΩ.
• SDA and SCL lines require pull up resistors in the range of 10 kΩ.
• The ACT pin is driven by an external safety microcontroller. When the ACT pin is driven high, the device
enters into ACTIVE mode as described in 节8.3.6.1. When the ACT pin is driven low, the device enters into
SHDN mode as described in 节8.3.6.5.
• The safety microcontroller is used to clear fault interrupts reported through the NIRQ interrupt pin and the
INT_SCR1 and INT_SCR2 registers. The interrupt flags can only be cleared by the host micrcontroller with a
write-1-to-clear operation; interrupt flags are not automatically cleared if the fault condition is no longer
present.
• The SLEEP pin is driven by the SOC. When the SLEEP pin is driven low, the device enters into Sleep mode
as shown in 节8.3.6.3. When the SLEEP pin is driven high, the device exits Sleep mode as shown in 节
8.3.6.4.
• The safety microcontroller should be connected to the NEM_PD input pin of the TPS38700-Q1 device in
order to enable emergency power down functionality. When this pin is driven low, the TPS38700-Q1 device
will enter into power down sequence. Power down due to NEM_PD is shown in 图8-12.
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9.2.4 Application Curves
图9-3. Power Down Sequence
图9-2. Power Up Sequence
图9-5. Sleep Exit Sequence
图9-4. Sleep Entry Sequence
图9-6. RESET Triggered by NRST_IN
图 9-2 depicts the power up sequencing order listed in 表 9-1. Notice EN1 rises at the same time as the ACT
signal due to the number 1 slot selection. Additonally, notice EN3 and EN4 rise 625us after EN1 due to the
number two slot selection. The TPS38700-Q1 timing tool found under the "Design tool's & simulation" section of
the TPS38700-Q1 web page can be used to assist in implementing a desired slot selection.
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10 Power Supply Recommendations
10.1 Power Supply Guidelines
This device is designed to operate from an input supply with a voltage range between 2.2 V to 5.5 V. It has a 6 V
absolute maximum rating on the VDD pin as well as on the VBBAT pin. It is good analog practice to place a 0.1-
µF to 1-µF capacitor between the VDD pin and the GND pin depending on the input voltage supply noise. If the
voltage supply providing power to VDD is susceptible to any large voltage transients that exceed maximum
specifications, additional precautions must be taken.
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11 Layout
11.1 Layout Guidelines
• Place the external components as close to the device as possible. This configuration prevents parasitic errors
from occurring.
• Do not use long traces for the VDD supply node. The VDD capacitor, along with parasitic inductance from the
supply to the capacitor, can form an LC circuit and create ringing with peak voltages above the maximum
VDD voltage.
• Do not use long traces of voltage to the sense pin. Long traces increase parasitic inductance and cause
inaccurate monitoring and diagnostics.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when absolutely necessary.
11.2 Layout Example
图11-1. Recommended Layout
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12 Device and Documentation Support
12.1 Device Nomenclature
表12-1 shows how to decode the function of the device based on the device ordering code, while
表 12-2 shows the sequence configuration based on the device ordering code. See 图 5-1 for more information
regarding how to decode the device part number.
表12-1. Device Comparison Table
TIME
SLOT
(μ
sec)
RESET
EN PINS ALT FUNC.
I2C
ADDR.
I2C PULL-UP
VOLTAGE (V)
ORDERING CODE
FUNCTIONS
DELAY WATCHDOG PEC(1)
(msec)
DEFAULT
PINS
Sequencer,
NEM_PD
Push-Pull
Low
TPS38700C03NRGERQ1
Open-Drain 625
3C
16
Disabled
Enabled
3.3
(1) For parts with PEC enabled:
a. PEC calculation is based on initializing to 0x00.
b. In case of a PEC violation there needs to be a subsequent I2C transaction before NIRQ is asserted.
c. If incorrect PEC is given it will assert NIRQ.
d. If there is an extra byte after successfully writing the correct PEC byte, NIRQ will be asserted and the write will fail.
表12-2. Sequence Configuration Table
ORDERING CODE
PINS
SEQUENCE UP
SEQUENCE DOWN
Power Down Slot 5
PWR_EN1
PWR_EN2
PWR_EN3
PWR_EN4
PWR_EN5
PWR_EN6
PWR_EN7
PWR_EN8
PWR_EN9
PWR_EN10
PWR_EN11
PWR_EN12
PWR_CLK32
Power Up Slot 1
Power Up Slot 1
Power Up Slot 2
Power Up Slot 2
Power Up Slot 4
Power Up Slot 6
Power Up Slot 1
Power Up Slot 2
Power Up Slot 4
Power Up Slot 0
Power Up Slot 4
Power Up Slot 0
Power Up Slot 4
Power Down Slot 1
Power Down Slot 4
Power Down Slot 4
Power Down Slot 2
Power Down Slot 1
Power Down Slot 1
Power Down Slot 4
Power Down Slot 2
Power Down Slot 0
Power Down Slot 2
Power Down Slot 0
Power Down Slot 4
03N
Sequence Down
Sleep Exit Slot 0
Sleep Exit Slot 1
Sleep Exit Slot 3
Sleep Exit Slot 0
Sleep Exit Slot 0
Sleep Exit Slot 2
Sleep Exit Slot 1
Sleep Exit Slot 3
Sleep Exit Slot 4
Sleep Exit Slot 0
Sleep Exit Slot 1
Sleep Exit Slot 0
Sleep Exit Slot 0
Sequence Up
SLP_EN1
SLP_EN2
SLP_EN3
SLP_EN4
SLP_EN5
SLP_EN6
SLP_EN7
SLP_EN8
SLP_EN9
SLP_EN10
SLP_EN11
SLP_EN12
SLP_CLK32
Sleep Entry Slot 0
Sleep Entry Slot 3
Sleep Entry Slot 2
Sleep Entry Slot 0
Sleep Entry Slot 0
Sleep Entry Slot 1
Sleep Entry Slot 3
Sleep Entry Slot 2
Sleep Entry Slot 1
Sleep Entry Slot 0
Sleep Entry Slot 1
Sleep Entry Slot 0
Sleep Entry Slot 0
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12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS38700C03NRGERQ1
ACTIVE
VQFN
RGE
24
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T38700C
03NQA1
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jan-2023
OTHER QUALIFIED VERSIONS OF TPS38700-Q1 :
Catalog : TPS38700
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jan-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS38700C03NRGERQ1 VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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24-Jan-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RGE 24
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
TPS38700C03NRGERQ1
3000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
VQFN - 1 mm max height
RGE0024N
PLASTIC QUAD FLATPACK-NO LEAD
4.1
3.9
A
B
4.1
3.9
PIN 1 INDEX AREA
0.1 MIN
(0.13)
SECTION A-A
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 2.5
2.45±0.1
(0.2) TYP
7
12
A
6
13
(0.16)
A
SYMM
25
2X
2.5
1
18
0.3
0.2
24X
20X 0.5
19
24
0.1
0.05
C A B
C
SYMM
PIN 1 ID
(OPTIONAL)
0.5
0.3
24X
4224736/A 12/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGE0024N
PLASTIC QUAD FLATPACK-NO LEAD
2X (3.8)
2X (2.5)
(
2.45)
24
19
24X (0.6)
24X (0.25)
1
18
20X (0.5)
25
SYMM
2X
2X
(2.5) (3.8)
2X
(0.975)
6
13
(R0.05) TYP
(Ø 0.2) VIA
TYP
7
12
2X (0.975)
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224736/A 12/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGE0024N
PLASTIC QUAD FLATPACK-NO LEAD
2X (3.8)
2X (2.5)
4X
1.08)
(
24
19
24X (0.6)
24X (0.25)
1
25
18
20X (0.5)
SYMM
2X
2X
(2.5) (3.8)
2X (0.64)
6
13
(R0.05) TYP
METAL
TYP
7
12
2X (0.64)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 18X
4224736/A 12/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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