TPS40000DGQ_技术文档

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SLUS507C − JANUARY 2002 − REVISED JUNE 2004

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ꢑꢋ ꢊꢀꢒꢓ ꢔꢍꢕ ꢋ ꢖꢔ

ꢛꢐꢘ ꢜ ꢘꢋ ꢏꢀ ꢚꢋ ꢊ ꢊꢔ ꢚ

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FEATURES

APPLICATIONS

D

Operating Input Voltage 2.25 V to 5.5 V

Output Voltage as Low as 0.7 V

1% Internal 0.7 V Reference

D

Networking Equipment

Telecom Equipment

Base Stations

Servers

Predictive Gate Drivet N-Channel MOSFET

Drivers for Higher Efficiency

DSP Power

Externally Adjustable Soft-Start and

Overcurrent Limit

Power Modules

DESCRIPTION

Source-Only Current or Source/Sink Current

Versions for Starting Into V

Pre-Bias

OUT

The TPS4000x are controllers for low-voltage,

10-Lead MSOP PowerPadt Package for

non-isolated synchronous buck regulators. These

controllers drive an N-channel MOSFET for the

primary buck switch, and an N-channel MOSFET

for the synchronous rectifier switch, thereby

achieving very high-efficiency power conversion. In

addition, the device controls the delays from main

switch off to rectifier turn-on and from rectifier

turn-off to main switch turn-on in such a way as to

minimize diode losses (both conduction and

recovery) in the synchronous rectifier with TI’s

proprietary Predictive Gate Drivet technology. The

reduction in these losses is significant and increases

efficiency. For a given converter power level, smaller

FETs can be used, or heat sinking can be reduced

or even eliminated.

Higher Performance

D

Thermal Shutdown

Internal Boostrap Diode

Fixed-Frequency, Voltage-Mode Control

− TPS40000/1/4 300-kHz

− TPS40002/3/5 600-kHz

SIMPLIFIED APPLICATION DIAGRAM

V

IN

TPS40000

1

2

3

4

ILIM

BOOT 10

FB

HDRV

9

COMP

SS/SD

V

OUT

SW

VDD

8

7

6

5

GND

LDRV

UDG−01141

PowerPADt and Predictive Gate Drivet are trademarks of Texas Instruments Incorporated.

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Copyright  2002, Texas Instruments Incorporated

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SLUS507C − JANUARY 2002 − REVISED JUNE 2004

DESCRIPTION (continued)

The current-limit threshold is adjustable with a single resistor connected to the device. The TPS4000x

controllers implement a closed-loop soft start function. Startup ramp time is set by a single external capacitor

connected to the SS/SD pin. The SS/SD pin is also used for shutdown.

ORDERING INFORMATION

(2)

PACKAGED DEVICES MSOP (DGQ)

APPLICATION

(3)

SOURCE/SINK

SOURCE

ONLY

SOURCE/SINK

T

FREQUENCY

A

(3)

WITH PREBIAS

TPS40001DGQ

TPS40003DGQ

300 kHz

600 kHz

TPS40000DGQ

TPS40002DGQ

TPS40004DGQ

TPS40005DGQ

−40°C to 85°C

(2)

(3)

The DGQ package is available taped and reeled. Add R suffix to device type (e.g.

TPS40000DGQR) to order quantities of 2,500 devices per reel and 80 units per tube.

See Application Information section, p. 8.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

(1)

TPS4000x

V + 6.5

SW

UNIT

BOOT

COMP, FB, ILIM, SS/SD

SW

−0.3 to 6

−0.7 to 10.5

−2.5

Input voltage range, V

IN

V

SW (SW transient < 50 ns)

T

VDD

6

Operating junction temperature range, T

−40 to 150

−55 to 150

260

J

Storage temperature, T

stg

°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions”

is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(4).(5

DGQ PACKAGE

(TOP VIEW)

)

BOOT

HDRV

SW

ILIM

FB

1

2

3

4

5

10

9

8

7

6

COMP

SS/SD

GND

VDD

LDRV

ACTUAL SIZE

3,05mm x 4,98mm

(4)

(5)

See technical brief SLMA002 for PCB guidelines for PowerPAD packages.

PowerPADt heat slug can be connected to GND (pin 5).

2

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SLUS507C − JANUARY 2002 − REVISED JUNE 2004

ELECTRICAL CHARACTERISTICS

over recommended operating temperature range, T = −40_C to 85_C, V

= 5.0 V, all parameters measured at zero

A

DD

power dissipation (unless otherwise noted)

input supply

PARAMETER

Input voltage range

High-side gate voltage

Shutdown current

Quiescent current

Switching current

Minimum on-voltage

Hysteresis

TEST CONDITIONS

MIN

2.25

TYP

MAX

5.5

UNIT

V

DD

V

− V

5.5

0.45

2.0

HGATE

BOOT

SW

SS/SD = 0 V,

FB = 0.8 V

Outputs off

0.25

1.4

1.5

I

mA

DD

No load at HDRV/LDRV

4.0

UVLO

1.95

80

2.05

140

2.15

200

V

mV

oscillator

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TPS40000

TPS40001

TPS40004

250

500

300

600

350

700

f

Oscillator frequency

2.25 V ≤ V

DD

≤ 5.00 V

kHz

OSC

TPS40002

TPS40003

TPS40005

V

Ramp voltage

V

PEAK

− V

0.80

0.24

0.93

0.31

1.07

0.41

RAMP

VALLEY

V

Ramp valley voltage

PWM

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TPS40000

TPS40001

TPS40004

87%

83%

94%

93%

97%

(2)

Maximum duty cycle

FB = 0 V,

V

DD

= 3.3 V

TPS40002

TPS40003

TPS40005

97%

0%

Minimum duty cycle

error amplifier

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Line,

Temperature

0.689

0.693

0.700

30

0.711

0.707

130

V

FB input voltage

V

FB

T

A

= 25°C

FB input bias current

High-level output voltage

Low-level output voltage

Output source current

Output sink current

nA

V

FB = 0 V,

I

= 0.5 mA

2.0

2.5

0.08

6

OH

V

FB =V

DD

,

= 0.5 mA

0.15

OL

I

COMP = 0.7 V,

FB = GND

FB = V

2

3

OH

mA

8

OL

DD

(1)

G

Gain bandwidth

Open loop gain

5

10

MHz

dB

BW

A

OL

55

85

(1)

(2)

Ensured by design. Not production tested.

At V input voltage of 2.25 V, derate the maximum duty cycle by 3%.

DD

3

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SLUS507C − JANUARY 2002 − REVISED JUNE 2004

ELECTRICAL CHARACTERISTICS

over recommended operating temperature range, T = −40_C to 85_C, V

= 5.0 V, all parameters measured at zero

A

DD

power dissipation (unless otherwise noted)

current limit

PARAMETER

TEST CONDITIONS

MIN

11

TYP

15

MAX

19

UNIT

V

= 5 V

DD

I

ILIM sink current

µA

SINK

= 2.25 V

9.5

−20

2

13.0

0

16.5

20

DD

(1)

V

Offset voltage SW vs ILIM

2.25 V ≤ V

DD

≤ 5.00

mV

V

OS

Input voltage range

VDD

300

ILIM

t

Minimum HDRV pulse time in overcurrent

V

DD

= 3.3 V

200

100

6

ns

ON

SW leading edge blanking pulse in over-

current detection

ns

(1)

Soft-start capacitor cycles as fault timer

t

SS

rectifier zero current comparator

PARAMETER

TEST CONDITIONS

LDRV output OFF

MIN

−15

TYP

MAX

−2

UNIT

Sense voltage to turn off

rectifier

TPS40000

TPS40002

V

SW

−7

75

mV

SW leading edge blanking pulse in zero

current detection

ns

predictive delay

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

mV

ns

V

SWP

Sense threshold to modulate delay time

Maximum delay modulation range time

Predictive counter delay time per bit

Maximum delay modulation range

Predictive counter delay time per bit

−350

75

T

LDRV OFF − to − HDRV ON

HDRV OFF − to − LDRV ON

50

3.0

40

100

6.2

90

LDHD

4.5

65

ns

T

ns

HDLD

2.4

4.0

5.6

ns

shutdown

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

Shutdown threshold voltage

Outputs OFF

0.09

0.14

0.13

0.17

0.18

0.21

SD

Device active threshold voltage

V

EN

soft start

PARAMETER

Soft-start source current

Soft-start clamp voltage

TEST CONDITIONS

MIN

TYP

MAX

UNIT

µA

I

Outputs OFF

2.0

1.1

3.7

1.5

5.4

1.9

SS

V

SS

bootstrap

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

= 3.3 V

= 5 V

50

35

100

70

DD

R

Bootstrap switch resistance

Ω

BOOT

DD

(1) Ensured by design. Not production tested.

(2) At V

DD

input voltage of 2.25 V, derate the maximum duty cycle by 3%.

4

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SLUS507C − JANUARY 2002 − REVISED JUNE 2004

ELECTRICAL CHARACTERISTICS

over recommended operating temperature range, T = −40_C to 85_C, V

= 5.0 V, all parameters measured at zero

A

DD

power dissipation (unless otherwise noted)

output driver

PARAMETER

TEST CONDITIONS

= 3.3 V

MIN

TYP

MAX

5.5

UNIT

V

−V

BOOT SW

,

R

HDRV pull-up resistance

3

HDHI

I

= −100 mA

SOURCE

V

SINK

− V

= 3.3 V

,

BOOT

SW

HDRV pull-down resistance

1.5

3

HDLO

Ω

I

= 100 mA

= 3.3 V,

R

LDRV pull-up resistance

LDRV pull-down resistance

LDRV rise time

V

I = −100 mA

SOURCE

3

1.0

15

10

15

10

5.5

2.0

35

25

35

25

LDHI

LDLO

RISE

FALL

DD

V

= 3.3 V,

I

= 100 mA

SINK

t

LDRV fall time

C

= 1 nF

ns

LOAD

HDRV rise time

HDRV fall time

thermal shutdown

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(1)

Shutdown temperature

t

165

15

SD

°C

(1)

Hysteresiss

sw node

PARAMETER

Leakage current in shutdown

(1) Ensured by design. Not production tested.

TYP

15

MAX

UNIT

(1)

I

µA

SW

(2) At V

DD

input voltage of 2.25 V, derate the maximum duty cycle by 3%.

5

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SLUS507C − JANUARY 2002 − REVISED JUNE 2004

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

Provides a bootstrapped supply for the topside MOSFET driver, enabling the gate of the topside

MOSFET to be driven above the input supply rail

BOOT

10

O

COMP

FB

3

2

O

I

Output of the error amplifier

Inverting input of the error amplifier. In normal operation the voltage at this pin is the internal reference level of 700 mV.

Power supply return for the device. The power stage ground return on the board requires a separate path from other

sensitive signal ground returns.

GND

5

9

−

This is the gate drive output for the topside N-channel MOSFET. HDRV is bootstrapped to near 2×V

for good en-

DD

HDRV

O

hancement of the topside MOSFET.

A resistor is connected between this pin and VDD to set up the over current threshold voltage. A 15-µA current sink at

the pin establishes a voltage drop across the external resistor that represents the drain-to-source voltage across the

top side N-channel MOSFET during an over current condition. The ILIM over current comparator is blanked for the

first 100 ns to allow full enhancement of the top

ILIM

1

6

I

MOSFET. Set the ILIM voltage level such that it is within 800 mV of V ; that is, (V

− 0.8) ≤ I

≤ V .

DD

ILIM

DD

LDRV

O

Gate drive output for the low-side synchronous rectifier N-channel MOSFET

Soft-start and overcurrent fault shutdown times are set by charging and discharging a capacitor connected to this pin.

A closed loop soft-start occurs when the internal 3-µA current source charges the external capacitor from 0.17 V to

0.70 V. During the soft-start period, the current sink capability of the TPS40001 and TPS40003 is disabled. When the

SS/SD voltage is less than 0.12 V, the device is shutdown and the HDRV and LDRV are driven low. In normal opera-

tion, the capacitor is charged to 1.5 V. When a fault condition is asserted, the HDRV is driven low, and the LDRV is

driven high. The soft-start capacitor goes through six charge/discharge cycles, restarting the converter on the seventh

cycle.

SS/SD

4

I

Connect to the switched node on the converter. This pin is used for overcurrent sensing in the topside N-channel

MOSFET, zero current sensing in synchronous rectifier N-channel MOSFET, and level sensing for predictive delay

circuit. Overcurrent is determined, when the topside N-channel MOSFET is on, by comparing the voltage on SW with

respect to VDD and the voltage on the ILIM with respect to VDD. Zero current is sensed, when the rectifier N-channel

MOSFET is on, by measuring the voltage on SW with respect to ground. Zero current sensing applies to the

TPS40000/2 devices only.

SW

8

7

O

I

VDD

Power input for the chip, 5.5-V maximum. Decouple close to the pin with a low-ESR capacitor, 1-µF or larger.

6

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SLUS507C − JANUARY 2002 − REVISED JUNE 2004

functional block diagram

VDD

FB

7

2

VDD

THERMAL

SHUTDOWN

LDRV

UVLO

2 V

ERROR AMPLIFIER

PWM COMP

10 BOOT

+

HI

0.7 V

REF

UVLO

9

HDRV

PREDICTIVE

GATE

OSC

CLK

PWM

DRIVE

PWM

LOGIC

COMP

SS/SD

3

4

UVLO

(VDD−1.2 V)

SS ACTIVE

FAULT

OC

8

6

1

SW

3 µA

SOFT

START

FAULT

COUNTER

VDD

DISCHARGE

LO

LDRV

ILIM

100 ns DELAY

EN

0.12 V

SHUT DOWN

GND

5

CURRENT

LIMIT COMP

15 µA

LDRV

75 ns

DELAY

EN

RECTIFIER

ZERO−CURRENT

COMPARATOR

UDG−01142

7

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SLUS507C − JANUARY 2002 − REVISED JUNE 2004

APPLICATION INFORMATION

The TPS4000x series of synchronous buck controller devices is optimized for high-efficiency dc-to-dc

conversion in non-isolated distributed power systems. A typical application circuit is shown in Figure 1.

The TPS40004 and TPS40005 are the controllers of choice for most general purpose synchronous buck

designs. Each operates in two quadrant mode (i.e. source or sink current) full time. This choice provides the

best performance for output voltage load transient response over the widest load current range.

The TPS40001 and TPS40003 add an additional feature: They operate in single quadrant mode (i.e. source

current only) during converter startup, and then when the converter has reached the regulation point, the

controllers change to operate in two quadrant mode. This is useful for applications that have outputs pre-biased

at some voltage before the controller is enabled. When the TPS40001 or TPS40003 is enabled, it does not sink

current during startup and therefore does not pull current from the pre-biased voltage supply.

The TPS40000 and TPS40002 operate in single quadrant mode (source current only) full time, allowing the

paralleling of converters. Single quadrant operation ensures one converter does pull current from a paralleled

converter. A converter using one of these controllers emulates a non-synchronous buck converter at light loads.

When current in the output inductor attempts to reverse, an internal zero-current detection circuit turns OFF the

synchronous rectifier and causes the current flow in the inductor to become discontinuous. At average load

currents greater than the peak amplitude of the inductor ripple current, the converter returns to operation as a

synchronous buck converter to maximize efficiency.

V

DD

3.0 V to 5.5 V

100 µF

10 µF

20 kW

TPS40001

ILIM BOOT

1

2

3

4

5

10

9

Si4836DY

V

1.8 V

OUT

10 A

IHLP5050CE−01

1.0 µH

FB

HDRV

SW

7.68 kΩ

3.6 nF

3.3 Ω

100 nF

COMP

SS/SD

GND

8

243 Ω

15.7 kΩ

470 µF

10 µF

100 pF

7

Si4836DY

VDD

LDRV

3.3 nF

4.7 nF

6

10 kΩ

UDG−02013

Figure 1. Typical Application Circuit

8

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SLUS507C − JANUARY 2002 − REVISED JUNE 2004

APPLICATION INFORMATION

error amplifier

The error amplifier has a bandwidth of greater than 5 MHz, with open loop gain of at least 55 dB. The COMP

output voltage is clamped to a level above the oscillator ramp in order to improve large-scale transient response.

oscillator

The oscillator uses an internal resistor and capacitor to set the oscillation frequency. The ramp waveform is a

triangle at the PWM frequency with a peak voltage of 1.25 V, and a valley of 0.25 V. The PWM duty cycle is limited

to a maximum of 95%, allowing the bootstrap capacitor to charge during every cycle.

bootstrap/charge pump

There is an internal switch between VDD and BOOT. This switch charges the external bootstrap capacitor for

the floating supply. If the resistance of this switch is too high for the application, an external schottky diode

between VDD and BOOT can be used. The peak voltage on the bootstrap capacitor is approximately equal to

VDD.

driver

The HDRV and LDRV MOSFET drivers are capable of driving gate-to-source voltages up to 5.5 V. At V , = 5 V

IN

and using appropriate MOSFETs, a 20-A converter can be achieved. The LDRV driver switches between VDD

and ground, while the HDRV driver is referenced to SW and switches between BOOT and SW. The maximum

voltage between BOOT and SW is 5.5 V.

synchronous rectification and predictive delay

In a normal buck converter, when the main switch turns off, current is flowing to the load in the inductor. This

current cannot be stopped immediately without using infinite voltage. For the current path to flow and maintain

voltage levels at a safe level, a rectifier or catch device is used. This device can be either a conventional diode,

or it can be a controlled active device if a control signal is available to drive it. The TPS4000x provides a signal

to drive an N-channel MOSFET as a rectifier. This control signal is carefully coordinated with the drive signal

for the main switch so that there is minimum delay from the time that the rectifier MOSFET turns off and the main

switch turns on, and minimum delay from when the main switch turns off and the rectifier MOSFET turns on.

This scheme, Predictive Gate Drivet delay, uses information from the current switching cycle to adjust the

delays that are to be used in the next cycle. Figure 2 shows the switch-node voltage waveform for a

synchronously rectified buck converter. Illustrated are the relative effects of a fixed-delay drive scheme

(constant, pre-set delays for the turn-off to turn-on intervals), an adaptive delay drive scheme (variable delays

based upon voltages sensed on the current switching cycle) and the predictive delay drive scheme.

Note that the longer the time spent in diode conduction during the rectifier conduction period, the lower the

efficiency. Also, not described in Figure 2 is the fact that the predictive delay circuit can prevent the body diode

from becoming forward biased at all while at the same time avoiding cross conduction or shoot through. This

results in a significant power savings when the main MOSFET turns on, and minimizes reverse recovery loss

in the body diode of the rectifier MOSFET.

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SLUS507C − JANUARY 2002 − REVISED JUNE 2004

APPLICATION INFORMATION

GND

Channel Conduction

Body Diode Conduction

Fixed Delay

Adaptive Delay

Predictive Delay

UDG−01144

Figure 2. Switch Node Waveforms for Synchronous Buck Converter

overcurrent

Overcurrent conditions in the TPS4000x are sensed by detecting the voltage across the main MOSFET while

it is on.

basic description

If the voltage exceeds a pre-set threshold, the current pulse is terminated, and a counter inside the device is

incremented. If this counter fills up, a fault condition is declared and the device disables switching for a period

of time and then attempts to restart the converter with a full soft-start cycle.

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APPLICATION INFORMATION

detailed description

During each switching cycle, a comparator looks at the voltage across the top side MOSFET while it is on. This

comparator is enabled after the SW node reaches a voltage greater than (V −1.2 V) followed by a 100-ns

DD

blanking time. If the voltage across that MOSFET exceeds a programmable threshold voltage, the

current-switching pulse is terminated and a 3-bit counter is incremented by one count. If, during the switching

cycle, the topside MOSFET voltage does not exceed a preset threshold, then this counter is decremented by

one count. (The counter does not wrap around from 7 to 0 or from 0 to 7). If the counter reaches a full count

of 7, the device declares that a fault condition exists at the output of the converter. In this fault state, HDRV is

turned off and LDRV is turned on and the soft-start capacitor is discharged. The counter is decremented by one

by the soft start capacitor (C ) discharge. When the soft-start capacitor is fully discharged, the discharging

SS

circuit is turned off and the capacitor is allowed to charge up at the nominal charging rate. When the soft-start

capacitor reaches about 700 mV, it is discharged again and the overcurrent counter is decremented by one

count. The capacitor is charged and discharged, and the counter decremented until the count reaches zero (a

total of six times). When this happens, the outputs are again enabled as the soft-start capacitor generates a

reference ramp for the converter to follow while attempting to restart.

During this soft-start interval (whether or not the controller is attempting to do a fault recovery or starting for the

first time), pulse-by-pulse current limiting is in effect, but overcurrent pulses are not counted to declare a fault

until the soft-start cycle has been completed. It is possible to have a supply attempt to bring up a short circuit

for the duration of the soft start period plus seven switching cycles. Power stage designs should take this into

account if it makes a difference thermally. Figure 3 shows the details of the overcurrent operation.

(+)

V

TS

(−)

Overcurrent

Threshold

Voltage

Internal PWM

V

TS

0V

External

Main Drive

Normal

Cycle

Overcurrent

Cycle

UDG−01145

Figure 3. Switch Node Waveforms for Synchronous Buck Converter

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SLUS507C − JANUARY 2002 − REVISED JUNE 2004

APPLICATION INFORMATION

Figure 4 shows the behavior of key signals during initial startup, during a fault and a successfully fault recovery.

At time t0, power is applied to the converter. The voltage on the soft-start capacitor (V ) begins to ramp up

CSS

and acts as the reference until it passes the internal reference voltage at t1. At this point the soft-start period

is over and the converter is regulating its output at the desired voltage level. From t0 to t1, pulse-by-pulse current

limiting is in effect, and from t1 onward, overcurrent pulses are counted for purposes of determining a possible

fault condition. At t2, a heavy overload is applied to the converter. This overload is in excess of the overcurrent

threshold. The converter starts limiting current and the output voltage falls to some level depending on the

overload applied. During the period from t2 to t3, the counter is counting overcurrent pulses, and at time t3

reaches a full count of 7. The soft-start capacitor is then discharged, the counter is decremented, and a fault

condition is declared.

0.7 V

V

CSS

FAULT

I

LOAD

V

OUT

t

t4

t0

t1

t2 t3

t5

t6

t7

t8

t9

t10

0

6

5

4

3

2

1

0

1

2 3 4 5 6 7

UDG−01144

Figure 4. Switch Node Waveforms for Synchronous Buck Converter

When the soft start capacitor is fully discharged, it begins charging again at the same rate that it does on startup,

with a nominal 3-µA current source. As the capacitor voltage reaches full charge, it is discharged again and the

counter is decremented by one count. These transitions occur at t3 through t9. At t9, the counter has been

decremented to 0. The fault logic is then cleared, the outputs are enabled, and the converter attempts to restart

with a full soft-start cycle. The converter comes into regulation at t10.

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SLUS507C − JANUARY 2002 − REVISED JUNE 2004

APPLICATION INFORMATION

setting the current limit

Connecting a resistor from VDD to ILIM sets the current limit. A 15-µA current sink internal to the device causes

a voltage drop at ILIM that is equal to the overcurrent threshold voltage. Ensure that (V −0.8 V) ≤ V ≤ V

.

DD

ILIM

The tolerance of the current sink is too loose to do an accurate current limit. The main purpose is for hard fault

protection of the power switches. Given the tolerance of the ILIM sink current, and the R range for a

DS(on)

MOSFET, it is generally possible to apply a load that thermally damages the converter. This device is intended

for embedded converters where load characteristics are defined and can be controlled.

soft-start and shutdown

These two functions are common to the SS/SD pin. The voltage at this pin is the controlling voltage of the error

amplifier during startup. This reduces the transient current required to charge the output capacitor at startup,

and allows for a smooth startup with no overshoot of the output voltage if done properly. A shutdown feature

can be implemented as shown in Figure 5.

TPS40000

3 µA

4

SS/SD

C

SS

SHUTDOWN

UDG−01143

Figure 5. Shutdown Implementation

The device shuts down when the voltage at the SS/SD pin falls below 120 mV. Because of this limitation, it is

recommended that a MOSFET be used as the controlling device, as in Figure 5. An open-drain CMOS logic

output would work equally well.

rectifier zero-current

Both the TPS40000 and TPS40002 parts are source-only, thus preventing reverse current in the synchronous

rectifier. Synchronous rectification is terminated by sensing the voltage, SW with respect to ground, across the

low-side MOSFET. When SW node is greater than −7 mV, rectification is terminated and stays off until the next

PWM cycle. In order to filter out undesired noise on the SW node, the zero-current comparator is blanked for

75 ns from the time the rectifier is turned on.

The TPS40001 and TPS40003 parts enable the zero-current comparator, (and therefore prevent reverse

current), while soft-start is active. However, when the output reaches regulation; that is, at the end of the

soft-start time, this comparator is disabled to allow the synchronous rectifier to sink current.

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APPLICATION INFORMATION

The following pages include design ideas for a few applications. For more ideas, detailed design information,

and helpful hints, visit the TPS40000 resources at http://power.ti.com.

V

DD

3.3 V

22 µF

TPS40002/3/5

15 kΩ

FDS6894A

1

2

3

4

5

10

9

ILIM

BOOT

HDRV

SW

1.0 µH

FB

V

OUT

1 nF

8.66 kΩ

3.3 Ω

1 µF

1.2 V

5 A

COMP

SS/SD

GND

8

2.2 Ω

.0033 µF

22 µF

7

VDD

68 pF

FDS6894A

4.7 nF

6

LDRV

PWP

1 µF

470 pF

12.1 kΩ

1 kΩ

16.9 kΩ

UDG−02081

Figure 6. Small-Form Factor Converter for 3.3 V to 1.2 V at 5 A.

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APPLICATION INFORMATION

Figure 7. High-Current Converter for 3.3 V to 1.2 V at 10 A.

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APPLICATION INFORMATION

22 µF

V

DD

2.5 V

BAT54

15 kΩ

TPS40002/3/5

1 µF

FDS6894A

1

2

3

4

5

10

9

ILIM BOOT

1.8 Ω

3.3 Ω

V

1.2 V

5 A

1.0 µH

L1

FB

OUT

HDRV

1500 pF 5.62 kΩ

COMP

8

SW

2.2 Ω

7

SS/SD VDD

100 pF

22 µF

4.7 nF

1.8 Ω

1 µF

FDS6894A

6

GND LDRV

PWP

3.3 nF

6.19 kΩ

536 Ω

1000 pF

8.66 kΩ

UDG−02083

Figure 8. Ultra-Low-Input Voltage Converter for 2.5 V to 1.2 V at 5 A

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APPLICATION INFORMATION

330 µF

22 µF

+

VDD

3.3 V

Q1

Si4866DY

TPS40000/1/4

ILIM BOOT

1 µF

11 kΩ

1

2

3

4

5

10

9

1.8 Ω

3.3 Ω

VOUT

2.5 V

10 A

1.0 µH

L2

FB

HDRV

2.2 nF

12.7 kΩ

COMP

8

SW

2.2 Ω

470 pF

+

22 µF

7

SS/SD VDD

Q2

Si4866DY

0.01 µF

470 µF

1.8 Ω

22 µF

4.7 nF

6

GND LDRV

PWP

1 µF

24.9 kΩ

820 pF

1.27 kΩ

9.76 kΩ

UDG−02084

Figure 9. Ultra-High-Efficiency Converter for 3.3 V to 2.5 V at 10 A

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TYPICAL CHARACTERISTICS

OSCILLATOR FREQUENCY PERCENT CHANGE

vs

INPUT VOLTAGE

TEMPERATURE

6

5

4

3

2

1

0

1

0

−1

−2

−3

−4

−5

−6

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

−50

−25

0

25

50

75

100 125

V

IN

− Input Voltage − V

Temperature − °C

Figure 10

Figure 11

FEEDBACK VOLTAGE

vs

FEEDBACK VOLTAGE

vs

INPUT VOLTAGE

TEMPERATURE

0.707

0.705

0.7010

0.7005

0.7000

0.703

0.701

0.699

0.697

0.6995

0.6990

0.695

0.693

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

−50

−25

0

25

50

75

100

125

Temperature − °C

V

IN

− Input Voltage − V

Figure 12

Figure 13

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SLUS507C − JANUARY 2002 − REVISED JUNE 2004

TYPICAL CHARACTERISTICS

CURRENT LIMIT SINK CURRENT

vs

INPUT VOLTAGE

TEMPERATURE

16.0

15.5

15.0

14.5

14.0

13.5

13.0

15.0

14.5

14.0

12.5

−50

−25

0

25

50

75

100

125

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Temperature − °C

V

IN

− Input Voltage − V

Figure 14

Figure 15

TYPICAL PREDICTIVE

DELAY SWITCHING

OVERCURRENT

SS/SD Node

(1 V/div)

LDRV

(2 V/div)

SW Node

(2 V/ div)

SW Node

(2 V/ div)

t − Time − 1 ms/div

t − Time − 400 ns/div

Figure 16

Figure 17

19

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Post Office Box 655303 Dallas, Texas 75265


型号：	TPS40000DGQ
厂家：	TEXAS INSTRUMENTS
描述：	LOW-INPUT VOLTAGE-MODE SYNCHRONOUS BUCK CONTROLLER 低输入电压模式同步降压控制器输入元件控制器
文件：	总20页 (文件大小：290K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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