TPS40009DGQRG4 [TI]
LOW-INPUT HIGH-EFFICIENCY SYNCHRNOUS BUCK CONTROLLER; 低投入高效率SYNCHRNOUS降压控制器
| 型号： | TPS40009DGQRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW-INPUT HIGH-EFFICIENCY SYNCHRNOUS BUCK CONTROLLER |
| 文件： | 总28页 (文件大小：858K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005
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FEATURES
APPLICATIONS
D
D
D
D
D
D
Operating Input Voltage 2.25 V to 5.5 V
Output Voltage as Low as 0.7 V
1% Internal 0.7 V Reference
D
D
D
D
D
D
Networking Equipment
Telecom Equipment
Base Stations
Servers
Predictive Gate Drivet N-Channel MOSFET
Drivers for Higher Efficiency
DSP Power
Externally Adjustable Soft-Start and
Overcurrent Limit
Power Modules
DESCRIPTION
Fixed-Frequency Voltage-Mode Control
− TPS40007, 300 kHz
− TPS40009, 600 kHz
The TPS4000x are controllers for low-voltage,
non-isolated synchronous buck regulators. These
controllers drive an N-channel MOSFET for the
primary buck switch, and an N-channel MOSFET
for the synchronous rectifier switch, thereby
achieving very high-efficiency power conversion. In
addition, the device controls the delays from main
switch off to rectifier turn-on and from rectifier
turn-off to main switch turn-on in such a way as to
minimize diode losses (both conduction and
recovery) in the synchronous rectifier with TI’s
proprietary Predictive Gate Drivet technology. The
reduction in these losses is significant and increases
efficiency. For a given converter power level, smaller
FETs can be used, or heat sinking can be reduced
or even eliminated.
D
D
Source/Sink with V
Prebias
OUT
10-Lead MSOP PowerPadt Package for
Higher Performance
D
Thermal Shutdown
D
Internal Boostrap Diode
SIMPLIFIED APPLICATION DIAGRAM
V
IN
TPS40007
TPS40009
1
2
3
4
ILIM
BOOT 10
FB
HDRV
9
COMP
SS/SD
V
OUT
SW
VDD
8
7
6
5
GND
LDRV
UDG−03161
PowerPADt and Predictive Gate Drivet are trademarks of Texas Instruments Incorporated.
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Copyright 2003, 2004 Texas Instruments Incorporated
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SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005
DESCRIPTION (continued)
The current-limit threshold is adjustable with a single resistor connected to the device. The TPS4000x
controllers implement a closed-loop soft start function. Startup ramp time is set by a single external capacitor
connected to the SS/SD pin. The SS/SD pin is also used for shutdown.
ORDERING INFORMATION
(1)
T
FREQUENCY
300 kHz
PACKAGED DEVICES MSOP (DGQ)
A
TPS40007DGQ
TPS40009DGQ
−40°C to 85°C
600 kHz
(1)
The DGQ package is available taped and reeled. Add R suffix to device type (e.g.
TPS40007DGQR) to order quantities of 2,500 devices per reel and 80 units per tube.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(2)
TPS4000x
V + 6.5
SW
UNIT
BOOT
COMP, FB, ILIM, SS/SD
SW
−0.3 to 6.5
−3 to 10.5
−5
Input voltage range, V
IN
V
SW (SW transient < 50 ns)
T
VDD
6.5
Operating junction temperature range, T
−40 to 150
−55 to 150
260
J
Storage temperature, T
stg
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(2)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions”
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(3)(4)
DGQ PACKAGE
(TOP VIEW)
BOOT
HDRV
SW
ILIM
FB
1
2
3
4
5
10
9
8
7
6
COMP
SS/SD
GND
VDD
LDRV
ACTUAL SIZE
3,05mm x 4,98mm
(3)
(4)
See technical brief SLMA002 for PCB guidelines for PowerPAD packages.
PowerPADt heat slug should be connected to GND (pin 5).
2
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SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005
ELECTRICAL CHARACTERISTICS
temperature range, T = −40_C to 85_C, V
= 5.0 V, T = T ; all parameters measured at zero power dissipation
A
DD
A
J
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
INPUT SUPPLY
V
DD
Input voltage range
High-side gate voltage
Shutdown current
Quiescent current
Switching current
Minimum on-voltage
Hysteresis
2.25
5.5
V
V
− V
6
0.45
2.0
HGATE
BOOT
SW
SS/SD = 0 V,
FB = 0.8 V
Outputs off
0.25
1.4
1.5
I
mA
DD
No load at HDRV/LDRV
4.0
UVLO
1.95
80
2.05
150
2.15
220
V
mV
OSCILLATOR
TPS40007
TPS40009
250
500
300
600
350
700
f
Oscillator frequency
2.25 V ≤ V
DD
≤ 5.00 V
kHz
V
OSC
V
Ramp voltage
V
− V
0.80
0.24
0.93
0.31
1.07
0.44
RAMP
PEAK VALLEY
Ramp valley voltage
PWM
TPS40007
TPS40009
87.0%
83.0%
94.0%
93.0%
(2)
Maximum duty cycle
FB = 0 V,
V
DD
= 3.3 V
Minimum duty cycle
0%
(1)(3)
Minimum controllable pulse width
100
150
ns
ERROR AMPLIFIER
Line,
Temperature
0.690
0.693
0.700
0.700
30
0.711
0.707
130
V
FB input voltage
V
FB
T
A
= 25°C
I
FB input bias current
High-level output voltage
Low-level output voltage
Output source current
Output sink current
nA
FB
V
OH
V
OL
FB = 0 V,
FB =V
I
I
= 1.0 mA
= 0.5 mA
2.0
2.5
0.08
6
OH
V
,
0.15
DD
OL
I
I
COMP = 0.7 V,
COMP = 0.7 V,
FB = GND
FB = V
2
3
OH
mA
8
OL
DD
(1)
G
Gain bandwidth
5
10
MHz
dB
BW
A
OL
Open loop gain
55
85
SHORT CIRCUIT CURRENT PROTECTION
I
I
ILIM sink current
V
V
= 5 V
11
9.5
−20
2
15
13.0
0
19
16.5
20
µA
µA
mV
V
SINK
DD
ILIM sink current
= 2.25 V
SINK
DD
(1)
V
V
Offset voltage SW vs ILIM
2.25 V ≤ V ≤ 5.00
DD
OS
Input voltage range
VDD
330
ILIM
t
Minimum HDRV pulse time in overcurrent
SW leading edge blanking pulse in over-
V
DD
= 3.3 V
220
100
6
ns
ON
ns
(1)
current detection
(1)
t
Soft-start capacitor cycles as fault timer
Ensured by design. Not production tested.
Derate the maximum duty cycle by 3% for V
SS
(1)
(2)
(3)
< 3 V
DD
Operating at PWM on-times of less than 100 ns could lead to overlap between HDRV and LDRV pulses.
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SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005
ELECTRICAL CHARACTERISTICS
temperature range, T = −40_C to 85_C, V
= 5.0 V, T = T ; all parameters measured at zero power dissipation
A J
A
DD
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT DRIVER
V
−V = 3.3 V
BOOT SW ,
R
R
HDRV pull-up resistance
3
5.5
HDHI
I
= −100 mA
SOURCE
V
SINK
− V
= 3.3 V
,
BOOT
SW
HDRV pull-down resistance
1.5
3
HDLO
Ω
I
= 100 mA
= 3.3 V,
R
R
LDRV pull-up resistance
LDRV pull-down resistance
LDRV rise time
V
I
I
= −100 mA
3
1.0
15
10
15
10
5.5
2.0
35
25
35
25
LDHI
LDLO
RLD
DD
DD
SOURCE
= 100 mA
V
= 3.3 V,
SINK
t
t
t
t
LDRV fall time
FLD
C
= 1 nF
ns
LOAD
HDRV rise time
RHD
FHD
HDRV fall time
PREDICTIVE DELAY
V
Sense threshold to modulate delay time
Maximum delay modulation range time
Predictive counter delay time per bit
Maximum delay modulation range
Predictive counter delay time per bit
−350
70
mV
ns
SWP
T
LDRV OFF − to − HDRV ON
LDRV OFF − to − HDRV ON
HDRV OFF − to − LDRV ON
HDRV OFF − to − LDRV ON
45
95
6.2
110
6.6
LDHD
2.8
50
4.3
80
T
HDLD
3.0
4.8
SHUTDOWN
V
V
Shutdown threshold voltage
Outputs OFF
Outputs OFF
0.21
0.25
0.26
0.29
0.31
0.35
SD
V
Device active threshold voltage
EN
SOFTSTART
I
Soft-start source current
2.0
3.7
5.4
µA
SS
V
SS
Soft-start voltage to begin V
start
0.35
0.65
0.95
V
OUT
BOOTSTRAP
Bootstrap switch resistance
PRE-BIAS
V
V
= 3.3 V
= 5 V
50
35
100
70
DD
R
Ω
BOOT
DD
V
OUT
Recommended VOUT pre-bias level as
(1)(4)
FB percent of 700 mV
90%
2
% of final regulation
SW NODE
Leakage current in shutdown
THERMAL SHUTDOWN
Shutdown temperature
Restart from thermal shutdown
I
µA
°C
SW
(1)
t
165
−15
SD
(1)
(1)
(2)
(3)
(4)
Ensured by design. Not production tested.
Derate the maximum duty cycle by 3% for V
< 3 V.
DD
Operating at PWM on-times of less than 100 ns could lead to overlap between HDRV and LDRV pulses.
Prebiased output greater than 90% of final regulation may lead to sinking current from the prebias output.
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SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Provides a bootstrapped supply for the topside MOSFET driver, enabling the gate of the topside
MOSFET to be driven above the input supply rail
BOOT
10
O
COMP
FB
3
2
O
I
Output of the error amplifier
Inverting input of the error amplifier. In normal operation the voltage at this pin is the internal reference level of 700 mV.
Power supply return for the device. The power stage ground return on the board requires a separate path from other
sensitive signal ground returns.
GND
5
9
−
This is the gate drive output for the topside N-channel MOSFET. HDRV is bootstrapped to near 2 × V
for good en-
DD
HDRV
O
hancement of the topside MOSFET.
A resistor is connected between this pin and VDD to set up the over current threshold voltage. A 15-µA current sink at
the pin establishes a voltage drop across the external resistor that represents the drain-to-source voltage across the
top side N-channel MOSFET during an over current condition. The ILIM over current comparator is blanked for the
first 100 ns to allow full enhancement of the top MOSFET. Set the ILIM voltage level such that it is within 800 mV of
ILIM
1
6
I
V
DD
; that is, (V
− 0.8) ≤ I
≤ V .
DD
ILIM
DD
LDRV
O
Gate drive output for the low-side synchronous rectifier N-channel MOSFET
Soft-start and overcurrent fault shutdown times are set by charging and discharging a capacitor connected to this pin.
A closed loop soft-start occurs when the internal 3-µA current source charges the external capacitor. There is a 0.65-V
offset between external SS pin and internal soft-start voltage at the error amplifier input. This allows the device to be
SS/SD
4
I
enabled before starting V
, thus ensuring that V soft starts smoothly. When the SS/SD voltage is less than 0.25
OUT
OUT
V, the device is shutdown and the HDRV and LDRV are driven low. In normal operation, the capacitor is charged to
VDD. When a fault condition is asserted, the soft-start capacitor goes through six charge/discharge cycles, restarting
the converter on the seventh cycle.
Connect to the switched node on the converter. This pin is used for overcurrent sensing in the topside N-channel
MOSFET, and level sensing for predictive delay circuit. Overcurrent is determined, when the topside N-channel MOS-
FET is on, by comparing the voltage on SW with respect to VDD and the voltage on the ILIM with respect to VDD.
This pin is also used for the return of the topside N-channel MOSFET driver.
SW
8
7
O
I
VDD
Power input for the chip, 5.5-V maximum. Decouple close to the pin with a low-ESR capacitor, 1-µF or larger.
FUNCTIONAL BLOCK DIAGRAM
VDD
VDD
7
VDD
THERMAL
SHUTDOWN
LDRV
UVLO
2 V
ERROR AMPLIFIER
PWM COMP
10 BOOT
FB
2
+
+
HI
0.7 V
REF
UVLO
9
HDRV
PREDICTIVE
GATE
OSC
CLK
PWM
0.65 V
DRIVE
PWM
LOGIC
COMP
SS/SD
3
4
UVLO
3.7 µA
(VDD−1.2 V)
SS ACTIVE
FAULT
OC
8
6
1
SW
SOFT
START
FAULT
COUNTER
VDD
DISCHARGE
LO
LDRV
ILIM
100 ns DELAY
EN
0.26 V
SHUT DOWN
GND
5
CURRENT
LIMIT COMP
15 µA
UDG−03162
5
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SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
The TPS4000x series of synchronous buck controller devices is optimized for high-efficiency dc-to-dc
conversion in non-isolated distributed power systems. A typical application circuit is shown in Figure 1.
The TPS40007 and TPS40009 are the controllers of choice for general-purpose synchronous buck designs.
They are designed to startup into applications where the output voltage is pre-biased, and without having the
synchronous rectifier interfere with the pre-bias condition. PWM pulses are enabled when the soft-start voltage
crosses the feedback level dictated by the pre-bias output. Moreover, the pre-biased output ramps up smoothly
from its pre-bias value and into regulation.
V
DD
10 µF
100 µF
3.0 V to 5.5 V
20 kW
TPS40007
1
2
3
4
5
10
9
ILIM
BOOT
HDRV
SW
Si4866DY
FB
IHLP5050CE−01
V
10 A
1.8 V
OUT
3.6 nF
7.68 kΩ
100 nF
8
COMP
10 µF
243 Ω
470 µF
100 pF
7
Si4866DY
SS/SD VDD
4.7 nF
15.7 kΩ
3.3 nF
6
GND
LDRV
10 kΩ
UDG−03159
Figure 1. Typical Application Circuit
6
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SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
ERROR AMPLIFIER
The error amplifier has a bandwidth of greater than 5 MHz, with open loop gain of at least 55 dB. The COMP
output voltage is clamped to a level above the oscillator ramp in order to improve large-scale transient response.
OSCILLATOR
The oscillator uses an internal resistor and capacitor to set the oscillation frequency. The ramp waveform is a
sawtooth at the PWM frequency with a peak voltage of 1.25 V, and a valley of 0.31 V. The PWM duty cycle is
limited to a maximum of 94%, allowing the bootstrap capacitor to charge during every cycle.
BOOTSTRAP/CHARGE PUMP
There is an internal switch between VDD and BOOT. This switch charges the external bootstrap capacitor for
the floating supply. If the resistance of this switch is too high for the application, an external schottky diode
between VDD and BOOT can be used. The peak voltage on the bootstrap capacitor is approximately equal to
VDD.
DRIVER
The HDRV and LDRV MOSFET drivers are capable of driving gate-to-source voltages up to 5.5 V. At V , = 5 V
IN
and using appropriate MOSFETs, a 20-A converter can be achieved. The LDRV driver switches between VDD
and ground, while the HDRV driver is referenced to SW and switches between BOOT and SW.
SYNCHRONOUS RECTIFICATION AND PREDICTIVE DELAY
In a normal buck converter, when the main switch turns off, current is flowing to the load in the inductor. This
current cannot be stopped immediately without using infinite voltage. In order to provide a path for current to
flow and maintain voltage levels at a safe level, a rectifier or catch device is used. This device can be either a
conventional diode, or it can be a controlled active device if a control signal is available to drive it. The TPS4000x
provides a signal to drive an N-channel MOSFET as a rectifier. This control signal is carefully coordinated with
the drive signal for the main switch so that there is minimum delay from the time that the rectifier MOSFET turns
off and the main switch turns on, and minimum delay from when the main switch turns off and the rectifier
MOSFET turns on. This scheme, Predictive Gate Drivet delay, uses information from the current switching
cycle to adjust the delays that are to be used in the next cycle. Figure 2 shows the switch-node voltage waveform
for a synchronously rectified buck converter. Illustrated are the relative effects of a fixed-delay drive scheme
(constant, pre-set delays for the turn-off to turn-on intervals), an adaptive delay drive scheme (variable delays
based upon voltages sensed on the current switching cycle) and the predictive delay drive scheme.
Note that the longer the time spent in diode conduction during the rectifier conduction period, the lower the
efficiency. Also, not described in Figure 2 is the fact that the predictive delay circuit can prevent the body diode
from becoming forward biased at all. This results in a significant power savings when the main MOSFET turns
on, and minimizes reverse recovery loss in the body diode of the rectifier MOSFET.
7
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SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
GND
Channel Conduction
Body Diode Conduction
Fixed Delay
Adaptive Delay
Predictive Delay
UDG−03166
Figure 2. Switch Node Waveforms for Synchronous Buck Converter
SHORT CIRCUIT PROTECTION
Overcurrent conditions in the TPS4000x are sensed by detecting the voltage across the main MOSFET while
it is on.
Basic Description
If the voltage exceeds a pre-set threshold, the current pulse is terminated, and a counter inside the device is
incremented. If this counter fills up, a fault condition is declared and the device disables switching for a period
of time and then attempts to restart the converter with a full soft-start cycle.
8
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SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
Detailed Description
During each switching cycle, a comparator looks at the voltage across the top side MOSFET while it is on. This
comparator is enabled after the SW node reaches a voltage greater than (V −1.2 V) followed by a 100-ns
DD
blanking time. If the voltage across that MOSFET exceeds the programmed voltage, the current-switching pulse
is terminated and a 3-bit counter is incremented by one count. If, during the switching cycle, the topside
MOSFET voltage does not exceed a preset threshold, then this counter is decremented by one count. (The
counter does not wrap around from 7 to 0 or from 0 to 7). If the counter reaches a full count of 7, the device
declares that a fault condition exists at the output of the converter. In this fault state, HDRV and LDRV are turned
off, and the soft-start capacitor is discharged. LDRV is maintained OFF during fault timeout to effectively support
pre-bias applications. The counter is decremented by one by the soft start capacitor (C ) discharge. When the
SS
soft-start capacitor is fully discharged, the discharging circuit is turned off and the capacitor is allowed to charge
up at the nominal charging rate. When the soft-start capacitor reaches approximately 1.3 V, it is discharged
again and the overcurrent counter is decremented by one count. The capacitor is charged and discharged, and
the counter decremented until the count reaches zero (a total of six times). When this happens, the outputs are
again enabled as the soft-start capacitor generates a reference ramp for the converter to follow while attempting
to restart.
During this soft-start interval (whether or not the controller is attempting to do a fault recovery or starting for the
first time), pulse-by-pulse current limiting is in effect, but overcurrent pulses are not counted to declare a fault
until the soft-start cycle has been completed. It is possible to have a supply attempt to bring up a short circuit
for the duration of the soft start period plus seven switching cycles. Power stage designs should take this into
account if it makes a difference thermally. Figure 3 shows the details of the overcurrent operation.
(+)
V
TS
(−)
Short Circuit Protection
Threshold Voltage
Internal PWM
V
TS
0V
External
Main Drive
Normal
Cycle
Overcurrent
Cycle
UDG−03165
Figure 3. Short Circuit Operation
9
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ꢀ ꢁ ꢂ ꢃ ꢄꢄ ꢄ ꢅ
ꢀ ꢁ ꢂ ꢃ ꢄꢄ ꢄ ꢆ
SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
Figure 4 shows the behavior of key signals during initial startup, during a fault and a successfully fault recovery.
At time t0, power is applied to the converter. The voltage on the soft-start capacitor (V ) begins to ramp up.
CSS
At t1, the soft-start period is completed and the converter is regulating its output at the desired voltage level.
From t0 to t1, pulse-by-pulse current limiting is in effect, and from t1 onward, overcurrent pulses are counted
for purposes of determining a possible fault condition. At t2, a heavy overload is applied to the converter. This
overload is in excess of the overcurrent threshold. The converter starts limiting current and the output voltage
falls to some level depending on the overload applied. During the period from t2 to t3, the counter is counting
overcurrent pulses, and at time t3 reaches a full count of 7. The soft-start capacitor is then discharged, the
counter is decremented, and a fault condition is declared.
V
DD
V
CSS
~ 1.3 V
~ 0.6 V
0.6 V
FAULT
I
LOAD
V
OUT
t
t4
t0
t1
t2 t3
t5
t6
t7
t8
t9
t10
COUNTER
0
6
5
4
3
2
1
0
1
2 3 4 5 6 7
UDG−03160
Figure 4. Overcurrent/Fault Waveforms
When the soft start capacitor is fully discharged, it begins charging again at the same rate that it does on startup,
with a nominal 3.7-µA current source. When the capacitor voltage crosses 1.3 V, it is discharged again and the
counter is decremented by one count. These transitions occur at t3 through t9. Not shown in Figure 4 is that
between t3 and t9, LDRV is maintained OFF. At t9, the counter has been decremented to 0. The fault logic is
then cleared, the outputs are enabled, and the converter attempts to restart with a full soft-start cycle. The
converter comes into regulation at t10.
10
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ꢀꢁ ꢂ ꢃꢄ ꢄꢄ ꢅ
ꢀꢁ ꢂ ꢃꢄ ꢄꢄ ꢆ
SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
SETTING THE CURRENT LIMIT
Connecting a resistor from VDD to ILIM sets the current limit. A 15-µA current sink internal to the device causes
a voltage drop at ILIM that becomes the short circuit threshold. Ensure that (V −0.8 V) ≤ V ≤ V . The
DD
ILIM
DD
tolerance of the current sink is too loose to do an accurate current limit. The main purpose is for hard fault
protection of the power switches. Given the tolerance of the ILIM sink current, and the R range for a
DS(on)
MOSFET, it is generally possible to apply a load that thermally damages the converter. This device is intended
for embedded converters where load characteristics are defined and can be controlled.
A local capacitor (with a value 50 pF to 150 pF) placed across the resistor between VDD and ILIM may improve
coupling a common mode noise between VDD and ILIM.
SOFT-START AND SHUTDOWN
These two functions are combined on the SS/SD pin. There is a VBE offset (0.65-V) between the external SS/SD
pin and internal soft-start voltage at the error amplifier input, allowing the device to be enabled before starting
V
as shown in Figure 5. This reduces the transient current required to charge the output capacitor at startup,
OUT
and allows for a smooth startup with no overshoot of the output voltage.
SS/SD
(200 mV/ div)
FB
(200 mV/ div)
t − Time − 1 ms/div
Figure 5. Offset Between SS/SD and FB at Startup
11
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ꢀ ꢁ ꢂ ꢃ ꢄꢄ ꢄ ꢅ
ꢀ ꢁ ꢂ ꢃ ꢄꢄ ꢄ ꢆ
SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
A shutdown feature can be implemented as shown in Figure 6. The device shuts down when the voltage at the
SS/SD pin falls below 260 mV. Because of this limitation, it is recommended that a MOSFET be used as the
controlling device, as in Figure 6. During shutdown, the total leakage current on the SW pin (I ) is less than
SW
2 µA. When V
is greater than 290 mV, the device is enabled with normal SW active bias currents.
SS/SD
TPS40007/9
3.7 µA
SS/SD
ERROR AMPLIFIER
4
+
+
0.7 V
FB
COMP
SDN
C
R
SS
SHUTDOWN
0.26 V
+
UDG−01163
Figure 6. Shutdown Implementation
Long soft start times may experience extended regions where the PWM pulse width is less than 100 ns. This
could lead to momentary overlap between HDRV and LDRV. As a result, there is a momentary increase in
ground or supply noise. It is important to ensure that the ground return of the synchronous rectifier be connected
directly to the ground return of the input bank of bypass capacitors, in order to minimize ground noise from
interfering with the controller during soft start. Also, if an external shutdown transistor is used in the application,
it is important to place a local bypass capacitor between its gate and source on the board in order to minimize
noise from interfering with the controller during soft-start.
OUTPUT PRE-BIAS
The TPS4000x supports pre-biased V
voltage applications. In cases, where the V
voltage is held up by
OUT
OUT
a pre-biasing supply while the controller is off, full synchronous rectification is disabled during the initial phase
of soft starting the V voltage. When the first PWM pulses are detected during soft-start, the controller slowly
OUT
activates synchronous rectification by starting the first LDRV pulses with a narrow on-time. It then increments
that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1−D), where D is the duty cycle
of the converter. This scheme prevents the initial sinking the pre-bias output, and ensures that the V
voltage
OUT
starts and ramps up smoothly into regulation. Note, if the V
voltage is pre-biased, PWM pulses start when
OUT
the error amplifier soft-start input voltage rises above the commanded FB voltage.
Figure 7 depicts the waveforms of the HDRV and LDRV output signals at the beginning PWM pulses. When
HDRV turns off, diode rectification is enabled. Before the next PWM cycle starts, LDRV is turned on for a short
pulse. With every cycle, the leading edge of LDRV is modulated, and the on-time of the synchronous rectifier
is increased. Eventually, the leading edge of LDRV coincides with the falling edge of HDRV to achieve full
synchronous rectification.
At most, synchronous rectifier modulation takes place for the first 128 cycles after PWM pulses start. Note that
during the synchronous rectifier modulation region, the controller monitors pulse skipping. If the main HDRV
skips a pulse, the controller also skips a LDRV pulse. Pulse skipping could be experienced if the loop response
is much faster than the commanding soft-start ramp, especially when soft start times are long. The output
voltage ratchets up as the soft-start ramp catches up to it. Appropriate setting of loop response curbs this effect.
During normal regulation of the V
voltage, the controller operates in full two-quadrant source/sink mode.
OUT
12
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ꢀꢁ ꢂ ꢃꢄ ꢄꢄ ꢅ
ꢀꢁ ꢂ ꢃꢄ ꢄꢄ ꢆ
SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
Figure 8 shows startup waveforms of a 1.2-V V
voltage under different pre-bias scenarios. The first trace
OUT
is when the output voltage starts with zero pre−bias. The second and third traces, respectively, the pre-bias
levels are 0.5 V and 1.0 V.
V
V
= 5 V
IN
= 1.2 V
OUT
(200 mV/div)
PREBIAS = 1 V
V
HDRV
PREBIAS = 0.5 V
PREBIAS = 0 V
V
LDRV
t − Time − 2 µs/div
t − Time − 500 µs/div
Figure 8.
Startup Waveforms
Figure 7.
MOSFET Drivers at Beginning of Soft-Start
The recommended V
voltage pre-bias range is less than or equal to 90% of final regulation. That is, a
OUT
pre-bias level between 90% and 100% of final regulation could lead to sinking the pre-bias supply. If the V
OUT
voltage is initially set to higher than 100% of final regulation, the controller forces sinking current at the end of
soft-start in order to bring the output quickly into regulation.
The following pages include design ideas for a few applications. For more ideas, detailed design information,
and helpful hints, visit the TPS40000 resources at http://power.ti.com.
13
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ꢀ ꢁ ꢂ ꢃ ꢄꢄ ꢄ ꢅ
ꢀ ꢁ ꢂ ꢃ ꢄꢄ ꢄ ꢆ
SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
V
DD
3.3 V
22 µF
22 µF
15 kΩ
TPS40009
1
2
3
4
5
10
9
FDS6894A
ILIM
BOOT
HDRV
SW
1.0 µH
FB
V
1.2 V
5 A
OUT
1 nF
8.66 kΩ
1 µF
COMP
8
2.2 Ω
22 µF
22 µF
7
SS/SD VDD
68 pF
FDS6894A
4.7 nF
6
GND
LDRV
0.0033 µF
1 µF
PWP
12.1 kΩ
1 kΩ
470 pF
16.9 kΩ
UDG−03164
Figure 9. Small-Form Factor Converter for 3.3 V to 1.2 V at 5 A.
14
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ꢀꢁ ꢂ ꢃꢄ ꢄꢄ ꢅ
ꢀꢁ ꢂ ꢃꢄ ꢄꢄ ꢆ
SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
UDG−04014
Figure 10. High-Current Converter for 3.3 V to 1.2 V at 10 A.
15
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ꢀ ꢁ ꢂ ꢃ ꢄꢄ ꢄ ꢅ
ꢀ ꢁ ꢂ ꢃ ꢄꢄ ꢄ ꢆ
SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
VDD
2.5 V
BAT54
22 µF
22 µF
15 kΩ
FDS6894A
TPS40009
1 µF
1
2
3
4
5
10
9
ILIM
BOOT
HDRV
SW
VOUT
1.2 V
5 A
1.0 µH
L1
FB
1500 pF
5.62 kΩ
COMP
8
2.2 Ω
7
SS/SD VDD
100 pF
22 µF
22 µF
4.7 nF
FDS6894A
6
GND
LDRV
PWP
3.3 nF
1 µF
6.19 kΩ
1000 pF
536 Ω
8.66 kΩ
UDG−04028
Figure 11. Ultra-Low-Input Voltage Converter for 2.5 V to 1.2 V at 5 A
16
www.ti.com
ꢀꢁ ꢂ ꢃꢄ ꢄꢄ ꢅ
ꢀꢁ ꢂ ꢃꢄ ꢄꢄ ꢆ
SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
V
IN
= 3.3 V
1
2
+
+
C5
22 µF
J1 3
4
C4
22 µF
C2
330 µF
C3
22 µF
C1
330 µF
C6
1 µF
R2
16.2 kΩ
TPS40007DGQ
Q1
Si4866DY
1
2
3
4
5
BOOT 10
ILIM
FB
L1
1.0 µH
9
8
7
6
HDRV
SW
V
OUT
= 2.5 V
10 A
R4
5.9 kΩ
C7
1.5 nF
COMP
SS/SD
GND
1
2
R3
2.2 Ω
Q2
Si4866DY
+
+
VDD
LDRV
3
4
J2
C13
4.7 nF
C9
470 µF
C8
470 µF
C11
180 pF
C12
10n F
C14
1 µF
PWP
R6
10 kΩ
C15
6.8 nF
R7
698 Ω
R8
3.92 kΩ
UDG−03169
Figure 12. TPS40007EVM−001 Ultra-High-Efficiency Converter for 3.3 V to 2.5 V at 10 A
17
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ꢀ ꢁ ꢂ ꢃ ꢄꢄ ꢄ ꢅ
ꢀ ꢁ ꢂ ꢃ ꢄꢄ ꢄ ꢆ
SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
Layout Considerations
Successful operation of the TPS4000x controllers is dependent upon proper converter layout and grounding
techniques. High current returns for the SR MOSFET’s source, and ground connection of the input and output
capacitors, should be kept on a single ground plane. Bypassing capacitors at the device should return closely
to the GND (pin 5) of the device. The GND (pin 5) and PowerPAD should connect together at the device and
return to the main ground plane.
Proper operation of the Predictive Gate Drive circuits is dependent upon detecting low-voltage thresholds on
the SW node. To ensure that the signal at the SW pin accurately represents the voltage at the main switching
node, the connection from SW (pin 8) to the main switching node of the converter should be kept as short and
as wide as possible. If the SW trace should traverse multiple board layers between the device and the
MOSFETs, multiple vias should be used.
Gate drive outputs, LDRV and HDRV, should be kept as short as possible to minimize inductances of the traces.
While the controller does not require the usage of external resistors between the driver pins and the gates of
the MOSFETs, adding small resistors in series with very high gate charge MOSFETs could minimize the effects
of high frequency ringing.
The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD
derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit
board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depend
on the size of the PowerPAD package (See Thermal Pad Mechanical Data on page 21)
18
www.ti.com
ꢀꢁ ꢂ ꢃꢄ ꢄꢄ ꢅ
ꢀꢁ ꢂ ꢃꢄ ꢄꢄ ꢆ
SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005
TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY PERCENT CHANGE
OSCILLATOR FREQUENCY PERCENT CHANGE
vs
vs
INPUT VOLTAGE
TEMPERATURE
6
5
4
3
2
1
0
1
0
−1
−2
−3
−4
−5
−6
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
−50
−25
0
25
50
75
100 125
Temperature − °C
V
IN
− Input Voltage − V
Figure 14
Figure 13
FEEDBACK VOLTAGE
vs
FEEDBACK VOLTAGE
vs
INPUT VOLTAGE
TEMPERATURE
0.707
0.705
0.7010
0.7005
0.7000
0.703
0.701
0.699
0.697
0.6995
0.6990
0.695
0.693
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
−50
−25
0
25
50
75
100
125
Temperature − °C
V
IN
− Input Voltage − V
Figure 15
Figure 16
19
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ꢀ ꢁ ꢂ ꢃ ꢄꢄ ꢄ ꢅ
ꢀ ꢁ ꢂ ꢃ ꢄꢄ ꢄ ꢆ
SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005
TYPICAL CHARACTERISTICS
CURRENT LIMIT SINK CURRENT
CURRENT LIMIT SINK CURRENT
vs
vs
INPUT VOLTAGE
TEMPERATURE
16.0
15.5
15.5
15.0
14.5
14.0
13.5
13.0
15.0
14.5
14.0
12.5
−50
−25
0
25
50
75
100
125
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Temperature − °C
V
IN
− Input Voltage − V
Figure 17
Figure 18
SHORT CIRCUIT PROTECTION
SS/SD Node
SW Node
t − Time − 1 ms/div
Figure 19
20
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
22-Apr-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TPS40007DGQ
ACTIVE
MSOP-
Power
PAD
DGQ
10
10
10
10
10
10
10
10
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS40007DGQG4
TPS40007DGQR
TPS40007DGQRG4
TPS40009DGQ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
MSOP-
Power
PAD
DGQ
DGQ
DGQ
DGQ
DGQ
DGQ
DGQ
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS40009DGQG4
TPS40009DGQR
TPS40009DGQRG4
MSOP-
Power
PAD
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Apr-2008
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Feb-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
2500
2500
2500
2500
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS40007DGQR
TPS40007DGQR
TPS40009DGQR
TPS40009DGQR
MSOP-
Power
PAD
DGQ
DGQ
DGQ
DGQ
10
10
10
10
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
5.3
5.3
5.3
5.3
3.4
3.3
3.3
3.4
1.4
1.3
1.3
1.4
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
MSOP-
Power
PAD
MSOP-
Power
PAD
MSOP-
Power
PAD
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Feb-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS40007DGQR
TPS40007DGQR
TPS40009DGQR
TPS40009DGQR
MSOP-PowerPAD
MSOP-PowerPAD
MSOP-PowerPAD
MSOP-PowerPAD
DGQ
DGQ
DGQ
DGQ
10
10
10
10
2500
2500
2500
2500
364.0
346.0
346.0
364.0
364.0
346.0
346.0
364.0
27.0
35.0
35.0
27.0
Pack Materials-Page 2
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