TPS40075RHLTG4 [TI]
具有电压前馈的 4.5V 至 28V 同步降压控制器 | RHL | 20 | -40 to 85;
| 型号： | TPS40075RHLTG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有电压前馈的 4.5V 至 28V 同步降压控制器 | RHL | 20 | -40 to 85 开关 控制器 开关式稳压器 开关式控制器 电源电路 开关式稳压器或控制器 |
| 文件： | 总44页 (文件大小：811K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS40075
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SLUS676–MAY 2006
MIDRANGE INPUT SYNCHRONOUS BUCK CONTROLLER
WITH VOLTAGE FEED-FORWARD
The TPS40075 drives external N-channel MOSFETs
using second generation Predictive Gate Drive to
minimize conduction in the body diode of the low
side FET and maximize efficiency. Pre-biased
outputs are supported by not allowing the low side
FET to turn on until the voltage commanded by the
closed loop soft start is greater than the pre-bias
voltage. Voltage feed forward provides good
response to input transients and provides a constant
PWM gain over a wide input voltage operating range
to ease compensation requirements. Programmable
short circuit protection provides fault current limiting
and hiccup recovery to minimize power dissipation
with a shorted output. The 20 pin QFN package
gives good thermal performance and a compact
footprint.
FEATURES
•
•
•
Operation Over 4.5-V to 28-V Input Range
Fixed-Frequency Voltage-Mode Controller
Integrated Unity Gain Amplifier for Remote
Output Sensing
•
Predictive Gate Drive™ Generation II for
Improved Efficiency
•
•
•
•
<1% Internal 700-mV Reference
Input Voltage Feed Forward Control
Prebiased Output Compatible
Internal Gate Drive Outputs for High-Side and
Synchronous N-Channel MOSFETs
•
•
•
•
Switching Frequency Programmable to 1 MHz
20-Pin QFN Package
SIMPLIFIED APPLICATION DIAGRAM
Thermal Shutdown Protection
V
−
V
+
OUT
OUT
(at Load)
(at Load)
Software Design Tool and EVM Available
1
20
APPLICATIONS
SA−
SA+
•
•
•
•
Power Modules
Networking/Telecom
Industrial
TPS40075
SYNC IN
2
3
4
5
6
SAO
GND
SS
SYNC 19
PGD 18
LVBP 17
RT 16
PowerGood OUT
Servers
CONTENTS
FB
COMP
KFF 15
Device Ratings
2
Electrical Characteristics
Terminal Information
Application Information
Design Example
4
7
8
PGND
LDRV
ILIM 14
VDD 13
V
IN
12
15
26
40
9
DBP
HDRV 12
SW
10
BOOST
11
Additional References
DESCRIPTION
The TPS40075 is a mid voltage, wide input (4.5-V to
28-V), synchronous, step-down controller, offering
design flexibility for a variety of user programmable
functions, including; soft start, UVLO, operating
frequency, voltage feed-forward and high-side FET
sensed short circuit protection.
V
OUT
−
V
+
OUT
UDG−04075
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Predictive Gate Drive is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS40075
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SLUS676–MAY 2006
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SLUS676–MAY 2006
ORDERING INFORMATION
TA
PACKAGE
PART NUMBER
TPS40075RHLT(1)
TPS40075RHLR(2)
40°C to 85°C
Plastic QFN (RHL)
(1) The TPS40075 is available taped and reeled only. Add an T suffix (i.e. TPS40075RHLT) to the orderable part number for quantities of
250 units per small reel. .
(2) Add an R suffix (i.e. TPS40075RHLR) to the orderable part number for quantities of 3,000 units per large reel.
DEVICE RATINGS
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TPS40075
30
UNIT
VDD, ILIM
FB, KFF, PGD, SYNC
SW
–0.3 to 6
–0.3 to 40
–0.3 to 11
–2.5
VDD
Input voltage range
SA+, SA-
SW, transient < 50 ns
COMP, RT, SS
BOOST, HDRV
DBP, SAO, LDRV
LVBP
V
–0.3 to 6
50
VOUT
Output voltage range
10.5
6
IOUT
IOUT
Output current source
Output current sink
LDRV, HDRV
LDRV, HDRV
KFF
1.5
A
2.0
10
RT
1
mA
°C
IOUT
Output current source
LVBP
1.5
TJ
Operating junction temperature range
Storage temperature
–40 to 125
–55 to 150
Tstg
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIIONS
MIN NOM
MAX
28
UNIT
V
VDD
TA
Input voltage
4.5
-40
Operating free-air temperature
85
°C
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
PARAMETER
MIN
TYP
MAX
UNIT
Human body model
CDM
1500
1500
V
V
PACKAGE DISSIPATION RATINGS(1)
THERMAL IMPEDANCE
AIRFLOW (LFM)
JUNCTION-TO-AMBIENT
TA = 25°C POWER RATING (W) TA = 85°C POWER RATING (W)
(°C/W)
Natural Convection
200
42
35
2.38
2.85
0.95
1.14
(1) For more information on the RHL package and the test method, refer to TI technical brief, literature number SZZA017. The ratings in this
table are for the JEDEC High-K board.
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PACKAGE DISSIPATION RATINGS (continued)
THERMAL IMPEDANCE
AIRFLOW (LFM)
400
JUNCTION-TO-AMBIENT
TA = 25°C POWER RATING (W) TA = 85°C POWER RATING (W)
(°C/W)
31
3.22
1.29
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SLUS676–MAY 2006
ELECTRICAL CHARACTERISTICS
TA = –40°C to 85°C, VIN = 12 Vdc, RT = 90.9 kΩ, IKFF = 300 µA, fSW = 500 kHz, all parameters at zero power dissipation
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT SUPPLY
VDD Input voltage range, VIN
OPERATING CURRENT
4.5
28
3.5
4.5
V
mA
V
IDD
Quiescent current
Output drivers not switching
2.5
4.2
LVBP
VLVBP
Output voltage
TA = TJ = 25°C
3.9
OSCILLATOR/RAMP GENERATOR
fOSC
VRT
Accuracy
450
500
550 kHz
RT voltage
2.23
2.40
2.58
150
5
V
tON(min)
VIH
Minimum output pulse time(1)
High-level input voltage, SYNC
Low-level input voltage, SYNC
Input current, SYNC
CHDRV = 0 nF
ns
2
V
VIL
0.8
ISYNC
5
0.40
12
10
µA
VFB = 0 V, 100 kHz ≤ fSW ≤ 500 kHz
84%
76%
0.35
20
95%
93%
0.45
1100
Maximum duty cycle
VFB = 0 V, fSW = 1 MHz
VKFF
IKFF
Feed-forward voltage
Feed-forward current operating range(1)
V
µA
SOFT START
ISS
Charge current
9.5
25
14.5
75
µA
µs
tDSCH
Discharge time
CSS = 3.9 nF
CSS = 3.9 nF, VSS rising from 0.7 V to 1.6
V
tSS
Soft-start time
210
290
275
500
VSSSD
VSSEN
Shutdown threshold, VSS falling
Enable threshold, VSS rising
225
310
35
325
410
130
mV
V
VSSSDHYS Shutdown threshold hysteresis
DBP
VDD > 10 V
7
8
9
VDBP
Output voltage
VVDD = 4.5 V, IOUT = 25 mA
4.0
4.3
ERROR AMPLIFIER
TA = TJ = 25°C
0.698 0.700 0.704
0.690 0.700 0.707
0.690 0.700 0.715
1
VFB
Feedback regulation voltage total variation
0°C ≤ TA = TJ ≤ 85°C
-40°C ≤ TA = TJ ≤ 85°C
Offset from VSS to error amplifier
V
VSS(offset) Soft-start offset from VSS(1)
GBWP
AVOL
ISRC
Gain bandwidth(1)
5
50
10
MHz
dB
Open loop gain
Output source current
Output sink current
Input bias current
2.5
4.5
6
mA
nA
ISINK
IBIAS
2.5
VFB = 0.7 V
–250
0
SHORT CIRCUIT CURRENT PROTECTION
IILIM Current sink into ILIM pin
VILIM(ofst) Current limit offset voltage
115
–50
135
–30
135
50
150
–10
225
µA
mV
ns
VILIM = 11.5 V, (VSW - VILIM) VVDD = 12 V
During short circuit
tHSC
Minimum HDRV pulse width
Propagation delay to output(1)
Blanking time(1)
ns
tBLANK
50
ns
(1) Ensured by design. Not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
TA = –40°C to 85°C, VIN = 12 Vdc, RT = 90.9 kΩ, IKFF = 300 µA, fSW = 500 kHz, all parameters at zero power dissipation
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
7
MAX UNIT
tOFF
VSW
tPC
Off time during a fault (SS cycle times)
Switching level to end precondition(1)
cycles
V
(VVDD - VSW
)
2
(2)
Precondition time
100
ns
V
VILIM(pre) Current limit precondition voltage threshold(2)
6.8
OUTPUT DRIVERS
tHFALL
tHRISE
tHFALL
tHRISE
tLFALL
tLRISE
tLFALL
tLRISE
High-side driver fall time(2)
High-side driver rise time(2)
High-side driver fall time(2)
High-side driver rise time(2)
Low-side driver fall time(2)
Low-side driver rise time(2)
Low-side driver fall time(2)
Low-side driver rise time(2)
36
48
CHDRV = 2200 pF, (HDRV - SW)
ns
ns
ns
ns
V
72
CHDRV = 2200 pF, (HDRV - SW)
VVDD= 4.5 V
96
24
CLDRV = 2200 pF
48
48
CLDRV = 2200 pF, VDD= 4.5 V
96
IHDRV= -0.01 A, (VBOOST- VHDRV
IHDRV = -0.1 A, (VBOOST - VHDRV
(VHDRV - VSW), IHDRV = 0.01A
(VHDRV - VSW), IHDRV = 0.1 A
(VDBP - VLDRV), ILDRV= -0.01A
(VDBP - VLDRV), ILDRV = -0.1 A
ILDRV = 0.01 A
)
0.7
0.95
0.06
0.65
0.65
1.0
1.35
0.10
1.00
1.00
VOH
VOL
VOH
VOL
High-level output voltage, HDRV
Low-level output voltage, HDRV
High-level output voltage, LDRV
Low-level output voltage, LDRV
)
V
V
0.875 1.300
0.03
0.3
0.05
0.5
V
ILDRV = 0.1 A
BOOST REGULATOR
VBOOST
UVLO
VUVLO
Output voltage
VVDD= 12 V
15.2
17.0
V
Programmable UVLO threshold voltage
Programmable UVLO hysteresis
Fixed UVLO threshold voltage
Fixed UVLO hysteresis
RKFF = 90.9 kΩ, turn-on, VVDD rising
RKFF = 90.9 kΩ
6.2
1.10
4.15
275
7.2
1.55
4.30
365
8.2
2.00
4.45
V
Turn-on, VVDD rising
mV
POWER GOOD
VPGD
VFBH
VFBL
Powergood voltage
IPGD = 1 mA
370
770
630
550
High-level output voltage, FB
Low-level output voltage, FB
mV
mV
SENSE AMPLIFIER
VSA+ = VSA- = 1.25 V, Offset referenced to
SA+ and SA-
VIO
Input offset voltage
-9
9
ADIFF
VICM
RG
Differential gain
VSA+ - VSA- = 4.5 V
0.995 1.000 1.005
Input common mode range(3)
Internal resistance for setting gain
Output source current
Output sink current
0
14
2
6
26
15
35
V
20
10
25
2
kΩ
IOH
mA
IOL
15
GBWP
Gain bandwidth(2)
MHz
THERMAL SHUTDOWN
Shutdown temperature threshold(2)
165
15
°C
Hysteresis(2)
(2) Ensured by design. Not production tested.
(3) 3 V at internal amplifier terminals, 6 V at SA+ and SA- pins.
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TYPICAL CHARACTERISTICS
LVBP VOLTAGE
vs
JUNCTION TEMPERATURE
DBP VOLTAGE
vs
JUNCTION TEMPERATURE
8.15
8.10
4.30
4.25
4.20
V
DD
= 28 V
V
DD
= 28 V
8.05
8.00
V
DD
= 12 V
4.15
V
DD
= 12 V
7.95
7.90
7.85
4.10
4.05
7.80
4.00
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
T − Junction Temperature − °C
J
T − Junction Temperature − °C
J
Figure 1.
Figure 2.
DBP VOLTAGE
vs
JUNCTION TEMPERATURE
BOOTSTRAP DIODE VOLTAGE
vs
JUNCTION TEMPERATURE
4.50
4.49
2.0
1.9
V
= 4.5 V
= 25 mA
DD
I
LOAD
4.48
4.47
1.8
1.7
1.6
1.5
4.46
4.45
4.44
4.43
1.4
1.3
4.42
4.41
1.2
1.1
1.0
4.40
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
T − Junction Temperature − °C
J
T − Junction Temperature − °C
J
Figure 3.
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
CURRENT LIMIT OFFSET VOLTAGE
CURRENT LIMIT SINK CURRENT
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
150
145
0
−10
−20
140
135
+3 S
130
125
Average
−30
120
115
−40
−50
VDD
28 V
12 V
4.5 V
−3 S
110
105
100
−60
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
T − Junction Temperature − °C
J
T − Junction Temperature − °C
J
Figure 5.
Figure 6.
FEEDBACK REGULATION VOLTAGE
SENSE AMPLIFIER OUTPUT CURRENT
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
704
30
25
20
15
VDD
28 V
4.5 V
12 V
703
702
Low Level Output Current
701
10
5
High Level Output Current
700
699
698
0
−5
−10
−15
697
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
T − Junction Temperature − °C
J
T − Junction Temperature − °C
J
Figure 7.
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
CURRENT SENSE AMPLIFIER GAIN
SWITCHING FREQUENCY
vs
vs
JUNCTION TEMPERATURE
INPUT VOLTAGE
500
499
1.0005
1.000
R
RT
= 90.1kΩ
498
497
V
= 2.5 V
DD
0.9995
0.9990
0.9985
0.9980
0.9975
0.9970
V
= 4.5 V
DD
496
495
V
DD
= 1.25 V
494
493
V
= 0.5 V
DD
492
491
490
0.9965
−50
−25
0
25
50
75
100
125
4
8
12
16
20
24
28
T − Junction Temperature − °C
J
V
VDD
− Input Voltage − V
Figure 9.
Figure 10.
MAXIMUM DUTY CYCLE
vs
JUNCTION TEMPERATURE
UNDERVOLTAGE LOCKOUT
vs
JUNCTION TEMPERATURE
93
92
4.35
4.30
91
90
V
4.25
4.20
UVLO(on)
f
SW
= 100 kHZ
89
88
87
86
4.15
4.10
f
SW
= 500 kHZ
4.05
V
UVLO(off)
4.00
3.95
85
84
f
SW
= 1 MHZ
83
−50
3.90
−50
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
T − Junction Temperature − °C
J
T − Junction Temperature − °C
J
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
PROGRAMMABLE UVLO THRESHOLD
SOFTSTART CHARGING CURRENT
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
1.10
1.08
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
V
UVLO(off)
V
1.06
1.04
UVLO(on)
1.02
1.00
0.98
0.96
0.94
0.92
0.90
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
T − Junction Temperature − °C
J
T − Junction Temperature − °C
J
Figure 13.
Figure 14.
ERROR AMPLIFIER INPUT BIAS CURRENT
MINIMUM OUTPUT VOLTAGE
vs
vs
JUNCTION TEMPERATURE
FREQUENCY
0
5.0
V
V
= 28 V
= 24 V
IN
−10
4.5
4.0
3.5
3.0
IN
V
= 18 V
−20
−30
−40
IN
V
IN
= 15 V
V
IN
= 12 V
V
= 10 V
IN
V
= 8 V
IN
−50
−60
2.5
2.0
1.5
V
IN
= 5 V
−70
−80
−90
1.0
0.5
−50
−25
0
25
50
75
100
125
100 200 300 400 500 600 700 800 900 1000
f
− Oscillator Frequency − kHz
OSC
T − Junction Temperature − °C
J
Figure 15.
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
SWITCHING FREQUENCY
TYPICAL SWITCHING FREQUENCY
vs
vs
TIMING RESISTANCE
INPUT VOLTAGE
520
515
510
600
500
400
300
200
505
500
495
490
485
480
100
0
0
2
6
10
14
18
22
26
30
200
400
600
800
1000
V
DD
− Input Voltage − V
f
SW
− Switching Frequency − kHz
Figure 17.
Figure 18.
UVLO THRESHOLD VOLTAGE
vs
FEEDFORWARD IMPEDANCE
UVLO THRESHOLD VOLTAGE
vs
FEEDFORWARD IMPEDANCE
20
20
f
SW
= 500 kHz
f
SW
= 300 kHz
UVLOV
ON
UVLOV
ON
18
16
18
16
14
14
12
10
12
10
UVLOV
OFF
UVLOV
OFF
8
6
8
6
4
2
4
2
60
90
120
150
180
210
240
270
100
150
200
250
300
350
400
450
R
KFF
− Feedforward Impedance − kΩ
R
KFF
− Feedforward Impedance − kΩ
Figure 19.
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
UVLO THRESHOLD VOLTAGE
TYPICAL MAXIMUM DUTY CYCLE
vs
vs
FEEDFORWARD IMPEDANCE
INPUT VOLTAGE
100
90
20
UVLO
= 15 V
(on)
f
SW
= 750 kHz
UVLOV
ON
18
16
80
70
UVLO
= 8 V
(on)
UVLO
= 12 V
14
(on)
12
10
UVLOV
OFF
60
UVLO
= 4.5 V
(on)
50
8
6
40
4
2
30
20
40
60
80
100
120
140
160
180
4
8
12
16
20
24
28
R
KFF
− Feedforward Impedance − kΩ
V
IN
− Input Voltage − V
Figure 21.
Figure 22.
INPUT VOLTAGE
vs
DBP VOLTAGE
INPUT VOLTAGE
vs
LOW VOLTAGE BYPASS VOLTAGE
10
4.50
4.45
4.40
9
8
7
4.35
4.30
4.25
4.20
4.15
6
5
4.10
4.05
4.00
4
5
10
15
20
25
30
0
5
10
15
20
25
V
DD
− Input Voltage − V
V
DD
− Input Voltage − V
Figure 23.
Figure 24.
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TERMINAL INFORMATION
RHL PACKAGE
(BOTTOM VIEW)
19
18
17
16
15
14
13
12
2
3
4
5
6
7
8
9
SYNC
PGD
LVBP
RT
SAO
GND
SS
20
1
FB
KFF
COMP
PGND
LDRV
DBP
ILIM
VDD
HDRV
11
10
Table 1. TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
The BOOST voltage is 8-V greater than the input voltage. The peak voltage on BOOST is equal to the SW node
voltage plus the voltage present at DBP less the bootstrap diode drop. This drop can be 1.4 V for the internal
bootstrap diode or 300 mV for an external schottkey diode. The voltage differential between this pin and SW is
the available drive voltage for the high-side FET.
BOOST
11
I
Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the
FB pin to compensate the overall loop. This pin is internally clamped to a 3.4-V maximum output drive capability
for quicker recovery from a saturated feedback loop situation.
COMP
DBP
6
9
O
O
8-V regulator output used for the gate drive of the N-channel synchronous rectifier and as the supply for charging
the bootstrap capacitor. This pin should be bypassed to ground with a 1.0-µF ceramic capacitor.
Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal reference
voltage, 0.7 V.
FB
5
3
I
-
GND
HDRV
Ground reference for the device.
Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW
(MOSFET off).
12
O
Short circuit protection programming pin. This pin is used to set the overcurrent threshold. An internal current sink
from this pin to ground sets a voltage drop across an external resistor connected from this pin to VDD. The
voltage on this pin is compared to the voltage drop (VVDD -VSW) across the high side N-channel MOSFET during
conduction. Just prior to the beginning of a switching cycle this pin is pulled to approximately VVDD/2 and released
when SW is within 2 V of VVDD or after a timeout (the precondition time) - whichever occurs first. Placing a
capacitor across the resistor from ILIM to VDD allows the ILIM threshold to decrease during the switch on time,
effectively programming the ILIM blanking time. See Applications Information section.
ILIM
14
15
I
A resistor is connected from this pin to VDD programs the amount of input voltage feed-forward. The current fed
into this pin is used to control the slope of the PWM ramp and program undervoltage lockout. Nominal voltage at
this pin is maintained at 400 mV.
KFF
I
Gate drive for the N-channel synchronous rectifier. This pin switches from DBP (MOSFET on) to PGND (MOSFET
off). For proper operation, the total gate charge of the MOSFET connected to LDRV should be less than 50nC.
LDRV
LVBP
PGD
8
O
O
O
4.2-V reference used for internal device logic and analog functions. This pin should be bypassed to GND with a
0.1-µF ceramic capacitor. External loads less than 1 mA and electrically quiet may be applied.
17
18
This is an open drain output that pulls to ground when soft start is active, or when the FB pin is outside a ±10%
band around the 700 mV reference voltage.
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TERMINAL INFORMATION (continued)
Table 1. TERMINAL FUNCTIONS (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of
the lower MOSFET(s).
PGND
7
RT
16
20
1
I
I
A resistor is connected from this pin to GND to set the switching frequency.
Noninverting input of the remote voltage sense amplifier.
Inverting input of the remote voltage sense amplifier.
Output of the remote voltage sense amplifier.
SA+
SA-
SAO
I
2
O
Soft-start programming pin. A capacitor connected from this pin to GND programs the soft-start time. The
capacitor is charged with an internal current source of 12 µA. The resulting voltage ramp on the SS pin is used as
a second non-inverting input to the error amplifier. The voltage at this error amplifier input is approximately 1 V
less that that on the SS pin. Output voltage regulation is controlled by the SS voltage ramp until the voltage on
the SS pin reaches the internal offset voltage of 1 V plus the internal reference voltage of 700 mV. If SS is below
the internal offset voltage of 1 V (300 mV minimum ensured), the resulting output voltage is zero. Also provides
timing for fault recovery attempts. Pulling this pin below 250 mV causes the controller to enter a shutdown state
with HDRV and LDRV held in a low state.
SS
4
I
This pin is connected to the switched node of the converter and used for overcurrent sensing as well as gate drive
timing. This pin is also the return path from the high-side FET for the floating high-side FET driver. A 1.5-Ω
resistor in series with this pin is required for protection against substrate current issues.
SW
10
I
SYNC
VDD
19
13
I
I
Logic input for pulse train to synchronize oscillator.
Supply voltage for the device.
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SIMPLIFIED BLOCK DIAGRAM
TPS40075
9
DBP
VDD
Reference
Regulator
UVLO
UVLO
VDD 13
LVBP 17
RT 16
14 ILIM
Controller
Ramp
Generator
Oscillator
SW
Pulse
Control
CLK
SYNC 19
KFF 15
R
R
20 SA+
+
SAO
2
1
SA−
R
PGD 18
R
770 mV
FB
630 mV
Power
Good
Logic
GND
3
10 SW
SS Active
Overcurrent
Comparator
and Control
RAMP
ILIM
CLK
OC
LVBP
OC
Soft Start
and
CLK
DBP
11 BOOST
12 HDRV
Fault Control
OC
CLK
Predictive
Gate Drive
Control
FB
5
PWM
SW
700 mV
Logic
+
+
UVLO
8
7
LDRV
PGND
SS
4
6
PGND
COMP
FAULT
IZERO
UDG−04076
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APPLICATION INFORMATION
The TPS40075 allows the user to construct synchronous voltage mode buck converters with inputs ranging from
4.5 V to 28 V and outputs as low as 700 mV. Predictive gate drive circuitry optimizes switching delays for
increased efficiency and improved converter output power capability. Voltage feed-forward is employed to ease
loop compensation for wide input range designs and provide better line transient response.
An on-board unity gain differential amplifier is provided for remote sensing in applications that require the
tightest load regulation. The TPS40075 incorporates circuitry to allow startup into a pre-existing output voltage
without sinking current from the source of the pre-existing output voltage. This avoids damaging sensitive loads
at startup. The controller can be synchronized to an external clock source or can free run at a user
programmable frequency. An integrated power good indicator is available for logic (open drain) output of the
condition of the output of the converter.
MINIMUM PULSE WIDTH
The TPS40075 has limitations on the minimum pulse width that can be used to design a converter. Reliable
operation is guaranteed for nominal pulse widths of 150 ns and above. This places some restrictions on the
conversion ratio that can be achieved at a given switching frequency. See Figure 16.
SLEW RATE LIMIT ON VDD
The regulator that supplies power for the drivers on the TPS40075 requires a limited rising slew rate on VDD for
proper operation if the input voltage is above 10 V. If the slew rate is too great, this regulator can over shoot and
damage to the part can occur. To ensure that the part operates properly, limit the slew rate to no more than
0.12 V/µs as the voltage at VDD crosses 8 V. If necessary, an R-C filter can be used on the VDD pin of the
device. Connect the resistor from the VDD pin to the input supply of the converter. Connect the capacitor from
the VDD pin to PGND. There should not be excessive (more than a 200-mV) voltage drop across the resistor in
normal operation. This places some constraints on the R-C values that can be used. Figure 25 is a schematic
fragment that shows the connection of the R-C slew rate limit circuit. Equation 1 and Equation 2 give values for
R and C that limits the slew rate in the worst case condition.
TPS40075
R
ILIM 14
13 VDD
VIN
HDRV 12
+
C
_
SW 10
7
PGND
LDRV
8
UDG−05058
Figure 25. Limiting the Slew Rate
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APPLICATION INFORMATION (continued)
0.2 V
Q
R t
f
) I
IDD
SW
g(TOT)
(1)
(2)
V
* 8 V
VIN
C u
R SR
where
•
•
•
•
•
VVIN is the final value of the input voltage ramp
fSW is the switching frequency
Qg(TOT) is the combined total gate charge for both upper and lower MOSFETs (from MOSFET data sheet)
IIDD is the TPS40075 input current (3.5 mA maximum)
SR is the maximum allowed slew rate [12 ×104] (V/s)
SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR)
The TPS40075 has independent clock oscillator and PWM ramp generator circuits. The clock oscillator serves
as the master clock to the ramp generator circuit. Connecting a single resistor from RT to ground sets the
switching frequency of the clock oscillator. The clock frequency is related to RT by:
1
R + ǒ
T
* 23ǓkW
*6
f
(kHz) 17.82 10
SW
(3)
PROGRAMMING THE RAMP GENERATOR CIRCUIT AND UVLO FUNCTION
The ramp generator circuit provides the actual ramp used by the PWM comparator and provides voltage
feed-forward by varying the PWM ramp slope as the line voltage changes. As the input voltage to the converter
increases, the slope of the PWM ramp increase by a proportionate amount. The programmable UVLO circuit
works by monitoring the level reached by the PWM ramp during a clock cycle. The PWM ramp must reach
approximately 1 V in amplitude during a clock cycle, or the converter is not be allowed to start. This
programmable UVLO point is set via a single resistor (RKFF) connected from KFF to VDD. RKFF , VSTART and RRT
are related by (approximately)
2
*3
*5
2
T
R
+ 0.131 R V
* 1.61 10 V
) 1.886 V
* 1.363 * 0.02 R * 4.87 10 R
UVLO T
KFF
T
UVLO(on)
UVLO(on)
(4)
where
•
•
VUVLO(on) is in volts
RKFF and RT are in kΩ
This yields typical numbers for the programmed startup voltage. The minimum and maximum values may vary
up ±15% from this number. Figure 19 through Figure 21 show the typical relationship of VUVLO(on), VUVLO(off) and
RKFF at three common frequencies.
The programmable UVLO circuit incorporates 20% hysteresis from the start voltage to the shutdown voltage. For
example, if the startup voltage is programmed to be 10 V, the controller starts when VDD reaches 10 V and shuts
down when VDD falls below 8 V. The maximum duty cycle begins to decrease as the input voltage rises to twice
the startup voltage. Below this point, the maximum duty cycle is as specified in the electrical table. Note that with
this scheme, the theoretical maximum output voltage that the converter can produce is approximately two times
the programmed startup voltage. For design, set the programmed startup voltage equal to or greater than the
desired output voltage divided by maximum duty cycle (85% for frequencies 500 kHz and below). For example,
a 5-V output converter should not have a programmed startup voltage below 5.9 V. Figure 22 shows the
theoretical maximum duty cycle (typical) for various programmed startup voltages
If the programmable UVLO voltage is set below 6.5V nominal, a possibility exists that the part may enter factory
test mode when powered down. This can cause an undesired output rise as power is removed from the
converter. To prevent this from happening, connect a 330 kΩresistor from SS to GND. An example of this can
be seen in Figure 37
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APPLICATION INFORMATION (continued)
Figure 26 shows the effect of changing input voltage on the duty cycle, and how that change takes place. The
pulse width modulator (PWM) ramp input is generated using a current that is proportional to the current into the
KFF pin. The TPS40075 holds this pin at a constant 400 mV, so connecting a resistor from KFF to the input
power supply causes a current to flow into the KFF pin that is proportional to the input voltage. The slope of the
ramp signal to the PWM is therefore proportional to the input voltage. This allows the duty cycle to change with
variations in Vin without requiring much response from the error amplifier, resulting in very good line transient
response. Another benefit is essentially constant PWM gain over the entire input voltage operating range. This
makes the output control loop easier to design for a wide input range converter.
VIN
VIN
SW
SW
RAMP
V
PEAK
COMP
COMP
RAMP
V
VALLEY
T
1
T
2
t
ON2
t
ON1
tON
T
d +
t
> t
and d > d
ON2 1 2
ON1
VDG−03172
Figure 26. Voltage Feed-Forward and PWM Duty Cycle Waveforms
PROGRAMMING SOFT START
TPS40075 uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft-start is
programmed by connecting an external capacitor (CSS) from the SS pin to GND. This capacitor is charged by a
fixed current, generating a ramp signal. The voltage on SS is level shifted down approximately 1 V and fed into a
separate non-inverting input to the error amplifier. The loop is closed on the lower of the level shifted SS voltage
or the 700-mV internal reference voltage. Once the level shifted SS voltage rises above the internal reference
voltage, output voltage regulation is based on the internal reference. To ensure a controlled ramp-up of the
output voltage the soft-start time should be greater than the L-COUT time constant or:
ǸL C
t
w 2p
(seconds)
START
OUT
(5)
where
•
•
•
L is the value of the filter inductor
COUT is the value of the output capacitance
tSTART is the output ramp up-time
For a desired soft-start time, the soft-start capacitance, CSS, can be found from:
I
SS
C
+ t
SS
SS
V
FB
(6)
Please note: There is a direct correlation between tSTART and the input current required during start-up. The
lower tSTART is, the higher the input current required during start-up since the output capacitance must be
charged faster.
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APPLICATION INFORMATION (continued)
PROGRAMMING SHORT CIRCUIT PROTECTION
The TPS40075 uses a two-tier approach to short circuit protection. The first tier is a pulse-by-pulse protection
scheme. Short circuit protection is implemented by sensing the voltage drop across the high-side MOSFET while
it is turned on. The MOSFET drain to source voltage is compared to the voltage dropped across a resistor (RILIM
)
connected from VDD to the ILIM pin. The voltage drop across this resistor is produced by a constant current
sink. If the voltage drop across the MOSFET exceeds the voltage drop across the ILIM resistor the switching
pulse is immediately terminated. The MOSFET remains off until the next switching cycle is initiated.
In addition, just prior to the high-side MOSFET turning on, the ILIM pin is pulled down to approximately half of
VDD. The ILIM pin is allowed to return to its nominal value after one of two events occur:
1. The SW node rises to within approximately 2 V of VDD
2. An internal timeout occurs, approximately 125-ns after ILIM is initially pulled down
If the SW node rises to within approximately 2-V of VDD, the device allows ILIM to go back to its nominal value.
This is illustrated in Figure 27 A. T1 is the delay time from the internal PWM signal being asserted and the rise
of SW. This includes the driver delay of 50 ns typical, and the turn on time of the high-side MOSFET. The
MOSFET used should have a turn on time less than 75 ns. T2 is the reaction time of the sensing circuit that
allows ILIM to start to return to its nominal value, typically 20ns.
ILIM
ILIM Threshold
(A)
Overcurrent
VIN − 2V
SW
T2
ILIM
ILIM Threshold
VIN − 2V
T1
(B)
SW
T1
T3
UDG−03173
Figure 27. Switching and Current Limit Waveforms and Timing Relationship
The second event that can cause ILIM to return to its nominal value is for an internal timeout to expire. This is
illustrated in Figure 27 B as T3. Here SW never rises to VDD-2, for whatever reason, and the internal timer
times out. This allows the ILIM pin to start its transition back to its nominal value.
Prior to ILIM starting back to its nominal value, short circuit sensing is not enabled. In normal operation, this
insures that the SW node is at a higher voltage than ILIM when short circuit sensing starts, avoiding false trips
while allowing for a quicker blanking delay than would ordinarily be possible. Placing a capacitor across RILIM
sets an exponential approach to the normal voltage at the ILIM pin. This exponential “decay” of the short circuit
threshold can be used to compensate for ringing on the SW node after its rising edge and to help compensate
for slower turn-on MOSFETs. Choosing the proper capacitance requires care. If the capacitance is too large, the
voltage at ILIM does not approach the desired short circuit level quickly enough, resulting in an apparent shift in
short circuit threshold as pulse width changes.
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APPLICATION INFORMATION (continued)
The comparator that looks at ILIM and SW to determine if a short circuit condition exists has a clamp on its SW
input. This clamp makes the SW node never appear to fall more than 1.4 V (approximately, could be as much as
2 V at – 40°C) below VDD. While ILIM is more than 1.4 V below VDD short circuit sensing is effectively disabled,
giving a programmable absolute blanking time. As a general rule, it is best to make the time constant of the R-C
at the ILIM pin 20% or less of the nominal pulse width of the converter (See Equation 11)
The second tier protection incorporates a fault counter. The fault counter is incremented on each cycle with an
overcurrent pulse and decremented on a clock cycle without an overcurrent pulse. When the counter reaches
seven (7) a fault condition is declared by the controller. When this happens, the output drivers turn both
MOSFETs off. Seven soft-start cycles are initiated (without activity on the HDRV and LDRV outputs) and the
PWM is disabled during this period. The counter is decremented on each soft-start cycle. When the counter is
decremented to zero the PWM is re-enabled and the controller attempts to restart. If the fault has been removed
the output starts up normally. If the output fault is still present the counter counts seven overcurrent pulses and
re-enters the second tier fault mode. Refer to Figure 28 for typical fault protection waveforms.
HDRV
Clock
t
BLANKING
V
ILIM
VIN SW
V
−V
SS
7 Current Limit Trips
(HDRV Cycle Terminated by Current Limit Trip)
7
Soft-Start
Cycles
VDG−03174
Figure 28. Typical Fault Protection Waveforms
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APPLICATION INFORMATION (continued)
The minimum short circuit limit threshold (ISCP) depends on tSTART, COUT, VOUT, and the load current at turn-on
(ILOAD).
C
V
OUT
t
OUT
I
u
) I
(A)
LOAD
SCP
START
(7)
The short circuit limit programming resistor (RILIM) is calculated from:
I
R
) V
DS(onMAX) ILIM (ofst)
SCP
R
+
W
ILIM
I
ILIM
(8)
where
•
•
•
•
IILIM is the current into the ILIM pin (135 µA typical)
VILIM(ofst) is the offset voltage of the ILIM comparator (-30 mV typical)
ISCP is the short-circuit protection current
RDS(on)MAX is the drain-to-source resistance of the high-side MOSFET
To find the range of the short circuit threshold values use the following equations.
I
R
) 50 mV
ILIM(max)
ILIM
DS(onMIN)
I
+
A
SCP(max)
R
(9)
I
R
) 10 mV
ILIM
ILIM(min)
I
+
A
SCP(min)
R
DS(onMAX)
(10)
The TPS40075 provides short-circuit protection only. As such, it is recommended that the minimum short circuit
protection level be placed at least 20% above the maximum output current required from the converter. The
maximum output of the converter should be the steady state maximum output plus any transient specification
that may exist.
The ILIM capacitor maximum value can be found from:
V
0.2
R f
ILIM
OUT
C
+
(Farads)
ILIM(max)
V
IN
SW
(11)
Note that this is a recommended maximum value. If a smaller value can be used, it should be to improve
protection. For most applications, consider using half the maximum value shown in Equation 11.
BOOST AND DBP BYPASS CAPACITANCE
The BOOST capacitance provides a local, low-impedance flying source for the high-side driver. The BOOST
capacitor should be a good quality, high-frequency ceramic capacitor. A minimum value of 100-nF is suggested.
The DBP capacitor has to provide energy storage for switching both the synchronous MOSFET and the
high-side MOSFET (via the BOOST capacitor). The suggested value for this capacitor is 1-µF ceramic,
minimum.
INTERNAL REGULATORS
The internal regulators are linear regulators that provide controlled voltages for the drivers and the internal
circuitry to operate from. The low-side driver operates directly from the 8-V regulator supply while the high-side
driver bootstrap capacitor is charged from this supply. The actual voltage delivered to the high-side driver is the
voltage on the DBP pin less any drop from the bootstrap diode. If the internal bootstrap diode is used, the drop
across that diode is nominally 1.4 V at room temperature. This regulator has two modes of operation. At
voltages below 8.5 V on VDD, the regulator is in a low dropout mode of operation and tries to provide as little
impedance as possible from VDD to DBP. When VDD is above 10 V, the regulator regulates DBP to 8 V.
Between these two voltages, the regulator is in whatever state it was in when VDD entered this region. The
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APPLICATION INFORMATION (continued)
LVBP pin is connected to a 4.2-V regulator that supplies power for the internal control circuitry. Small amounts of
current can be drawn from these pins for other external circuit functions, as long as power dissipation in the
controller chip remains at acceptable levels and junction temperature does not exceed 125°C. Any external load
connected to LVBP should be electrically quiet to avoid degrading performance of the TPS40075. Typical output
voltages for these two regulators are shown in Figure 23 and Figure 24.
DIFFERENTIAL SENSE AMPLIFIER
The TPS40075 has an on board differential amplifier intended for use as a remote sensing amplifier for the
output voltage. Use of this amplifier for remote sensing eliminates load regulation issues due to voltage drops
that occur between the converter and the actual point of load. The amplifier is powered from the DBP pin and
can be used to monitor output voltages up to 6 V with a DBP voltage of 8 V. For lower DBP voltages, the sense
amplifier can be used to monitor output voltages up to 2-V below the DBP voltage. The internal resistors used to
configure the amplifier for unity gain match each other closely, but their absolute values can vary as much as
30%, so adding external resistance to alter the gain is not accurate in a production environment.
SYNCHRONIZATION
The SYNC pin accepts logic level signals and is used to synchronize the TPS40075 to an external clock source.
Synchronization occurs on the rising edge of the signal at the SYNC pin. There is a fixed delay of approximately
300 ns from the rising edge of the waveform at SYNC to the HDRV output turning on the high-side FET. The pin
may be left floating in this function is not used, or it may be connected to GND. The frequency of the external
clock must be greater than the free running frequency of the device as set by the resistor on the RT pin (RRT).
This pin requires a totem pole drive, or open collector/drain if pull up resistor to either LVBP or a separate supply
between 2.5 V and 5 V is used. Synchronization does not affect the modulator gain due to the voltage feed
forward circuitry. The programmable UVLO thresholds are affected by synchronization. The thresholds are
shifted by the ratio of the sync frequency to the free running frequency of the converter. For example,
synchronizing to a frequency 20% higher than the free running frequency results in the programmable UVLO
thresholds shifting up 20% from their calculated free run values. The synchronization frequency should be kept
less than 1.5 times the free run frequency for best performance, although higher multiples can be used.
POWERGOOD OPERATION
The PGD pin is an open drain output that actively pulls to GND if any of the following conditions are met
(assuming that the input voltage is above 4.5 V)
•
•
•
•
•
•
Soft-start is active (VVSS < 3.5 V)
VFB < 0.63 V
VFB > 0.77 V
Programmable UVLO condition not satisfied (VIN below programmed level)
Overcurrent condition exists
Die temperature is greater than 165°C
PRE-BIASED OUTPUTS
Some applications require that the converter not sink current during startup if a pre-existing voltage exists at the
output. Since synchronous buck converters inherently sink current some method of overcoming this
characteristic must be employed. Applications that require this operation are typically power rails for a multi
supply processor or ASIC. The method used in this controller, is to not allow the low side or rectifier FET to turn
on until there the output voltage commanded by the start up ramp is higher than the pre-existing output voltage.
This is detected by monitoring the internal pulse width modulator (PWM) for its first output pulse. Since this
controller uses a closed loop startup, the first output pulse from the PWM does not occur until the output voltage
is commanded to be higher than the pre-existing voltage. This effectively limits the controller to sourcing current
only during the startup sequence.
If the pre-existing voltage is higher that the intended regulation point for the output of the converter, the
converter starts and sinks current when the soft-start time has completed
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APPLICATION INFORMATION (continued)
SHUTDOWN AND SEQUENCING
The TPS40075 can be shut down by pulling the SS pin to a level below 250 mV. Pulling the pin low resets the
internal pre-bias circuitry to ensure that the converter does not damage sensitive loads.
Automatic startup sequencing can be accomplished by connecting the PGD pin of a master supply based on the
TPS40075 to the SS pin of a slave supply. The master comes up first and release the salve SS pin to allow the
slave to come up. Controlled shutdown of sequenced supplies can be accomplished by either pulling the SS pin
of the master below the shutdown threshold and letting the PGD pin pull the slave SS pin down, or by pulling
down the SS pins of all supplies simultaneously.
TPS40075 POWER DISSIPATION
The power dissipation in the TPS40075 is largely dependent on the MOSFET driver currents and the input
voltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver power
(neglecting external gate resistance) can be calculated from:
P
+ Q V f
(Wattsńdriver)
SW
g
D
DR
(12)
where
•
VDR is the driver output voltage
The total power dissipation in the TPS40075, assuming the same MOSFET is selected for both the high-side
and synchronous rectifier is described in Equation 13.
2 P
P + ǒ Ǔ
D
) I
V
(Watts)
IN
T
Q
V
DR
(13)
(14)
or
P + ǒ2 Q f
Ǔ
) I V (Watts)
g
T
SW
Q
IN
where
•
IQ is the quiescent operating current (neglecting drivers)
The maximum power capability of the TPS40075 PowerPAD package is dependent on the layout as well as air
flow. The thermal impedance from junction to air ambient assuming 2-oz. copper trace and thermal pad with
solder and no air flow is θJA = 60 °C/W
The maximum allowable package power dissipation is related to ambient temperature by Equation 15.
T * T
J
A
P +
(Watts)
T
q
JA
(15)
Substituting Equation 15 into Equation 14 and solving for fSW yields the maximum operating frequency for the
TPS4007x. The result is described in Equation 16.
ǒ
AǓ
T *T
ƪ ƫ* I
ǒ Ǔ
J
Q
ǒ
INǓ
q
V
JA
f
+
(Hz)
SW
ǒ
gǓ
2 Q
(16)
BOOST DIODE
The TPS40075 has internal diodes to charge the boost capacitor connected from SW to BOOST. The drop
across this diode is rather large at 1.4-V nominal at room temperature resulting in the drive voltage to the
high-side MOSFET being reduced by this amount from the DBP voltage. If this drop is too large for a particular
application, an external diode may be connected from DBP (anode) to BOOST (cathode). This provides
significantly improved gate drive for the high-side MOSFET, especially at lower input voltages.
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APPLICATION INFORMATION (continued)
GROUNDING AND BOARD LAYOUT
The TPS40075 provides separate signal ground (GND) and power ground (PGND) pins. Care should be given
to proper separation of the circuit grounds. Each ground should consist of a plane to minimize its impedance if
possible. The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling
capacitor (DBP), and the input capacitor should be connected to PGND plane.
Sensitive nodes such as the FB resistor divider and RT should be connected to the GND plane. The GND plane
should only make a single point connection to the PGND plane. It is suggested that the GND pin be tied to the
copper area for the PowerPAD underneath the chip. Tie the PGND to the PowerPAD copper area as well and
make the connection to the power circuit ground from the PGND pin. Reference the output voltage divider to the
GND pin.
Component placement should ensure that bypass capacitors (LVPB and DBP) are located as close as possible
to their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be
located near high dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW). Failure to follow
careful layout practices results in sub-optimal operation.
SYNCHRONOUS RECTIFIER CONTROL
Table 2 describes the state of the rectifier MOSFET control under various operating conditions.
Table 2. Synchronous Rectifier MOSFET States
SYNCHRONOUS RECTIFIER OPERATION DURING
FAULT
SOFT-START
NORMAL
(FAULT RECOVERY IS SAME
AS SOFT-START)
OVERVOLTAGE
Off until first high-side pulse is
detected, then on when high-side
MOSFET is off
Turns off at the start of a new
cycle. Turns on when the
high-side MOSFET is turned off
Turns OFF only at start of next
cycle ON if duty cycle is > 0
OFF
For proper operation, the total gate charge of the MOSFET connected to LDRV should be less than 50nC.
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DESIGN EXAMPLE
1. SPECIFICATIONS
PARAMETER
INPUT CURRENT
TEST CONDITIONS
MIN
10.8
1.47
TYP
MAX UNIT
VIN
VO
Input voltage
12.0
1.5
13.2
Output voltage
IOUT = 10 A
5
V
Regulation
1.53
VRIPPLE
VOVER
VUNDER
ILOAD
ISCP
Output ripple voltage
Output overshoot
Output undershoot
Output current
IO(max) = 15 A
ISTEP = 8 A
ISTEP = 8 A
30
50
50
mV
A
0
15
30
Short circuit current trip point
Efficiency
16
η
VIN = 12 V, ILOAD = 15 A
85%
400
fSW
Switching frequency
kHz
2. SCHEMATIC
V
IN
−SENSE
+SENSE
SYNC
C
IN
ELCO
1
20
SA−
SA+
C
PZ1
R
P1
TPS40075
R
KFF
R
LIM
R
Z1
2
3
4
5
6
7
8
9
SAO
GND
SS
SYNC 19
PGD 18
LVBP 17
RT 16
R
PGD
C
Z2
C
P2
R
PZ2
FB
COMP
PGND
LDRV
DBP
KFF 15
ILIM 14
VDD 13
HDRV 12
BOOST
C
LIM
QSW
L
V
O
C
VDD
C
VLVBP
SW
10
R
T
11
1.5 Ω
QSR
R
SET2
R
SET1
D
BOOST
C
O
C
BOOST
C
O
ELCO MLCC
C
DBP
C
SS
0V
UDG−04125
Figure 29. TPS40075 Reference Design Schematic
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3. COMPONENT SELECTION
3. 1 Power Train Components
Designers familiar with the buck converter can skip to section 3.2 Component Selection for TPS40075.
3.1.1 Output Inductor, LO
The output inductor is one of the most important components to select. It stores the energy necessary to keep
the output regulated when the switch MOSFET is turned off. The value of the output inductor dictates the peak
and RMS currents in the converter. These currents are important when selecting other components. Equation 17
can be used to calculate a value for L.
ǒ
OǓ
* V
V
V
IN(max)
O
L +
V
f
DI
SW
IN(max)
(17)
∆ I is the allowable ripple in the inductor. Selecting ∆I also sets the output current when the converter goes into
discontinuous mode (DCM) operation. Since this converter utilizes MOSFETs for the rectifier, DCM is not a
major concern. Select ∆I to be between 20% and 30% of maximum ILOAD. For this design, ∆I of 3 A was
selected. The calculated L is 1.1 µH. A standard inductor with value of 1.0 µH was chosen. This increases ∆I by
about 10% to 3.3 A.
With this ∆I value, calculate the RMS and peak current flowing in LO. Note this peak current is also seen by the
switching MOSFET and synchronous rectifier.
2
2
DI
+ Ǹ
I
I
)
+ 15.03 A
LOAD_RMS
LOAD
12
(18)
(19)
2
DI
I
+ I
)
+ 16.65 A
PK
LOAD
2
3.1.2 Output Capacitor, CO, ELCO and MLCC
Several parameters must be considered when selecting the output capacitor. The capacitance value should be
selected based on the output overshoot, VOVER, and undershoot, VUNDER, during a transient load, ISTEP, on the
converter. The equivalent series resistance (ESR) is chosen to allow the converter meet the output ripple
specification, VRIPPLE. The voltage rating must be greater than the maximum output voltage. Other parameters to
consider are: equivalent series inductance which is important in fast transient load situations. Also size and
technology can be factors when choosing the output capacitor. In this design a large capacitance electrolytic
type capacitor, CO ELCO, is used to meet the overshoot and under shoot specifications. Its ESR is chosen to
meet the output ripple specification. While a smaller multiple layer ceramic capacitor, CO MLCC, is used to filter
high frequency noise.
The minimum required capacitance and maximum ESR can be calculated using the equations below.
2
L I
STEP
C
u
O
ǒ
OǓ
V * V
MAX IN
2 V
D
UNDER
(20)
2
L I
STEP
C
u
O
2 V
V
O
OVER
(21)
(22)
V
RIPPLE
DI
ESR t
Using Equation 20 through Equation 22, the capacitance for CO should be greater than 495 µF and its ESR
should be less than 9.1mΩ. The 1000 µF/25 V capacitor from Rubycon's MBZ or Panasonic's series EEU-FL
was chosen. Its ESR is 19 mΩ, so two in parallel are used. The slightly higher ESR is offset by the four times
increase in capacitance. A 2.2 µF/16 V MLCC is also added in parallel to reduce high frequency noise.
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3.1.3. Input Capacitor, CIN, ELCO and MLCC
The input capacitor is selected to handle the ripple current of the buck stage. Also a relative large capacitance is
used to keep the ripple voltage on the supply line low. This is especially important where the supply line is high
impedance. It is recommended that the supply line be kept low impedance. The input capacitor ripple current
can be calculated using Equation 23.
2
Ǔ) ƫ
D ) I
2
2
DI
12
ƪǒ
+ Ǹ
(
1 * D)
IN(avg)
I
I
* I
CAP(RMS)
LOAD(max)
IN(avg)
(23)
where
•
IIN(avg) is the average input current
This is calculated simply by multiplying the output DC current by the duty cycle. The ripple current in the input
capacitor is 5.05 A. A 1206 MLCC using X7R material has a typical dissipation factor of 5%. For a 2.2 µF
capacitor at 400 kHz the ESR is approximately 7.2 mΩ. If two capacitors are used in parallel the power
dissipation in each capacitor is less than 46 mW.
A 470 µF/16 V electrolytic capacitor is added to maintain the voltage on the input rail.
3.1.4 Switching MOSFET, QSW
The following key parameters must be met by the selected MOSFET.
•
Drain source voltage, VDS, must be able to withstand the input voltage plus spikes that may be on the
switching node. For this design a VDS rating of 25 V to 30 V is recommended.
•
Drain current, ID, at 25°C, must be greater than that calculated using Equation 24. For this design, ID should
be greater than 5 A.
V
2
2
DI
)
O
ǒ
I
Ǔ
I
+
ǸV
D
LOAD(max)
12
IN(min)
(24)
•
Gate source voltage, VGS must be able to withstand the gate voltage from the control device . For the
TPS40075 this is 9 V.
Once the above boundary parameters are defined the next step in selecting the switching MOSFET is to select
the key performance parameters. Efficiency is the performance characteristic which drives the other selection
criteria. Target efficiency for this design is 90%. Based on 1.5-V output and 15 A this equates to a power loss in
the converter of 2.5 W. Using this figure a target of 0.5 W dissipated in the switching MOSFET was chosen.
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Equation 25 through Equation 28 can be used to calculate the power loss, PQSW, in the switching MOSFET
P
+ P
) P
) P
QSW
QSW(CON)
QSW(SW)
QSW(GATE)
(25)
(26)
V
2
2
2
)
O
DI
ǒ
I
LOAD
Ǔ
P
+ R
I + R
QSW(CON)
DS(on)
D
DS(on)
12
V
IN
ǒ
DIǓ ǒ
2
gdǓ
) Q
ȱ
ȳ
ȧ
ȴ
I
)
Q
Q
) Q
gs1
LOAD
OSS(SW)
OSS(SR)
P
+ V f
)
ȧ
Ȳ
QSW(SW)
IN
SW
2
I
g
(27)
(28)
P
+ Q
V F
g
g(TOT) SW
QSW(GATE)
where
•
•
•
•
•
•
•
•
•
•
PQSW(CON) = conduction losses
PQSW(SW) = switching losses
PQSW(GATE) = gate drive losses
Qgd = drain source charge or miller charge
Qgs1 = gate source post threshold charge
Ig = gate drive current
QOSS(SW) = switching MOSFET output charge
QOSS(SR) = synchronous MOSFET output charge
Qg(TOT) = total gate charge from zero volts to the gate voltage
Vg = gate voltage
If the total estimated loss is split evenly between conduction and switching losses, Equation 25 and Equation 26
yields preliminary values for RDS(on) and (Qgs1 + Qgd). Note output losses due to QOSS and gate losses have been
ignored here. Once a MOSFET is selected these parameters can be added.
The switching MOSFET for this design should have an RDS(on) of less than 9 mΩ. The sum of Qgd and Qgs
should be approximately 4 nC.
It is not always possible to get a MOSFET which meets both these criteria so a comprise may have to be made.
Also by selecting different MOSFETs close to this criteria and calculating power loss the final selection can be
made. It was found that the PH6325L MOSFET from Philips semiconductor gave reasonable results. This device
has an RDS(on) of 6.3 mΩ and a (Qgs1+Qgd) of 5.9 nC. The estimated conduction losses are 0.178 W and the
switching losses are 0.270 W. This gives a total estimated power loss of 0.448 W versus 0.5 W for our initial
boundary condition. Note this does not include gate losses of approximately 10 mW and output losses of less
than 1 mW.
3.1.5 Rectifier MOSFET, QSR
Similar criteria can be used for the rectifier MOSFET. There is one significant difference. Due to the body diode
conducting, the rectifier MOSFET switches with near zero voltage across its drain and source so effectively with
near zero switching losses. However, there are some losses in the body diode. These are minimized by
reducing the delay time between the transition from the switching MOSFET turn off to rectifier MOSFET turn on
and vice versa. The TPS40075 incorporates TI's proprietary predictive gate drive which helps reduce this delay
to between 10 ns and 20 ns.
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The calculations for the losses in the rectifier MOSFET are show in Equation 29 through Equation 32.
P
+ P
) P
) P
QSR
QSR(CON)
DIODE QSR(GATE)
(29)
V
2
2
2
)
O
DI
ǒ
I
LOAD
Ǔ
P
P
K
+ R
I + R
QSW(CON)
DS(on)
D
DS(on)
12
V
IN
(30)
(31)
ǒ
Ǔ
+ V I
t ) t f
1 2
SW
DIODE
f
LOAD
V
UVLO
^
PWM
1 V
(32)
where
•
•
•
•
PDIODE = body diode losses
t1 = body diode conduction prior to turn on of channel = 10 ns for predictive gate drive
t2 = body diode conduction after turn off of channel = 10 ns for predictive gate drive
Vf = body diode forward voltage
Estimating the body diode losses based on a forward voltage of 1.2 V gives 0.142 W. The gate losses are
unknown at this time so assume 0.1 W gate losses. This leaves 0.258 W for conduction losses. Using this figure
a target RDS(on) of 1.1 mΩ was calculated. This is an extremely low value. It is not possible to meet this without
paralleling multiple MOSFETs. Paralleling MOSFETs increases the gate capacitance and slows down switching
speeds. This increases body diode and gate losses.
The PH2625L from Philips was chosen. Using the parameters from its data sheet the actual expected power
losses were calculated. Conduction loss is 0.527 W, body diode loss is 0.142 W and the gate loss was 0.174 W.
This totals 0.843 W associated with the rectifier MOSFET. This is somewhat greater than the initial allowance.
Because of this the converter may not hit its efficiency figure at the maximum load.
Two other criteria should be verified before finalizing on the rectifier MOSFET. One is the requirement to ensure
that predictive gate drive functions correctly. The maximum turn off delay of the PH2625L is 67 ns. The minimum
turn on delay of the PH6325L is 25 ns. These devices easily meet the 100 ns difference requirement.
Secondly the ratio between Cgs and Cgd should be greater than 1. The Cgs of the PH2625L is 2133 pF and the
Cgd is 1622 pF, so the Cgs:Cgd ratio is 1.3:1. This helps reduce the risk of dv/dt induced turn on of the rectifier
MOSFET. If this is likely to be a problem a small resistor may be added in series with the boost capacitor,
CBOOST
.
3.2 Component Selection for TPS40075
3.2.1 Timing Resistor, RT
The timing resistor is calculated using the following equation.
1
R +
* 23
T
*6
f
17.82 10
SW
(33)
This gives a resistor value of 89.2 kΩ. Using the E24 range of resistor values a 118-kΩ resistor was selected.
The nominal frequency using this resistor is 398 kHz.
3.2.2 Feed Forward and UVLO Resistor, RKFF
A resistor connected to the KFF pin of the device feeds into the ramp generator. This resistor provides current
into the ramp generator proportional to the input voltage. The ramp is then adjusted to compensate for different
input voltages. Is provides the voltage feed forward feature of the TPS40075.
The same resistor also sets the under voltage lock out point. The input start voltage should be used to calculate
a value for RKFF. For this converter the minimum input voltage is 10.8 V however due to tolerances in the device,
a start voltage of 15% less than the minimum input voltage is selected. The start voltage for RKFF calculation is
9.18 V. Using Equation 34 RKFF can be selected.
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ǒ
Ǔ
* 0.5
V
UVLO(on)
R
+
KFF
0.018 ) ǒ5 Ǔ
ǒ Ǔ
R
T
(34)
This equation gives a RKFF value of 136 kΩ. The closest lower standard value should be selected. For this
design and using E24 resistor range 133 kΩ was chosen. This yields a typical start voltage of 8.52 V.
3.2.3 Soft Start Capacitor
It is good practice to limit the rise time of the output voltage. This helps prevent output overshoot and possible
damage to the load. The selection of the soft start time is arbitrary, but it must meet one condition; it should be
greater than the time constant of the output filter, L and CO. This time is given by Equation 35
ǸL C
w 2p
t
START
O
(35)
The soft-start time must be greater than 0.281 ms. A time of 1 ms was chosen, this time also helps keep the
initial input current during start up low. The value of CSS can be calculated using Equation 36.
*6
12 10
C
w
t
START
SS
0.7
(36)
CSS should be greater than 17 nF, a 22 nF MLCC was chosen. The calculated start time using this capacitor is
1.28 ms.
3.2.4 Short Circuit Protection, RILIM and CILIM
Short circuit protection is programmed using the RILIM resistor. Selection of this resistor depends on the RDS(on) of
the switching MOSFET selected and the required short circuit current trip point, ISCP. The minimum ISCP is limited
by the inductor peak current, the output voltage, the output capacitor and the soft start time. Their relationship is
given by Equation 37. A short circuit current trip point greater than that calculated by this equation should be
used.
C
V
O
t
OUT
DI
2
I
w
) I
SCP
LOAD
START
(37)
The minimum short circuit current trip point for this design is 16.35 A. This value is used in Equation 38 to
calculate the minimum RILIM value.
I
R
) V
SCP
w
DS(on)MAX ILIM(min)
R
ILIM
I
SINK(max)
(38)
RILIM is calculated to be 1.14 kΩ . The closest standard value greater than 1.14 kΩ is chose, this is 1.15 kΩ. To
verify that the short circuit current requirements are met the minimum and maximum short circuit current can be
calculated using Equation 39 and Equation 40.
I
R
* V
SINK(min)
ILIM(min) ILIM(max)
I
+
SCP(min)
R
DS(on)MIN
(39)
(40)
I
R
* V
ILIM(max) ILIM(min)
SINK(max)
I
+
SCP(max)
R
DS(on)MAX
The minimum ISCP is 17.09 A and the maximum is 29.45 A.
It is recommended to add a small capacitor, CILIM, across RILIM. The value of this capacitor should be less than
that calculated in Equation 41.
V
0.2
O
C
+
ILIM(max)
V
R
f
ILIM SW
IN
(41)
This equation yields a maximum CILIM of 44 pF. A value half this is chosen, 22 pF.
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3.2.5 Voltage Decoupling Capacitors, CDBP, CLVBP and CVDD
Several pins on the TPS40075 have DC voltages. It is recommended to add small decoupling capacitors to
these pins. Below is a list of the recommended values.
•
•
•
CDBP = 1.0 µF
CLVBP = 0.1 µF
CVDD = 4.7 µF
3.2.6 Boost Voltage, CBOOST and DBOOST (optional)
A capacitor charge pump or boost circuit is required to drive an N-channel MOSFET in the switch location of a
buck converter . The TPS40075 contains the elements for this boost circuit. The designer just has to add a
capacitor, CBOOST, from the switch node of the buck power stage to the BOOST pin of the device. Selection of
this capacitor is based on the total gate charge of the switching MOSFET and the allowable ripple on the boost
voltage, ∆VBOOST. A ripple of 0.15 V is assumed for this design. Using these two parameters and Equation 42
the minimum value for CBOOST can be calculated.
Q
g(TOTAL)
C
u
BOOST
DV
BOOST
(42)
The total gate charge of the switching MOSFET is 13.3 nC. A minimum CBOOST of 0.089 µF is required. A 0.1 µF
capacitor was chosen.
This capacitor must be able to withstand the maximum voltage on DBP (10 V in this instance ). A 50 V capacitor
is used for expediancy.
To reduce losses in the TPS40075 and to increase the available gate voltage for the switching MOSFET an
external diode can be added between the DBP pin and the BOOST pin of the device. A small signal schottky
should be used here, such as the BAT54.
3.3 Closing the Feedback Loop, RZ1, RP1, RPZ2, RSET1, RSET2, CZ2, CP2 and CPZ1
A graphical method is used to select the compensation components. This is a standard feedforward buck
converter. Its PWM gain is shown in Equation 43.
V
UVLO
K
^
PWM
1 V
(43)
(44)
(45)
The gain of the output L-C filter is given by Equation 44
ǒ
OǓ
1 ) s ESR C
K
+
LC
L
ǒ Ǔ) s L C
2
1 ) s
O
R
LOAD
The PWM and LC gain is, shown in Equation 45.
ǒ
OǓ
1 ) s ESR C
V
UVLO
G (s) + K
e
K
+
PWM
LC
1 V
L
ǒ Ǔ) s L C
2
1 ) s
O
R
LOAD
To describe this in a Bode plot, the DC gain must be expressed in dB. The DC gain is equal to KPWM. To
express this in dB we take its LOG and multiple by 20. For this converter the DC gain is shown in Equation 46.
V
ǒ Ǔ+ 20 LOG(8.752) + 18.8 dB
UVLO
DCGAIN + 20 LOG
1 V
(46)
The pole and zero frequencies should be calculated, also. A double pole is associated with the L-C and a zero is
associated with the ESR of the output capacitor. The frequency at where these occur can be calculated using
the following two equations.
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1
ǸL C
f
+
+ 3559 Hz
LC_Pole
2p
O
(47)
(48)
1
f
+
+ 8377 Hz
ESR_Zero
2p ESR C
O
The resulting bode plot is shown in Figure 30.
30
Double Pole
20
10
0
ESR Zero
−10
−20
−40
ESR = 0.0095 Ω
Slope = −20 dB / decade
−50
−60
ESR = 0 Ω
Slope = −40 dB / decade
100
1 k
10 k
100 k
1 M
Frequency − Hz
Figure 30. PWM and LC Filter Gain
The next step is to establish the required compensation gain to achieve the desired overall system response.
The target response is to have the crossover frequency between 1/10 to 1/4 times the switching frequency. To
have a phase margin greater than 45° and a gain margin greater than 6 dB.
A Type III compensation network, as shown in Figure 31, was used for this design. This network gives the best
overall flexibility for compensating the converter.
C
PZ1
R
P1
TPS40075
SAO
R
Z1
2
5
6
C
Z2
C
P2
FB
R
PZ2
COMP
R
SET2
R
SET1
UDG−04126
Figure 31. Type III Conpensation with TPS40075
A typical bode plot to this type of compensation network is shown in Figure 32.
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40
30
High Frequency Gain
20
10
0
−10
−20
100
1 k
10 k
Frequency − Hz
100 k
1 M
f
P1
f
P2
f
Z1
f
Z2
Figure 32. Type III Compensation Bode Plot
The high frequency gain and the break (pole and zero) frequencies are calculated using the following equations.
R
) R
Z1
SET
V
+ V
O
FB
R
SET
(49)
(50)
R
R
) R
SET1
SET1
R
SET2
SET2
R
+
SET
R
PZ2
GAIN +
R
ǒRZ1 Ǔ
R
P1
)R
Z1
P1
(51)
(52)
1
f
+
P1
2p R C
P1
PZ1
C
) C
Z2
P2
1
f
f
f
+
+
+
^
P2
Z1
Z2
2p R
C C
2p R
C
PZ2
P2
Z2
PZ2 P2
(53)
(54)
1
2p R C
Z1
PZ1
1
1
^
2p R
C
Z2
ǒ
Ǔ
2p R
) R
C
PZ2
PZ2
P1 Z2
(55)
Using this PWM and L-C bode plot the following actions ensure stability.
1. Place two zero’s close to the double pole, i.e. fZ1 = fZ2 = 3559 Hz
2. Place a pole at one octave below the desired crossover frequency. The crossover frequency was selected
as one quarter the switching frequency, fCO = 100 kHz, fP1 = 50 kHz
3. Place the second pole about an octave above fco. This ensures that the overall system gain falls off quickly
to give good gain margin, fP2 = 200 kHz
4. The high-frequency gain is sufficient to ensure 0 dB at the required crossover frequency, GAIN = -1 GAIN
of PWM and LC at the crossover frequency, GAIN = 17.6 dB, or 7.586
Desired frequency response and resultant overall system response can be seen in Figure 33.
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40
30
Overall System
Response
ESR = 0 Ω
GBWP
Overall System
Response
ESR = 0.0095 Ω
20
10
0
Compensation
Response
−10
−20
−30
−40
−50
PWM and LC Response
ESR = 0 Ω
PWM and LC Response
ESR = 0.0095 Ω
f
f
CO1
CO2
−60
100
1 k
10 k
Frequency − Hz
100 k
1 M
Figure 33. Overall System Bode Plot
Using these values and the equations above the resistors and capacitors around the compensation network can
be calculated.
1. Set RZ1 = 10 kΩ.
2. Calculate RSET using Equation 49; RSET = 8750 Ω. Two resistors in parallel, RSET1 and RSET2, are used to
make up RSET. RSET1 = 9.53 kΩ, RSET2 = 105 kΩ.
3. Using Equation 54 and fZ1 = 3559 Hz, CPZ1 can be calculated to be 4.47 nF; CPZ1= 4.7 nF.
4. FP1 and Equation 52 yields RP1 to be 677 Ω, RP1 = 680 Ω.
5. The required gain of 17.6 dB (7.586) and Equation 52 sets the value for RPZ1. Note actual gain used for this
calculation was 20 dB (10), this ensures that the gain of the transfer function is high enough, RPZ1 = 6.2 kΩ.
6. CZ2 is calculated using Equation 55 and the desired frequency for the second zero, CZ2 = 6.8 nF.
7. CP2 is calculated using the second pole frequency and Equation 53, CP2 = 150 pF.
Using MathCAD the above values were used to draw the actual Bode plot for gain and phase. From these plots
the crossover frequency, phase margin and gain margin can be recorded.
Table 3. Equivalent Series Resistance
ESR
(Ω)
CROSSOVER FREQUENCY
(kHz)
PHASE MARGIN
GAIN MARGIN
(dB)
(°)
0
23.1
98.6
72
> 46
> 33
0.0095
78.8
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GAIN
vs
FREQUENCY
PHASE
vs
FREQUENCY
200
180
160
140
60
40
System Phase
ESR = 0 Ω
System Gain
ESR = 0.95 mΩ
20
120
100
80
60
40
20
0
0
−20
−40
System Gain
ESR = 0 Ω
System Phase
ESR = 0.95 mΩ
−60
100
100
1 k
10 k
100 k
1 M
1 k
10 k
100 k
1 M
Frequency − Hz
Frequency − Hz
Figure 34.
Figure 35.
ALTERNATE APPLICATIONS
Some alternative applicaiton diagrams are shown in Figure 36 through Figure 38.
35
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1
20
External Logic Supply
SA−
SA+
TPS40075
2
3
4
5
SAO
GND
SS
SYNC 19
PGD 18
LVBP 17
10 kΩ
402 Ω
Power Good
10 nF
1 µF
10 kΩ
VDD
12 V
2 nF
118 kΩ
FB
RT 16
KFF 15
ILIM 14
2 nF
10 kΩ
118 kΩ
6
COMP
120 µF
75 pF
120 µF
14 kΩ
1.27 kΩ
22 pF
7
8
PGND
LDRV
VDD 13
ꢂ
1 µF
Si7390DP
9
DBP
HDRV 12
22 µF
22 µF
SW
10
BOOST
11
100 nF
1.3 µH ꢀ
1.5 Ω
ꢁ
1.2 V
10 A
100 nF
Si7868DP
UDG−04109
ꢀ COEV DXM1306
ꢁ100 µF, TDK, C3225X5R0J107M (× 3)
ꢂ TDK C4532X5R1C226M (× 2)
Figure 36. 400 kHz, 12 V to 1.2 V Converter with Powergood Indication
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1
20
From 3.3 V
Logic Clock Source
SA−
TPS40075
SA+
2
3
SAO
GND
SYNC 19
PGD 18
LVBP 17
294 Ω
1 µF
10 nF
10 kΩ
330 kΩ
11.3 kΩ
VDD
5 V to 12 V
4
5
SS
FB
165 kΩ
3.9 nF
RT 16
KFF 15
ILIM 14
88.7 kΩ
3.3 nF
6
COMP
120 µF
120 µF
1.74 kΩ
39 pF
100 pF
7
8
PGND
LDRV
2.67 kΩ
VDD 13
ꢂ
1 µF
Si7344DP
22 µF
9
DBP
HDRV 12
22 µF
100 nF
SW
10
BOOST
11
2.2 µH
ꢀ
BAT54
1.5 Ω
100 nF
3.3 V
15 A
ꢁ
180 µF
180 µF
Si7868DP
UDG−04110
ꢀ
C
o
i
l
t
r
o
n
i
c
s
H
C
2
L
P
−
2
R
2
o
r
Vishay IHLP5050FDRZ2R2M01
ꢁ
PanasonicEEF−SE0J181R (× 2)
ꢂ TDK C4532X5R1C226M (×2)
Figure 37. 300 kHz Intermediate Bus (5 V to 12 V) to 3.3 V Converter
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Figure 38. Sequenced Supplies, Synchronized 180° Out of Phase
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ADDITIONAL REFERENCES
The following parts are similar to the TPS40075 and may be of interest:
1. TPS40071 Mid Range Input (4.5 V to 28 V) up to 1-MHz Frequency Synchronous Buck Controller
2. TPS40100 Wide Input Range Synchronous Buck Controller for Sequencing
3. TPS40057 Wide Input (8 V to 40 V) up to 1MHz Frequency Synchronous Buck Controller, source/sink with
prebias
4. TPS40190 Low Pin Count Synchronous Buck DC/DC Controller
39
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EXAMPLE LAND PATTERN
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