TPS40304ADRCT [TI]
3-V TO 20-V INPUT SYNCHRONOUS BUCK CONTROLLER; 3 V至20 V输入同步降压控制器
| 型号： | TPS40304ADRCT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3-V TO 20-V INPUT SYNCHRONOUS BUCK CONTROLLER |
| 文件： | 总20页 (文件大小：527K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS40304A
www.ti.com
SLUSA30 –FEBRUARY 2010
3-V TO 20-V INPUT SYNCHRONOUS BUCK CONTROLLER
Check for Samples: TPS40304A
1
FEATURES
CONTENTS
•
•
•
Input Voltage Range from 3 V to 20 V
Device Ratings
2
3
Fixed 600-kHz Switching Frequency
Electrical Characteristics
Device Information
High- and Low-Side FET RDS(on) Current
Sensing
8
Application Information
Additional References
10
13
•
Programmable Thermally Compensated OCP
Levels
X
•
•
•
•
•
•
•
Programmable Soft-Start
591-mV, 1% Reference Voltage
Voltage Feed-Forward Compensation
Supports Pre-Biased Output
APPLICATIONS
•
•
•
•
POL Modules
Printer
Digital TV
Telecom
Frequency Spread Spectrum
Thermal Shutdown Protection at 145°C
10-Pin 3 mm × 3 mm SON Package with
Ground Connection to Thermal Pad
DESCRIPTION
The TPS40304A is a cost-optimized synchronous buck controller that operates from 3-V to 20-V input. The
controller implements a voltage-mode control architecture with input-voltage feed-forward compensation that
responds instantly to input voltage change. The switching frequency is fixed at 600 kHz.
Frequency Spread Spectrum feature adds dither to the switching frequency, significantly reducing the peak EMI
noise and making it much easier to comply with EMI standards.
The TPS40304A offers design with a variety of user programmable functions, including soft-start, overcurrent
protection (OCP) levels, and loop compensation.
The OCP level is programmed by a single external resistor connected from LDRV pin to circuit ground. During
initial power on, the TPS40304A enters a calibration cycle, measures the voltage at the LDRV pin, and sets an
internal OCP voltage level. During operation, the programmed OCP voltage level is compared to the voltage drop
across the low-side FET when it is on to determine whether there is an overcurrent condition. The TPS40304A
then enters a shutdown and restart cycle until the fault is removed.
SIMPLIFIED APPLICATION DIAGRAM
V
OUT
V
TPS40304A
IN
5
4
3
2
1
FB
BOOT
HDRV
SW
6
7
8
9
COMP
V
OUT
PGOOD
EN/SS LDRV/OC
SD
V
VDD
BP 10
GND
PAD
IN
UDG-10008
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TPS40304A
SLUSA30 –FEBRUARY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
OPERATING FREQUENCY
PACKAGE
TAPE AND REEL QUANTITY
PART NUMBER
TPS40304ADRCT
TPS40304ADRCR
250
600 kHz
Plastic 10-Pin SON (DRC)
3000
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE
–0.3 to 22
–3 to 27
–5
UNIT
V
VDD
SW
V
SW (< 100 ns pulse width, 10 µJ)
V
BOOT
–0.3 to 30
–5 to 30
–0.3 to 7
–0.3 to 7
–40 to 145
–55 to 150
V
HDRV
V
BOOT-SW, HDRV-SW (differential from BOOT or HDRV to SW)
COMP, PGOOD, FB, BP, LDRV, EN/SS
V
V
TJ
Operating junction temperature range
Storage temperature
°C
°C
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other condition beyond those included under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.
DISSIPATION RATINGS
R
qJA HIGH-K BOARD(1)
(°C/W)
POWER RATING (W)
TA = 25°C
POWER RATING (W)
TA = 85°C
PACKAGE
AIRFLOW (LFM)
0 (Natural Convection)
47.9
40.5
38.2
2.08
2.46
2.61
0.835
0.987
1.04
10-Pin SON (DRC)
200
400
(1) Ratings based on JEDEC High Thermal Conductivity (High K) Board. For more information on the test method, see TI technical brief
(SZZA017).
RECOMMENDED OPERATING CONDITIONS
MIN
3
NOM
MAX
20
UNIT
V
VDD
TJ
Input voltage
Operating junction temperature
–40
125
°C
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
MIN
TYP
2000
1500
MAX UNIT
Human body model (HBM)
Charge device model (CDM)
V
V
2
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ELECTRICAL CHARACTERISTICS
TJ = –40°C to 125°C, VVDD = 12 V, all parameters at zero power dissipation (unless otherwise noted)
PARAMETER
VOLTAGE REFERENCE
TEST CONDITIONS
MIN
TYP
MAX UNIT
TJ = 25°C, 3 V < VVDD < 20 V
588
585
591
591
594
VFB
FB input voltage
mV
–40°C < TJ < 125°C,
3 V < VVDD < 20 V
597
INPUT SUPPLY
VVDD
IDDSD
IDDQ
Input supply voltage range
3
20
100
3.5
V
Shutdown supply current
Quiescent, non-switching
VEN/SS < 0.2 V
70
µA
mA
Let EN/SS float, VFB = 1 V
2.5
ENABLE/SOFT-START
VIH
VIL
ISS
High-level input voltage, EN/SS
0.55
0.27
8
0.70
0.30
10
1.00
0.33
12
V
V
Low-level input voltage, EN/SS
Soft-start source current
Soft-start voltage level
µA
V
VSS
0.4
0.8
1.3
BP REGULATOR
VBP
Output voltage
IBP = 10 mA
6.2
6.5
70
6.8
V
VDO
Regulator dropout voltage, VVDD – VBP
IBP = 25 mA, VVDD = 3 V
110
mV
OSCILLATOR
fSW
PWM frequency
Ramp amplitude
3 V < VVDD < 20 V
540
600
660
kHz
V
(1)
VRAMP
VVDD/6.6
VVDD/6 VVDD/5.4
Frequency spread spectrum frequency
deviation
fSWFSS
12%
fSW
fMOD
Modulation frequency
25
KHz
PWM
(1)
DMAX
Maximum duty cycle
VFB = 0 V, 3 V < VVDD < 20 V
90%
(1)
tON(min)
Minimum controllable pulse width
45
25
25
75
35
30
ns
ns
HDRV off to LDRV on
LDRV off to HDRV on
5
5
tDEAD
Output driver dead time
ERROR AMPLIFIER
(1)
GBWP
Gain bandwidth product
Open loop gain
Input bias current (current out of FB pin) VFB = 0.6 V
10
60
24
MHz
dB
(1)
AOL
IIB
75
nA
IEAOP
IEAOM
Output source current
Output sink current
VFB = 0 V
VFB = 1 V
2
2
mA
(1) Ensured by design. Not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
TJ = –40°C to 125°C, VVDD = 12 V, all parameters at zero power dissipation (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
PGOOD
Feedback upper voltage limit for
PGOOD
VOV
646
491
666
516
691
Feedback lower voltage limit for
PGOOD
mV
VUV
541
VPGD-HYST
RPGD
PGOOD hysteresis voltage at FB
PGOOD pull down resistance
25
30
40
VFB = 0 V, IFB = 5 mA
70
Ω
541 mV < VFB < 646 mV,
VPGOOD = 5 V
IPGDLK
PGOOD leakage current
10
20
µA
OUTPUT DRIVERS
RHDHI
RHDLO
RLDHI
RLDLO
tHRISE
tHFALL
tLRISE
tLFALL
High-side driver pull-up resistance
VBOOT – VSW = 5 V, IHDRV = –100 mA
VBOOT – VSW = 5 V, IHDRV = 100 mA
ILDRV = -100 mA
0.8
0.5
1.5
1.0
1.5
0.60
15
2.5
2.2
Ω
Ω
High-side driver pull-down resistance
Low-side driver pull-up resistance
Low-side driver pull-down resistance
High-side driver rise time
0.8
2.5
Ω
ILDRV = 100 mA
0.35
1.20
Ω
(2)
(2)
(2)
(2)
CLOAD = 5 nF
ns
ns
ns
ns
High-side driver fall time
12
Low-side driver rise time
15
Low-side driver fall time
10
OVERCURRENT PROTECTION
(2)
tPSSC(min)
Minimum pulse time during short circuit
250
150
450
10.0
340
ns
ns
(2)
tBLNKH
Switch leading-edge blanking pulse time
OC threshold for high-side FET
OCSET current source
VOCH
TJ = 25°C
TJ = 25°C
360
9.5
580
10.5
400
mV
µA
mV
IOCSET
VLD-CLAMP
Maximum clamp voltage at LDRV
260
OC comparator offset voltage for
low-side FET
VOCLOS
TJ = 25°C
TJ = 25°C
–8
12
8
mV
mV
Programmable OC range for low-side
FET
(2)
VOCLPRO
300
OC threshold temperature coefficient
(both high-side and low-side)
(2)
VTHTC
3000
4
ppm
tOFF
OC retry cycles on EN/SS pin
Cycle
BOOT DIODE
VDFWD
Bootstrap diode forward voltage
IBOOT = 5 mA
0.8
V
THERMAL SHUTDOWN
(2)
TJSD
Junction shutdown temperature
Hysteresis
145
20
°C
°C
(2)
TJSDH
(2) Ensured by design. Not production tested.
4
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TYPICAL CHARACTERISTICS
SWITCHING FREQUENCY
vs
QUIESCENT CURRENT
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
625
620
615
610
605
600
595
590
585
580
2.24
2.22
2.20
2.18
VVDD = 20 V
VVDD = 12 V
VVDD = 3V
2.16
2.14
2.12
VVDD = 12 V
20 35 50 65 80 95 110 125
–40 –25 –10
5
–40 –25 –10
5
20 35 50 65 80 95 110 125
T
– Junction Temperature – °C
J
T
– Junction Temperature – °C
J
Figure 1.
Figure 2.
SHUTDOWN CURRENT
vs
OCSET CURRENT SOURCE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
14
13
12
11
10
9
72
70
68
66
64
62
60
58
8
7
VVDD = 12 V
20 35 50 65 80 95 110 125
6
–40 –25 –10
5
–40 –25 –10
5
20 35 50 65 80 95 110 125
T
– Junction Temperature – °C
J
T
– Junction Temperature – °C
J
Figure 3.
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
FEEDBACK REFERENCE VOLTAGE
ENABLE HIGH-LEVEL THRESHOLD VOLTAGE
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
592.0
740
720
700
680
660
640
620
591.5
591.0
590.5
590.0
589.5
589.0
588.5
588.0
–40 –25 –10
5
20 35 50 65 80 95 110 125
–40 –25 –10
5
20 35 50 65 80 95 110 125
T
– Junction Temperature – °C
T
– Junction Temperature – °C
J
J
Figure 5.
Figure 6.
ENABLE LOW-LEVEL THRESHOLD VOLTAGE
HIGH-SIDE OVERCURRENT THRESHOLD
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
303.0
302.5
302.0
301.5
301.0
300.5
300.0
600
550
500
450
400
350
–40 –25 –10
5
20 35 50 65 80 95 110 125
–40 –25 –10
5
20 35 50 65 80 95 110 125
T
– Junction Temperature – °C
J
T
– Junction Temperature – °C
J
Figure 7.
Figure 8.
6
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TYPICAL CHARACTERISTICS (continued)
POWER GOOD THRESHOLD VOLTAGE
SOFT-START VOLTAGE
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
800
750
700
650
600
550
500
450
400
1000
975
950
925
900
875
850
825
800
775
750
Overvoltage
Undervoltage
–40 –25 –10
5
20 35 50 65 80 95 110 125
–40 –25 –10
5
20 35 50 65 80 95 110 125
T
– Junction Temperature – °C
T
– Junction Temperature – °C
J
J
Figure 9.
Figure 10.
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DEVICE INFORMATION
TERMINAL CONFIGURATION
The package is an 10-Pin SON (DRC) package. Note: The thermal pad is an electrical ground connection.
FB COMP PGOOD EN/SS VDD
5
4
3
2
1
Thermal Pad
6
7
8
9
10
LDRV/
OC
BOOT HDRV SW
BP
PIN FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Gate drive voltage for the high-side N-channel MOSFET. A 100 nF capacitor (typical) must be connected
between this pin and SW. For low input voltage operation, an external schottky diode from BP to BOOT is
recommended to maximize the gate drive voltage for the high-side.
BOOT
6
I
Output bypass for the internal regulator. Connect a low ESR bypass ceramic capacitor of 1 µF or greater from
this pin to GND.
BP
10
4
O
O
COMP
Output of the error amplifier and connection node for loop feedback components.
Logic level input which starts or stops the controller via an external user command. Letting this pin float turns
the controller on. Pulling this pin low disables the controller. This is also the soft-start programming pin. A
capacitor connected from this pin to GND programs the soft-start time. The capacitor is charged with an
internal current source of 10 µA. The resulting voltage ramp of this pin is also used as a second non-inverting
input to the error amplifier after a 0.8 V (typical) level shift downwards. Output regulation is controlled by the
internal level shifted voltage ramp until that voltage reaches the internal reference voltage of 591 mV – the
voltage ramp of this pin reaches 1.4 V (typical). Optionally, a 267 kΩ resistor from this pin to BP enables
frequency spread spectrum feature.
EN/SS
2
I
Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal
reference voltage.
FB
5
I
PGOOD
HDRV
3
7
O
O
Open drain power good output.
Bootstrapped gate drive output for the high-side N-channel MOSFET.
Gate drive output for the low-side synchronous rectifier N-channel MOSFET. A resistor from this pin to GND
is also used to determine the voltage level for OCP. An internal current source of 10 µA flows through the
resistor during initial calibration and that sets up the voltage trip point used for OCP.
LDRV/OC
9
O
Power input to the controller. Bypass VDD to GND with a low ESR ceramic capacitor of at least 1.0-µF close
to the device.
VDD
SW
1
8
I
Sense line for the adaptive anti-cross conduction circuitry. Serves as common connection for the flying
high-side FET driver.
O
Ground connection to the controller. This is also the thermal pad used to conduct heat from the device. This
connection serves a twofold purpose. The first is to provide an electrical ground connection for the device.
The second is to provide a low thermal impedance path from the device die to the PCB. This pad should be
tied externally to a ground plane.
Thermal
Pad
GND
8
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TPS40304A BLOCK DIAGRAM
0.591 V
+ 12.5%
+
REF
10 mA
Soft Start
SS
SS
FB
BP
EN/SS
2
+
SD
0.591 V
OC
– 12.5%
Fault
REF
Clock
6
7
BOOT
HDRV
Controller
+
6-V
VDD
BP
1
10
4
Regulator
References
BP
0.591 V
REF
SD
8
SW
Calibration
Circuit
Spread
Spectrum
Oscillator
COMP
Clock
BP
Anti-Cross
Conduction
and
PWM
Logic
9
LDRV/OC
Pre-Bias
Circuit
FB
5
PWM
+
+
10 mA
0.591 V
REF
Thermal
SS
OC
750 kW
Shutdown
Threshold
Setting
PGOOD
3
Fault Controller
OC
PAD
GND
UDG-01009
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APPLICATION INFORMATION
Introduction
The TPS40304A is a cost-optimized synchronous buck controller providing high-end features to construct
high-performance DC/DC converters. Pre-bias capability eliminates concerns about damaging sensitive loads
during startup. Programmable overcurrent protection levels and hiccup overcurrent fault recovery maximize
design flexibility and minimize power dissipation in the event of a prolonged output short. Frequency Spread
Spectrum (FSS) feature reduces peak EMI noise by spreading the initial energy of each harmonic along a
frequency band, thus giving a wider spectrum with lower amplitudes.
Voltage Reference
The 591-mV band gap cell is internally connected to the non-inverting input of the error amplifier. The reference
voltage is trimmed with the error amplifier in a unity gain configuration to remove amplifier offset from the final
regulation voltage. The 1% tolerance on the reference voltage allows the user to design a very accurate power
supply.
Enable Functionality, Startup Sequence and Timing
After input power is applied, an internal current source of 40 µA starts to charge up the soft-start capacitor
connected from EN/SS to GND. When the voltage across that capacitor increases to 0.7 V, it enables the internal
BP regulator followed by a calibration. The total calibration time is about 1.9 ms. See Figure 11. During the
calibration, the device performs in the following way. It disables the LDRV drive and injects an internal 10 µA
current source to the resistor connected from LDRV to GND. The voltage developed across that resistor is then
sampled and latched internally as the OCP trip level until one cycles the input or toggles the EN/SS.
2.0
V
EN/SS
Calibration
Time
1.9 ms
1.6
1.2
0.8
0.4
0
1.3 V
0.7 V
V
SS_INT
t – Time – ms
UDG-09159
Figure 11. Startup Sequence and Timing
The voltage at EN/SS is internally clamped to 1.3 V before and/or during calibration to minimize the discharging
time once calibration is complete. The discharging current is from an internal current source of 140 µA and it
pulls the voltage down to 0.4 V. It then initiates the soft-start by charging up the capacitor using an internal
current source of 10 µA. The resulting voltage ramp on this pin is used as a second non-inverting input to the
error amplifier after an 800 mV (typical) downward level-shift; therefore, actual soft-start will not take place until
the voltage at this pin reaches 800 mV.
If EN/SS is left floating, the controller starts automatically. EN/SS must be pulled down to less than 270 mV to
guarantee that the chip is in shutdown mode.
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Soft-Start Time
The soft-start time of the TPS40304A is user programmable by selecting a single capacitor. The EN/SS pin
sources 10 µA to charge this capacitor. The actual output ramp-up time is the amount of time that it takes for the
10 µA to charge the capacitor through a 591-mV range. There is some initial lag due to calibration and an offset
(800 mV) from the actual EN/SS pin voltage to the voltage applied to the error amplifier.
The soft-start is done in a closed loop fashion, meaning that the error amplifier controls the output voltage at all
times during the soft start period and the feedback loop is never open as occurs in duty cycle limit soft-start
schemes. The error amplifier has two non-inverting inputs, one connected to the 591-mV reference voltage, and
the other connected to the offset EN/SS pin voltage. The lower of these two voltages is what the error amplifier
controls the FB pin to. As the voltage on the EN/SS pin ramps up past approximately 1.4 V (800 mV offset
voltage plus the 591-mV reference voltage), the 591-mV reference voltage becomes the dominant input and the
converter has reached its final regulation voltage.
The capacitor required for a given soft-start ramp time for the output voltage is given by Equation 1.
æ
ç
è
ö
÷
ø
ISS
CSS
=
´ t
SS
VFB
where
•
•
•
•
CSS is the required capacitance on the EN/SS pin (F)
ISS is the soft-start source current (10 µA)
VFB is the feedback reference voltage (591 mV)
tSS is the desired soft-start ramp time (s)
(1)
Oscillator and Frequency Spread Spectrum (FSS)
The oscillator frequency is internally fixed at 600 kHz.
Connecting a resistor with a value of 267 kΩ ± 10% from BP to EN/SS enables the FSS feature. When enabled,
it spreads the internal oscillator frequency over a minimum 12% window using a 25-kHz modulation frequency
with triangular profile. By modulating the switching frequency, side-bands are created. The emission power of the
fundamental switching frequency and its harmonics is distributed into smaller pieces scattered around many
side-band frequencies. The effect significantly reduces the peak EMI noise and makes it much easier for the
resultant emission spectrum to pass EMI regulations.
Overcurrent Protection
Programmable OCP level at LDRV is from 6 mV to 150 mV at room temperature with 3000 ppm temperature
coefficient to help compensate for changes in the low-side FET channel resistance as temperature increases.
With a scale factor of 2, the actual trip point across the low-side FET is in the range of 12 mV to 300 mV. The
accuracy of the internal current source is ±5%. Overall offset voltage, including the offset voltage of the internal
comparator and the amplifier for scale factor of 2, is limited to ±8 mV.
Maximum clamp voltage at LDRV is 340 mV to avoid turning on the low-side FET during calibration and in a
pre-biased condition. The maximum clamp voltage is fixed and it does not change with temperature. If the
voltage drop across ROCSET reaches the 340 mV maximum clamp voltage during calibration (No ROCSET resistor
included), it disables OCP. Once disabled, there is no low-side or high-side current sensing.
OCP level at HDRV is fixed at 450 mV with 3000 ppm temperature coefficient to help compensate for changes in
the high-side FET channel resistance as temperature increases. OCP at HDRV provides pulse-by-pulse current
limiting.
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OCP sensing at LDRV is a true inductor valley current detection, using sample and hold. Equation 2 can be used
to calculate ROCSET
:
æ
ç
ç
ç
ö
÷
÷
÷
æ
ç
è
ö
÷
ø
I
æ
ç
è
ö
÷
ø
P-P
I
-
´R
- V
OCLOS
DS on
OUT max
(
)
( )
2
R
=
OCSET
2 ´ I
OCSET
ç
ç
è
÷
÷
ø
where
•
•
•
•
•
•
IOCSET is the internal current source
VOCLOS is the overall offset voltage
IP-P is the peak-to-peak inductor current
RDS(on) is the drain to source on-resistance of the low-side FET
IOUT(max) is the trip point for OCP
ROCSET is the resistor used for setting the OCP level
(2)
To avoid overcurrent tripping in normal operating load range, calculate ROCSET using the equation above with:
•
•
The maximum RDS(ON) at room temperature
The lower limit of VOCLOS (–8 mV) and the lower limit of IOCSET (9.5 µA) from the Electrical Characteristics
table.
•
The peak-to-peak inductor current IP-P at minimum input voltage
Overcurrent is sensed across both the low-side FET and the high-side FET. If the voltage drop across either FET
exceeds the OC threshold, a count increments one count. If no OC is detected on either FET, the fault counter
decrements by one count. If three OC pulses are summed, a fault condition is declared which cycles the
soft-start function in a hiccup mode. Hiccup mode consists of four dummy soft-start timeouts followed by a real
one if overcurrent condition is encountered during normal operation, or five dummy soft-start timeouts followed
by a real one if overcurrent condition occurs from the beginning during start. This cycle continues indefinitely until
the fault condition is removed.
Drivers
The drivers for the external high-side and low-side MOSFETs are capable of driving a gate-to-source voltage of
VBP. The LDRV driver for the low-side MOSFET switches between BP and GND, while HDRV driver for the
high-side MOSFET is referenced to SW and switches between BOOT and SW. The drivers have
non-overlapping timing that is governed by an adaptive delay circuit to minimize body diode conduction in the
synchronous rectifier.
Pre-Bias Startup
The TPS40304A contains a circuit to prevent current from being pulled from the output during startup in the
condition the output is pre-biased. There are no PWM pulses until the internal soft-start voltage rises above the
error amplifier input (FB pin), if the output is pre-biased. Once the soft-start voltage exceeds the error amplifier
input, the controller slowly initiates synchronous rectification by starting the synchronous rectifier with a narrow
on time. It then increments that on time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D),
where D is the duty cycle of the converter. This approach prevents the sinking of current from a pre-biased
output, and ensures the output voltage startup and ramp to regulation is smooth and controlled.
12
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s) :TPS40304A
TPS40304A
www.ti.com
SLUSA30 –FEBRUARY 2010
Power Good
The TPS40304A provides an indication that output is good for the converter. This is an open drain signal and
pulls low when any condition exists that would indicate that the output of the supply might be out of regulation.
These conditions include the following:
•
•
•
VFB is more than ±12.5% from nominal
Soft-start is active
A short circuit condition has been detected
NOTE
When there is no power to the device, PGOOD is not able to pull close to GND if an
auxiliary supply is used for the power good indication. In this case, a built in resistor
connected from drain to gate on the PGOOD pull down device makes the PGOOD pin
look approximately like a diode to GND.
Thermal Shutdown
If the junction temperature of the device reaches the thermal shutdown limit of 145°C, the PWM and the oscillator
are turned off and HDRV and LDRV are driven low. When the junction cools to the required level (125°C typical),
the PWM initiates soft start as during a normal power-up cycle.
ADDITIONAL REFERENCES
Related Devices
The devices listed in have characteristics similar to the TPS40304A and may be of interest.
Table 1. Related Devices
DEVICE
DESCRIPTION
TPS40303/4/5
3-V to 20-V Input Synchronous Buck Controller
References
These references, design tools and links to additional references, including design software, may be found at
http://power.ti.com
1. Additional PowerPAD™ information may be found in Applications Briefs (SLMA002A) and (SLMA004).
2. Under The Hood Of Low Voltage DC/DC Converters – SEM1500 Topic 5 – 2002 Seminar Series
3. Understanding Buck Power Stages in Switchmode Power Supplies, (SLVA057), March 1999
4. Designing Stable Control Loops – SEM 1400 – 2001 Seminar Series
Package Outline and Recommended PCB Footprint
The following pages outline the mechanical dimensions of the 10-pin DRC package and provide
recommendations for PCB layout.
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Link(s) :TPS40304A
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2010
PACKAGING INFORMATION
Orderable Device
TPS40304ADRCR
TPS40304ADRCT
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SON
DRC
10
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
DRC
10
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS40304ADRCR
TPS40304ADRCT
SON
SON
DRC
DRC
10
10
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS40304ADRCR
TPS40304ADRCT
SON
SON
DRC
DRC
10
10
3000
250
346.0
190.5
346.0
212.7
29.0
31.8
Pack Materials-Page 2
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