TPS43350QDAPRQ1 [TI]
LOW IQ, DUAL SYNCHRONOUS BUCK CONTROLLER; 智商低，双路同步降压控制器
| 型号： | TPS43350QDAPRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW IQ, DUAL SYNCHRONOUS BUCK CONTROLLER |
| 文件： | 总31页 (文件大小：1154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS43350-Q1
TPS43351-Q1
www.ti.com
SLVSAR7B –JUNE 2011–REVISED MAY 2012
LOW IQ, DUAL SYNCHRONOUS BUCK CONTROLLER
Check for Samples: TPS43350-Q1, TPS43351-Q1
1
FEATURES
2
•
Qualified for Automotive Applications
•
•
Frequency Spread Spectrum (TPS43351-Q1)
•
AEC-Q100 Test Guidance With the Following
Results:
Selectable Forced Continuous Mode or
Automatic Low-Power Mode at Light Loads
–
Device Temperature Grade 1: –40°C to
125°C Ambient Operating Temperature
•
•
Sense Resistor or Inductor DCR Sensing
Out-of-Phase Switching Between Buck
Channels
–
–
Device HBM ESD Classification Level H2
Device HBM CDM Classification Level C2
•
•
Peak Gate Drive Current 1.5 A
•
•
•
Two Synchronous Buck Controllers
Thermally Enhanced, 38-Pin HTSSOP (DAP)
PowerPAD™ Package
Input Range up to 40 V, (Transients up to 60 V)
Low-Power Mode IQ: 30 µA (One Buck On),
35 µA (Two Bucks On)
APPLICATIONS
•
Automotive Infotainment, Navigation, and
Instrument Cluster Systems
•
•
•
Low Shutdown Current Ish < 4 µA
Buck Output Range 0.9 V to 11 V
•
Industrial/Automotive Multi-Rail DC Power
Distribution Systems and Electronic Control
Units
Programmable Frequency and External
Synchronization Range 150 kHz to 600 kHz
•
Separate Enable Inputs (ENA, ENB)
DESCRIPTION
The TPS43350-Q1 and TPS43351-Q1 include two current-mode synchronous buck controllers designed for the
harsh environment in automotive applications. The part is ideally suited for a multi-rail system with low quiescent
requirements, as the part automatically operates in low-power mode (consuming only 30 µA) at light loads. The
part offers protection features such as thermal, soft-start, and overcurrent protection. During short-circuit
conditions of the regulator output, the current through the MOSFETs can be limited for power dissipation by
activation of the current foldback feature. The two independent soft-start inputs allow ramp-up of the output
voltage independently during start-up.
The switching frequency can be programmed over 150 kHz to 600 kHz or synchronized to an external clock in
the same range. Additionally, the TPS43351-Q1 offers frequency-hopping spread-spectrum operation.
spacer
VBAT
Reverse
Battery
MOSFET
Control
VBUCKA
Internal
VREG
RCOSC
External
SYNC
Sync
ENA
ENB
Buck
Enalbe
SSA
VBUCKB
SSA
SoftStart
DLYAB
Figure 1. Typical Application Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
TPS43350-Q1
TPS43351-Q1
SLVSAR7B –JUNE 2011–REVISED MAY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)(2)
TJ
OPTION
PACKAGE
ORDERABLE PART NUMBER
TPS43350QDAPRQ1
Frequency-hopping spread spectrum OFF
Frequency-hopping spread spectrum ON
–40ºC to 150ºC
DAP
TPS43351QDAPRQ1
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS(1)
MIN
–0.3
–0.3
–0.3
–0.7
–1
MAX UNIT
Voltage
Input voltage: VIN, VBAT
60
60
68
60
V
V
Enable inputs: ENA, ENB
Bootstrap inputs: CBA, CBB
Phase inputs: PHA, PHB
V
V
Phase inputs: PHA, PHB (for 150 ns)
Feedback inputs: FBA, FBB
V
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
13
13
V
Error amplifier outputs: COMPA, COMPB
High-side MOSFET driver: GA1-PHA, GB1-PHB
Low-side MOSFET drivers: GA2, GB2
Current-sense voltage: SA1, SA2, SB1, SB2
Soft start: SSA, SSB
V
Voltage
(Buck function:
BuckA and BuckB)
8.8
8.8
13
V
V
V
13
V
Power-good output: PGA, PGB
Power-good delay: DLYAB
13
V
13
V
Switching-frequency timing resistor: RT
SYNC, EXTSUP
13
V
13
V
P-channel MOSFET driver: GC2
P-channel MOSFET driver: VIN-GC2
Gate-driver supply: VREG
60
V
Voltage
(PMOS driver)
8.8
8.8
150
125
165
V
V
Junction temperature: TJ
°C
°C
°C
Temperature
Operating temperature: TA
–40
Storage temperature: Tstg
–55
Human-body model (HBM) AEC-
Q11 Classification Level H2
±2
kV
FBA, FBB, RT, DLYAB
±400
±750
±500
±150
±200
Charged-device model (CDM)
AEC-Q11 Classification Level C2
Electrostatic
VBAT, SYNC, VIN
All other pins
PGA, PGB
discharge ratings
V
Machine model (MM)
All other pins
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to GND.
2
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS43350-Q1 TPS43351-Q1
TPS43350-Q1
TPS43351-Q1
www.ti.com
SLVSAR7B –JUNE 2011–REVISED MAY 2012
THERMAL INFORMATION
TPS4335x-Q1
THERMAL METRIC(1)
DAP
38 PINS
27.3
UNIT
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
θJCtop
θJB
19.6
15.9
°C/W
ψJT
0.24
ψJB
6.6
θJCbot
1.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS
MIN
4
MAX
40
UNIT
V
Input voltage: VIN, VBAT
Enable inputs: ENA, ENB
Boot inputs: CBA, CBB
0
40
V
4
48
V
Buck function:
BuckA and BuckB
voltage
Phase inputs: PHA, PHB
Current-sense voltage: SA1, SA2, SB1, SB2
Power-good output: PGA, PGB
SYNC, EXTSUP
–0.6
0
40
V
11
V
0
11
V
0
9
V
Operating temperature: TA
–40
125
°C
Copyright © 2011–2012, Texas Instruments Incorporated
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TPS43350-Q1
TPS43351-Q1
SLVSAR7B –JUNE 2011–REVISED MAY 2012
www.ti.com
DC ELECTRICAL CHARACTERISTICS
VIN = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
NO.
1.0
1.1
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input Supply
VBat
Supply voltage
After initial start-up, condition is satisfied.
Input voltage required for device on initial start-up
Buck regulator operating range after initial start-up
VIN falling
4
6.5
4
40
40
40
3.8
4
V
V
V
V
V
Device operating range
1.2
1.3
VIN
3.5
3.6
3.8
VIN UV
Buck undervoltage lockout
VIN rising
VIN = 13 V, BuckA: LPM, BuckB: off
VIN = 13 V, BuckB: LPM, BuckA: off
VIN = 13 V, BuckA, B: LPM
30
35
40
45
40
45
50
55
µA
µA
µA
µA
LPM quiescent current:
TA = 25°C(1)
1.5
1.6
Iq_LPM_
VIN = 13 V, BuckA: LPM, BuckB: off
VIN = 13 V, BuckB: LPM, BuckA: off
VIN = 13 V, BuckA, B: LPM
LPM quiescent current:
TA = 125°C(1)
Iq_LPM
Normal operation, SYNC = 5 V
VIN = 13 V, BuckA: CCM, BuckB: off
VIN = 13 V, BuckB: CCM, BuckA: off
VIN = 13 V, BuckA, B: CCM
Quiescent current:
TA = 25°C(1)
1.7
1.8
Iq_NRM
4.85
7
5.3
7.6
mA
mA
Normal operation, SYNC = 5V
VIN = 13 V, BuckA: CCM, BuckB: off
VIN = 13 V, BuckB: CCM, BuckA: off
VIN = 13 V, BuckA, B: CCM
Quiescent current:
TA = 125°C(1)
Iq_NRM
5
5.5
mA
7.5
2.5
8
4
mA
µA
1.9
2.0
Ibat_sh
Shutdown current
BuckA, B: off, VBat = 13 V
Input Voltage VIN - Overvoltage Lockout
VIN rising
VIN falling
45
43
1
46
44
2
47
45
3
V
V
2.1
VOVLO
Overvoltage shutdown
2.2
2.3
OVLOHys
OVLOfilter
Hysteresis
Filter time
V
5
µs
Gate Driver for PMOS
3.1
3.2
3.3
4.0
4.1
rDS(on)
PMOS OFF
10
5
20
10
Ω
mA
µs
IPMOS_ON
tdelay_ON
Gate current
Turnon delay
VIN = 13.5 V, Vgs = –5 V
C = 10 nF
10
Buck Controllers
VBuckA/B Adjustable output voltage range
0.9
0.792
–1%
11
0.808
1%
V
V
Measure FBX pin
0.800
0.800
Internal reference voltage in
normal mode
4.2
4.3
Vref, NRM
Internal tolerance on reference
Measure FBX pin
0.784
–2%
0.816
2%
V
Internal reference voltage in low
power mode
Vref, LPM
Internal tolerance on reference
V sense for forward current limit in Maximum sense voltage FBx = 0.75 V
4.4
4.5
60
75
90
mV
mV
CCM
(low duty cycles)
Vsense
V sense for reverse current limit in
CCM
Minimum sense voltage FBx = 1 V
Sense voltage in foldback FBx = 0 V
–65
17
–37.5
–23
48
4.6
4.7
VI-Foldback
tdead
V sense for output short
32.5
100
mV
ns
Shoot-through delay, blanking time
High-side minimum on-time
100
ns
4.8
4.9
DCNRM
DCLPM
Duty cycle
Maximum duty cycle (digitally controlled)
98.75%
Duty cycle LPM
80%
(1) Quiescent current specification is non-switching current consumption without including the current in the external feedback resistor
divider.
4
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Product Folder Link(s): TPS43350-Q1 TPS43351-Q1
TPS43350-Q1
TPS43351-Q1
www.ti.com
SLVSAR7B –JUNE 2011–REVISED MAY 2012
DC ELECTRICAL CHARACTERISTICS (continued)
VIN = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LPM entry threshold load current
as fraction of maximum set load
current
ILPM_Entry
1%
The exit threshold is specified to be always higher
than entry threshold
4.10
LPM exit threshold load current as
fraction of maximum set load
current
ILPM_Exit
10%
1.5
High-Side External NMOS Gate Drivers for Buck Controller
4.11
4.12
IGX1_peak
rDS(on)
Gate driver peak current
Source and sink driver
A
VREG = 5.8 V, IGX1 current = 200 mA
VREG = 5.8 V, IGX2 current = 200 mA
2
2
Ω
Low-Side NMOS Gate Drivers for Buck Controller
4.13
4.14
IGX2_peak
rDS(on)
Gate-driver peak current
Source and sink driver
1.5
A
Ω
Error Amplifier (OTA) for Buck Converters
COMPA, COMPB = 0.8 V,
source/sink = 5 µA, test in feedback loop
4.15
GmBUCK
Transconductance
0.72
50
1
1.35
200
mS
nA
4.16
5.0
5.1
5.2
5.3
5.4
IPULLUP_FBx
Pullup current at FBx pins
FBx = 0 V
100
Digital Inputs: ENA, ENB, SYNC
Vih
Higher threshold
Lower threshold
Resistance
VIN = 13 V
1.7
V
V
Vil
VIN = 13 V
0.7
2
Rih_SYNC
Ril_ENC
VSYNC = 5 V, SYNC: pulldown resistance
VENC = 5 V, ENC: pulldown resistance
500
500
kΩ
kΩ
Resistance
VENx = 0 V,
ENA, ENB: pull up current source
5.5
Iil_ENx
Pullup current
0.5
µA
6.0
6.1
6.2
6.3
6.4
6.5
7.0
Switching Parameters – Buck DC-DC Controllers
fSW_Buck
fSW_Buck
fSW_adj
fSYNC
Buck switching frequency
Buck switching frequency
Buck adjustable range
Buck synch. range
RT pin: GND
360
360
150
150
400
400
440
440
600
600
kHz
kHz
kHz
kHz
RT pin: 60-kΩ external resistor
RT pin: using external resistor
External clock input
fSS
Spread-spectrum spreading
TPS43351 only
5%
Internal Gate-Driver Supply
Internal regulated supply
VIN = 8 V to 18 V, EXTSUP = 0 V, SYNC = High
5.5
7.2
5.8
0.2%
7.5
6.1
1%
7.8
1%
V
V
7.1
VREG
IVREG = 0 mA to 100 mA, EXTSUP = 0 V,
SYNC = high
Load regulation
Internal regulated supply
Load regulation
EXTSUP = 8.5 V
7.2
7.3
VREG-EXTSUP
IEXTSUP = 0 mA to 125 mA, SYNC = High
EXTSUP = 8.5 V to 13 V
0.2%
IVREG = 0 mA to 100 mA ,
EXTSUP ramping positive
VEXTSUP-VREG Switchover voltage
4.4
4.6
4.8
V
7.4
7.5
VEXTSUP-Hys
IREG-Limit
Switchover hysteresis
Current limit on VREG
150
100
250
400
mV
mA
EXTSUP = 0 V, normal mode as well as LPM
IREG_EXTSUP-
Current limit on VREG when using IVREG = 0 mA to 100 mA,
7.6
125
400
mA
EXTSUP
EXTSUP = 8.5 V, SYNC = High
Limit
8.0
8.1
Soft Start
ISSx
Soft-start source current
SSA and SSB = 0 V
0.75
1
1.25
µA
V
9.0
Oscillator (RT)
VRT
9.1
Oscillator reference voltage
1.2
10.0
10.1
10.2
10.3
10.4
10.5
10.6
10.7
Power Good / Delay
PGpullup
PGth1
Pullup for A and B
internal pullup to Sx2
FBx falling
50
–7%
2%
kΩ
Power-good threshold
Hysteresis
–5%
–9%
PGhys
PGdrop
Voltage drop
IPGA = 5 mA
450
100
1
mV
mV
µA
us
IPGA = 1 mA
PGleak
tdeglitch
Leakage
VSx2 = VPGx = 13 V
Power-good deglitch
Deglitch time
2
16
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TPS43350-Q1
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SLVSAR7B –JUNE 2011–REVISED MAY 2012
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DC ELECTRICAL CHARACTERISTICS (continued)
VIN = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
External capacitor = 1 nF
VBUCKX < PGth1
10.8
tdelay
Reset delay
1
ms
10.9
10.10
10.11
11.0
tdelay_fix
Fixed reset delay
No external capacitor, pin open
Current to charge external capacitor
Current to discharge external capacitor
20
40
40
50
50
50
µs
µA
µA
Ioh
Iil
Activate current source
Activate current sink
30
30
Overtemperature Protection
Tshutdown Shutdown threshold
Thys
11.1
Junction temperature
Hysteresis
150
165
15
°C
°C
11.2
6
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Product Folder Link(s): TPS43350-Q1 TPS43351-Q1
TPS43350-Q1
TPS43351-Q1
www.ti.com
SLVSAR7B –JUNE 2011–REVISED MAY 2012
DEVICE INFORMATION
DAP Package
(Top View)
1
VIN
VBAT
NC
28
EXTSUP
NC
2
3
37
36
NC
4
5
35
34
VREG
CBB
GC2
CBA
GA1
GB1
6
33
PHB
PHA
GA2
7
8
9
32
31
30
GB2
PGNDB
SB1
PGNDA
SA1
10
29
SB2
SA2
11
12
28
27
FBB
FBA
COMPB
SSB
COMPA
SSA
13
14
15
26
25
24
PGB
PGA
ENA
ENB
NC
16
23
AGND
RT
17
18
22
21
DLYAB
SYNC
AGND
19
20
PIN FUNCTIONS
NAME
NO.
I/O
DESCRIPTION
19,
23
AGND
O
Analog ground reference
A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck
controller BuckA. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the
high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
CBA
5
I
I
A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck
controller BuckB. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the
high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
CBB
34
13
26
21
16
17
37
12
27
Error-amplifier output of BuckA and compensation node for voltage loop stability. The voltage at this node sets the
target for the peak current through the inductor of BuckA. This voltage is clamped on the upper and lower ends to
provide current-limit protection for the external MOSFETs.
COMPA
COMPB
DLYAB
ENA
O
O
O
I
Error amplifier output of BuckB and compensation node for voltage loop stability. The voltage at this node sets the
target for the peak current through the inductor of BuckB. This voltage is clamped on the upper and lower ends to
provide current-limit protection for the external MOSFETs.
The capacitor at the DLYAB pin sets the power-good delay interval used to de-glitch the outputs of the power-
good comparators. When this pin is left open, the power-good delay is set to an internal default value of 20 µs
typical.
Enable inputs for BuckA (active-high with an internal pullup current source). An input voltage higher than 1.5 V
enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and
ENB are low, the device is shut down and consumes less than 4 µA of current.
Enable inputs for BuckB (active-high with an internal pullup current source). An input voltage higher than 1.5 V
enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and
ENB are low, the device is shut down and consumes less than 4 µA of current.
ENB
I
EXTSUP can be used to supply the VREG regulator from one of the TPS43350-Q1 or TPS43351-Q1 buck
regulator rails to reduce power dissipation in cases where VIN is expected to be high. When EXTSUP is open or
lower than 4.6 V, the regulator is powered from VIN.
EXTSUP
FBA
I
Feedback voltage pin for BuckA. The buck controller regulates the feedback voltage to the internal reference of
0.8 V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output
voltage.
I
Feedback voltage pin for BuckB. The buck controller regulates the feedback voltage to the internal reference of
0.8 V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output
voltage.
FBB
I
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PIN FUNCTIONS (continued)
NAME
GA1
NO.
I/O
DESCRIPTION
External high-side N-channel MOSFET for buck regulator BuckA can be driven from this output. The output
provides high peak currents to drive capacitive loads. The gate drive is referred to a floating ground reference
provided by PHA and has a voltage swing provided by CBA.
6
O
External low-side N-channel MOSFET for buck regulator BuckA can be driven from this output. The output
provides high peak currents to drive capacitive loads. The voltage swing on this pin is provided by VREG.
GA2
GB1
8
O
O
External high-side N-channel MOSFET for buck regulator BuckB can be driven from this output. The output
provides high peak currents to drive capacitive loads. The gate drive is referred to a floating ground reference
provided by PHB and has a voltage swing provided by CBB.
33
External low-side N-channel MOSFETs forbuck regulator BuckB can be driven from this output. The output
provides high peak currents to drive capacitive loads. The voltage swing on this pin is provided by VREG.
GB2
GC2
31
4
O
O
A floating output drive to control the external P-channel MOSFET is available at this pin. This MOSFET can be
used to bypass a reverse-protection diode, and thus reduce power losses.
2, 3,
18,
36
NC
–
PGNDA
PGNDB
9
O
O
Power ground connection to the source of the low-side N-channel MOSFETs of BuckA.
Power ground connection to the source of the low-side N-channel MOSFETs of BuckB
30
Open-drain power-good indicator pin for BuckA. An internal power-good comparator monitors the voltage at the
feedback pin and pulls this output low when the output voltage falls below 93% of the set value.
PGA
PGB
PHA
PHB
15
24
7
O
O
O
O
Open-drain power-good indicator pin for BuckB. An internal power-good comparator monitors the voltage at the
feedback pin and pulls this output low when the output voltage falls below 93% of the set value.
Switching terminal of buck regulator BuckA, providing a floating ground reference for the high-side MOSFET gate-
driver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired.
Switching terminal of buck regulator BuckB, providing a floating ground reference for the high-side MOSFET gate-
driver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired.
32
The operating switching frequency of the buck controllers is set by connecting a resistor to ground on this pin. A
short circuit to ground on this pin defaults operation to 400 kHz for the buck controllers.
RT
22
10
O
I
SA1
High-impedance differential-voltage inputs from the current-sense element (sense resistor or inductor DCR) for
each buck controller. The current-sense element should be chosen to set the maximum current through the
inductor based on the current-limit threshold (subject to tolerances) and considering the typical characteristics
across duty cycle and VIN. (SA1 positive node, SA2 negative node)
SA2
SB1
SB2
11
29
28
I
I
I
High-Impedance differential-voltage inputs from the current-sense element (sense resistor or inductor DCR) for
each buck controller. The current-sense element should be chosen to set the maximum current through the
inductor based on the current-limit threshold (subject to tolerances) and considering the typical characteristics
across duty cycle and VIN. (SB1 positive node, SB2 negative node)
Soft-start or tracking input for buck controller BuckA. The buck controller regulates the FBA voltage to the lower of
0.8 V or the SSA pin voltage. An internal pullup current source of 1 µA is present at the pin, and an appropriate
capacitor connected here can be used to set the soft-start ramp interval. A resistor divider connected to another
supply can also be used to provide a tracking input to this pin.
SSA
SSB
14
25
O
O
Soft-start or tracking input for buck controller BuckB. The buck controller regulates the FBB voltage to the lower of
0.8 V or the SSB pin voltage. An internal pullup current source of 1 µA is present at the pin, and an appropriate
capacitor connected here can be used to set the soft-start ramp interval. A resistor divider connected to another
supply can also be used to provide a tracking input to this pin.
If an external clock is present on this pin, the device detects it, and the internal PLL locks on to the external clock.
This overrides the internal oscillator frequency. The device can synchronize to frequencies from 150 kHz to 600
kHz. A high logic level on this pin ensures forced continuous-mode operation of the buck controllers and inhibits
transition to low-power mode. An open or low allows discontinuous-mode operation and entry into low-power
mode at light loads. On the TPS43351, a high level enables frequency-hopping spread spectrum, whereas an
open or a low level disables it.
SYNC
20
I
VBAT
VIN
1
I
I
Supply pin
Main input pin. This is the buck controller input pin. Additionally, it powers the internal control circuits of the
device.
38
An external capacitor on this pin is required to provide a regulated supply for the gate drivers of the buck
controllers. A capacitance in the order of 4.7 µF is recommended. The regulator can be used such that it is either
powered from VIN or EXTSUP. This pin has current-limit protection and should not be used to drive any other
loads.
VREG
35
O
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Internal ref (Band gap)
Gate Driver Supply
38
1
5
6
7
8
9
VIN
CBA
GA1
VBAT
PWM logic
PHA
VREG
37
35
22
EXTSUP
VREG
RT
GA2
PGNDA
Internal Oscillator
180deg
Slope
Comp
+
10
11
12
SA1
SA2
FBA
SYNC &LPM
+ Current
Sense Amp
20
SYNC
GC2
+
-
-
PWM comp
-
Source/Sink
Logic
4
+
gm OTA
+
0.8
V
SSA
EN
13
15
COMPA
PGA
1µA
SA2
-
FBA
14
SSA
ENA
+
VIN
VIN
500 nA
500 nA
16
ENA
ENB
17
25
34
33
32
31
30
29
28
27
26
24
CBB
GB1
1µA
SSB
PHB
ENB
GB2
VREF
PGNDB
SB1
40 µA
Second Buck Controller Channel
SB2
21
23
DLYAB
AGND
FBB
40 µA
COMPB
PGB
Figure 2. Functional Block Diagram
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TYPICAL CHARACTERISTICS
EFFICIENCY ACROSS OUTPUT CURRENTS (BUCKS)
VIN = 12V, VOUT = 5V, SWITCHING FREQUENCY = 400kHz
INDUCTOR = 4.7µH, RSENSE = 10mW
10000
100
EFFICIENCY,
SYNC = LOW
90
80
70
60
50
40
30
20
10
0
1000
100
10
POWER LOSS,
SYNC = HIGH
POWER LOSS,
SYNC = LOW
1
EFFICIENCY,
SYNC = HIGH
0.1
0.0001
0.001
0.01
0.1
1
10
OUTPUT CURRENT (A)
Figure 3.
Figure 4.
SOFT-START OUTPUTS (BUCK)
VOUTA
VOUTB
1V/DIV
2ms/DIV
Figure 5.
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
BUCK LOAD STEP: LOW POWER MODE EXIT
(90 mA TO 4 A AT 2.5 A/µs)
VIN = 12 V, VOUT = 5 V, SWITCHING FREQUENCY = 400 kHz
INDUCTOR = 4.7 µH, RSENSE = 10 mW
100 mV/DIV
VOUT AC-COUPLED
2 A/DIV
IIND
50 µs/DIV
Figure 8.
Figure 7.
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TYPICAL CHARACTERISTICS (continued)
BUCKx PEAK CURRENT LIMIT vs. COMPx VOLTAGE
NO-LOAD QUIESCENT CURRENT
ACROSS TEMPERATURE
75
62.5
50
60
50
40
30
20
10
0
37.5
25
BOTH BUCKS ON
12.5
0
SYNC = LOW
ONE BUCK ON
-12.5
-25
NEITHER BUCK ON
SYNC = HIGH
0.8 0.95
-37.5
0.65
1.1
1.25
1.4
1.55
-40 -15 10
35
60
85 110 135 160
COMPx VOLTAGE (V)
Temperature (°C)
Figure 9.
Figure 10.
FOLDBACK CURRENT LIMIT (BUCK)
CURRENT SENSE PINS INPUT CURRENT (BUCK)
0.9
80
70
60
50
40
30
20
10
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
150°C
25°C
-0.1
-0.2
-0.3
0
1
2
3
4
5
6
7
8
9
10 11 12
0
0.2
0.4
0.6
0.8
OUTPUT VOLTAGE (V)
FBx VOLTAGE (V)
Figure 11.
Figure 12.
REGULATED FBx VOLTAGE vs TEMPERATURE (BUCK)
CURRENT LIMIT VS DUTY CYCLE (BUCK)
805
804
803
802
801
800
799
798
797
796
795
80
70
60
50
40
30
20
10
0
VIN = 8V
VIN = 12V
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
-40 -15 10
35
60
85 110 135 160
TEMPERATURE (°C)
Figure 13.
Figure 14.
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DETAILED DESCRIPTION
BUCK CONTROLLERS: NORMAL MODE PWM OPERATION
Frequency Selection and External Synchronization
The buck controllers operate using constant-frequency peak-current mode control for optimal transient behavior
and ease of component choices. The switching frequency is programmable between 150 kHz and 600 kHz,
depending upon the resistor value at the RT pin. A short circuit to ground at this pin sets the default switching
frequency to 400 kHz. The frequency can also be set by a resistor at RT according to the formula:
X
f
=
(X=24kΩ×MHz)
SW
RT
9
10
f
=24×
SW
RT
Equation 1. Switching Frequency
For example,
600 kHz requires 40 kΩ
150 kHz requires 160 kΩ
It is also possible to synchronize to an external clock at the SYNC pin in the same frequency range of 150 kHz to
600 kHz. The device detects clock pulses at this pin, and an internal PLL locks on to the external clock within the
specified range. The device can also detect a loss of clock at this pin, and when this is detected it sets the
switching frequency to the internal oscillator. The two buck controllers operate at identical switching frequencies,
180 degrees out of phase.
Enable Inputs
The buck controllers are enabled using independent enable inputs from the ENA and ENB pins. These are high-
voltage pins with a threshold of 1.5 V for high level and can be connected directly to the battery for self-bias. The
low threshold is 0.7 V. Both these pins have internal pullup currents of 0.5 µA (typical). As a result, an open
circuit on these pins enables the respective buck controllers. When both buck controllers are disabled, the device
is shut down and consumes a current less than 4 µA.
Feedback Inputs
The output voltage is set by choosing the right resistor feedback divider network connected to the FBx (feedback)
pins. This is to be chosen such that the regulated voltage at the FBx pin equals 0.8 V. The FBx pins have a 100-
nA pullup current source as a protection feature in case the pins open up as a result of physical damage.
Soft-Start Inputs
In order to avoid large inrush currents, the buck controllers have independent programmable soft-start timers.
The voltage at the SSx pins acts as the soft-start reference voltage. A 1-µA pullup current is available at the SSx
pins, and by choosing a suitable capacitor, a ramp of the desired soft-start speed can be generated. After start-
up, the pullup current ensures that this node is higher than the internal reference of 0.8 V ,which then becomes
the reference for the buck controllers. The soft-start ramp time is defined by:
I
×Δt
SS
C
=
(Farads)
SS
ΔV
Equation 2. SoftStart Ramp Time
where,
ISS = 1 µA (typical)
∆V = 0.8 V
CSS is the required capacitor for ∆t, the desired soft-start time.
Alternatively, the soft-start pins can be used as tracking inputs. In this case, they should be connected to the
supply to be tracked via a suitable resistor divider network.
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Current-Mode Operation
Peak current-mode control regulates the peak current through the inductor such that the output voltage is
maintained at its set value. The error between the feedback voltage at FBx and the internal reference produces a
signal at the output of the error amplifier (COMPx) which serves as a target for the peak inductor current. The
current through the inductor is sensed as a differential voltage at Sx1 – Sx2 and compared with this target during
each cycle. A fall or rise in load current produces a rise or fall in voltage at FBx, causing COMPx to fall or rise
respectively, thus increasing/decreasing the current through the inductor until the average current matches the
load. In this way, the output voltage is maintained in regulation.
The top N-channel MOSFET is turned on at the beginning of each clock cycle and kept on until the inductor
current reaches its peak value. Once this MOSFET is turned off, and after a small delay (shoot-through delay)
the lower N-channel MOSFET is turned on until the start of the next clock cycle. In dropout operation, the high-
side MOSFET stays on continuously. In every fourth clock cycle, the duty cycle is limited to 95% in order to
charge the bootstrap capacitor at CBx. This allows a maximum duty cycle of 98.75% for the buck regulators.
During dropout, the buck regulator switches at one-fourth of its normal frequency.
Current Sensing and Current Limit With Foldback
The maximum value of COMPx is clamped such that the maximum current through the inductor is limited to a
specified value. When the output of the buck regulator (and hence the feedback value at FBx) falls to a low value
due to a short-circuit or overcurrent condition, the clamped voltage at COMPx successively decreases, thus
providing current foldback protection. This protects the high-side external MOSFET from excess current (forward-
direction current limit).
Similarly, if due to a fault condition the output is shorted to a high voltage and the low-side MOSFET turns fully
on, the COMPx node drops low. It is clamped on the lower end as well, in order to limit the maximum current in
the low-side MOSFET (reverse-direction current limit).
The current through the inductor is sensed by an external resistor. The sense resistor should be chosen such
that the maximum forward peak current in the inductor generates a voltage of 75 mV across the sense pins. This
value is specified at low duty cycles only. At typical duty-cycle conditions around 40% (assuming 5-V output and
12-V input), 50 mV is a more reasonable value, considering tolerances and mismatches. The typical
characteristics provide a guide for using the correct current-limit sense voltage.
The current-sense pins Sx1 and Sx2 are high-impedance pins with low leakage across the entire output range.
This allows DCR current sensing using the dc resistance of the inductor for higher efficiency. DCR sensing is
shown in Figure 15. Here the series resistance (DCR) of the inductor is used as the sense element. The filter
components should be placed close to the device for noise immunity. It should be remembered that while the
DCR sensing gives high efficiency, it is inaccurate due to the temperature sensitivity and a wide variation of the
parasitic inductor series resistance. Hence, it may often be advantageous to use the more-accurate sense
resistor for current sensing.
Inductor L
TPS43350-Q1
TPS43351-Q1
VBUCK X
DCR
R1
C1
Sx2
VC
Sx1
Figure 15. DCR Sensing Configuration
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Slope Compensation
Optimal slope compensation, which is adaptive to changes in input voltage and duty cycle, allows stable
operation at all conditions. For optimal performance of this circuit, the following condition must be satisfied in the
choice of inductor and sense resistor:
L×f
SW
=200
R
S
Equation 3 Inductor and Sense Resistor Choice
where
L is the buck regulator inductor in henries
RS is the sense resistor in ohms
fsw is the buck regulator switching frequency in hertz
Power Good Outputs and Filter Delays
Each buck controller has an independent power-good comparator monitoring the feedback voltage at the FBx
pins and indicating whether the output voltage has fallen below a specified power-good threshold. This threshold
has a typical value of 93% of the regulated output voltage. The power-good indicator is available as an open-
drain output at the PGx pins. An internal 50-kΩ pullup resistor to Sx2 is available or an external resistor can be
used. When a buck controller is shut down, the power-good indicator is pulled down internally. Connecting the
pullup resistor to a rail other than the output of that particular buck channel causes a constant current flow
through the resistor when the buck controller is powered down.
In order to avoid triggering the power-good indicators due to noise or fast transients on the output voltage, an
internal delay circuit for de-glitching is used. Similarly, when the output voltage returns to its set value after a long
negative transient, the power-good indicator is asserted high (the open-drain pin released) after the same delay.
This can be used to delay the reset to the circuits being powered from the buck regulator rail. The delay of this
circuit can be programmed by using a suitable capacitor at the DLYAB pin according to the equation:
tDELAY
1 msec
=
CDLYAB
1 nF
Equation 4 Power Good Indicator Delay
When the DLYAB pin is open, the delay is set to a default value of 20 µs, typical. The power-good delay timing is
common to both the buck rails, but the power-good comparators and indicators function independently.
Light Load PFM Mode
An external clock or a high level on the SYNC pin results in forced continuous-mode operation of the bucks.
When the SYNC pin is low or open, the buck controllers are allowed to operate in discontinuous mode at light
loads by turning off the low-side MOSFET whenever a zero-crossing in the inductor current is detected.
In discontinuous mode, as the load decreases, the duration of the clock period when both the high-side and the
low-side MOSFETs are turned off increases (deep discontinuous mode). In case the duration exceeds 60% of
the clock period and VBAT > 8 V, the buck controller switches to a low-power operation mode. The design
ensures that this typically occurs at 1% of the set full-load current if the inductor and the sense resistor have
been chosen appropriately as recommended in the Slope Compensation section.
In low-power PFM mode, the buck monitors the FBx voltage and compares it with the 0.8-V internal reference.
Whenever the FBx value falls below the reference, the high-side MOSFET is turned on for a pulse duration
inversely proportional to the difference VIN – Sx2. At the end of this on-time, the high-side MOSFET is turned off
and the current in the inductor decays until it becomes zero. The low-side MOSFET is not turned on. The next
pulse occurs the next time FBx falls below the reference value. This results in a constant volt-second ton
hysteretic operation with a total device quiescent current consumption of 30 µA when a single buck channel is
active and 35 µA when both channels are active.
As the load increases, the pulses become more and more frequent and move closer to each other until the
current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed-frequency
current-mode control. Another criterion to exit the low-power mode is when VIN falls low enough to require higher
than 80% duty cycle of the high-side MOSFET.
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The TPS43350-Q1 and TPS43351-Q1 can support the full current load during low-power mode until the
transition to normal mode takes place. The design ensures that exit from the low-power mode occurs at 10%
(typical) of full-load current if the inductor and sense resistor have been chosen as recommended. Moreover,
there is always a hysteresis between the entry and exit thresholds to avoid oscillating between the two modes.
In the event that both buck controllers are active, low-power mode is only possible when both buck controllers
have light loads that are low enough for low-power-mode entry.
Frequency-Hopping Spread Spectrum (TPS43351 Only)
The TPS43351-Q1 features a frequency-hopping pseudo-random spectrum spreading architecture. On this
device, whenever the SYNC pin is high, the internal oscillator frequency is varied from one cycle to the next
within a band of ±5% around the value programmed by the resistor at the RT pin. The implementation uses a
linear feedback shift register that changes the frequency of the internal oscillator based on a digital code. The
shift register is long enough to make the hops pseudo-random in nature and is designed in such a way that the
frequency shifts only by one step at each cycle to avoid large jumps in the buck switching frequencies.
Table 1. Frequency Hopping Control
SYNC
TERMINAL
FREQUENCY SPREAD SPECTRUM (FSS)
COMMENTS
Device in forced continuous mode, internal PLL locks into external clock
between 150 kHz and 600 kHz.
External clock
Not active
Not active
Device can enter discontinuous mode. Automatic LPM entry and exit,
depending on load conditions
Low or open
High
TPS43350: FSS not active
TPS43351: FSS active
Device in forced continuous mode
Table 2. Mode of Operation
ENABLE AND INHIBIT PINS
BUCK CONTROLLER STATUS
DEVICE STATUS
QUIESCENT CURRENT
ENA
Low
ENB
SYNC
Low
X
Shutdown
Shutdown
≈4 µA
Low
High
Low
High
Low
High
BuckB: LPM enabled
BuckB: LPM inhibited
BuckA: LPM enabled
BuckA: LPM inhibited
BuckA/B: LPM enabled
BuckA/B: LPM inhibited
≈30 µA (light loads)
mA range
Low
High
High
High
Low
High
BuckB running
≈30 µA (light loads)
mA range
BuckA running
≈35 µA (light loads)
mA range
Bucks A and B running
Gate Driver Supply (VREG, EXTSUP)
The gate drivers of the buck controllers are supplied from an internal linear regulator whose output (5.8 V typical)
is available at the VREG pin and should be decoupled using at least a 3.3-µF ceramic capacitor. This pin has an
internal current-limit protection and should not be used to power any other circuits.
The VREG linear regulator is powered from VIN by default when the EXTSUP voltage is lower than 4.6 V (typ.).
In case VIN expected to go to high levels, there can be excessive power dissipation in this regulator, especially
at high switching frequencies and when using large external MOSFETs. In this case, it is advantageous to power
this regulator from the EXTSUP pin, which can be connected to a supply lower than VIN but high enough to
provide the gate drive. When EXTSUP is connected to a voltage greater than 4.6 V, the linear regulator
automatically switches to EXTSUP as its input to provide this advantage. Efficiency improvements are possible
when one of the switching regulator rails from the TPS4335x-Q! or any other voltage available in the system is
used to power EXTSUP. The maximum voltage that should be applied to EXTSUP is 13 V.
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VIN
EXTSUP
LDO
EXTSUP
LDO
VIN
typ 5.8 V
typ 7.5 V
typ 4.6 V
VREG
Figure 16. Internal Gate Driver Supply
Using a large value for EXTSUP is advantageous as it provides a large gate drive and hence better on-
resistance of the external MOSFETs. A 0.1-µF ceramic capacitor is recommended for decoupling the EXTSUP
pin when not being used.
During low-power mode, the EXTSUP functionality is not available. The internal regulator operates as a shunt
regulator powered from VIN and has a typical value of 7.5 V. Current -limit protection for VREG is available in
low-power mode as well.
External P-Channel Drive (GC2) and Reverse Battery Protection
The TPS43350x-Q1 includes a gate driver for an external P-channel MOSFET which can be connected across
the reverse-battery diode. This is useful to reduce power losses and the voltage drop over a typical diode. The
gate driver provides a swing of 6 V typical below the VIN voltage in order to drive a P-channel MOSFET.
GC2
TPS43350/1
VBAT
VIN
Fuse
VBAT
Figure 17. Reverse-Battery Protection Option
Undervoltage Lockout and Overvoltage Protection
The TPS4335x-Q1 starts up at a VIN voltage of 6.5 V (minimum), required for the internal supply (VREG). Once
it has started up, the device operates down to a VIN voltage of 3.6 V; below this voltage level, the undervoltage
lockout disables the device. Note: if Vin drops, VREG drops as well; hence, the gate-drive voltage is reduced
while the digital logic is fully functional. A voltage of 46 V at VIN triggers the overvoltage comparator, which shuts
down the device. In order to prevent transient spikes from shutting down the device, under- and overvoltage
protection have filter times of 5 µs (typical).
When the voltages return to the normal operating region, the enabled switching regulators start including a new
soft-start ramp for the buck regulators.
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Thermal Protection
The TPS43350/1 protects itself from overheating using an internal thermal shutdown circuit. If the die
temperature exceeds the thermal shutdown threshold of 165 degrees Celsius due to excessive power dissipation
(for example, Due to fault conditions such as a short circuit at the gate drivers or VREG), the controllers are
turned off and restarted when the temperature has fallen by 15 degrees.
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APPLICATION INFORMATION
The following example illustrates the design process and component selection for the TPS43350-Q1. The design
goal parameters are given in Table 3.
Table 3. Application Example
PARAMETER
VBUCK A
VBUCK B
VIN 6 V to 30 V
12 V - typ
VIN 6 V to 30 V
12 V - typ
Input voltage
Output voltage, VO
5 V
3 A
3.3 V
2 A
Max - output current, IO
Load step output tolerance, ∆VO
Current output load step, ∆IO
±0.2 V
±0.12 V
0.1 A to 2 A
400 kHz
0.1 A to 3 A
400 kHz
Converter switching frequency, fSW
This is a starting point, and theoretical representation of the values to be used for the application; further
optimization of the components derived may be required to improve the performance of the device.
BuckA Component Selection
Minimum ON Time, tON min
VO
5 V
tON min
=
=
= 416 ns
VIN max ´ fSW 30 V ´ 400 kHz
This is higher than the minimum on-time specified (100 ns typical). Hence, the minimum duty cycle is achievable
at this frequency.
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Current Sense Resistor RSENSE
Based on the typical characteristics for VSENSE limit with VIN versus duty cycle, the sense limit is approximately 65
mV (at VIN = 12 V and duty cycle of 5 V / 12 V = 0.416). Allowing for tolerances and ripple currents, choose
VSENSE max of 50 mV.
Select 15 mΩ.
Inductor Selection L
As explained in the description of the buck controllers, for optimal slope compensation and loop response, the
inductor should be chosen such that:
KFLR = Coil selection constant = 200
Choose a standard value of 8.2 µH. For the buck converter, the inductor saturation currents and core should be
chosen to sustain the maximum currents.
Inductor Ripple Current IRIPPLE
At nominal input voltage of 12V, this gives a ripple current of 30% of IO max ≈ 1A.
Output Capacitor CO
Select an output capacitance CO of 100 µF with low ESR in the range of 10 mΩ. This gives ∆VO(Ripple) ≈ 15 mV
and ∆V drop of ≈ 180 mV during a load step, which does not trigger the power-good comparator and is within the
required limits.
Bandwidth of Buck Converter fC
Use the following guidelines to set frequency poles, zeroes and crossover values for a tradeoff between stability
and transient response.
•
•
•
Crossover frequency fC between fSW / 6 and fSW / 10. Assume fC = 50 kHz.
Select the zero fz ≈ fC / 10.
Make the second pole fP2 ≈ fSW / 2.
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SLVSAR7B –JUNE 2011–REVISED MAY 2012
Selection of Components for Type II Compensation
VO
RESR
R1
R2
VSENSE
RL
COMP
Type 2A
GmBUCK
CO
Vref
R3
C1
R0
C2
Figure 18. Buck Compensation Components
2p´ fC ´ VO ´ CO
2p´ 50 kHz ´ 5 V ´100μF
R3 =
=
= 23.57 kW
GmBUCK ´KCFB ´ VREF
GmBUCK ´KCFB ´ VREF
Use the standard value of R3 = 24 kΩ,
Where VO = 5 V, CO = 100 µF, GmBUCK = 1 mS, VREF = 0.8 V
KCFB = 0.125 / RSENSE = 8.33 S (0.125 is an internal constant)
10
10
C1=
=
2p´R3 ´ fC 2p´ 24 kW ´ 50 kHz
= 1.33 nF
Use the standard value of 1.5 nF.
The resulting bandwidth of Buck Converter fC
GmBUCK ´R3 ´KCFB
VREF
fC =
´
2p´ CO
VO
1mS ´ 24 kW ´ 8.33 S ´ 0.8 V
2p´100 μF ´ 5 V
fC =
= 50.9 kHz
This is close to the target bandwidth of 50 kHz.
The resulting zero frequency fZ1
This is close to the fC / 10 guideline of 5 kHz.
The second pole frequency fP2
This is close to the fSW / 2 guideline of 200 kHz. Hence, all requirements for a good loop response are satisfied.
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Resistor Divider Selection for setting VO Voltage
VREF
0.8 V
b =
=
= 0.16
VO
5 V
Choose the divider current through R1 and R2 to be 50 µA. Then
and
Therefore, R2 = 16 kΩ and R1 = 84 kΩ.
BuckB Component Selection
Using the same method as VBUCKA, the following parameters and components are realized
VO
5 V
tON min
=
=
IN max ´ fSW 30 V ´ 400 kHz
= 416 ns
V
This is higher than the minimum duty cycle specified (100 ns typical).
∆Iripple current ≈ 0.4 A (approx. 20% of IO max
)
Select an output capacitance CO of 100 µF with low ESR in the range of 10 mΩ. This gives ∆VO (Ripple) ≈ 7.5
mV and a ∆V drop ≈ 120 mV during a load step.
Assume fC = 50 kHz.
2p´ fC ´ VO ´ CO
R3 =
GmBUCK ´KCFB ´ VREF
2p´ 50 kHz ´ 3.3 V ´100 mF
=
= 31kW
1mS ´ 4.16 S ´ 0.8 V
Use the standard value of R3 = 30 kΩ.
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SLVSAR7B –JUNE 2011–REVISED MAY 2012
10
10
C1=
=
2p´R3 ´ fC 2p´ 30 kW ´ 50 kHz
= 1.1nF
C1
f
C2 =
æ
ö
÷
ø
SW
2p´R3 ´ C1´
-1
ç
è
2
1.1nF
=
= 27 pF
400 kHz
2
æ
ö
÷
ø
2p´ 30 kW ´1.1nF´
-1
ç
è
GmBUCK ´R3 ´KCFB VREF
´
fC =
2p´ CO
VO
1mS ´ 30 kW ´ 4.16 S ´ 0.8 V
2p´100 μF ´ 3.3 V
=
= 48 kHz
This is close to the target bandwidth of 50 kHz.
The resulting zero frequency fZ1
1
1
fZ1
=
=
2p´R3 ´ C1 2p´ 30 kW ´1.1nF
= 4.8 kHz
This is close to the fC guideline of 5 kHz.
The second pole frequency fP2
1
1
fP2
=
=
2p´R3 ´ C2 2p´ 30 kW ´ 27 pF
= 196 kHz
This is close to the fSW / 2 guideline of 200 kHz.
Hence, all requirements for a good loop response are satisfied.
Resistor Divider Selection for Setting VO Voltage
VREF
0.8 V
b =
=
= 0.242
VO
3.3 V
Choose the divider current through R1 and R2 to be 50 µA. Then
and
Therefore, R2 = 16 kΩ and R1 = 50 kΩ.
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BuckX High-Side and Low-Side N-Channel MOSFETs
The gate-drive supply for these MOSFETs is supplied by an internal supply which is 5.8 V typical under normal
operating conditions. The output is a totem pole allowing full voltage drive of VREG to the gate with peak output
current of 1.2 A. The high-side MOSFET is referenced to a floating node at the phase terminal (PHx) and the
low-side MOSFET is referenced to the power ground (PGx) terminal. For a particular application, these
MOSFETs should be selected with consideration for the following parameters: rds(on), gate charge Qg, drain-to-
source breakdown voltage BVDSS, maximum dc current IDC(max), and thermal resistance for the package.
The times tr and tf denote the rising and falling times of the switching node and are related to the gate-driver
strength of the TPS43350x-Q1 and gate Miller capacitance of the MOSFET. The first term denotes the
conduction losses, which are minimized when the on-resistance of the MOSFET is low. The second term
denotes the transition losses, which arise due to the full application of the input voltage across the drain-source
of the MOSFET as it turns on or off. They are lower at low currents and when the switching time is low.
V ´I
æ
ç
è
O ö
÷
ø
= (IO )2 ´rDS(on)(1+ TC)´D +
´(tr + tf )´ fSW
I
P
BuckTOPFET
2
P
= (IO )2 ´rDS(on)(1+ TC)´(1-D) + VF ´IO ´(2´ td )´ fSW
buckLOWERFET
In addition, during dead time td when both the MOSFETs are off, the body diode of the low-side MOSFET
conducts, increasing the losses. This is denoted by the second term in the foregoing equation. Using external
Schottky diodes in parallel to the low-side MOSFETs of the buck converters helps to reduce this loss.
Note: The rDS(on) has a positive temperature coefficient which is accounted for in the TC term for rDS(on). TC = d ×
delta T[°C]. The temperature coefficient d is available as a normalized value from MOSFET data sheets and can
be assumed to be 0.005 / °C as a starting value.
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SLVSAR7B –JUNE 2011–REVISED MAY 2012
Schematic
The following section summarizes the previously calculated example and gives schematic and component
proposals. Table 3.
Table 4. Application Example
PARAMETER
VbuckA
VbuckB
VIN 6 V to 30 V
12 V, typ.
VIN 6 V to 30 V
12 V, typ.
Input voltage
Output voltage, VO
5 V
3 A
3.3 V
2 A
Max - output current, IO
Load step output tolerance, ∆VO
Current output load step, ∆IO
±0.2 V
±0.12 V
0.1 A to 2 A
400 kHz
0.1 A to 3 A
400 kHz
Converter switching frequency, fSW
VBAT
VIN
0.1µF
0.1µF
0.1µF
VIN
EXTSUP
VREG
SWRB
1kΩ
GC2
VBAT
0.1µF
VIN
VIN
SWBH
CBA
CBB
GB1
SWAH
GA1
PHA
PHB
SWBL
SWAL
GA2
GB2
L1
8.2µH
L2
15µH
PGNDA
PGNDB
VBUCKA
5V, 3A
VBUCKB
3.3V, 2A
SA1
SA2
FBA
SB1
SB2
FBB
0.015Ω
0.03Ω
COUTA
100µA
COUTB
100µA
84kΩ
16kΩ
50kΩ
16kΩ
5kΩ
27pF
5kΩ
33pF
1.1nF
1.5nF
COMPA
SSA
COMPB
SSB
24kΩ
30kΩ
10nF
10nF
PGA
PGB
ENA
ENB
AGND
RT
1nF
DLYAB
SYNC
Figure 19. Simplified Application Schematic Example
Table 5. Application Example – Component Proposals
NAME
COMPONENT PROPOSAL
VALUE
L1
MSS1278T-822ML (Coilcraft)
MSS1278T-153ML (Coilcraft)
SK103 (Micro Commercial Components)
IRF7416 (International Rectifier)
8.2 µH
15 µH
L2
D1
SWRB
SWAH, SWAL, SWBH,
SWBL
Si4840DY-T1-E3 (Vishay)
COUTA, COUTB
CIN
ECASD91A107M010K00 (Murata)
EEEFK1V331P (Panasonic)
100 µF
330 µF
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Power Dissipation Derating Profile, 38-Pin HTTSOP PowerPAD Package
Figure 20. Power Dissipation Derating Profile Based on High-K JEDEC PCB
PCB Layout Guidelines
Grounding and PCB Circuit Layout Considerations
Buck Converter
1. Connect the drain of SWAH and SWBH MOSFETs together with the positive terminal of the input capacitor
COUTA. The trace length between these terminals should be short.
2. Connect a local decoupling capacitor between the drain of SWxH and source of SWxL.
3. The Kelvin current sensing for the shunt resistor should have minimum trace spacing and routed parallel to
each other. Any filtering capacitors for noise should be placed near the IC pins.
4. The resistor divider for sensing output voltage is connected between the positive terminal of the respective
output capacitor and COUTA or COUTB and the IC signal ground. These components and the traces should
not be routed near any switching nodes or high-current traces.
Other Considerations
1. PGNDx and AGND should be shorted to the thermal pad. Use a star ground configuration if connecting to a
nonground plane system. Use tie-ins for the EXTSUP capacitor, compensation-network ground, and voltage-
sense feedback-ground networks to this star ground.
2. Connect a compensation network between the compensation pins and IC signal ground. Connect the
oscillator resistor (frequency setting) between the RT pin and IC signal ground. These sensitive circuits
should NOT be located near the dv/dt nodes; these include the gate-drive outputs and phase pins.
3. Reduce the surface area of the high-current-carrying loops to a minimum by ensuring optimal component
placement. Ensure the bypass capacitors are located as close as possible to their respective power and
ground pins.
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SLVSAR7B –JUNE 2011–REVISED MAY 2012
PCB Layout
POWER
INPUT
Power Lines
Connection to GND Plane of PCB through vias
Connection to top/bottom of PCB through vias
Voltage Rail Outputs
VIN
EXTSUP
NC
VBAT
NC
NC
VREG
CBB
GC2
CBA
GA1
PHA
GA2
PGNDA
SA1
GB1
PHB
GB2
PGNDB
SB1
SB2
SA2
FBB
FBA
COMPB
SSB
COMPA
SSA
PGA
ENA
ENB
NC
PGB
AGND
RT
DLYAB
SYNC
Exposed Pad
connected to GND
Plane
AGND
Microcontroller
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Apr-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS43350QDAPRQ1
TPS43351QDAPRQ1
ACTIVE
ACTIVE
HTSSOP
HTSSOP
DAP
DAP
38
38
1
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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相关型号：
TPS43351QDAPQ1
IC 0.4 A DUAL SWITCHING CONTROLLER, 600 kHz SWITCHING FREQ-MAX, PDSO38, PLASTIC, HTSSOP-38, Switching Regulator or Controller
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