TPS51163DRCR [TI]
SYNCHRONOUS BUCK CONTROLLER WITH HIGH-CURRENT GATE DRIVER; 高电流栅极驱动器同步降压控制器
| 型号： | TPS51163DRCR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SYNCHRONOUS BUCK CONTROLLER WITH HIGH-CURRENT GATE DRIVER |
| 文件： | 总26页 (文件大小：2200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS51113, TPS51163
www.ti.com ........................................................................................................................................................................................................ SLUS864–MAY 2009
SYNCHRONOUS BUCK CONTROLLER WITH HIGH-CURRENT GATE DRIVER
1
FEATURES
DESCRIPTION
•
•
•
•
•
Flexible Power Rails: 5 V to 12 V
Reference: 800 mV ± 0.8%
Voltage Mode Control
The TPS51113 and TPS51163 are cost-optimized,
feature rich, single-channel synchronous-buck
controllers that operates from a single 4.5-V to 13.2-V
supply and can convert an input voltage as low as
1.5 V.
Support Pre-biased Startup
Programmable Overcurrent Protection with
Low-Side RDS(on) Current Sensing
The controller implements voltage mode control with
a
fixed 300-kHz (TPS51113) and 600-kHz
•
Fixed 300-kHz (TPS51113) and 600-kHz
(TPS51163) Switching Frequency
(TPS51163) switching frequency. The overcurrent
(OC) protection employs the low-side RDS(on) current
sensing and has user-programmable threshold. The
OC threshold is set by the resistor from LDRV_OC
pin to GND. The resistor value is read when the
over-current programming circuit applies 10 µA of
current to the LDRV_OC pin during the calibration
phase of the start-up sequence.
•
•
•
UV/OV Protections and Power Good Indicator
Internal Soft-start
Integrated High-Current Drivers Powered by
VDD
•
10-Pin 3 × 3 SON Package
The TPS51113/TPS51163 also supports output
pre-biased startup.
APPLICATIONS
•
Server and Desktop Computer Subsystem
Power Supplies (MCH, IOCH, PCI, Termination)
Distributed Power Supplies
General DC-DC Converters
The strong gate drivers with low deadtime allow for
the utilization of larger MOSFETs to achieve higher
efficiency. An adaptive anti-cross conduction scheme
is used to prevent shoot-through between the power
FETs.
•
•
TYPICAL APPLICATION CIRCUIT
V
OUT
VDD
V
C3
IN
D1
TPS51113\TPS51163
R6
R4
1
2
3
4
5
BOOT
PGOOD 10
R1
Q1
Q2
C5
R3
SW
VOS
FB
9
8
7
6
L1
+
HDRV
C1
C2
C6
C7
LDRV_OC COMP_EN
R
V
R2
BIAS
OUT
R5
R
GND
VDD
Enable
OC
–
C4
11
UDG-08105
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TPS51113, TPS51163
SLUS864–MAY 2009........................................................................................................................................................................................................ www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
LEAD/BALL
FINISH
MSL PEAK
TEMPERATURE
ORDERABLE
DEVICE
TYPE
DRAWING PINS
QTY
ECO PLAN
TPS51113DRCR
TPS51163DRCR
TPS51113DRCT
TPS51163DRCT
Green
(RoHS and no Sb/Br)
SON
DRC
DRC
10
10
3000
CU NiPDAU
CU NiPDAU
Level-2-260C-1Year
Level-2-260C-1Year
Green
(RoHS and no Sb/Br)
SON
250
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Over operating free-air temperature range (unless otherwise noted, all voltages are with respect to GND.)
PARAMETER
VALUE
–0.3 to 15
–0.3 to 30
UNIT
VDD
BOOT
BOOT, to SW (negative overshoot –5 V for t < 25 ns,
125 V × ns/t for 25 ns < t< 100 ns)
–5.0 to 15
–5.0 to 37
Input voltage range
V
BOOT, (negative overshoot –5 V for t < 25ns,
125 V × ns/t for 25 ns < t < 100 ns)
All other pins
SW
–0.3 to 3.6
–0.3 to 22
SW, (negative overshoot –5 V for t < 25ns,
125 V × ns/t for 25 ns < t < 100 ns)
–5.0 to 30
–0.3 to 30
–5.0 to 15
HDRV
HDRV to SW (negative overshoot –5 V for t < 25 ns,
125 V × ns/t for 25 ns < t< 100 ns)
Output voltage range
HDRV (negative overshoot –5 V for t < 25ns,
125 V × ns/t for 25 ns < t < 100 ns)
V
–5.0 to 37
–0.3 to 15
–5.0 to 15
LDRV_OC
LDRV_OC (negative overshoot –5 V for t < 25ns,
125 V × ns/t for 25 ns < t < 100 ns)
PGOOD
–0.3 to 15
–0.3 to 3.6
–40 to 125
–55 to 150
All other pins
TJ
Operating junction temperature
°C
Tstg Storage junction temperature
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
MIN
TYP
MAX
2500
1500
UNIT
Human Body Model (HBM)
V
Charged Device Model (CDM)
2
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PACKAGE DISSIPATION RATINGS
R
θJA HIGH-K BOARD(1)
POWER RATING (W)
TA = 25°C
POWER RATING (W)
TA = 85°C
PACKAGE
AIRFLOW (LFM)
(°C/W)
0 (natural convection)
47.9
40.5
38.2
2.08
2.46
2.61
0.835
0.987
1.04
DRC
200
400
(1) Ratings based on JEDEC High Thermal Conductivity (High K) Board. For more information on the test method, see TI Technical Brief
(SZZA017).
RECOMMENDED OPERATING CONDITIONS
(unless otherwise noted, all voltages are with respect to GND)
MIN
–0.1
–0.1
TYP
MAX UNIT
13.2
VDD
BOOT
28.0
BOOT, to SW (negative overshoot –5 V for t < 25 ns,
125 V × ns/t for 25 ns < t< 100 ns)
–3.0
–3.0
13.2
V
Supply voltages
BOOT, (negative overshoot –5 V for t < 25 ns,
125 V × ns/t for 25 ns < t < 100 ns)
35.0
All other pins
SW
–0.1
–0.1
3.0
20.0
SW, (negative overshoot –5 V for t < 25 ns,
125 V × ns/t for 25 ns < t < 100 ns)
–3.0
–0.1
–3.0
28.0
28.0
13.2
HDRV
HDRV to SW (negative overshoot –5 V for t < 25 ns,
125 V × ns/t for 25 ns < t< 100 ns)
Output voltages
HDRV (negative overshoot –5 V for t < 25 ns,
125 V × ns/t for 25 ns < t < 100 ns)
V
–3.0
–0.1
–3.0
35.0
LDRV_OC
13.2
13.2
LDRV_OC (negative overshoot –5 V for t < 25 ns,
125 V × ns/t for 25 ns < t < 100 ns)
PGOOD
–0.1
–0.1
–40
13.2
3.0
All other pins
TA
Operating ambient temperature
85
°C
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ELECTRICAL CHARACTERISTICS
These specifications apply for -40°C ≤ TA ≤ to 85°C, VVDD = 12 Vdc. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
INPUT SUPPLY
VVDD
4.5
13.2
30
6
V
IVDD
Supply current
Shutdown current
Switching enabled(1)
mA
mA
Switching inhibited
VDD UVLO
UVLO
VDD UVLO
VDD raising
4.0
4.3
4.6
V
UVLOHYS
REFERENCE
VREF
UVLO threshold hysteresis
250
mV
Reference voltage
Reference voltage
0°C ≤ TA ≤ 85°C
794
792
800
800
806
808
mV
mV
–40°C ≤ TA ≤ 85°C
OSCILLATOR
TPS51113
TPS51163
270
540
300
600
1.5
330
660
Measured on the SW pin,
TA = 25°C
fSW
Switching frequency
kHz
V
VRAMP
PWM ramp amplitude(1)
PWM
TPS51113
TPS51163
72%
69%
DMAX
Maximum duty cycle
TONMIN
TNO
Minimum controlled pulse(1)
Output driver dead time
100
ns
ns
30
SOFT START
TSSD
Soft-start delay time
Soft-start time
4.0
2.0
5.5
3.5
7.0
5.0
ms
ms
TSS
ERROR AMPLIFIER
GBWP
Aol
Gain bandwidth product(1)
DC gain(1)
CCOMP < 20 pF
16
MHz
dB
89
–100
6
IIB
Input bias current
Error amplifier output slew rate(1)
nA
EASR
VCOMPDIS
CCOMP < 20 pF
V/µs
V
COMP_EN pin disabling voltage
0.8
SHORT CIRCUIT PROTECTION
IILIM
Overcurrent threshold set current
9.3
10.0
10.7
µA
GATE DRIVERS
IHDHI
High-side driver pull-up current(1)
BOOT to HDRV voltage is 5 V
VVDD = 12 V; IDRV = –100 mA
VDD to LDRV voltage is 5 V
VVDD = 12 V
1.5
1.4
1.5
0.8
A
Ω
A
Ω
RHDLO
ILDHI
High-side driver pull-down resistance
Low-side driver pull-up current(1)
RLDLO
Low-side driver pull-down resistance
(1) Ensured by design. Not production tested.
4
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ELECTRICAL CHARACTERISTICS (continued)
These specifications apply for -40°C ≤ TA ≤ to 85°C, VVDD = 12 Vdc. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
POWER GOOD
VPGLR
VPGLF
VPGUR
VPGUF
VPG
Lower powergood threshold
Lower powergood threshold
Upper powergood threshold
Upper powergood threshold
PGOOD pin voltage
VOS voltage rising
0.728 0.752 0.776
0.696 0.720 0.744
0.856 0.880 0.904
0.824 0.848 0.872
0.4
V
V
VOS voltage falling
VOS voltage rising
VOS voltage falling
IPDG = 4 mA
V
V
V
IPGDLK
Leakage current
VPGOOD = 5 V
20
µA
UV/OV PROTECTION
VUVP
VOVP
VOVPL
IOS
UVP threshold
VOS voltage falling
VOS voltage rising
VOS voltage falling
0.576 0.600 0.624
V
V
OVP threshold
0.96
0.376 0.400 0.424
–100 100
1.00
1.04
OVP latch threshold
VOS input bias current
V
nA
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TERMINAL INFORMATION
TERMINAL FUNCTIONS
TERMINAL
PIN
NO.
NAME
I/O
DESCRIPTION
Gate drive voltage for the high-side N-channel MOSFET. Typically, a 100 nF capacitor must be connected between this pin
and SW. Also, a diode from VDD to BOOT should be externally provided.
BOOT
COMP_EN
FB
1
I
Output of the error amplifier and the shutdown pin. Pulling the voltage on this pin lower than 800 mV shuts the controller
down.
7
8
I/O
I
Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal reference voltage of
800 mV.
GND
5
3
–
Common reference for the device.
HDRV
O
Gate drive output for the high-side N-channel MOSFET.
Gate drive output for the low-side or rectifier MOSFET. The set point is read during start up calibration with the 10 µA
current source present.
LDRV_OC
4
O
PGOOD
SW
10
2
O
O
I
Open drain power good output. An external pull-up resistor is required.
Sense line for the adaptive anti-cross conduction circuitry. Serves as common connection for the flying high-side FET driver.
Power input to the controller, 4.5 V to 13.2 V.
VDD
6
Input to set undervoltage and overvoltage protections. Undervoltage protection occurs when VOS voltage is lower than 600
mV. The controller shuts down with both MOSFETs latched off. Overvoltage protection occurs when VOS voltage is higher
than 1V, the upper MOSFET is turned off and the lower MOSFET is forced on until VOS voltage reaches 400 mV. Then the
lower MOSFET is also turned off. After the undervoltage or overvoltage events, normal operation can be restored only by
cycling the VDD voltage.
VOS
9
I
SON PACKAGE
(TOP VIEW)
BOOT
SW
1
2
3
4
5
10 PGOOD
9
8
7
6
VOS
TPS51113DRC
TPS51163DRC
HDRV
FB
LDRV_OC
GND
COMP_EN
VDD
6
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FUNCTIONAL BLOCK DIAGRAM
TPS51113\TPS51163
PGOOD 10
1
3
2
BOOT
HDRV
SW
UV/OV and
PGOOD
Control
VOS
VDD
9
6
7
3.3-V
Regulator
3.3 V
PWM
COMP_EN
3.3 V
+
PWM
Logic
Anti-Cross
Conduction
FB
8
SS
+
RAMP
Oscillator
S1
0.8 V
+
CLK
4
5
LDRV_OC
GND
Current Sense
Self-Calibration and
Soft-Start Control
OCP Logic
UDG-08106
PERFORMANCE DATA
1.605
1.603
1.605
I
= 20 A
OUT
1.603
1.601
1.601
1.599
1.597
1.599
V
V
V
= 5 V, V
= 5 V
BOOT
VDD
VDD
VDD
1.597
1.595
= 10 V, V
= 12 V, V
= 10 V
= 12 V
BOOT
BOOT
1.595
0
4
8
12 16
– Output Current – A
20
24
5
6
7
8
9
10
11
12
I
V
– Input Voltage – V
IN
OUT
Figure 1. Load Regulation
Figure 2. Line Regulation
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PERFORMANCE DATA (continued)
Figure 3. Startup Waveform at VIN = 5 V,
VOUT = 1.6 V (IOUT = 0 A)
Figure 4. Startup Waveform at VIN= 12 V,
VOUT= 1.6 V, IOUT=0 A
CH1: COMP_EN
CH1: COMP_EN
CH2: PGOOD
CH3: VOUT
CH4: LDRV
CH2: PGOOD
CH3: VOUT
CH4: LDRV
Figure 5. Load Step 0 A to 5 A
Figure 6. Load Step 5 A to 0 A
8
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DETAILED DESCRIPTION
TPS51113 and TPS51163 are cost-optimized, single channel synchronous buck controllers that operate at a
300-kHz (TPS51113) and 600-kHz (TPS51163) fixed switching frequency, from a single 4.5-V to 13.2-V supply,
and supports output pre-biased startup. The overcurrent protection uses the low-side RDS(on) current sensing for
a low-cost, loss-less solution. Other features include input undervoltage lockout (UVLO), programmable
overcurrent threshold, soft-start, output oververvoltage/undervoltage (OV/UV) protection.
SOFT START AND SELF-CALIBRATION
When VDD is above 4.3 V and the COMP_EN pin is released from being pulled low with open-drain system
logic, the controller enters the start-up sequence. There is a two stage start-up sequence for the COMP_EN
voltage. In the first phase of start-up (tSS_delay), the controller completes self-calibration and inhibits FET
switching, leaving both the upper and lower MOSFETs in the off state. In the second phase of start-up (tSS),
soft-start begins and switching is enabled. The internal reference gradually rises to 800 mV, and the output
voltage gets within its regulation point. The soft-start time (tSS) is internally programmed at 3.5 ms, and tSS_Delay is
programmed at 5.5 ms. On average, it takes approximately 9 ms for the output voltage to come into regulation
after the COMP_EN pin is released.
Figure 7 shows the typical startup and shutdown sequence. The overcurrent protection is enabled when the
soft-start begins and the soft-start voltage exceeds the pre-biased VOS voltage. The output overvoltage
protection is enabled approximately 64 clock cycles after the COMP pin voltage rises above 0.8 V (thereby
enabling the device). When the soft-start ends, the output undervoltage protection is enabled, and PGOOD
signal also goes high at the same time.
1 V
V
t
t
SS
COMP_EN
SS_Delay
6% of V
OUT
V
OUT
PGOOD Delay
at Shutdown
V
PGOOD
PGOOD Delay at Startup
t – Time
UDG-08108
Figure 7. Typical Startup and Shutdown Sequence
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OVERCURRENT PROTECTION
Overcurrent detection is done by comparing a user programmable threshold with the voltage drop across the
low-side FET at the end of the switching period (The low-side FET is on). The OC threshold is set with a single
external resistor connected from the LDRV_OC pin to GND.
The overcurrent programming circuit applies 10-µA of current to the LDRV_OC pin during the calibration phase
of the start-up sequence. Voltage drop on the LDRV_OC pin is measured and digitized, and the related code is
stored in the internal latch. This code determines a reference level for the overcurrent comparator. The value of
the OC set resistor ROCSET can be determined in Equation 1.
I
æ
ö
÷
ø
RIPPLE
R
´ I
-
ç OC
LDS on
( )
2
è
R
=
OCSET
10mA
(1)
where
•
•
•
•
RLDS(on) is the drain-to-source resistance of the lower MOSFET in the ON state
IOC is the desired value of the overcurrent protection threshold for load current
IRIPPLE is the peak-to-peak amplitude of the inductor ripple current
the valley of the inductor current is compared with the overcurrent threshold for protection
When the controller senses the overcurrent condition for more than two clock cycles, both the upper and the
lower MOSFETs are latched off. To restart the controller, the VDD input should be cycled.
If the overcurrent set resistor value is higher than 50 kΩ, for example, the voltage drop on the LDRV_OC pin
exceeds 0.5 V, the controller stays in the calibration state without entering soft-start. This prevents the controller
from being activated if the overcurrent set resistor is missing.
OVERVOLTAGE (OV) AND UNDERVOLTAGE (UV) PROTECTION
The controller employs the dedicated VOS input to set output undervoltage and overvoltage protections. A
resistor divider with the same ratio as on the FB input is recommended for the VOS input. The overvoltage and
undervoltage thresholds for VOS are set to 25% of the internal reference, which is 800 mV.
When the voltage on VOS is lower than 600 mV, the undervoltage protection is triggered. The controller is
latched off with both the upper and lower MOSFETs turned off.
When the voltage on VOS is higher than 1 V, the overvoltage protection is activated. In the event of overvoltage,
the upper MOSFET is turned off and the lower MOSFET is forced on until VOS voltage reaches 400 mV. Then
the lower MOSFET is also turned off, and the controller is latched off.
After both the undervoltage and overvoltage events, normal operation can only be restored by cycling the VDD
voltage.
PGOOD
The TPS51113 and TPS51163 have a power good output that indicates HIGH when the output voltage is within
the target range. The PGOOD function is activated as soon as the soft-start ends. When the output voltage goes
± 10% outside of the target value, PGOOD goes low. When the output voltage returns to be within ± 6% of the
target value, PGOOD signal goes HIGH again. The PGOOD output is an open drain and needs external pull up
resistor.
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APPLICATION INFORMATION
EXTERNAL PARTS SELECTION
CHOOSING THE INDUCTOR
The value of the output filtering inductor determines the magnitude of the current ripple, which also affects the
output voltage ripple for a certain output capacitance value. Increasing the inductance value reduces the ripple
current, and thus, results in reduced conduction loss and output ripple voltage. On the other hand, low
inductance value is needed due to the demand of low profile and fast transient response. Therefore, it is
important to obtain a compromise between the low ripple current and low inductance value.
In practical application, to ensure high power conversion efficiency at light load condition, the peak-to-peak
current ripple is usually designed to be between 1/4 to 1/2 of the rated load current. Since the magnitude of the
current ripple is determined by inductance value, switching frequency, input voltage and output voltage, the
required inductance value for a certain required ripple ∆I is shown in Equation 2,
V
- V ´ V
OUT OUT
(
)
IN RIPPLE SW
IN
L =
V
´I
´ f
(2)
where
•
•
•
•
VIN is the input voltage
VOUT is the output voltage
IRIPPLE is the required current ripple
fSW is the switching frequency
CALCULATING OUTPUT CAPACITANCE
When the inductance value is determined, the output capacitance value can also be derived according to the
output ripple voltage and output load transient response requirement. The output ripple voltage is a function of
both the output capacitance and capacitor ESR. Considering the worst case and assume the capacitance value
is COUT, the peak-to-peak ripple voltage can be derived in Equation 3.
æ
ö
÷
÷
ø
1
DV = IRIPPLE ´ çESR +
ç
è
8 ´ C
´ f
OUT SW
(3)
Thus, output capacitors with suitable ESR and capacitance value should be chosen to meet the ripple voltage
(ΔV) requirement.
Minimum capacitance value is also calculated according to the demand of the load transient response. When the
load current changes, the energy that the inductor needs to release or absorb is derived in Equation 4.
2
2
æ
ö
1
2
E
=
´L ´
I
- I
ç(OH) (OL ) ÷
L
è
ø
(4)
At the same time, the energy that is delivered to or provided by the output capacitor can also be derived as
shown in Equation 5.
1
2
2
2
EC
=
´ COUT ´ Vf - Vi
( ) ( )
(
)
(5)
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As a result, to meet the load transient response demand, the minimum output capacitance should be
2
2
L ´ I
- I
(OH ) (OL )
(
)
C
=
OUT
2
2
V
- V
( ) ( )
i
f
(6)
where
•
•
•
•
IOH is the output current under heavy load conditions
IOL is the output current under light load conditions
Vƒ is the final peak capacitor voltage
Vi is the initial capacitor voltage
By considering the demand of both output ripple voltage and load transient response, the minimum output
capacitance can be determined.
INPUT CAPACITOR SELECTION
For a certain rated load current, input and output voltage, the input ripple voltage caused by the input
capacitance value and ESR are shown in Equation 7 and Equation 8, respectively.
I
´ V
OUT
OUT
IN min
V
=
RIPPLE C
C
´ V ´ f
IN SW
( )
IN
(
)
(7)
(8)
1
2
æ
ö
V
= ESR
´ I
+
´I
RIPPLE
ç
÷
C
OUT
RIPPLE ESR _C
(
)
IN
è
ø
IN
Based on the required input voltage ripple, suitable capacitors can be chosen by using the above equations.
CHOOSING MOSFETS
Choosing suitable MOSFETs is extremely important to achieve high power conversion efficiency for the
converter. For a buck converter, suitable MOSFETs should not only meet the requirement of voltage and current
rating, but also ensure low power loss.
High-Side MOSFET
Power loss of the high-side MOSFETs primarily consists of the conduction loss (PCOND1) and the switching loss
(PSW1).
The conduction loss of the high-side MOSFET is the I2R loss in the MOSFET’s on-resistance, RDS(on)1. The RMS
value of the current passing through the top MOSFET depends on the average load current, ripple current and
duty cycle the converter is operating.
2
æ
ç
ö
÷
÷
I
(
)
2
RIPPLE
I
=
D´
I
+
ç(OUT )
RMS1
12
ç
è
÷
ø
(9)
The conduction loss can, thus, be calculated as follows.
2
P
= I
(
´R
DS ON 1
)
COND1
RMS1
(
)
(10)
12
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Also, the switching loss can be approximately described as
æ
ç
è
ö
÷
ø
I
´ t
I
´ t
æ
ç
è
ö
÷
ø
æ
ö
D1
S1
D2
S2
P
= V
´
+
´ f
SW
ç
è
÷
ø
SW1
IN
6
2
(11)
(12)
where
•
ID1 and ID2 are the current magnitudes at the time instance when the MOSFETs switch
1
2
1
2
I
= I
-
´ I
and
I
= I
+
´ I
RIPPLE
D1
OUT
RIPPLE
D2
OUT
where
•
•
ts1 is the MOSFET switching-on time
ts2 is the MOSFET switching-off time
Therefore, the total power loss of the high-side MOSFET is estimated by the sum of the above power losses,
= P + P
P
HFET _Loss
COND1
SW1
(13)
Synchronous Rectifier MOSFET Power Loss
Power loss associated with the synchronous rectifier (SR) MOSFET mainly consists of RDS(on) conduction loss,
body diode conduction loss and reverse recovery loss.
Similarly to the high-side MOSFET, the conduction loss of the SR MOSFET is also the I2R loss of the MOSFET’s
on-resistance, RDS(on)2. Since the switching on-time of the SR MOSFET is (1-D)
ה
, where T is the duration of one switching cycle, the RMS current of the SR MOSFET can be calculated as follows.
2
æ
ç
ö
÷
÷
I
(
)
2
RIPPLE
I
=
1- D ´
I
+
(
)
ç(OUT )
RMS2
12
ç
è
÷
ø
(14)
The symchronous rectifier (SR) MOSFET conduction loss is
2
P
= I
(
´R
DS ON 2
)
COND2
RMS2
(
)
(15)
(16)
The body diode conduction loss is
= I ´ V ´ t ´ f
SW
P
COND3
OUT
F
D
where
•
•
VF is the forward voltage of the MOSFET body diode
tD is the total conduction time of the body diode in one switching cycle
The body diode recovery time – the time it takes for the body diode to restore its blocking capability from forward
conduction state, determines the reverse recovery losses.
1
P
=
´ Q
´ V ´ f
RR IN SW
RR
2
(17)
where
•
QRR is the reverse recovery charge of the body diode
Therefore, the total power loss of the SR MOSFET is estimated by the sum of the above power losses.
= P + P + P
P
SR _Loss
COND2
COND3
RR
(18)
13
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Feedback Loop Compensation
Since TPS51113/TPS51163 utilizes voltage-mode control for buck converters, Type III network is recommended
for loop compensation. Suitable poles and zeros can be set by choosing proper parameters for the loop
compensation network.
To calculate loop compensation parameters, the poles and zeros for the buck converter should be obtained. The
double pole, determined by the L, and COUT of the buck converter, is located at the frequency as shown in the
following equation.
1
f
=
0
2p´ L ´ C
OUT
(19)
Also, the ESR zero of the buck converter can be achieved.
1
f
=
Z
2p ´ ESR ´ C
OUT
(20)
Figure 8 shows the configuration of Type III compensation. The transfer function of the compensator is described
in Equation 21. Also, poles and zeros for the Type III network are shown in Equation 22 through Equation 26.
C2
C3
R3
R2
C1
R1
FB
COMP
V
OUT
+
R
BIAS
VREF
UDG-08109
Figure 8. Type III Compensation Network
14
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sR C + 1 ´ s R + R
C
+ 1
3
(
)
(
R2C1C2
)
(
)
2
1
1
3
G s =
( )
æ
ö
æ
ç
è
ö
÷
ø
sR1 C + C ´ s
+ 1 ´ sR C + 1
(
2 ) ç
÷ (
)
1
3
3
ç
è
÷
C1 + C2
ø
(21)
(22)
1
f
=
Z1
2p´R ´ C
2
1
1
f
=
P1
æ
ç
ç
ö
C ´ C
(
)
)
1
2
2p´R ´
÷
÷
2
C + C
(
1
2
è
ø
(23)
(24)
1
f
=
P2
2p´R ´ C
3
3
1
fZ2
=
2p´ R + R ´ C
(
)
1
3
3
(25)
(26)
1
fC
=
2p´R ´ C + C
2
(
)
1
1
fP1 is usually used to cancel the ESR zero in Equation 20. fP2 can be placed at higher frequency in order to
attenuate the high frequency noise and the switching ripple. fZ1 and fZ2 are chosen to be lower than the switching
frequency, and fZ1 is lower than resonant frequency f0. Suitable values can be selected to achieve the
compromise between high phase margin and fast response. A phase margin of over 60° is usually
recommended. Then, the compensator gain is chosen to achieve the desired bandwidth.
The value of RBIAS is calculated to set the output voltage VOUT
.
0.8´R
1
R
=
BIAS
V
- 0.8
OUT
(27)
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Layout Considerations
For the grounding and circuit layout, certain points need to be considered.
•
It is important that the signal ground and power ground properly use separate copper planes to prevent the
noise of power ground from influencing the signal ground. The impedance of each ground is minimized by
using its copper plane. Sensitive nodes, such as the FB resistor divider and VOS resistor divider, should be
connected to the signal ground plane, which is also connected with the GND pin of the device. The high
power noisy circuits, such as synchronous rectifier, MOSFET driver decoupling capacitors, the input
capacitors and the output capacitors should be connected to the power ground plane. Finally, the two
separate ground planes should be strongly connected together near the device by using a single path/trace.
•
A minimum of 0.1-µF ceramic capacitor must be placed as close to VDD pin and GND pin as possible with a
trace at least 20 mils wide, from the bypass capacitor to the GND. Usually a capacitance value of 1 µF is
recommended for the bypass capacitor.
•
•
The PowerPAD should be electrically connected to GND.
A parallel pair of trace (with at least 15 mils wide) connects the regulated voltage back to the chip. The trace
should be away from the switching components. The bias resistor of the resistor divider should be connected
to the FB pin and GND pin as close as possible.
•
The component placement of the power stage should ensure minimized loop areas to suppress the radiated
emissions. The input current loop is consisted of the input capacitors, the main switching MOSFET, the
inductor, the output capacitors and the ground path back to the input capacitors. The SR MOSFET, the
inductor, the output capacitors and the ground path back to the source of the SR MOSFET consists of the
output current loop. The connection/trace should be as short as possible to reduce the parasitic inductance.
•
•
Connections from the drivers to the respective gate of the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance. A trace of 25 mils or wider is recommended.
Connect the overcurrent setting resistor from LDRV_OC to GND close to the device.
TPS51113 Design Example
The following example illustrates the design process and component selection for a single output synchronous
buck converter using the TPS51113. The schematic of a design example is shown in Figure 9. The specification
of the converter is listed in Table 1.
Table 1. Specification of the Single Output Synchronous Buck Converter
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
V
VIN
Input voltage
10.8
12
1.6
13.2
VOUT
VRIPPLE
IOUT
Output voltage
Output ripple
V
IOUT = 10 A
2% of VOUT
10
V
Output current
Switching frequency
V
fSW
300
kHz
16
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V
OUT
V
IN
D1
MBR0530Tx
R6
TPS51113
PGOOD 10
C3
47 kW
R4
8.2 nF
R1
1
2
3
4
5
BOOT
SW
10 kW
2 kW
Q1
C5
R3
BSC079N03S
0.1 mF
130 W
VOS
FB
9
8
7
6
L1
1.5 mH
+
C2
HDRV
3.9 nF
Q2
C1
22 nF
BSC079N03S
R2
R
BIAS
LDRV_OC COMP_EN
2.7 kW
V
2 kW
OUT
C6
470 mF
C7
R5
47 mF
R
OC
10 kW
GND
VDD
Enable
7 kW
–
C4
11
1 mF
UDG-08107
Figure 9. Design Example, 12 V to 1.6 V/10 A DC-DC Converter
Choosing the Inductor
Typically the peak-to-peak inductor current ΔI is selected to be approximately between 20% and 40% of the rated
output current. In this design, IRIPPLE is targeted at around 30% of the load current. Using Equation 2.
V
- V ´ V
O O
(
)
IN RIPPLE SW
IN
L =
= 1.534mH
V
´I
´ f
Therefore, an inductor value of 1.5 µH is selected in practical, and the inductor ripple current is 3.08 A.
Calculating Output Capacitance
Minimum capacitance value can be calculated according to the demand of the load transient response.
Considering 0-A to 10-A step load and 10% overshoot and undershoot, the output capacitance value can be
estimated by using Equation 6,
2
2
L ´ I
- I
(OH ) (OL )
(
)
C
=
= 279mF
OUT
2
2
V
- V
( ) ( )
i
f
(29)
A 470-µF POS-CAP with 18-mΩ ESR and a 47-µF ceramic capacitor are paralleled for the output capacitor.
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Input Capacitor Selection
Considering 100 mV VRIPPLE(Cin) and 50 mV VRIPPLE(ESR_Cin), the input capacitance value and ESR value can be
calculated according to Equation 7 and Equation 8, respectively.
IOUT ´ VOUT
CIN min
=
= 44mF
(
)
VRIPPLE C ´ VIN ´ fSW
(
)
IN
(30)
(31)
VRIPPLE ESR _C
(
)
IN
ESRC
=
= 4.3mW
IN
æ
ö
I
(
+ IRIPPLE
)
OUT
ç
ç
è
÷
÷
ø
2
Therefore, two 22-µF ceramic capacitors with 2-mΩ ESR can meet this requirement.
Choosing MOSFETS
High-Side MOSFET Power Loss
BSC079N03S is used for the high-side MOSFET. The on-resistance, RDS(on)1 is 7.9 mΩ. MOSFET switching-on
time (ts1) and switching-off time (ts2) are approximately 9 ns and 24 ns, respectively. By using Equation 9 through
Equation 13, the total power loss of the high-side MOSFET is estimated.
I
D1 ´ tS1 ID2 ´ tS2
æ
ç
è
ö
÷
ø
PHFET _Loss = PCOND1 + PSW1 = I
2 ´RDS on 1 + V
´
+
´ f
= 649mW
(
)
RMS1
IN
SW
( )
6
2
(32)
Synchronous Rectifier MOSFET Power Loss
BSC032N03S is used for the synchronous rectifier MOSFET. The on-resistance, RDS(on)1 is 3.2 mΩ. The body
diode has a 0.84-V diode forward voltage and 15-nC reverse recovery charge. The output driver deadtime is 30
ns. By using Equation 14 through Equation 18, the total power loss of the synchronous MOSFET is estimated,
1
PSR _Loss = PCOND2 + PCOND3 + PRR = I
é RMS2
2 ´RDS on 2 +IO ´ VF ´ tD ´ fSW
+
´QRR ´ VIN ´ fSW = 382mW
ù
û
ë
( )
2
(33)
Feedback Loop Compensation
Since TPS51113 and TPS51163 utilize voltage-mode control for buck converters, Type III network is
recommended for loop compensation. The converter utilizes a 1.5-µH inductor and 470-µF capacitor with 18-mΩ
ESR. The double pole, determined by the L, and COUT of the buck converter, is derived by Equation 19
1
f
=
= 6.0kHz
0
2p ´ L ´ C
OUT
(34)
(35)
Also, the ESR zero of the buck converter can be achieved by using Equation 20.
1
f
=
= 18.8kHz
Z
2p ´ ESR ´ C
OUT
18
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Figure 10 shows the detailed parameters used for the Type III compensation. Also, poles and zeros for the Type
III network are derived based on Equation 22 through Equation 26.
C2
3.9 nF
C3
R3
R2
C1
8.2 nF
130 W
2.7 kW 22 nF
R1
FB
V
OUT
COMP
+
R
BIAS
2 kW
VREF
UDG-08110
Figure 10. Parameters for Type III Compensation Network
sR C + 1 ´ s R + R
C
+ 1
3
(
)
(
R2C1C2
)
(
)
2
1
1
3
G s =
( )
æ
ö
æ
ç
è
ö
÷
ø
sR1 C + C ´ s
+ 1 ´ sR C + 1
(
2 ) ç
÷ (
)
1
3
3
ç
÷
C1 + C2
è
ø
(36)
(37)
1
f
=
= 2.7kHz
Z1
2p´R ´ C
2
1
1
fZ2
=
= 9.2kHz
2p´ R + R ´ C
(
)
1
3
3
(38)
1
f
=
= 17.8kHz
P1
æ
ç
ç
ö
C ´ C
(
)
)
1
2
2p´R ´
÷
÷
2
C + C
(
1
2
è
ø
(39)
(40)
1
f
=
= 149.4kHz
P2
2p´R ´ C
3
3
1
fC
=
= 3.1kHz
2p´R ´ C + C
2
(
)
1
1
(41)
fP1 is used to cancel the ESR zero. fP2 is placed at higher frequency to attenuate the high-frequency noise and
the switching ripple. fZ1 is lower than resonant frequency f0.
The value of RBIAS is calculated to set the output voltage VOUT by using Equation 27.
0.8´R
1
R
=
= 2kW
BIAS
V - 0.8
O
(42)
Based on Equation 42 and the power stage parameters, the bode-plot by simulation is shown in Figure 10
(VIN=12 V and IOUT=0 A). The achieved cross-over frequency is approximately 35.7 kHz, and the phase margin is
approximately 60°.
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60
40
Frequency = 35.7 kHz
Gain = 0.0226 dB
20
0
-20
0
-45
Frequency = 35.7 kHz
Phase = –120°
-90
-135
-180
100
10 k
100 k
1 k
f – Frequency – Hz
UGD-08111
Figure 11. Bode Plot of the Design Example Circuit by Simulation (VIN=12 V and IOUT=0 A)
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PACKAGE MATERIALS INFORMATION
www.ti.com
22-May-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TPS51113DRCR
TPS51113DRCT
TPS51163DRCR
TPS51163DRCT
SON
SON
SON
SON
DRC
DRC
DRC
DRC
10
10
10
10
3000
250
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-May-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS51113DRCR
TPS51113DRCT
TPS51163DRCR
TPS51163DRCT
SON
SON
SON
SON
DRC
DRC
DRC
DRC
10
10
10
10
3000
250
346.0
190.5
346.0
190.5
346.0
212.7
346.0
212.7
29.0
31.8
29.0
31.8
3000
250
Pack Materials-Page 2
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灌电流和拉电流 DDR 终端稳压器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS51200AQDRCRQ1
灌电流和拉电流 DDR 终端稳压器 | DRC | 10 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS51200AQDRCTQ1
灌电流和拉电流 DDR 终端稳压器 | DRC | 10 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS51200DRCR
SINK/SOURCE DDR TERMINATION REGULATORWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
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