TPS5120 [TI]
DUAL OUTPUT, TWO PHASE SYNCHRONOUS BUCK DC/DC CONTROLLER; 双输出，两相同步降压型DC / DC控制器
| 型号： | TPS5120 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL OUTPUT, TWO PHASE SYNCHRONOUS BUCK DC/DC CONTROLLER |
| 文件： | 总20页 (文件大小：292K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
ꢇꢈ ꢉꢊ ꢋ ꢈꢀꢁ ꢈꢀꢌ ꢀꢍ ꢋ ꢎꢁꢏꢉ ꢂꢐ ꢂꢑ ꢒꢓꢏꢔꢋ ꢒꢋ ꢈꢂ ꢕꢈꢓ ꢖ ꢇꢓꢗ ꢇꢓ ꢓꢋ ꢒꢀꢔ ꢋ ꢊꢊ ꢐꢔ
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
DBT PACKAGE
(TOP VIEW)
D
Independent Dual-Outputs Operate 180°
Out of Phase
D
D
D
D
D
Wide Input Voltage Range: 4.5-V – 28-V
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INV1
FB1
SOFTSTART1
PWM/SKIP
CT
LH1
OUT1_u
LL1
OUT1_d
OUTGND1
TRIP1
2
Adjustable Output Voltage Down to 0.9 V
3
Pin-Selectable PWM/SKIP Mode for High
Efficiency Under Light Loads
4
5
Synchronous Buck Operation Allows up to
95% Efficiency
6
5V_STBY
GND
7
V
CC
8
Separate Standby Control and Overcurrent
Protection for Each Channel
REF
STBY1
STBY2
TRIP2
9
VREF5
REG5V_IN
OUTGND2
OUT2_d
LL2
10
11
12
13
14
15
D
Programmable Short-Circuit Protection
FLT
D
Low Supply (1 mA) and Shutdown (1 nA)
Current
POWERGOOD
SOFTSTART2
FB2
D
D
D
Power Good Output
OUT2_u
LH2
INV2
High-Speed Error Amplifiers
Sequencing Easily Achieved by Selecting
Softstart Capacitor Values.
D
D
5-V Linear Regulator Power Internal IC
Circuitry
30-Pin TSSOP Packaging
description
The TPS5120 is a dual channel, high-efficiency synchronous buck controller where the outputs run 180 degrees
out of phase, which lowers the input current ripple, thereby reducing the input capacitance cost. The PWM/SKIP
pin allows the operating mode to switch from PWM mode to skip mode under light load conditions. The skip
mode enables a lower operating frequency and shortens the pulse width to the low-side MOSFET, increasing
the efficiency under light load conditions. These two modes, along with synchronous-rectifier drivers, dead time,
and very low quiescent current, allow power to be conserved and the battery life to be extended under all load
conditions. The 1.5 A (typical) high-side and low-side MOSFET drivers on-chip are designed to drive less
expensive N-channel MOSFETs. The resistorless current protection and fixed high-side driver voltage simplify
the power supply design and reduce the external parts count. Each channel is independent, offering a separate
controller, overcurrent protection, and standby control. Sequencing is flexible and can be tailored by choosing
different softstart capacitor values. Other features, such as undervoltage lockout, power good, overvoltage,
undervoltage, and programmable short-circuit protection promote system reliability.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
ꢁ
ꢁ
ꢔ
ꢋ
ꢨ
ꢇ
ꢣ
ꢈ
ꢓ
ꢡ
ꢀ
ꢢ
ꢘ
ꢜ
ꢋ
ꢚ
ꢒ
ꢛ
ꢇ
ꢉ
ꢀ
ꢉ
ꢙ
ꢚ
ꢤ
ꢛ
ꢜ
ꢢ
ꢝ
ꢞ
ꢟ
ꢟ
ꢠ
ꢠ
ꢙ
ꢙ
ꢜ
ꢜ
ꢚ
ꢚ
ꢙ
ꢡ
ꢡ
ꢥ
ꢢ
ꢣ
ꢝ
ꢝ
ꢤ
ꢤ
ꢚ
ꢠ
ꢟ
ꢞ
ꢡ
ꢡ
ꢜ
ꢛ
ꢥ
ꢀꢤ
ꢣ
ꢦ
ꢡ
ꢧ
ꢙ
ꢢ
ꢟ
ꢡ
ꢠ
ꢙ
ꢠ
ꢜ
ꢝ
ꢚ
ꢣ
ꢨ
ꢟ
ꢚ
ꢠ
ꢠ
ꢤ
ꢡ
ꢩ
ꢝ
ꢜ
ꢢ
ꢠ
ꢜ
ꢝ
ꢞ
ꢠ
ꢜ
ꢡ
ꢥ
ꢙ
ꢛ
ꢙ
ꢢ
ꢤ
ꢝ
ꢠ
ꢪ
ꢠ
ꢤ
ꢝ
ꢜ
ꢛ
ꢫ
ꢟ
ꢘ
ꢚ
ꢞ
ꢤ
ꢡ
ꢠ
ꢟ
ꢚ
ꢨ
ꢟ
ꢝ
ꢨ
ꢬ
ꢟ
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ
ꢝ
ꢝ
ꢟ
ꢚ
ꢠ
ꢭ
ꢩ
ꢁ
ꢝ
ꢜ
ꢨ
ꢣ
ꢢ
ꢠ
ꢙ
ꢜ
ꢚ
ꢥ
ꢝ
ꢜ
ꢢ
ꢤ
ꢡ
ꢡ
ꢙ
ꢚ
ꢮ
ꢨ
ꢜ
ꢤ
ꢡ
ꢚ
ꢜ
ꢠ
ꢚ
ꢤ
ꢢ
ꢤ
ꢡ
ꢡ
ꢟ
ꢝ
ꢙ
ꢧ
ꢭ
ꢙ
ꢚ
ꢢ
ꢧ
ꢣ
ꢨ
ꢤ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢈ
ꢀ
ꢁ
ꢈ
ꢀ
ꢌ
ꢀꢍ
ꢋ
ꢎ
ꢁꢏ
ꢉ
ꢂ
ꢐ
ꢂ
ꢑꢒ
ꢓ
ꢏ
ꢔ
ꢋ
ꢒ
ꢋ
ꢈ
ꢂ
ꢕ
ꢈ
ꢓ
ꢖ
ꢇ
ꢓ
ꢗ
ꢇ
ꢓ
ꢓ
ꢋ
ꢒ
ꢀ
ꢔ
ꢋ
ꢊ
ꢊꢐ
ꢔ
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
typical design
V
I
R1
R2
Q1
C1
U1
TPS5120DBT
R7
R3
C3
L1
GND
D1
C11
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
LH1
INV1
V
O
1
Q2
OUT1_u
FB1
C4
3
4
5
6
LL1
OUT1_d
OUTGND1
TRIP1
SOFTSTART1
PWM/SKIP
CT
C13
C5
C6
C15
5V_STBY
GND
R8
R9
7
8
Vcc
TRIP2
REF
9
VREF5
STBY1
STBY2
FLT
C16
10
11
12
REG5V_IN
OUTGND2
OUT2_d
C7
C8
POWERGOOD
SOFTSTART2
FB2
13
14
LL2
OUT2_u
LH2
C12
C14
D2
Q3
Q4
15
16
V
O
2
INV2
R4
R10
L2
C10
C15
R5
R6
Figure 1. EVM Typical Design
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
ꢇꢈ ꢉꢊ ꢋ ꢈꢀꢁ ꢈꢀꢌ ꢀꢍ ꢋꢎꢁ ꢏꢉꢂꢐ ꢂꢑ ꢒꢓꢏꢔꢋ ꢒꢋ ꢈꢂ ꢕꢈꢓ ꢖ ꢇꢓꢗ ꢇꢓ ꢓꢋ ꢒꢀꢔ ꢋ ꢊꢊ ꢐꢔ
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
functional block diagram
SOFTSTART1
SOFTSTART1
LH1
PWM Comp.
_
Skip Comp.
DLY
OUT1_u
_
+
LL1
+
DLY
OUT1_d
FB1
_
OUTGND1
INV1
+
+
_
Err Amp.
LSD Trip
+
0.85 V
–(
– VTRIP1)
V
CC
CT
+
HSD Trip
_
OSC
TRIP1
OVP1
_
Current Comp.
FLT
Current
Protection
Trigger
UVLO
SIGNAL
STBY1
+
0.85 V+12%
V
– VTRIP1
CC
OVP2
_
STBY2
V
CC
+
0.85 V+12%
V
– VTRIP2
UVP1
CC
+
_
Timer
_
+
TRIP2
0.85 V –19.4%
Phase
UVP2
+
Inverter
HSD Trip
_
_
0.85 V –19.4%
+
LSD Trip
–( – VTRIP2)
FB2
V
CC
OUTGND2
OUT2_d
Err Amp.
_
INV2
+
+
DLY
DLY
PWM Comp.
LL2
PWM/SKIP
_
_
+
OUT2_u
+
Skip Comp.
LH2
UVLO
SIGNAL
0.85 V
SOFTSTART2
_
SOFTSTART2
SFT1
SFT2
+
5.0 V
UVLO
Comp.
VCC
VREF5
_
+
V
REG5V_IN
5 VREG
ref
_
+
STBY1
INV1
4.5 V
STBY2
REF
PGcomp1
0.85 V
0.85 V–7%
POWERGOOD
5V_STBY
INV2
+
_
INV1
+
_
GND
_
+
INV2
PGcomp4
0.85 V +7%
PGcomp3
0.85 V +7%
PGcomp2
0.85 V –7%
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ
ꢇ ꢈꢉꢊ ꢋꢈ ꢀ ꢁꢈ ꢀꢌ ꢀꢍ ꢋ ꢎꢁꢏ ꢉꢂ ꢐ ꢂ ꢑꢒ ꢓꢏꢔ ꢋ ꢒꢋ ꢈꢂ ꢕꢈꢓ ꢖ ꢇꢓꢗ ꢇꢓ ꢓꢋ ꢒꢀ ꢔꢋ ꢊ ꢊꢐ ꢔ
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
AVAILABLE OPTIONS
PACKAGE
T
A
EVM
TSSOP
(DBT)
TPS5120DBT
TPS5120EVM-151
–40°C to 85°C
TPS5120DBTR
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
5
CT
I/O External capacitor from CT to GND for adjusting the triangle oscillator
FB1
FB2
GND
INV1
INV2
LH1
LH2
LL1
2
O
O
Feedback output of CH1 error amplifier
Feedback output of CH2 error amplifier
Control GND
14
7
1
I
I
Inverting input of the CH1 error amplifier, skip comparator, and OVP1/UVP1 comparator
Inverting input of the CH2 error amplifier, skip comparator, and OVP2/UVP2 comparator
15
30
16
28
I/O Bootstrap capacitor connection for CH1 high-side gate drive
I/O Bootstrap capacitor connection for CH2 high-side gate drive
I/O Bootstrap this pin low for CH1 high-side gate driving return and output current protection. Connect this pin to
the junction of the high-side and low-side FETs for a floating drive configuration.
LL2
18
I/O Bootstrap this pin low for CH2 high-side gate driving return and output current protection. Connect this pin to
the junction of the high-side and low-side FETs for a floating drive configuration.
OUT1_d
27
19
29
17
26
20
12
O
O
O
O
Gate drive output for CH1 low-side gate drive
Gate drive output for CH2 low-side gate drive
Gate drive output for CH1 high-side switching FETs
Gate drive output for CH2 high-side switching FETs
Ground for CH1 FET drivers
OUT2_d
OUT1_u
OUT2_u
OUTGND1
OUTGND2
POWERGOOD
Ground for CH2 FET drivers
O
I
Power good open-drain output. When low, POWERGOOD reports an output fail condition. PG comparators
monitor both SMPS’s over voltage and UVLO of VREF5. The threshold is ±7%. When the SMPS starts up, the
POWERGOOD pin’s output goes high. POWERGOOD also monitors VREF5’s UVLO output.
PWM/SKIP
4
PWM/SKIP mode select pin. The PWM/SKIP pin is used to change the output’s operating mode. If this terminal
is lower than 0.5 V, it works in PWM mode. When a minimum voltage of 2 V is applied, the device operates in
skip mode. In light load condition (< 0.2 A), the skip mode gives a short pulse to the low-side FETs instead of a
full pulse. With this control, switching frequency is lowered and switching loss is reduced. Also, the output
capacitor energy discharging through the output inductor and low-side FETs is stopped. Therefore, TPS5120
achieves a higher efficiency in light load conditions.
REF
8
O
I
0.85-V reference voltage output. The 0.85-V reference voltage is used for setting the output voltage and the
voltage protection. This reference voltage is dropped down from a 5-V regulator.
REG5V_IN
FLT
21
11
3
External 5-V input
I/O Fault latch timer pin. An external capacitor is connected between FLT and GND to set the FLT enable time up.
SOFTSTART1
I/O External capacitor from SOFTSTART1 to GND for CH1 softstart control. Separate soft-start terminals make it
possible to set the start-up time of each output independently.
SOFTSTART2
13
I/O External capacitor from SOFTSTART2 to GND for CH2 softstart control. Separate soft-start terminals make it
possible to set the start-up time of each output independently.
STBY1
STBY2
TRIP1
9
I
I
I
Standby control for CH1. SMPS1 can be switched into standby mode separately by grounding the STBY1 pin.
Standby control for CH2. SMPS2 can be switched into standby mode separately by grounding the STBY2 pin.
External resistor connection for CH1 output current control
10
25
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
ꢇꢈ ꢉꢊ ꢋ ꢈꢀꢁ ꢈꢀꢌ ꢀꢍ ꢋꢎꢁ ꢏꢉꢂꢐ ꢂꢑ ꢒꢓꢏꢔꢋ ꢒꢋ ꢈꢂ ꢕꢈꢓ ꢖ ꢇꢓꢗ ꢇꢓ ꢓꢋ ꢒꢀꢔ ꢋ ꢊꢊ ꢐꢔ
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
NO.
23
24
22
6
TRIP2
I
External resistor connection for CH2 output current control
Supply voltage input
V
CC
VREF5
O
I
5-V internal regulator output
5V_STBY
5-V linear regulator control
detailed description
switching-mode power supply (SMPS) 1, 2
TPS5120 includes dual SMPS controllers that operate 180° out of phase and at the same frequency. Both
channels have standby and softstart.
5-V regulator
An internal linear voltage regulator is used for the high-side driver bootstrap voltage and source of VREF
(0.85 V). When the 5-V regulator is disconnected from the MOSFET drivers, it is only used for the source of
VREF. Since the input voltage range is from 4.5 V to 28 V, this feature offers a fixed voltage for the bootstrap
voltage so that the drive design is much easier. It is also used for powering the low-side driver. The tolerance
is 4%. The 5-V regulator is disabled when STBY1, STBY2, and 5V_STBY are all set low.
5-V switch
If the internal 5-V switch senses the 5-V input from the REG5V_IN pin, the internal 5-V linear regulator is
disconnected from the MOSFET drivers. The external 5 V is then used for both the low-side driver and the
high-side bootstrap, thus, increasing the efficiency.
error amplifier
Each channel has its own error amplifier to regulate the output voltage of the synchronous buck converter. It
is used in the PWM mode for the high output current condition (> 0.2 A). The unity gain bandwidth is 2.5 MHz.
This decreases the amplifier delay during fast load transients and contributes to a fast transient response.
skip comparator
In skip mode, each channel has its own hysteretic comparator to regulate the output voltage of the synchronous
buck converter. The hysteresis is set internally and is typically set at 9 mV. The delay from the comparator input
to the driver output is typically 1.2 µs.
low-side driver
The low-side driver is designed to drive low r
N-channel MOSFETs. The maximum drive voltage is 5 V from
ds(on)
VREF5. The current rating of the driver is typically 1.5 A at source and sink.
high-side driver
The high-side driver is designed to drive low r
N-channel MOSFETs. The current rating of the driver is 1.2 A
ds(on)
at source and sink. When configured as a floating driver, the bias voltage to the driver is developed from VREF5,
limiting the maximum drive voltage between OUTx_u and LLx to 5 V. The maximum voltage that can be applied
between LHx and OUTGND is 33 V.
deadtime
Deadtime prevents shoot through current from flowing through the main power FETs during switching transitions
by actively controlling the turnon time of the MOSFETs drivers.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ
ꢇ ꢈꢉꢊ ꢋꢈ ꢀ ꢁꢈ ꢀꢌ ꢀꢍ ꢋ ꢎꢁꢏ ꢉꢂ ꢐ ꢂ ꢑꢒ ꢓꢏꢔ ꢋ ꢒꢋ ꢈꢂ ꢕꢈꢓ ꢖ ꢇꢓꢗ ꢇꢓ ꢓꢋ ꢒꢀ ꢔꢋ ꢊ ꢊꢐ ꢔ
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
detailed description (continued)
current protection
Overcurrent protection is achieved by comparing the drain-to-source voltage of the high-side and low-side
MOSFET devices to a set-point voltage. This voltage is set using an external resistor between V and the
CC
TRIP1 or TRIP2 terminals. If the drain-to-source voltage up exceeds the set-point voltage during high-side
conduction, the current limit circuit terminates the high-side driver pulse. If the set-point voltage is exceeded
during low-side conduction, the low-side pulse is extended through the next cycle. Together this action has the
effect of decreasing the output voltage until the undervoltage protection circuit is activated and the fault latch
is set and both the high and low-side MOSFET drivers are shut off.
overvoltage protection
For overvoltage protection (OVP), the TPS5120 monitors INV pin voltage. When the INV voltage is higher than
0.95 V (+12%), the OVP comparator output goes high and the FLT timer starts to charge an external capacitor
connected to FLT. After a set time, the FLT circuit latches the MOSFET drivers off.
undervoltage protection
For undervoltage protection (UVP), the TPS5120 monitors INV pin voltage. When the INV voltage is lower than
0.68 V (–19.4%), the OVP comparator output goes high, and the FLT timer starts to charge an external capacitor
connected to FLT. Also, when the current comparator triggers the OCP, the UVP comparator detects the under
voltage output and starts the FLT capacitor charge. After a set time, the FLT circuit latches off all of the MOSFET
drivers.
FLT
When an OVP or UVP comparator output goes high, the FLT circuit starts to charge the FLT capacitor. If the
FLT pin voltage goes beyond a constant level, the TPS5120 latches the MOSFET drivers. At this time, the state
of MOSFET is different depending on the OVP alert and the UVP alert. Also, the enable time used to latch the
MOSFET driver is decided by the capacity of the FLT capacitor. The charging constant current value is also
different depending on whether it is an OVP alert or a UVP alert. The difference is shown in the following
equation:
FLT source current (OVP) = FLT source current (UVP) × 5
shutdown
The TPS5120 can be shut down by grounding STBY1, STBY2, and 5V_STBY. The shutdown current is as low
as 1 µA.
UVLO
When the input voltage goes up to about 4 V, the TPS5120 is operational. When the input voltage is lower than
the turnon value, the device is turned off. The typical hysteresis voltage is 40 mV.
phase Inverter
Phase inverter controls the phase of SMPS1 and SMPS 2. SMPS1 operates in phase with the OSC. SMPS2
operates 180° out of phase from SMPS1. This allows smaller input capacitors to be used.
oscillator
TPS5120 has a triangle oscillator generator internal to the IC. The oscillation frequency is set by the size of the
capacitor connected to the CT pin. The voltage amplitude is 0.43 V ~ 1.17 V.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
ꢇꢈ ꢉꢊ ꢋ ꢈꢀꢁ ꢈꢀꢌ ꢀꢍ ꢋꢎꢁ ꢏꢉꢂꢐ ꢂꢑ ꢒꢓꢏꢔꢋ ꢒꢋ ꢈꢂ ꢕꢈꢓ ꢖ ꢇꢓꢗ ꢇꢓ ꢓꢋ ꢒꢀꢔ ꢋ ꢊꢊ ꢐꢔ
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
Table 1. Logic Chart
5V_STBY
STBY1
STBY2
SMPS1
Disable
Disable
Enable
Enable
Disable
Disable
Enable
Enable
SMPS2
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
5 V REGULATOR
Disable
POWERGOOD
L
L
L
L
L
H
L
Disable
†
Enable
Active
Active
†
L
H
H
L
Enable
L
H
L
Enable
Active
L
H
H
H
H
Enable
†
L
H
L
Enable
Active
†
H
H
Enable
Active
H
Enable
Active
†
PG is set high during a softstart.
POWERGOOD timing sequence
T
SS
H
POWERGOOD
STBY1
L
H
L
H
STBY2
L
0.91 V
0.85 V
0.78 V
INV1
0 V
0.91 V
INV2
0.85 V
0.78 V
0 V
During a softstart, this channel’s powergood comparator output is fixed low (POWERGOOD output is high).
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ
ꢇ ꢈꢉꢊ ꢋꢈ ꢀ ꢁꢈ ꢀꢌ ꢀꢍ ꢋ ꢎꢁꢏ ꢉꢂ ꢐ ꢂ ꢑꢒ ꢓꢏꢔ ꢋ ꢒꢋ ꢈꢂ ꢕꢈꢓ ꢖ ꢇꢓꢗ ꢇꢓ ꢓꢋ ꢒꢀ ꢔꢋ ꢊ ꢊꢐ ꢔ
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 30 V
CC
Input voltage: INV1, INV2, CT, PWM/SKIP, REG5V_IN, SOFTSTART1, SOFTSTART2, . . . . . –0.3 V to 7 V
FLT, POWERGOOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
STBY1, STBY2, 5V_STBY, TRIP1, TRIP2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 30 V
Output voltage: LL1, LL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.0 V to 30 V
OUT1_u, OUT2_u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.0 V to 35 V
LH1, LH2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 35 V
OUT1_d, OUT2_d, 5V_OUT, FB1, FB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
REF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 3 V
OUT1_u, LH1 to LL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
OUT2_u, LH2 to LL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Power dissipation (T ≤ 25°C), P
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874 mW
A
D
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the network ground terminal unless otherwise noted.
2. This rating is specified at duty = 10% on output rise and fall each pulse. Each pulse width (rise and fall) for the peak current should
not exceed 2 µs.
3. See Dissipation Rating Table for free-air temperature range above 25°C.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
POWER DISSIPATION
= 85°C
A
PACKAGE
POWER RATING
ABOVE T = 25°C
T
A
A
DBT
874 mW
6.993 mW/°C
454 mW
recommended operating conditions
MIN NOM
MAX
28
UNIT
Supply voltage, V
CC
4.5
V
INV1, INV2, CT, PWM/SKIP, SOFTSTART1, SOFTSTART2, FLT
REG5V_IN, POWERGOOD
6
–0.1
5.5
28
STBY1, STBY2, 5V_STBY
Input voltage, V
V
I
OUT1_u, OUT2_u, LH1, LH2
33
TRIP1, TRIP2
–0.1
–40
28
Oscillator frequency, f
osc
300
500
85
kHz
Operating free-air temperature range, T
°C
A
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
ꢇꢈ ꢉꢊ ꢋ ꢈꢀꢁ ꢈꢀꢌ ꢀꢍ ꢋꢎꢁ ꢏꢉꢂꢐ ꢂꢑ ꢒꢓꢏꢔꢋ ꢒꢋ ꢈꢂ ꢕꢈꢓ ꢖ ꢇꢓꢗ ꢇꢓ ꢓꢋ ꢒꢀꢔ ꢋ ꢊꢊ ꢐꢔ
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
electrical characteristics over recommended free-air temperature range, V
otherwise noted)
= 7 V (unless
CC
reference voltage
PARAMETER
Reference voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
ref
0.85
V
T
= 25°C,
I = 50 µA
I = 50 µA
I = 50 µA
I = 50 µA
–1%
–1.5%
–2%
1%
1.5%
2%
3
A
T
A
= –20°C to 85°C,
= –40°C to 85°C,
V
Reference voltage tolerance
ref(tol)
T
A
R
R
Line regulation
Load regulation
V
= 4.5 V to 28 V,
0.05
0.15
mV
mV
(egin)
(egl)
CC
I = 0.1 µA to 1 mA
5
oscillator
PARAMETER
TEST CONDITIONS
MIN
1
TYP
300
1.1
MAX
1.2
UNIT
f
Frequency
PWM mode, CT = 44 pF,
DC
T
A
= 25 °C
kHz
osc
V
High level output voltage
Low level output voltage
V
V
OH
OL
f
= 300 kHz
1.17
0.5
osc
DC
0.4
0.6
V
f
= 300 kHz
0.43
osc
error amplifier
PARAMETER
Input offset voltage
TEST CONDITIONS
= 25°C
A
MIN
TYP
MAX
UNIT
mV
V
IO
T
2
10
Open-loop voltage gain
Unity-gain bandwidth
Output sink current
50
dB
2.5
0.7
0.9
MHz
mA
I
I
V
V
= 1 V
= 1 V
0.3
0.2
(snk)
O
Output source current
mA
(src)
O
skip comparator
PARAMETER
PARAMETER
PARAMETER
TEST CONDITIONS
SKIP mode
MIN
MIN
TYP
MAX
MAX
MAX
UNIT
V
Hysteresis window
9
mV
hys
duty control
TEST CONDITIONS
300 kHz, V = 0 V
TYP
UNIT
DUTY
Maximum duty cycle
83%
I
control
TEST CONDITIONS
STBY1, STBY2
MIN
2.2
TYP
UNIT
V
V
High-level input voltage
V
IH
PWM/SKIP, 5V_STBY
STBY1, STBY2
2.2
0.3
0.3
Low-level input voltage
V
IL
PWM/SKIP, 5V_STBY
5-V internal switch
PARAMETER
TEST CONDITIONS
MIN
4.2
4.1
30
TYP
MAX
4.8
UNIT
V
V
V
(TO_H)
(TO_L)
hys
Threshold
Hysteresis
V
4.7
200
mV
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ
ꢇ ꢈꢉꢊ ꢋꢈ ꢀ ꢁꢈ ꢀꢌ ꢀꢍ ꢋ ꢎꢁꢏ ꢉꢂ ꢐ ꢂ ꢑꢒ ꢓꢏꢔ ꢋ ꢒꢋ ꢈꢂ ꢕꢈꢓ ꢖ ꢇꢓꢗ ꢇꢓ ꢓꢋ ꢒꢀ ꢔꢋ ꢊ ꢊꢐ ꢔ
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
electrical characteristics over recommended free-air temperature range, V
otherwise noted) (continued)
= 7 V (unless
CC
5-V regulator
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
T
= 0 mA to 50 mA,
= 25°C
V
CC
= 5.5 V to 28 V,
O
A
V
O
Output voltage
4.8
5.2
V
R
R
Line regulation
V
= 5.5 V to 28 V,
I =10 mA
V = 5.5 V
20
40
mV
mV
mA
(egin)
(egl)
CC
Load regulation
I = 1 mA to 10 mA,
5VREG = 0 V,
CC
= 25°C
A
I
Short circuit output current
T
65
3.6
3.5
OS
V
V
V
4.2
4.1
(TO_H)
(TO_L)
hys
UVLO threshold voltage
Hysteresis
5V_OUT voltage
5V_OUT voltage
V
30
150
mV
output drivers
PARAMETER
TEST CONDITIONS
MIN
TYP
1.2
MAX
UNIT
A
OUT_u sink current
V
O
V
O
V
O
V
O
= 3 V
= 2 V
= 3 V
= 2 V
= 25°C
OUT_u source current
OUT_d sink current
OUT_d source current
TRIP pin current
–1.5
1.5
A
A
–1.5
13
A
I
T
A
11.5
14.5
µA
(TRIP)
soft start
PARAMETER
TEST CONDITIONS
MIN
TYP
2.3
3.7
2.5
MAX
UNIT
I
Soft start current
1.6
2.9
µA
(SOFT)
V
(TO_H)
(TO_L)
Threshold voltage (SKIP mode)
V
V
output voltage monitor
PARAMETER
OVP comparator threshold
TEST CONDITIONS
MIN
0.91
0.64
0.75
0.88
TYP
0.95
0.68
0.78
0.91
13
MAX
0.99
0.72
0.81
0.94
UNIT
V
V
V
V
UVP comparator threshold
PG comparator 1, 2 threshold
PG comparator 3, 4 threshold
Turnon
PG propagation delay from INV to POWERGOOD
Timer latch current source
µs
Turnoff
1.2
UVP protection
OVP protection
1.5
8
2.3
3.1
15
µA
11.5
supply current
PARAMETER
Supply current
Shutdown current
TEST CONDITIONS
T = 25°C, CT = 0 V, INV = 0 V
A
MIN
TYP
1.1
MAX
1.5
UNIT
mA
I
I
CC
STBY 1, STBY2, 5V_STBY = 0 V
0.001
10
µA
CC(S)
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
ꢇꢈ ꢉꢊ ꢋ ꢈꢀꢁ ꢈꢀꢌ ꢀꢍ ꢋꢎꢁ ꢏꢉꢂꢐ ꢂꢑ ꢒꢓꢏꢔꢋ ꢒꢋ ꢈꢂ ꢕꢈꢓ ꢖ ꢇꢓꢗ ꢇꢓ ꢓꢋ ꢒꢀꢔ ꢋ ꢊꢊ ꢐꢔ
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
TYPICAL CHARACTERISTICS
QUIESCENT CURRENT
vs
QUIESCENT CURRENT (SHUTDOWN)
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
1.30
1.25
1200
1000
800
V
CC
= 28 V
V
= 28 V
CC
1.20
1.15
V
= 7 V
CC
600
400
200
0
V
= 4.5 V
CC
0
1.10
1.05
V
CC
= 4.5 V
100
V
CC
= 7 V
–50
0
50
150
–50
50
100
150
T
– Junction Temperature – °C
J
T
– Junction Temperature – °C
J
Figure 2
Figure 3
DRIVE OUTPUT CURRENT (OUT_u)
DRIVE OUTPUT CURRENT (OUT_u)
vs
vs
DRIVE OUTPUT VOLTAGE
DRIVE OUTPUT VOLTAGE
–1.80
–1.70
–1.60
–1.50
–1.40
–1.30
–1.20
–1.10
–1.00
–0.90
–0.80
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
0.60
T = –40 °C
J
T = –40 °C
J
T = 25 °C
J
T = 85 °C
J
T = 85 °C
J
T = 125 °C
J
T = –20 °C
T = 25 °C
T = 125 °C
J
J
J
T = –20 °C
J
1.5
2.5
3.5
4.5
0.5
1.5
2.5
3.5
2
3
4
1
2
3
V
O
– Drive Output Voltage (OUT_u) – V
V
O
– Drive Output Voltage (OUT_u) – V
Figure 4
Figure 5
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ
ꢇ ꢈꢉꢊ ꢋꢈ ꢀ ꢁꢈ ꢀꢌ ꢀꢍ ꢋ ꢎꢁꢏ ꢉꢂ ꢐ ꢂ ꢑꢒ ꢓꢏꢔ ꢋ ꢒꢋ ꢈꢂ ꢕꢈꢓ ꢖ ꢇꢓꢗ ꢇꢓ ꢓꢋ ꢒꢀ ꢔꢋ ꢊ ꢊꢐ ꢔ
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
TYPICAL CHARACTERISTICS
DRIVE OUTPUT CURRENT (OUT_d)
DRIVE OUTPUT CURRENT (OUT_d)
vs
vs
DRIVE OUTPUT VOLTAGE
DRIVE OUTPUT VOLTAGE
1.80
1.70
1.60
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
–2.00
–1.80
–1.60
–1.40
–1.20
T = –40 °C
T = –20 °C
J
J
T = –40 °C
T = –20 °C
J
J
T = 25 °C
J
T = 85 °C
J
–1.00
–0.80
T = 25 °C
T = 125 °C
J
J
T = 85 °C
J
T = 125 °C
J
1.5
2.5
3.5
4.5
2
3
4
0.5
1.5
2.5
3.5
1
2
3
V
– Drive Output Voltage (OUT_d) – V
O
V
– Drive Output Voltage (OUT_d) – V
O
Figure 6
Figure 7
OSCILLATOR OUTPUT VOLTAGE
vs
OSCILLATOR OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
1.20
1.18
1.16
1.14
1.12
1.10
1.08
1.06
1.04
1.02
1.00
500
495
490
485
480
V
CC
V
CC
V
CC
= 4.5 V,
= 7 V,
= 28 V
V
V
V
= 4.5 V,
= 7 V,
= 28 V
CC
CC
CC
–50
–50
0
50
100
150
0
50
100
150
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 8
Figure 9
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
ꢇꢈ ꢉꢊ ꢋ ꢈꢀꢁ ꢈꢀꢌ ꢀꢍ ꢋꢎꢁ ꢏꢉꢂꢐ ꢂꢑ ꢒꢓꢏꢔꢋ ꢒꢋ ꢈꢂ ꢕꢈꢓ ꢖ ꢇꢓꢗ ꢇꢓ ꢓꢋ ꢒꢀꢔ ꢋ ꢊꢊ ꢐꢔ
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
TYPICAL CHARACTERISTICS
ERROR AMPLIFIER OUTPUT VOLTAGE
vs
ERROR AMPLIFIER INPUT OFFSET VOLTAGE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
2.55
2.50
2.45
2.40
2.35
2.30
2.25
2.20
3.00
2.75
2.50
2.25
2.00
1.75
1.50
V
CC
V
CC
V
CC
= 4.5 V,
= 7 V,
V
CC
= 28 V
= 28 V
V
V
= 4.5 V,
= 7 V
CC
CC
–50
0
50
100
150
–50
0
50
100
150
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 10
Figure 11
ERROR AMPLIFIER OUTPUT VOLTAGE
SKIP COMPARATOR HYSTERESIS VOLTAGE
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
9.0
8.8
8.6
8.4
8.2
8.0
7.8
7.6
7.4
7.2
7.0
V
CC
= 28 V
V
CC
= 7 V
V
CC
V
CC
V
CC
= 4.5 V,
= 7 V,
= 28 V
V
CC
= 4.5 V
–50
–50
0
50
100
150
0
50
100
150
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 12
Figure 13
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ
ꢇ ꢈꢉꢊ ꢋꢈ ꢀ ꢁꢈ ꢀꢌ ꢀꢍ ꢋ ꢎꢁꢏ ꢉꢂ ꢐ ꢂ ꢑꢒ ꢓꢏꢔ ꢋ ꢒꢋ ꢈꢂ ꢕꢈꢓ ꢖ ꢇꢓꢗ ꢇꢓ ꢓꢋ ꢒꢀ ꢔꢋ ꢊ ꢊꢐ ꢔ
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
TYPICAL CHARACTERISTICS
VREF5 SHORT-CIRCUIT OUTPUT CURRENT
vs
VREF5 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
5.20
JUNCTION TEMPERATURE
–120
–100
–80
–60
–40
–20
0
T
J
= 125 °C
5.10
5.00
4.90
4.80
4.70
4.60
4.50
V
CC
= 28 V
T
= 85 °C
J
V
CC
= 7 V
T
J
= 25 °C
V
= 4.5 V
0
CC
T
= –20 °C
–30
T = –40 °C
J
J
–50
50
100
150
–10
–20
–40
–50
–60
0
I
– Output Current – mA
T
J
– Junction Temperature – °C
O
Figure 15
Figure 14
UVLO HYSTERESIS VOLTAGE
vs
UVLO THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
4.00
3.90
3.80
3.70
3.60
3.50
140
120
100
80
V
(TO_H)
60
V
(TO_L)
40
20
0
–50
0
50
100
150
–50
0
50
100
150
T
J
– Junction Temperature – °C
T
– Junction Temperature – °C
J
Figure 16
Figure 17
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
ꢇꢈ ꢉꢊ ꢋ ꢈꢀꢁ ꢈꢀꢌ ꢀꢍ ꢋꢎꢁ ꢏꢉꢂꢐ ꢂꢑ ꢒꢓꢏꢔꢋ ꢒꢋ ꢈꢂ ꢕꢈꢓ ꢖ ꢇꢓꢗ ꢇꢓ ꢓꢋ ꢒꢀꢔ ꢋ ꢊꢊ ꢐꢔ
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
TYPICAL CHARACTERISTICS
REG5V_IN HYSTERESIS VOLTAGE
vs
REG5V_IN THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
140
120
100
80
4.7
4.7
4.6
4.6
4.5
4.5
4.4
V
(TO_L)
60
V
40
(TO_H)
20
0
–50
0
50
100
150
–50
0
50
100
150
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 18
Figure 19
SOFTSTART CURRENT
vs
OVP THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
–2.30
–2.28
–2.26
–2.24
–2.22
–2.20
–2.18
–2.16
–2.14
–2.12
–2.10
956
V
CC
V
CC
= 7 V,
= 28 V
954
952
950
948
946
944
V
CC
V
CC
= 7 V,
= 28 V
V
CC
= 4.5 V
V
= 4.5 V
CC
–50
–50
0
50
100
150
0
50
100
150
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 20
Figure 21
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ
ꢇ ꢈꢉꢊ ꢋꢈ ꢀ ꢁꢈ ꢀꢌ ꢀꢍ ꢋ ꢎꢁꢏ ꢉꢂ ꢐ ꢂ ꢑꢒ ꢓꢏꢔ ꢋ ꢒꢋ ꢈꢂ ꢕꢈꢓ ꢖ ꢇꢓꢗ ꢇꢓ ꢓꢋ ꢒꢀ ꢔꢋ ꢊ ꢊꢐ ꢔ
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
TYPICAL CHARACTERISTICS
SCP (OVP) SOURCE CURRENT
vs
POWERGOOD THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
950
925
900
875
850
825
800
775
750
–12.0
–11.9
–11.8
–11.7
–11.6
–11.5
–11.4
–11.3
–11.2
–11.1
–11.0
V(TO_H)
V
CC
V
CC
V
CC
= 4.5 V,
= 7 V,
= 28 V
V
CC
V
CC
= 7 V,
= 28 V
V
CC
V
CC
V
CC
= 4.5 V,
= 7 V,
= 28 V
V
CC
= 4.5 V
V(TO_L)
0
–50
–50
0
50
100
150
50
100
150
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 23
Figure 22
TRIP SINK CURRENT
vs
SCP (OVP) SOURCE CURRENT
vs
TRIP INPUT VOLTAGE
JUNCTION TEMPERATURE
14.0
13.8
13.6
13.4
13.2
13.0
12.8
12.6
12.4
12.2
12.0
–2.40
–2.38
–2.35
–2.33
–2.30
–2.28
–2.25
–2.23
–2.20
T
J
= 125 °C
T
J
= 85 °C
V
CC
V
CC
= 7 V,
= 28 V
T
= 25 °C
J
T
= –20 °C
J
V
= 4.5 V
CC
T
J
= –40 °C
0
4
8
12
16
20
24
28
32
–50
0
50
100
150
– TRIP Input Voltage – V
V
I
T
J
– Junction Temperature – °C
Figure 24
Figure 25
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
ꢇꢈ ꢉꢊ ꢋ ꢈꢀꢁ ꢈꢀꢌ ꢀꢍ ꢋꢎꢁ ꢏꢉꢂꢐ ꢂꢑ ꢒꢓꢏꢔꢋ ꢒꢋ ꢈꢂ ꢕꢈꢓ ꢖ ꢇꢓꢗ ꢇꢓ ꢓꢋ ꢒꢀꢔ ꢋ ꢊꢊ ꢐꢔ
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
TYPICAL CHARACTERISTICS
OUTPUT MAXIMUM DUTY CYCLE
vs
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
CAPACITANCE
85.0
84.5
84.0
83.5
83.0
82.5
82.0
81.5
81.0
1000
V
= 7 V,
V
CC
V
CC
= 7 V,
= 28 V
CC
T
J
= 25 °C
100
V
= 4.5 V
CC
f
= 300 kHz
100
osc
10
0
–50
50
100
150
200
250
0
50
150
T
J
– Junction Temperature – °C
CT – Capacitance – pF
Figure 26
Figure 27
SOFTSTART TIME
vs
SCP DELAY TIME
vs
SOFTSTART CAPACITANCE
CAPACITANCE
100 k
10 k
1 k
100 k
10 k
1 k
100
100
10
10
1
100
1 k
10 k
100 k
10
100
1 k
10 k
100 k
Softstart Capacitance – pF
SCP – Capacitance – pF
Figure 28
Figure 29
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ
ꢇ ꢈꢉꢊ ꢋꢈ ꢀ ꢁꢈ ꢀꢌ ꢀꢍ ꢋ ꢎꢁꢏ ꢉꢂ ꢐ ꢂ ꢑꢒ ꢓꢏꢔ ꢋ ꢒꢋ ꢈꢂ ꢕꢈꢓ ꢖ ꢇꢓꢗ ꢇꢓ ꢓꢋ ꢒꢀ ꢔꢋ ꢊ ꢊꢐ ꢔ
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
TYPICAL CHARACTERISTICS
DRIVER DEAD TIME (OUT_u FALL)
DRIVER DEAD RISE TIME (OUT_u RISE)
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
175.0
172.5
170.0
167.5
100
95
90
85
80
75
70
V
= 4.5 V
CC
V
CC
V
CC
= 7 V,
= 28 V
V
CC
= 4.5 V
165.0
162.5
V
V
= 7 V,
= 28 V
CC
CC
–50
0
50
100
150
–50
0
50
100
T
– Junction Temperature – °C
J
T
J
– Junction Temperature – °C
Figure 30
Figure 31
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
ꢇꢈ ꢉꢊ ꢋ ꢈꢀꢁ ꢈꢀꢌ ꢀꢍ ꢋꢎꢁ ꢏꢉꢂꢐ ꢂꢑ ꢒꢓꢏꢔꢋ ꢒꢋ ꢈꢂ ꢕꢈꢓ ꢖ ꢇꢓꢗ ꢇꢓ ꢓꢋ ꢒꢀꢔ ꢋ ꢊꢊ ꢐꢔ
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
MECHANICAL DATA
DBT (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
30 PINS SHOWN
0,27
0,17
M
0,50
30
0,08
16
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
15
0°–ā8°
0,75
0,50
A
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
28
30
38
44
50
DIM
7,90
7,70
7,90
7,70
9,80
9,60
11,10
12,60
12,40
A MAX
10,90
A MIN
4073252/D 09/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-153
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, maskworkright, orotherTIintellectualpropertyrightrelatingtoanycombination, machine, orprocess
in which TI products or services are used. Information published by TI regarding third–party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明