TPS51200AQDRCRQ1 [TI]
灌电流和拉电流 DDR 终端稳压器 | DRC | 10 | -40 to 125;
| 型号： | TPS51200AQDRCRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 灌电流和拉电流 DDR 终端稳压器 | DRC | 10 | -40 to 125 双倍数据速率 光电二极管 接口集成电路 稳压器 |
| 文件： | 总38页 (文件大小：1694K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS51200A-Q1
ZHCSIL4A –JUNE 2018–REVISED DECEMBER 2018
TPS51200A-Q1 灌电流和拉电流 DDR 终端稳压器
1 特性
2 应用
1
•
符合面向汽车应用的 AEC-Q100 AEC-Q100 标
准：
•
用于 DDR、DDR2、DDR3、低功耗 DDR3 和
DDR4 的存储器终端稳压器
•
•
笔记本电脑、台式机、服务器
–
器件温度等级 1：
–40°C ≤ TA ≤ 125°C
电信和数据通信、GSM 基站、液晶 (LCD) 电视和
等离子 (PDP) 电视、复印机和打印机、机顶盒
–
–
器件 HBM ESD 分类等级 2
器件 CDM ESD 分类等级 C4B
3 说明
•
•
•
•
•
扩展的可靠性测试
TPS51200A-Q1 器件是一款灌电流和拉电流双倍数据
速率 (DDR) 终端稳压器，专门针对低输入电压、低成
本、低噪声的空间受限型系统而设计。
输入电压：支持 2.5V 和 3.3V 电源轨
VLDOIN 电压范围：1.1V 至 3.5V
具有压降补偿功能的灌电流和拉电流终端稳压器
所需最小输出电容为 20μF（通常为 3 × 10μF
MLCC），用于存储器终端 应用 (DDR)
此器件可保持快速的瞬态响应，最低仅需 20μF 输出电
容。此器件支持遥感功能，并且可满足 DDR、
DDR2、DDR3、低功耗 DDR3 和 DDR4 VTT 总线终
端的所有电源要求。
•
•
•
用于监视输出稳压的 PGOOD
EN 输入
REFIN 输入允许直接或通过电阻分压器灵活进行输
入跟踪
此外，该器件还提供一个开漏 PGOOD 信号来监测输
出稳压，并提供一个 EN 信号在 S3（挂起至 RAM）
期间针对 DDR 应用进行 VTT 放电。
•
•
•
•
•
远程检测 (VOSNS)
±10mA 缓冲基准 (REFOUT)
内置软启动、UVLO 和 OCL
热关断
此器件采用高效散热型 VSON-10 封装，具有绿色环保
和无铅的特性。该器件的额定温度范围为 –40°C 至
125°C。
符合 DDR、DDR2 JEDEC 规范；支持 DDR3、低
功耗 DDR3 和 DDR4 VTT 应用
器件信息(1)
•
带外露散热焊盘的 VSON-10 封装
器件型号
封装
VSON (10)
封装尺寸（标称值）
TPS51200A-Q1
3.00mm × 3.00mm
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
简化的 DDR 应用
1
REFIN
VIN 10
3.3 VIN
VDDQ
TPS51200A-Q1
VLDOIN
VTT
2
3
4
5
VLDOIN
VO
PGOOD
9
8
7
6
PGOOD
GND
EN
PGND
VOSNS
SLP_S3
VTTREF
REFOUT
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSD58
TPS51200A-Q1
ZHCSIL4A –JUNE 2018–REVISED DECEMBER 2018
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 6
6.7 Typical Characteristics.............................................. 6
Detailed Description ............................................ 10
7.1 Overview ................................................................ 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 12
8
9
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application ................................................. 14
Power Supply Recommendations...................... 25
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 26
10.3 Thermal Considerations........................................ 27
11 器件和文档支持 ..................................................... 29
11.1 器件支持................................................................ 29
11.2 文档支持................................................................ 29
11.3 接收文档更新通知 ................................................. 29
11.4 社区资源................................................................ 29
11.5 商标....................................................................... 29
11.6 静电放电警告......................................................... 29
11.7 术语表 ................................................................... 29
12 机械、封装和可订购信息....................................... 29
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (June 2018) to Revision A
Page
•
•
•
已添加 “扩展的可靠性测试”添加到特性列表中的项目 ............................................................................................................. 1
已更改 将文档状态从“预告信息”更改为“生产数据”.................................................................................................................. 1
Updated device number error in schematic illustrations ...................................................................................................... 14
2
Copyright © 2018, Texas Instruments Incorporated
TPS51200A-Q1
www.ti.com.cn
ZHCSIL4A –JUNE 2018–REVISED DECEMBER 2018
5 Pin Configuration and Functions
DRC Package
10-Pin VSON With Exposed Thermal Pad
Top View
REFIN
VLDOIN
VO
1
2
3
4
10 VIN
9
8
7
PGOOD
GND
EN
Thermal
Pad
PGND
VOSNS
5
6
REFOUT
Pin Functions
PIN
NAME
I/O
DESCRIPTION
NO.
For DDR VTT application, connect EN to SLP_S3. For any other applications, use EN as the ON/OFF
function. Keep EN voltage equal or lower than VIN voltage at all times.
EN
7
I
GND
8
4
9
1
—
—
O
I
Ground. Signal ground. Connect to negative pin of the output capacitor.
Power ground output for the LDO
PGND(1)
PGOOD
REFIN
PGOOD output. Indicates regulation.
Reference input
Reference output. Connect to GND through 0.1-μF ceramic capacitor. If there is REFOUT capacitor at DDR
side, keep the total capacitance on REFOUT pin below 1 μF. The REFOUT pin can not be open.
REFOUT
VIN
6
O
I
2.5-V or 3.3-V power supply A ceramic decoupling capacitor with a value between 1-μF and 4.7-μF is
required.
10
VLDOIN
VO
2
3
5
I
O
I
Supply voltage for the LDO.
Power output for the LDO. Minimum 20-μF capacitance is required. No maximum capacitance limit.
Voltage sense output for the LDO. Connect to positive pin of the output capacitor or the load.
VOSNS
(1) Thermal pad connection. See 图 35 in the Thermal Considerations section for additional information.
Copyright © 2018, Texas Instruments Incorporated
3
TPS51200A-Q1
ZHCSIL4A –JUNE 2018–REVISED DECEMBER 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range, unless otherwise noted.(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
UNIT
VIN, VLDOIN, VOSNS, REFIN
3.6
6.5
0.3
3.6
6.5
150
150
Input voltage(2)
EN
V
PGND to GND
VO, REFOUT
PGOOD
Output voltage(2)
V
Operating junction temperature, TJ
Storage temperature, Tstg
°C
°C
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground pin unless otherwise noted.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human body model (HBM), per AEC Q100-002(1)
Electrostatic
discharge
V(ESD)
Corner pins (1, 5, 6, and 10)
Other pins
V
Charged device model (CDM), per
AEC Q100-011
±500
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
MAX
UNIT
V
Supply voltage
VIN
2.375
–0.1
0.5
3.500
3.5
EN, VLDOIN, VOSNS
REFIN
1.8
Voltage range
VO, PGOOD
REFOUT
–0.1
–0.1
–0.1
–40
3.5
1.8
PGND
0.1
Operating free-air temperature, TA
125
°C
6.4 Thermal Information
TPS51200A-Q1
DRC (VSON)
10 PINS
55.7
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCtop
RθJB
62.2
28.0
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
3.1
ψJB
27.9
RθJCbot
12.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2018, Texas Instruments Incorporated
TPS51200A-Q1
www.ti.com.cn
ZHCSIL4A –JUNE 2018–REVISED DECEMBER 2018
6.5 Electrical Characteristics
Over recommended free-air temperature range, VVIN = 3.3 V, VVLDOIN = 1.8 V, VREFIN = 0.9 V, VVOSNS = 0.9 V, VEN = VVIN, COUT
= 3 × 10 μF and circuit shown in the 简化的 DDR 应用 section (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IIN
Supply current
TA = 25 °C, VEN = 3.3 V, No Load
0.7
65
1
80
mA
TA = 25 °C, VEN = 0 V, VREFIN = 0, No Load
TA = 25 °C, VEN = 0 V, VREFIN > 0.4 V, No Load
TA = 25 °C, VEN = 3.3 V, No Load
IIN(SDN)
Shutdown current
μA
200
1
400
50
ILDOIN
Supply current of VLDOIN
μA
μA
ILDOIN(SDN)
Shutdown current of VLDOIN
TA = 25 °C, VEN = 0 V, No Load
0.1
50
INPUT CURRENT
IREFIN
Input current, REFIN
VEN = 3.3 V
1
μA
VO OUTPUT
1.25
0.9
V
mV
V
VREFOUT = 1.25 V (DDR1), IO = 0 A
VREFOUT = 0.9 V (DDR2), IO = 0 A
VREFOUT = 0.75 V (DDR3), IO = 0 A
VREFOUT = 0.675 V (DDR3L), IO = 0 A
VREFOUT = 0.6 V (DDR4), IO = 0 A
–15
–15
–15
-15
15
15
15
15
mV
V
0.75
0.675
0.6
VVOSNS
Output DC voltage, VO
mV
V
mV
V
-15
–25
3
15
25
mV
mV
A
VVOTOL
IVOSRCL
IVOSNCL
IDSCHRG
Output voltage tolerance to REFOUT
VO source current Limit
VO sink current Limit
–2A < IVO < 2A
With reference to REFOUT, VOSNS = 90% × VREFOUT
With reference to REFOUT, VOSNS = 110% × VREFOUT
VREFIN = 0 V, VVO = 0.3 V, VEN = 0 V, TA = 25°C
4.5
5.5
25
3.5
A
Discharge current, VO
18
Ω
POWERGOOD COMPARATOR
PGOOD window lower threshold with respect to REFOUT
PGOOD window upper threshold with respect to REFOUT
PGOOD hysteresis
–23.5%
17.5%
–20%
20%
5%
–17.5%
23.5%
VTH(PG)
VO PGOOD threshold
VPGOODLOW
IPGOODLK
Output low voltage
Leakage current(1)
ISINK = 4 mA
0.4
1
V
VOSNS = VREFIN (PGOOD high impedance), PGOOD = VIN
+ 0.2 V
μA
REFIN AND REFOUT
VREFIN
REFIN voltage range
0.5
1.8
V
mV
mV
V
VREFINUVLO
VREFINUVHYS
VREFOUT
REFIN undervoltage lockout
REFIN undervoltage lockout hysteresis
REFOUT voltage
REFIN rising
360
390
20
420
REFIN
–10 mA ≤ IREFOUT ≤ 10 mA, 0.6 V ≤ VREFIN ≤ 1.25 V
–1 mA ≤ IREFOUT ≤ 1 mA, 0.6 V ≤ VREFIN ≤ 1.25 V
VREFOUT = 0.5 V
–15
-12
10
15
12
VREFOUTTOL
REFOUT voltage tolerance to VREFIN
mV
IREFOUTSRCL
IREFOUTSNCL
REFOUT source current limit
REFOUT sink current limit
40
40
mA
mA
VREFOUT = 1.5 V
10
UVLO / EN LOGIC THRESHOLD
Wake up, TA = 25°C
Hysteresis
Enable
2.2
1.7
2.3
50
2.375
V
mV
V
VVINUVLO
UVLO threshold
VENIH
High-level input voltage
Low-level input voltage
Hysteresis voltage
VENIL
Enable
0.3
1
V
VENYST
IENLEAK
Enable
0.5
V
Logic input leakage current
EN, TA = 25°C
–1
μA
THERMAL SHUTDOWN
Shutdown temperature
Hysteresis
150
25
TSDN
Thermal shutdown threshold(1)
°C
(1) Ensured by design. Not production tested.
Copyright © 2018, Texas Instruments Incorporated
5
TPS51200A-Q1
ZHCSIL4A –JUNE 2018–REVISED DECEMBER 2018
www.ti.com.cn
6.6 Switching Characteristics
Over recommended free-air temperature range, VVIN = 3.3 V,VVLDOIN = 1.8 V, VREFIN = 0.9 V, VVOSNS = 0.9 V, VEN = VVIN, COUT
= 3 × 10 μF and circuit shown in the 简化的 DDR 应用 section (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWERGOOD COMPARATOR
Startup rising edge, VOSNS within
15% of REFOUT
TPGSTUPDLY
TPBADDLY
PGOOD startup delay
PGOOD bad delay
2
ms
VOSNS is outside of the ±20%
PGOOD window
10
μs
6.7 Typical Characteristics
For 图 1 through 图 18, 3 × 10-μF MLCCs (0805) are used on the output.
1.3
1.28
1.26
1.24
1.22
940
TA
TA
œ 40°C
0°C
25°C
85°C
œ 40°C
930
920
0°C
25°C
85°C
910
900
890
880
870
1.2
1.18
œ3
œ2
œ1
Output Current (A)
VVIN = 3.3 V
0
1
2
3
œ3
œ2
œ1
0
1
2
3
Output Current (A)
DDR
VVIN = 3.3 V
DDR2
图 1. Load Regulation
图 2. Load Regulation
790
780
770
720
710
700
690
680
670
660
650
640
TA
TA
œ40°C
0°C
25°C
85°C
œ 40°C
0°C
25°C
85°C
760
750
740
730
720
710
700
œ3
œ2
œ1
Output Current (A)
VVIN = 3.3 V
0
1
2
3
3
œ3
œ2
œ1
0
1
2
Output Current (mA)
DDR3
VVIN = 3.3 V
DDR3L
图 3. Load Regulation
图 4. Load Regulation
6
版权 © 2018, Texas Instruments Incorporated
TPS51200A-Q1
www.ti.com.cn
ZHCSIL4A –JUNE 2018–REVISED DECEMBER 2018
Typical Characteristics (接下页)
For 图 1 through 图 18, 3 × 10-μF MLCCs (0805) are used on the output.
670
650
630
1.3
1.25
1.2
TA
œ 40°C
0°C
25°C
85°C
1.15
1.1
610
590
1.05
TA
1
0.95
0.9
œ 40°C
0°C
25°C
85°C
570
550
œ3
œ2
œ1
Output Current (A)
VVIN = 3.3 V
0
1
2
3
œ3
œ2
œ1
Output Current (A)
VVIN =2.5 V
0
1
2
3
LP DDR3 or DDR4
DDR
图 5. Load Regulation
图 6. Load Regulation
1
0.95
0.9
800
825
750
725
700
675
650
TA
œ 40°C
0°C
25°C
85°C
0.85
0.8
TA
œ 40°C
0°C
25°C
85°C
0.75
0.8
œ3
œ2
œ1
Output Current (A)
VVIN = 2.5 V
0
1
2
3
œ3
œ2
œ1
Output Current (A)
VVIN = 2.5 V
0
1
2
3
DDR2
DDR3
图 8. Load Regulation
图 7. Load Regulation
720
710
700
690
680
670
660
650
640
630
620
750
700
650
600
550
500
TA
TA
œ40°C
0°C
25°C
85°C
œ 40°C
0°C
25°C
85°C
œ3
œ2
œ1
Output Current (A)
VVIN = 2.5 V
0
1
2
3
3
œ3
œ2
œ1
Output Current (mA)
VVIN = 2.5 V
0
1
2
LP DDR3 or DDR4
DDR3L
图 10. Load Regulation
图 9. Load Regulation
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TPS51200A-Q1
ZHCSIL4A –JUNE 2018–REVISED DECEMBER 2018
www.ti.com.cn
Typical Characteristics (接下页)
For 图 1 through 图 18, 3 × 10-μF MLCCs (0805) are used on the output.
1.255
1.254
1.253
1.252
1.251
1.25
905
904
903
902
901
900
899
898
897
TA
TA
œ 40°C
25°C
85°C
œ 40°C
25°C
85°C
1.249
1.248
1.247
œ15
œ10
œ5
0
5
10
15
œ15
œ10
œ5
0
5
10
15
REFOUT Output Current (mA)
REFOUT Output Current (mA)
DDR
DDR2
图 11. REFOUT Load Regulation
图 12. REFOUT Load Regulation
755
754
753
752
751
750
749
748
747
680
TA
TA
œ40°C
25°C
85°C
œ 40°C
25°C
85°C
679
678
677
676
675
674
673
672
15
DDR3L
œ15
œ10
œ5
0
5
10
15
-15
-10
-5
0
5
10
REFOUT Output Current (mA)
REFOUT Output Current (mA)
DDR3
图 13. REFOUT Load Regulation
图 14. REFOUT Load Regulation
1.4
605
604
603
602
601
600
599
598
597
TA
œ 40°C
25°C
85°C
1.2
1
0.8
0.6
0.4
0.2
0
VOUT (V)
0.6
0.75
0.9
1.25
0
0.5
1
1.5
2
2.5
3
3.5
œ15
œ10
œ5
REFOUT Output Current (mA)
LP DDR3 or DDR4
0
5
10
15
Output Current (A)
图 16. DROPOUT Voltage vs Output Current
图 15. REFOUT Load Regulation
8
版权 © 2018, Texas Instruments Incorporated
TPS51200A-Q1
www.ti.com.cn
ZHCSIL4A –JUNE 2018–REVISED DECEMBER 2018
Typical Characteristics (接下页)
For 图 1 through 图 18, 3 × 10-μF MLCCs (0805) are used on the output.
200
60
200
150
60
50
50
150
40
30
40
30
100
50
100
50
20
20
0
0
10
0
10
0
œ50
œ50
œ100
œ150
œ200
œ100
œ150
œ200
œ10
œ10
Gain
Phase
Gain
Phase
œ20
œ30
œ20
œ30
1 k
10 k
100 k
1 M
10 M
1 k
10 k
100 k
1 M
10 M
Frequency (Hz)
Frequency (Hz)
DDR2
DDR3
图 17. Gain and Phase vs Frequency
图 18. Gain and Phase vs Frequency
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TPS51200A-Q1
ZHCSIL4A –JUNE 2018–REVISED DECEMBER 2018
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7 Detailed Description
7.1 Overview
The TPS51200A-Q1 device is a sink and source, double data-rate (DDR) termination regulator specifically
designed for low-input voltage, low-cost, and low-noise systems where space is a key consideration.
The TPS51200A-Q1 device is designed to provide proper termination voltage and a 10-mA buffered reference
voltage for DDR memory which includes the following DDR specifications (core voltage, reference voltage) with
minimal external components: DDR (2.5 V, 1.25 V), DDR2 (1.8 V, 0.9 V), DDR3 (1.5 V, 0.75 V), LP DDR3 or
DDR4 (1.2 V, 0.6 V).
7.2 Functional Block Diagram
2
6
VLDOIN
REFIN
1
+
REFOUT
2.3 V
UVLO
+
VIN 10
Gm
DchgREF
DchgVTT
VOSNS
5
3
VO
+
ENVTT
EN
7
8
Gm
4
9
PGND
REFINOK
GND
PGOOD
+
+
Start-up
Delay
UDG-08019
7.3 Feature Description
7.3.1 Sink and Source Regulator (VO Pin)
The TPS51200A-Q1 device is a sink and source (sink/source) tracking termination regulator specifically designed
for low input voltage, low-cost, and low external-component count systems where space is a key application
parameter. The TPS51200A-Q1 device integrates a high-performance, low-dropout (LDO) linear regulator that is
capable of both sourcing and sinking current. The LDO regulator employs a fast feedback loop so that small
ceramic capacitors can be used to support the fast load transient response. To achieve tight regulation with
minimum effect of trace resistance, a remote sensing pin, VOSNS, must be connected to the positive pin of the
output capacitors as a separate trace from the high current path from the VO pin.
7.3.2 Reference Input (REFIN Pin)
The output voltage, VO, is regulated to the REFOUT pin. When the REFIN pin is configured for standard DDR
termination applications, the REFIN pin can be set by an external equivalent ratio voltage divider connected to
the memory supply bus (VDDQ). The TPS51200A-Q1 device supports the REFIN voltage from 0.5 V to 1.8 V,
making the device versatile and ideal for many types of low-power LDO applications.
10
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Feature Description (接下页)
7.3.3 Reference Output (REFOUT Pin)
When the device is configured for DDR termination applications, the REFOUT pin generates the DDR VTT
reference voltage for the memory application. The device is capable of supporting both a sourcing and sinking
load of 10 mA. The REFOUT pin becomes active when the REFIN voltage rises to 0.390 V and the VIN pin is
above the UVLO threshold. When the REFOUT pin is less than 0.375 V, it is disabled and subsequently
discharges to the GND pin through an internal 10-kΩ MOSFET. The REFOUT pin is independent of the EN pin
state.
7.3.4 Soft-Start Sequencing
The soft-start function of the VO pin is achieved through a current clamp. The current clamp allows the output
capacitors to be charged with low and constant current, providing a linear ramp-up of the output voltage. When
the VO pin is outside of the powergood window, the current clamp level is one-half of the full overcurrent limit
(OCL) level. When the VO pin rises or falls within the PGOOD window, the current clamp level switches to the
full OCL level. The soft-start function is completely symmetrical and works not only from GND to the REFOUT
voltage, but also from the VLDOIN pin to the REFOUT voltage.
7.3.5 Enable Control (EN Pin)
When the EN pin is driven high, the TPS51200A-Q1 VO-regulator begins normal operation. When the EN pin is
driven low, the VO pin discharges to the GND pin through an internal 18-Ω MOSFET. The REFOUT pin remains
on when the EN pin is driven low.
7.3.6 Powergood Function (PGOOD Pin)
The TPS51200A-Q1 device provides an open-drain PGOOD output that goes high when the VO output is within
±20% of the REFOUT pin. The PGOOD pin deasserts within 10 μs after the output exceeds the size of the
powergood window. During initial VO startup, the PGOOD pin asserts high 2 ms (typ) after the VO pin enters
power good window. Because the PGOOD pin is an open-drain output, a 100-kΩ, pullup resistor between the
PGOOD pin and a stable active supply voltage rail is required.
7.3.7 Current Protection (VO Pin)
The LDO has a constant overcurrent limit (OCL). Note that the OCL level reduces by one-half when the output
voltage is not within the powergood window. This reduction is a non-latch protection.
7.3.8 UVLO Protection (VIN Pin)
For the VIN undervoltage-lockout (UVLO) protection, the device monitors the VIN voltage. When the VIN voltage
is lower than the UVLO threshold voltage, both the VO and REFOUT regulators are powered off. This shutdown
is a non-latch protection.
7.3.9 Thermal Shutdown
The TPS51200A-Q1 device monitors the junction temperature. If the device junction temperature exceeds the
threshold value, (typically 150°C), the VO and REFOUT regulators are both shut off, discharged by the internal
discharge MOSFETs. This shutdown is a non-latch protection.
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7.4 Device Functional Modes
The TPS51200A-Q1 device can be used in an application system where either a 2.5-V rail or a 3.3-V rail is
available. The minimum input voltage requirement is 2.375 V. If a 2.5-V rail is used, ensure that the absolute
minimum voltage (both DC and transient) at the device pin is be 2.375 V or greater. The voltage tolerance for a
2.5-V rail input is between –5% and 5% accuracy, or better.
7.4.1 S3 and Pseudo-S5 Support
The TPS51200A-Q1 device provides S3 support by an EN function. The EN pin can be connected to an SLP_S3
signal in the end application. Both the REFOUT and VO pin are on when EN = high (S0 state). The REFOUT pin
is maintained while the VO pin is turned off and discharged through an internal discharge MOSFET when EN =
low (S3 state). When EN = low and the REFIN voltage is less than 0.390 V, the TPS51200A-Q1 device enters
pseudo-S5 state. Both the VO and REFOUT outputs are turned off and discharged to the GND pin through
internal MOSFETs when pseudo-S5 support is engaged (S4/S5 state). 图 19 shows a typical startup and
shutdown timing diagram for an application that uses S3 and pseudo-S5 support. It is also allowed to turn on
VLDOIN earlier than VIN during power on, and turn off VIN earlier than VLDOIN during power off.
7.4.2 Tracking Startup and Shutdown
The TPS51200A-Q1 device also supports tracking startup and shutdown when the EN pin is tied directly to the
system bus and not used to turn on or turn off the device. During tracking startup, the VO pin follows the
REFOUT pin when the REFIN voltage is greater than 0.39 V. The REFIN pin follows the rise of the VDDQ rail
though a voltage divider. The typical soft-start time for the VDDQ rail is approximately 3 ms, however this soft-
star time can vary depending on the system configuration. The SS time of the VO output no longer depends on
the OCL setting, but is a function of the SS time of the VDDQ rail. PGOOD is asserted 2 ms after the VO pin is
within ±20% of the REFOUT pin. During tracking shutdown, the VO pin falls following the REFOUT pin until the
REFOUT pin reaches 0.37 V. When the REFOUT pin falls below 0.37 V, the internal discharge MOSFETs are
turned on and quickly discharge both the REFOUT and VO pins to GND. The PGOOD pin is deasserted when
the VO pin is beyond the ±20% range of the REFOUT pin. 图 20 shows the typical timing diagram for an
application that uses tracking startup and shutdown.
3.3VIN
V
VDDQ
= 1.5 V
VLDOIN
REFIN
REFOUT
(VTTREF)
EN
(S3_SLP)
V
t
= 0.75 V
VO
t
SS .
VO
C
x V
O
OUT
=
SS
I
OOCL
PGOOD
2 ms
图 19. Typical Timing Diagram for S3 and Pseudo-S5 Support
12
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Device Functional Modes (接下页)
3.3VIN
EN
VLDOIN
REFIN
REFOUT
(VTTREF)
tSS determined
by the SS time
of VLDOIN
V
= 0.75 V
VO
VO
PGOOD
2 ms
图 20. Typical Timing Diagram of Tracking Startup and Shutdown
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS51200A-Q1 device is specifically designed to power up the memory termination rail (as shown in 图 21).
The DDR memory termination structure determines the main characteristics of the VTT rail, which is to be able to
sink and source current while maintaining acceptable VTT tolerance. See 图 22 for typical characteristics for a
single memory cell.
8.2 Typical Application
8.2.1 VTT DIMM Applications
DDR3 240 Pin Socket
VO
TPS51200A-Q1
10 µF
10 µF
10 µF
UDG-08022
图 21. Typical Application Diagram for DDR3 VTT DIMM using TPS51200A-Q1
8.2.1.1 Design Parameters
Use the information listed in 表 1 as the design parameters.
表 1. DDR, DDR2, DDR3, LP DDR3 and DDR4 Termination Technology and Differences
LP DDR3 or
DDR4
PARAMETER
DDR
DDR2
DR3
FSB Data Rates
200, 266, 333 and 400 MHz
400, 533, 677 and 800 MHz
800, 1066, 1330 and 1600 MHz
Same as DDR3
On-die termination for data group. VTT On-die termination for data group. VTT
Motherboard termination to VTT
for all signals
Termination
termination for address, command and
control signals
termination for address, command and
control signals
Same as DDR3
Same as DDR3
Not as demanding
Not as demanding
•
Only
34
signals
(address,
•
Only
34
signals
(address,
Termination Current Max source/sink transient
Demand
command, control) tied to VTT
command, control) tied to VTT
currents of up to 2.6 A to 2.9 A
•
ODT handles data signals
•
ODT handles data signals
Less than 1 A of burst current
2.5-V Core and I/O 1.25-V VTT 1.8-V Core and I/O 0.9-V VTT
Less than 1A of burst current
1.5-V Core and I/O 0.75-V VTT
1.2-V Core and I/O
0.6-V VTT
Voltage Level
14
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 VIN Capacitor
Add a ceramic capacitor, with a value between 1-μF and 4.7-μF, placed close to the VIN pin, to stabilize the bias
supply (2.5-V rail or 3.3-V rail) from any parasitic impedance from the supply.
8.2.1.2.2 VLDO Input Capacitor
Depending on the trace impedance between the VLDOIN bulk power supply to the device, a transient increase of
source current is supplied mostly by the charge from the VLDOIN input capacitor. Use a 10-μF (or greater)
ceramic capacitor to supply this transient charge. Provide more input capacitance as more output capacitance is
used at the VO pin. In general, use one-half of the COUT value for input.
8.2.1.2.3 Output Capacitor
For stable operation, the total capacitance of the VO output pin must be greater than 20 μF. Attach three, 10-μF
ceramic capacitors in parallel to minimize the effect of equivalent series resistance (ESR) and equivalent series
inductance (ESL). If the ESR is greater than 2 mΩ, insert an R-C filter between the output and the VOSNS input
to achieve loop stability. The R-C filter time constant must be almost the same as or slightly lower than the time
constant of the output capacitor and its ESR.
8.2.1.2.4 Output Tolerance Consideration for VTT DIMM Applications
图 22 shows the typical characteristics for a single memory cell.
V
V
TT
DDQ
Q1
Q2
25 W
R
S
20 W
Receiver
Ouput
Buffer
(Driver)
V
V
IN
OUT
V
SS
UDG-08023
图 22. DDR Physical Signal System Bi-Directional SSTL Signaling
In 图 22, when Q1 is on and Q2 is off:
•
•
The current flows from VDDQ via the termination resistor to VTT
VTT sinks current
In 图 22, when Q2 is on and Q1 is off:
•
•
The current flows from VTT via the termination resistor to GND
VTT sources current
Because VTT accuracy has a direct impact on the memory signal integrity, it is imperative to understand the
tolerance requirement on VTT. Based on JEDEC VTT specifications for DDR and DDR2 (JEDEC standard: DDR
JESD8-9B May 2002; DDR2 JESD8-15A Sept 2003).
VTTREF – 40 mV < VTT < VTTREF + 40 mV, for both DC and AC conditions
The specification indicates that VTT must keep track of VTTREF for proper signal conditioning.
The TPS51200A-Q1 device ensures the regulator output voltage to be:
VTTREF –25 mV < VTT < VTTREF + 25 mV, for both DC and AC conditions and –2 A < IVTT < 2 A
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The regulator output voltage is measured at the regulator side, not the load side. The tolerance is applicable to
DDR, DDR2, DDR3 and low-power DDR3/DDR4 applications (see 表 1 for detailed information). To meet the
stability requirement, a minimum output capacitance of 20 μF is needed. Considering the actual tolerance on the
MLCC capacitors, three 10-μF ceramic capacitors are sufficient to meet the above requirement.
The TPS51200A-Q1 device is designed as a Gm driven LDO. The voltage droop between the reference input
and the output regulator is determined by the transconductance and output current of the device. The typical Gm
is 250 S at 2 A and changes with respect to the load to conserve the quiescent current (that is, the Gm is very
low at no load condition). The Gm LDO regulator is a single pole system. Its unity gain bandwidth for the voltage
loop is only determined by the output capacitance, as a result of the bandwidth nature of the Gm (see 公式 1).
Gm
F
=
UGBW
2´ p´ C
OUT
where
•
•
•
FUGBW is the unity gain bandwidth
Gm is transconductance
COUT is the output capacitance
(1)
This type of regulator has two limitations on the output bulk capacitor requirement. To maintain stability, the zero
location contributed by the ESR of the output capacitors must be greater than the –3-dB point of the current loop.
This constraint means that higher ESR capacitors must not be used in the design. In addition, the impedance
characteristics of the ceramic capacitor must be well understood to prevent the gain peaking effect around the
Gm –3-dB point because of the large ESL, the output capacitor and parasitic inductance of the VO trace.
图 23. Bode Plot for a Typical DDR3 Configuration
图 23 shows the bode plot simulation for a typical DDR3 configuration of the TPS51200A-Q1 device, where:
•
•
•
•
•
•
•
VIN = 3.3 V
VVLDOIN = 1.5 V
VVO = 0.75 V
IIO = 2 A
3 × 10-μF capacitors included
ESR = 2.5 mΩ
ESL = 800 pH
The unity-gain bandwidth is approximately 1 MHz and the phase margin is 52°. The 0-dB level is crossed, the
gain peaks because of the ESL effect. However, the peaking is kept well below 0 dB.
图 24 shows the load regulation and 图 25 shows the transient response for a typical DDR3 configuration. When
the regulator is subjected to ±1.5-A load step and release, the output voltage measurement shows no difference
between the DC and AC conditions.
16
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8.2.1.3 Application Curves
790
780
770
TA
œ 40°C
0°C
25°C
85°C
760
750
740
730
720
710
700
œ3
œ2
œ1
Output Current (A)
VVIN = 3.3 V
0
1
2
3
DDR3
图 24. Output Current vs Output voltage
图 25. Transient Waveform
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8.2.2 Design Example 1
This design example describes a 3.3-VIN, DDR2 configuration.
TPS51200A-Q1
REFIN
R1
10 kꢀ
VVDDQ = 1.8 V
VVLDOIN = VVDDQ = 1.8 V
VVTT = 0.9 V
1
2
VIN 10
3.3 VIN
R2
10 kꢀ
C4
1000 pF
R3
100 kꢀ
C6
4.7 µF
VLDOIN
PGOOD
9
PGOOD
C7
10 µF
C8
10 µF
3
4
5
VO
GND
EN
8
7
6
C1
C2
10 µF
C3
10 µF
PGND
VOSNS
SLP_S3
VTTREF
10 µF
REFOUT
C5
0.1 µF
UDG-08028
图 26. 3.3-VIN, DDR2 Configuration
8.2.2.1 Design Parameters
For this design example, use the parameters listed in 表 2.
表 2. Design Example 1 List of Materials
REFERENCE
DESIGNATOR
DESCRIPTION
Resistor
SPECIFICATION
PART NUMBER
MANUFACTURER
R1, R2
10 kΩ
R3
100 kΩ
C1, C2, C3
C4
10 μF, 6.3 V
1000 pF
GRM21BR70J106KE76L
Murata
C5
Capacitor
0.1 μF
C6
4.7 μF, 6.3 V
10 μF, 6.3 V
GRM21BR60J475KA11L
GRM21BR70J106KE76L
Murata
Murata
C7, C8
18
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ZHCSIL4A –JUNE 2018–REVISED DECEMBER 2018
8.2.3 Design Example 2
This design example describes a 3.3-VIN, DDR3 configuration.
TPS51200A-Q1
REFIN
VVDDQ = 1.5 V
VVLDOIN = VVDDQ = 1.5 V
VVTT = 0.75 V
1
2
VIN 10
3.3 VIN
R2
10 kꢀ
C4
1000 pF
R3
100 kꢀ
C6
4.7 µF
VLDOIN
PGOOD
9
PGOOD
C7
10 µF
C8
10 µF
3
4
5
VO
GND
EN
8
7
6
C1
10 µF
C2
10 µF
C3
10 µF
PGND
VOSNS
SLP_S3
VTTREF
REFOUT
C5
0.1 µF
UDG-08029
图 27. 3.3-VIN, DDR3 Configuration
8.2.3.1 Design Parameters
For this design example, use the parameters listed in 表 3.
表 3. Design Example 2 List of Materials
REFERENCE
DESIGNATOR
DESCRIPTION
Resistor
SPECIFICATION
PART NUMBER
MANUFACTURER
R1, R2
10 kΩ
R3
100 kΩ
C1, C2, C3
C4
10 μF, 6.3 V
1000 pF
GRM21BR70J106KE76L
Murata
C5
Capacitor
0.1 μF
C6
4.7 μF, 6.3 V
10 μF, 6.3 V
GRM21BR60J475KA11L
GRM21BR70J106KE76L
Murata
Murata
C7, C8
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8.2.4 Design Example 3
This design example describes a 2.5-VIN, DDR3 configuration.
TPS51200A-Q1
REFIN
R1
10 kꢀ
VVDDQ = 1.5 V
VVLDOIN = VVDDQ = 1.5 V
VVTT = 0.75 V
1
2
VIN 10
2.5 VIN
R2
10 kꢀ
C4
1000 pF
C6
4.7 µF
R3
100 kꢀ
VLDOIN
PGOOD
9
PGOOD
C7
10 µF
C8
10 µF
3
4
5
VO
GND
EN
8
7
6
C1
10 µF
C2
10 µF
C3
10 µF
PGND
VOSNS
SLP_S3
VTTREF
REFOUT
C5
0.1 µF
UDG-08030
图 28. 2.5-VIN, DDR3 Configuration
8.2.4.1 Design Parameters
For this design example, use the parameters listed in 表 4.
表 4. Design Example 3 List of Materials
REFERENCE
DESIGNATOR
DESCRIPTION
SPECIFICATION
PART NUMBER
MANUFACTURER
R1, R2
10 kΩ
Resistor
R3
100 kΩ
C1, C2, C3
C4
10 μF, 6.3 V
1000 pF
GRM21BR70J106KE76L
Murata
C5
Capacitor
0.1 μF
C6
4.7 μF, 6.3 V
10 μF, 6.3 V
GRM21BR60J475KA11L
GRM21BR70J106KE76L
Murata
Murata
C7, C8
20
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ZHCSIL4A –JUNE 2018–REVISED DECEMBER 2018
8.2.5 Design Example 4
This design example describes a 3.3-VIN, LP DDR3 or DDR4 configuration.
TPS51200A-Q1
VVDDQ = 1.2 V
VVLDOIN = VVDDQ = 1.2 V
VVTT = 0.6 V
1
2
REFIN
VIN 10
3.3 VIN
R2
10 kꢀ
C4
1000 pF
C6
4.7 µF
R3
100 kꢀ
VLDOIN
PGOOD
9
PGOOD
C7
10 µF
C8
10 µF
3
4
5
VO
GND
EN
8
7
6
C1
10 µF
C2
10 µF
C3
10 µF
PGND
VOSNS
SLP_S3
VTTREF
REFOUT
C5
0.1 µF
UDG-08031
图 29. 3.3-VIN, LP DDR3 or DDR4 Configuration
8.2.5.1 Design Parameters
For this design example, use the parameters listed in 表 5.
表 5. Design Example 4 List of Materials
REFERENCE
DESIGNATOR
DESCRIPTION
Resistor
SPECIFICATION
PART NUMBER
MANUFACTURER
R1, R2
10 kΩ
R3
100 kΩ
C1, C2, C3
C4
10 μF, 6.3 V
1000 pF
GRM21BR70J106KE76L
Murata
C5
Capacitor
0.1 μF
C6
4.7 μF, 6.3 V
10 μF, 6.3 V
GRM21BR60J475KA11L
GRM21BR70J106KE76L
Murata
Murata
C7, C8
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8.2.6 Design Example 5
This design example describes a 3.3-VIN, DDR3 tracking configuration.
TPS51200A-Q1
REFIN VIN 10
R1
10 kꢀ
VVDDQ = 1.5 V
VVLDOIN = VVDDQ = 1.5 V
VVTT = 0.75 V
1
2
3.3 VIN
R2
10 kꢀ
C4
1000 pF
C6
4.7 µF
R3
100 kꢀ
VLDOIN
PGOOD
9
PGOOD
C8
10 µF
C7
10 µF
3
4
5
VO
GND
EN
8
7
6
C1
10 µF
C2
10 µF
C3
10 µF
PGND
VOSNS
REFOUT
VTTREF
C5
0.1 µF
UDG-08032
图 30. 3.3-VIN, DDR3 Tracking Configuration
8.2.6.1 Design Parameters
For this design example, use the parameters listed in 表 6.
表 6. Design Example 5 List of Materials
REFERENCE
DESIGNATOR
DESCRIPTION
Resistor
SPECIFICATION
PART NUMBER
MANUFACTURER
R1, R2
10 kΩ
R3
100 kΩ
C1, C2, C3
C4
10 μF, 6.3 V
1000 pF
GRM21BR70J106KE76L
Murata
C5
Capacitor
0.1 μF
C6
4.7 μF, 6.3 V
10 μF, 6.3 V
GRM21BR60J475KA11L
GRM21BR70J106KE76L
Murata
Murata
C7, C8
22
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ZHCSIL4A –JUNE 2018–REVISED DECEMBER 2018
8.2.7 Design Example 6
This design example describes a 3.3-VIN, LDO configuration.
TPS51200A-Q1
REFIN VIN 10
2.5 V
VVLDOIN = VVLDOREF = 2.5 V
VVLDO = 1.8 V
1
2
3.3 VIN
R2
10 kꢀ
C4
1000 pF
R3
100 kꢀ
C6
4.7 µF
VLDOIN
PGOOD
9
PGOOD
C7
10 µF
C8
10 µF
3
4
5
VO
GND
EN
8
7
6
C1
10 µF
C2
10 µF
C3
10 µF
PGND
VOSNS
ENABLE
REFOUT
REFOUT
C5
0.1 µF
UDG-08033
图 31. 3.3-VIN, LDO Configuration
8.2.7.1 Design Parameters
For this design example, use the parameters listed in 表 7.
表 7. Design Example 6 List of Materials
REFERENCE
DESIGNATOR
DESCRIPTION
SPECIFICATION
PART NUMBER
MANUFACTURER
R1
R2
R3
10 kΩ
Resistor
3.86 kΩ
100 kΩ
C1, C2, C3
C4
10 μF, 6.3 V
1000 pF
GRM21BR70J106KE76L
Murata
C5
Capacitor
0.1 μF
C6
4.7 μF, 6.3 V
10 μF, 6.3 V
GRM21BR60J475KA11L
GRM21BR70J106KE76L
Murata
Murata
C7, C8
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8.2.8 Design Example 7
This design example describes a 3.3-VIN, DDR3 configuration with Low Pass Filter (LPF).
TPS51200A-Q1
VVDDQ = 1.5 V
VVLDOIN = VVDDQ = 1.5 V
VVTT = 0.75 V
1
2
REFIN
VIN 10
3.3 VIN
R2
10 kꢀ
C4
1000 pF
C6
4.7 µF
R3
100 kꢀ
VLDOIN
PGOOD
9
PGOOD
C7
10 µF
C8
10 µF
3
4
5
VO
GND
EN
8
7
6
R4(1)
C1
10 µF
C2
10 µF
C3
10 µF
PGND
VOSNS
SLP_S3
VTTREF
REFOUT
C5
0.1 µF
C9(1)
UDG-08034
图 32. 3.3-VIN, DDR3 Configuration with LPF
8.2.8.1 Design Parameters
For this design example, use the parameters listed in 表 8.
表 8. Design Example 7 List of Materials
REFERENCE
DESIGNATOR
DESCRIPTION
SPECIFICATION
PART NUMBER
MANUFACTURER
R1, R2
10 kΩ
R3
Resistor
100 kΩ
R4(1)
C1, C2, C3
C4
10 μF, 6.3 V
1000 pF
GRM21BR70J106KE76L
Murata
C5
0.1 μF
Capacitor
C6
4.7 μF, 6.3 V
10 μF, 6.3 V
GRM21BR60J475KA11L
GRM21BR70J106KE76L
Murata
Murata
C7, C8
C9(1)
(1) The values of R4 and C9 must be chosen to reduce the parasitic effect of the trace (between VO and the output MLCCs) and the output
capacitors (ESR and ESL).
24
版权 © 2018, Texas Instruments Incorporated
TPS51200A-Q1
www.ti.com.cn
ZHCSIL4A –JUNE 2018–REVISED DECEMBER 2018
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply with a range between 2.375 V and 3.5 V. This
input supply must be well regulated. TI recommends adding at least one 1-µF to 4.7-µF ceramic capacitor at the
VIN pin.
10 Layout
10.1 Layout Guidelines
Consider the following points before starting the layout design.
•
•
•
The input bypass capacitor for VLDOIN must be placed as close as possible to the pin with short and wide
connections.
The output capacitor for VO must be placed close to the pin with short and wide connection to avoid
additional ESR or ESL trace inductance.
VOSNS must be connected to the positive node of VO output capacitors as a separate trace from the high
current power line. This configuration is strongly recommended to avoid additional ESR, ESL, or both. If
sensing the voltage at the point of the load is required, TI recommends to attach the output capacitors at that
point. Also, it is recommended to minimize any additional ESR, ESL, or both of ground trace between the
GND pin and the output capacitors.
•
•
Consider adding low-pass filter at VOSNS if the ESR of the VO output capacitors is larger than 2 mΩ.
REFIN can be connected separately from VLDOIN. Remember that this sensing potential is the reference
voltage of REFOUT. Avoid any noise-generating lines.
•
•
The negative node of the VO output capacitors and the REFOUT capacitor must be tied together by avoiding
common impedance to the high current path of the VO source/sink current.
The GND and PGND pins must be connected to the thermal land underneath the die pad with multiple vias
connecting to the internal system ground planes (for better result, use at least two internal ground planes).
Use as many vias as possible to reduce the impedance between PGND/GND and the system ground plane.
Also, place bulk caps close to the DIMM load point, route the VOSNS to the DIMM load sense point.
•
•
To effectively remove heat from the package, properly prepare the thermal land. Apply solder directly to the
thermal pad of the package. The wide traces of the component and the side copper connected to the thermal
land pad help to dissipate heat. Numerous vias 0,33 mm in diameter connected from the thermal land to the
internal/solder side ground planes must also be used to help dissipation.
See the TPS51200-EVM User's Guide (SLUU323) for detailed layout recommendations.
10.1.1 LDO Design Guidelines
The minimum input to output voltage difference (headroom) decides the lowest usable supply voltage
transconductance to drive a certain load. For device, a minimum of 300 mV (VLDOINMIIN – VOMAX) is needed to
support a Gm driven sourcing current of 2 A based on a design of VIN = 3.3 V and COUT = 3 × 10 μF. Because
the TPS51200A-Q1 device is essentially a Gm driven LDO, the impedance characteristics are both a function of
the 1 / Gm and RDS(on) of the sourcing MOSFET (see 图 33). The current inflection point of the design is between
2 A and 3 A. When ISRC is less than the inflection point, the LDO is considered to be operating in the Gm region;
when ISRC is greater than the inflection point but less than the overcurrent limit point, the LDO is operating in the
RDS(on) region. The maximum sourcing RDS(on) is 0.144 Ω with VIN = 3 V and TJ = 125°C.
版权 © 2018, Texas Instruments Incorporated
25
TPS51200A-Q1
ZHCSIL4A –JUNE 2018–REVISED DECEMBER 2018
www.ti.com.cn
Layout Guidelines (接下页)
1/Gm
1/RDS(on)
Inflection
Point
(between
2 A and 3 A)
Overcurrent
Limit
Source Current, ISRC (A)
UDG-08026
图 33. Impedance Characteristics
10.2 Layout Example
REFIN
VLDOIN
VO
1
2
3
4
5
10
9
VIN
PGOOD
GND
8
PGND
VOSNS
7
EN
6
REFOUT
图 34. Layout Example
26
版权 © 2018, Texas Instruments Incorporated
TPS51200A-Q1
www.ti.com.cn
ZHCSIL4A –JUNE 2018–REVISED DECEMBER 2018
10.3 Thermal Considerations
Because the TPS51200A-Q1 device is a linear regulator, the VO current flows in both source and sink directions,
thereby dissipating power from the device. When the device is sourcing current, the voltage difference between
VLDOIN and VO times IO (IIO) current becomes the power dissipation as shown in 公式 2.
P
=
V
(
- V
x I
O _SRC
)
DISS _SRC
VLDOIN
VO
(2)
In this case, if VLDOIN is connected to an alternative power supply lower than the VDDQ voltage, overall power
loss can be reduced. For the sink phase, VO voltage is applied across the internal LDO regulator, and the power
dissipation, PDISS_SNK can be calculated by 公式 3.
P
= V ´ I
VO O _SNK
DISS _SNK
(3)
Because the device does not sink and source current at the same time and the IO current may vary rapidly with
time, the actual power dissipation must be the time average of the above dissipations over the thermal relaxation
duration of the system. Another source of power consumption is the current used for the internal current control
circuitry from the VIN supply and the VLDOIN supply. This can be estimated as 5 mW or less during normal
operatiing conditions. This power must be effectively dissipated from the package.
Maximum power dissipation allowed by the package is calculated by 公式 4.
PPKG = (TJ(MAX) – TA(MAX)) / RθJA
T
J(max) ´ TA(max)
PPKG
=
RqJA
where
•
•
•
TJ(MAX) is 125°C
TA(MAX) is the maximum ambient temperature in the system
RθJA is the thermal resistance from junction to ambient
(4)
The thermal performance of an LDO depends on the printed circuit board (PCB) layout. The TPS51200A-Q1
device is housed in a thermally-enhanced package that has an exposed die pad underneath the body. For
improved thermal performance, this die pad must be attached to ground via thermal land on the PCB. This
ground trace acts as a both a heatsink and heatspreader. The typical thermal resistance, RθJA, 55.7°C/W, is
achieved based on a land pattern of 3 mm × 1,9 mm with four vias (0,33-mm via diameter, the standard thermal
via size) without air flow (see 图 35).
Land Pad
3 mm × 1.9 mm
Exposed Thermal
Die Pad,
2.48 mm × 1.74 mm
UDG-08018
图 35. Recommend Land Pad Pattern for TPS51200A-Q1
版权 © 2018, Texas Instruments Incorporated
27
TPS51200A-Q1
ZHCSIL4A –JUNE 2018–REVISED DECEMBER 2018
www.ti.com.cn
Thermal Considerations (接下页)
TT on top of package
TB on PCB surface
1 mm
图 36. Package Thermal Measurement
To further improve the thermal performance of this device, using a larger than recommended thermal land as
well as increasing the number of vias helps lower the thermal resistance from junction to thermal pad. The typical
thermal resistance from junction to thermal pad, RθJP, is 12.1°C/W (based on the recommend land pad and four
standard thermal vias).
28
版权 © 2018, Texas Instruments Incorporated
TPS51200A-Q1
www.ti.com.cn
ZHCSIL4A –JUNE 2018–REVISED DECEMBER 2018
11 器件和文档支持
11.1 器件支持
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.2 文档支持
11.2.1 相关文档
请参阅如下相关文档：
《TPS51200-EVM 用户指南》，SLUU323
11.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2018, Texas Instruments Incorporated
29
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS51200AQDRCRQ1
TPS51200AQDRCTQ1
ACTIVE
ACTIVE
VSON
VSON
DRC
DRC
10
10
3000 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
512AQ
512AQ
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS51200AQDRCRQ1
TPS51200AQDRCTQ1
VSON
VSON
DRC
DRC
10
10
3000
250
330.0
330.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS51200AQDRCRQ1
TPS51200AQDRCTQ1
VSON
VSON
DRC
DRC
10
10
3000
250
338.0
205.0
355.0
200.0
50.0
33.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
www.ti.com
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED
THERMAL PAD
4X (0.25)
5
6
2X
2
11
SYMM
2.4 0.1
10
1
8X 0.5
0.30
0.18
10X
SYMM
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
0.5
0.3
10X
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
(3.4)
SYMM
(0.95)
8X (0.5)
6
5
(R0.05) TYP
(
0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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