TPS51221RTVTG4 [TI]
DUAL SWITCHING CONTROLLER, 333kHz SWITCHING FREQ-MAX, PQCC32, 5 X 5 MM, GREEN, PLASTIC, QFN-32;
| 型号： | TPS51221RTVTG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL SWITCHING CONTROLLER, 333kHz SWITCHING FREQ-MAX, PQCC32, 5 X 5 MM, GREEN, PLASTIC, QFN-32 开关 |
| 文件： | 总40页 (文件大小：946K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS51221
www.ti.com ............................................................................................................................................... SLVS786A–NOVEMBER 2007–REVISED MARCH 2009
Fixed Frequency, 99% Duty Cycle Peak Current Mode
Notebook System Power Controller
1
FEATURES
APPLICATIONS
•
Notebook Computer System and I/O Bus
2
•
Input Voltage Range: 4.5 V to 28 V
•
Point of load in LCD TV, MFP
•
•
Output Voltage Range: 1 V to 12 V
Selectable Light Load Operation (Continuous /
Auto Skip / Out-Of-Audio™ Skip)
DESCRIPTION
The TPS51221 is a dual synchronous buck regulator
controller with 2 LDOs. It is optimized for 5-V/3.3-V
system controller, enabling designers to cost
effectively complete 2-cell to 4-cell notebook system
power supply. The TPS51221 supports high
efficiency, fast transient response and 99% duty cycle
operation. It supports supply input voltage ranging
from 4.5 V to 28 V, and output voltages from 1 V to
12 V. Peak current mode supports stability operation
with lower ESR capacitor and output accuracy. The
high duty (99%) operation and wide input/ output
voltage range supports flexible design for small
mobile PCs and a wide variety of other applications.
The fixed frequency can be adjusted from 200 kHz to
1MHz by a resistor, and each channel runs 180° out
of phase. The TPS51221 can also synchronize to the
external clock, and the interleaving ratio can be
adjusted by its duty. The TPS51221 is available in the
32-pin 5×5 QFN package and is specified from –40°C
to 85°C.
•
•
•
•
•
•
•
•
•
•
•
•
•
Programmable Droop Compensation
Voltage Servo Adjustable Soft Start
200 kHz to 1 MHz Fixed Frequency PWM
Current Mode Architecture
180° Phase Shift Between Channels
Resistor or Inductor DCR Current Sensing
Powergood Output for each channel
OCL/OVP/UVP/UVLO protections
Current Monitor Output for CH1
Thermal Shutdown (Non-latch)
Output Discharge Function (Disable option)
Integrated Boot Strap MOSFET Switch
QFN32 (RTV)
TYPICAL APPLICATION CIRCUIT
VREG5
5V/100mA
VBAT
VBAT
Q11
C12
Q21
C22
C01
L2
C14
C24
L1
PGND
PGND
VO2
3.3V
Q12
VO1
5.0V
GND
PGND
PGND
C21
Q22
C11
32 31 30 29 28 27 26 25
PGND
PGND
PGND
PGND
1
2
3
4
5
6
7
8
24
DRVH1
DRVH2
VO1
V5SW
RF
VIN 23
VREG3 22
EN2 21
VBAT
R01
VREG3
3.3V/10mA
C03
GND
EN1
EN1
EN2
TPS51221RTV
(QFN32)
PGOOD1
PGOOD1
SKIPSEL1
PGOOD2 20
SKIPSEL2 19
CSP2 18
PGOOD2
GND
SKIPSEL1
R14
SKIPSEL2
R24
PowerPAD
CSP1
CSN1
C23
C13
CSN2
17
9
10 11
12 13 14 15 16
R23
GND
R12
EN
VO1
VREG5
VO2
R02
IMON1
R21
C04
GND
R11
R22
C02
R13
GND
GND
GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
Out-Of-Audio, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2009, Texas Instruments Incorporated
TPS51221
SLVS786A–NOVEMBER 2007–REVISED MARCH 2009............................................................................................................................................... www.ti.com
FUNCTIONAL BLOCK DIAGRAM
VIN
EN
V5SW
1.25V
+
+
+
+
4.7V/ 4.5V
4.7V/ 4.5V
VREG3
VREG5
GND
V5OK
THOK
+
4.2V/ 3.8V
Ready
GND
+
VREF2
150/ 140
Deg-C
1.25V
GND
GND
CLK2
CLK1
OSC
RF
GND
1V +5%/ 10%
1V - 5%/ 10%
+
+
PGOOD1
Delay
1V -30%
+
+
GND
UVP
OVP
CLK1
Ready
Fault2
SDN2
1V +15%
Fault1
SDN1
COMP1
VFB1
Ramp
Comp
+
+
PWM
VREG5
1V
+
+
VFB-AMP
EN1
Enable/
Soft-start
VREF2
VBST1
DRVH1
SW1
Ramp
Comp
Control
Logic
IMON1
+
Skip
Filter
Amp.
(CH1 only)
CSN1
CS-AMP
+
OCP
XCON
+
CSP1
TRIP
VREG5
100mV
DRVL1
Discharge
Control
GND
GND
N-OCP
+
100mV
VREF2
GND
OOA
Ctrl
GND
SKIPSEL1
Channel-1 Switcher shown
2
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Product Folder Link(s): TPS51221
TPS51221
www.ti.com ............................................................................................................................................... SLVS786A–NOVEMBER 2007–REVISED MARCH 2009
ORDERING INFORMATION(1)
ORDERABLE
PART NUMBER
MINIMUM
ORDER
QUANTITY
OUTPUT
SUPPLY
TA
PACKAGE
PINS
ECO PLAN
TPS51221RTVT
TPS51221RTVR
Tape and reel
Tape and reel
250
Green (RoHS
and no Sb/Br)
PLASTIC QUAD
FLAT PACK (QFN)
–40°C to 85°C
32
3000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
–0.3 to 30
–0.3 to 35
–0.3 to 7
–5 to 30
–1 to 13.5
–0.3 to 7
–1 to 7
UNIT
V
VIN
VBST1, VBST2
VBST1, VBST2(3)
V
V
SW1, SW2
V
(2)
Input voltage range
CSP1, CSP2, CSN1, CSN2
V
EN, EN1, EN2, VFB1, VFB2, TRIP, SKIPSEL1, SKIPSEL2
V
V5SW
V
V5SW (to VREG5)(4)
DRVH1, DRVH2
DRVH1, DRVH2(3)
–7 to 7
V
–5 to 35
–0.3 to 7
V
V
(2)
Output voltage range
DRVL1, DRVL2, COMP1, COMP2, VREG5, RF, VREF2, IMON1 PGOOD1,
PGOOD2
–0.3 to 7
V
VREG3
–0.3 to 3.6
–40 to 125
–55 to 150
V
Operating junction temperature range, TJ
Storage temperature, Tst
°C
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
(3) Voltage values are with respect to the corresponding SW terminal.
(4) When EN is high and V5SW is grounded, or voltage is applied to V5SW when EN is low.
DISSIPATION RATINGS (2 oz Trace and Copper Pad with Solder)
PACKAGE
TA < 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
32 pin RTV
1.7 W
17 mW/°C
0.7 W
Copyright © 2007–2009, Texas Instruments Incorporated
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SLVS786A–NOVEMBER 2007–REVISED MARCH 2009............................................................................................................................................... www.ti.com
RECOMMENDED OPERATING CONDITIONS
MIN
4.5
TYP
MAX
28
6
UNIT
VIN
Supply voltage
I/O voltage
V
V5SW
–0.8
–0.1
–4.0
–0.1
–4.0
–0.8
VBST1, VBST2
DRVH1, DRVH2
DRVH1, DRVH2 (wrt SW1, 2)
SW1, SW2
33
33
6
28
13
V
CSP1, CSP2, CSN1, CSN2
EN, EN1, EN2, VFB1, VFB2, TRIP, DRVL1, DRVL2, COMP1, COMP2,
VREG5, RF, VREF2, PGOOD1, PGOOD2, SKIPSEL1, SKIPSEL2, IMON1
–0.1
6
VREG3
–0.1
–40
3.5
85
Operating free-air temperature, TA
°C
4
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www.ti.com ............................................................................................................................................... SLVS786A–NOVEMBER 2007–REVISED MARCH 2009
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, EN=3.3V, VIN=12V, V5SW=5V (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIN shutdown current, TA = 25°C,
No Load, EN = 0V, V5SW = 0 V
IVINSDN
VIN shutdown current
VIN standby current 1
Vbat standby current
7
80
15
µA
µA
µA
VIN standby current, TA = 25°C, No Load,
EN1=EN2=V5SW = 0 V
IVINSTBY1
IVBATSTBY
120
Vbat standby current, TA = 25°C, No Load
500
SKIPSEL2=2V, EN2=open, EN1=V5SW=0V(1)
TRIP = 5 V
TRIP = 0 V
1.2
1.4
mA
mA
V5SW current, TA = 25°C, No Load,
ENx=5V, VFBx=1.05 V
IV5SW
V5SW supply current
VREF2 OUTPUT
IVREF2 < ±10 µA, TA = 25°C
1.98
1.97
2.00
2.00
2.02
2.03
VVREF2
VREF2 output voltage
V
IVREF2 < ±100 µA, 4.5V < VIN < 25 V
VREG3 OUTPUT
V5SW = 0 V, IVREG3 = 0 mA, TA = 25°C
3.279 3.313
3.135 3.300
3.347
3.400
20
VVREG3
VREG3 output voltage
VREG3 output current
V
V5SW = 0 V, 0 mA < IVREG3 <10 mA,
5.5 V <VIN<25 V
IVREG3
VREG5 OUTPUT
VREG3 = 3 V
10
15
mA
V5SW = 0 V, IVREG5 = 0 mA, TA = 25°C
4.99
4.90
5.04
5.03
5.09
5.15
V
V5SW = 0 V, 0 mA < IVREG5 <100 mA,
6 V <VIN<25 V
VVREG5
VREG5 output voltage
V5SW = 0 V, 0 mA < IVREG5 <100 mA,
5.5 V <VIN<25 V
4.50
5.03
5.15
V
V5SW = 0 V, VREG5 = 4.5 V
V5SW = 5 V, VREG5 = 4.5 V
Turning on
100
200
150
300
4.7
200
400
4.8
IVREG5
VREG5 output current
Switchover threshold
mA
4.55
0.15
VTHV5SW
V
Hysteresis
0.20
7.7
0.25
tdV5SW
Switchover delay
Turning on
ms
RV5SW
5V SW On-resistance
IVREG5 = 100 mA
0.5
Ω
OUTPUT
TA = 25°C, No Load
0.9925 1.000 1.0075
VFB regulation voltage
tolerance
VVFB
V
TA = –40°C to 85°C , No Load
0.990 1.000
–50
1.010
50
IVFB
VFB input current
IVFB VFBx = 1.05 V, COMPx = 1.8 V, TA = 25°C
nA
CSNx discharge
resistance
RDischg
ENx = 0 V, CSNx = 0.5 V, TA = 25°C
20
40
30
Ω
VOLTAGE TRANSCONDUCTANCE AMPLIFIER
GmV
Gain
TA = 25°C
500
–30
µS
Differential input voltage
range
Vind
mV
COMP maximum sink
current
ICOMPSNK
ICOMPSRC
COMPx = 1.8 V
COMPx = 1.8 V
33
µA
µA
COMP maximum source
current
–33
(1) Specified by design. Detailed external condition follows the application circuit of Figure 51
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, EN=3.3V, VIN=12V, V5SW=5V (unless otherwise noted)
PARAMETER
CURRENT AMPLIFIER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TRIP = 0V/2V, CSN = 5V, TA = 25°C(2)
TRIP=3.3V/5V, CSN=5V, TA = 25°C(2)
3.333
1.667
GC
VIC
Gain
Common mode input
voltage range
0
13
75
V
Differential input voltage
range
VID
TA = 25°C
–75
mV
POWERGOOD
PG in from lower
PG in from higher
PG hysteresis
92.5%
95%
97.5%
VTHPG
PG threshold
102.5% 105% 107.5%
5%
5
IPG
PG sink current
PGOOD Delay
PGOOD = 0.5 V
Delay for PG in
mA
ms
tPGDLY
SOFTSTART
tSSDYL
tSS
0.8
1
1.2
Soft start delay
Soft start time
Delay for Soft Start, ENx=Hi to SS-ramp starts
Internal soft start
200
960
µs
µs
FREQUENCY AND DUTY CONTROL
fSW
Switching frequency
Rf = 330 kΩ
Lo to Hi
273
0.7
303
1.3
0.2
333
2.0
kHz
V
VTHRF
RF threshold
Hysteresis
V
Sync input frequency
range
fSYNC
Specified by design
200
1000
kHz
tONMIN
Minimum on-time
Minimum off-time
VDRVH = 90% to 10%, No Load
VDRVH = 10% to 90%, No Load
DRVH-off to DRVL-on
120
290
30
150
440
50
ns
ns
ns
ns
V
tOFFMIN
10
30
tD
Dead time
DRVL-off to DRVH-on
40
70
(2)
VDTH
VDTL
DRVH-off threshold
DRVL-off threshold
DRVH to GND
1.0
1.0
DRVL to GND(2)
V
OUTPUT DRIVERS
Source, VVBST-DRVH = 0.1 V
Sink, VDRVH-SW = 0.1 V
1.7
1.0
1.3
0.7
5.0
3.0
4.0
2.0
RDRVH DRVH resistance
Ω
Ω
Source, VV5IN-DRVL = 0.1 V
Sink, VDRVL-PGND = 0.1 V
RDRVL
DRVL resistance
CURRENT SENSE
TRIP = 0V/2V, TA = 25°C
TRIP = 0V/2V
27
25
56
54
31
31
60
60
35
37
64
66
Current limit threshold
(Ultra low voltage)
VOCL-ULV
mV
TRIP = 3.3V/5V, TA = 25°C
TRIP = 3.3V/5V
Current limit threshold
( low voltage)
VOCL-LV
VZC
mV
mV
mV
Zero cross detection
comparator offset
0.95V < CSNx < 12.6V
–4
0
4
TRIP = 0V/2V, TA = 25°C
TRIP = 0V/2V
–24
–22
–51
–49
–31
–31
–60
–60
–38
–40
–69
–71
Negative current limit
threshold (ULV)
VOCLN-ULV
TRIP = 3.3V/5V, TA = 25°C
TRIP = 3.3V/5V
Negative current limit
threshold (LV)
VOCLN-LV
mV
(2) Specified by design.
6
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, EN=3.3V, VIN=12V, V5SW=5V (unless otherwise noted)
PARAMETER
UVP, OVP AND UVLO
TEST CONDITIONS
MIN
TYP
MAX UNIT
VOVP
OVP trip threshold
OVP prop delay
UVP trip threshold
UVP delay
OVP detect
UVP detect
110% 115%
1.5
120%
µs
tOVPDLY
VUVP
65%
0.8
70%
1
73%
tUVPDLY
1.2
1.9
ms
V
Wake up
Hysteresis
Wake up
Hysteresis
Wake up
Hysteresis
1.7
1.8
VUVREF2
VUVREG3
VUVREG5
VREF2 UVLO threshold
VREG3 UVLO threshold
VREG5 UVLO threshold
75
100
3.1
125
3.2
mV
3.0
V
0.10
4.1
0.15
4.2
0.20
4.3
V
V
0.35
0.40
0.44
INTERFACE AND LOGIC THRESHOLD
Wake up
Hysteresis
Wake up
Hysteresis
0.8
0.1
1.0
0.2
1.2
0.3
VEN
EN threshold
V
0.45
0.1
0.50
0.2
0.55
0.3
VEN12
EN1/EN2 threshold
V
V
EN1/EN2 SS start
threshold
VEN12SS
SS-ramp start threshold at external soft start
SS-End threshold at external soft start
1.0
EN1/EN2 SS end
threshold
VEN12SSEND
IEN12
2.0
2.0
V
EN1/EN2 source current
VEN1/EN2 = 0V
1.5
2.6
1.5
2.1
3.4
µA
Continuous
Auto Skip
1.9
3.2
3.8
SKIPSEL1/SKIPSEL2
logic setting voltage
VSKIPSEL
V
V
OOA Skip (min 1/8 Fsw)
OOA Skip (min 1/16 Fsw)
VOCL-ULV, Discharge ON
VOCL-ULV, Discharge OFF
VOCL-LV, Discharge OFF
VOCL-LV, Discharge ON
TRIP = 0V
1.5
2.1
3.4
1.9
3.2
VTRIP
TRIP logic setting voltage
3.8
–1
1
1
ITRIP
TRIP input current
µA
µA
TRIP =5V
–1
SKIPSELx = 0 V
SKIPSELx = 5 V
–0.5
–0.5
0.5
0.5
ISKIPSEL
SKIPSEL input current
BOOT STRAP SW
VFBST Forward voltage
IBSTLK VBST leakage current
THERMAL SHUTDOWN
VVREG5-VBST, IF = 10 mA, TA = 25°C
VBST = 30 V, SW = 25 V
0.10
0.01
0.20
1.5
V
µA
Shutdown temperature(3)
Hysteresis(3)
150
10
TSDN
Thermal SDN threshold
°C
(3) Specified by design.
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, EN=3.3V, VIN=12V, V5SW=5V (unless otherwise noted)
PARAMETER
CURRENT MONITOR
TEST CONDITIONS
MIN
TYP
MAX UNIT
TRIP = 0V/2V
100
50
GIMON
Current monitor gain
TRIP = 3.3V/5V
TRIP = 0V/2V, VCSPx-CSNx = 30 mV, 0.95V<CNSx<12.6V,
TA = 25°C
2.65
2.75
2.95
3.0
3.25
V
VIMON
Current monitor output
TRIP = 3.3V/5V, VCSPx-CSNx = 60 mV,
0.95V<CNSx<12.6V, TA = 25°C
3.25
TRIP = 0V/2V, VCSPx-CSNx = 0 V, 0.95V<CNSx<12.6V, TA
= 25°C
–300
–200
300
mV
200
Current monitor output
offset
VIMON-OFF
TRIP = 3.3V/5V, VCSPx-CSNx = 0 V, 0.95V<CNSx<12.6V,
TA = 25°C
DEVICE INFORMATION
PINOUT
RTV PACKAGE
(TOP VIEW)
DRVH1
V5SW
1
2
3
4
5
6
7
8
24
23
22
21
20
19
DRVH2
VIN
RF
VREG3
EN2
EN1
PGOOD1
SKIPSEL1
CSP1
PGOOD2
SKIPSEL2
CSP2
18
17
CSN2
CSN1
8
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TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
DRVH1
DRVH2
SW2
NO.
1
High-side MOSFET gate driver outputs. Source 1.7 Ω, sink 1.0 Ω, SW-node referenced floating driver. Drive
O
voltage corresponds to VBST to SW voltage.
24
25
32
I/O
O
I
High-side MOSFET gate driver returns.
SW1
Always alive 3.3-V, 10-mA low dropout linear regulator output. Bypass to (signal) GND by more than 1-µF
ceramic capacitor. Runs from VIN supply or from VREG5 when it is switched over to V5SW input.
VREG3
22
EN1
4
21
5
Channel 1 and Channel 2 SMPS enable pins. When turning on, apply greater than 0.55 V and less than 6 V,
or leave floating. Connect to GND to disable. Adjustable soft-start capacitance to be attached here.
EN2
PGOOD1
PGOOD2
SKIPSEL1
Power good window comparator outputs for channel 1 and 2. The applied voltage should be less than 6V
and recommended pull-up resistance value is from 100 kΩ to 1 MΩ.
O
I
20
6
Skip Mode Selection pin.
GND: Continuous Conduction Mode
VREF2: Auto Skip
SKIPSEL2
19
VREG3: OOA Auto Skip, maximum 7 skips (use with < 400 kHz)
VREG5: OOA Auto Skip, maximum 15 skips (use with more than 400 kHz)
CSP1
CSP2
7
Current sense comparator inputs (+). An RC network with high quality X5R or X7R ceramic capacitor should
be used to extract voltage drop across DCR. 0.1 µF is a good value to start design. Refer to current sensing
scheme section for more details.
I/O
18
CSN1
CSN2
VFB1
8
Current sense comparator inputs (–). (See the current sensing scheme section.) Used as power supply for
the current sense circuit for 5 V or higher output voltage setting. Also, used for output discharge.
I
I
17
9
SMPS feedback inputs. Connect the feedback resistor divider and should refer to (signal) GND.
VFB2
16
10
15
COMP1
COMP2
Loop compensation pin (error amplifier output). Connect R (and C if required) from this pin to VREF2 for
proper loop compensation with current mode operation.
I
Frequency setting pin. Connect a frequency setting resistor to (signal) GND. Connect to an external clock for
synchronization.
RF
3
I/O
IMON1
VREF2
11
13
O
O
Current monitor outputs for CH1. Adding RC filter is recommended.
2-V reference output. Bypass to (signal) GND by 0.22-µF ceramic capacitor.
Over current trip level and discharge mode selection pin.
GND: VOCL-ULV, Discharge on
VREF2: VOCL-ULV, Discharge off
VREG3: VOCL-LV, Discharge off
VREG5: VOCL-LV, Discharge on
TRIP
14
I
VREF2 and VREG5 Linear Regulators Enable Pin. When turning on, apply greater than 1.2 V and less than
6 V. Connect to GND to Disable.
EN
12
I
I
VBST1
VBST2
31
26
Supply inputs for high-side N-channel FET driver (boot strap terminal). Connect a capacitor (0.1 µF or
greater is recommended) from this pin to respective SW terminal. Additional SB diode from VREG5 to this
pin is an optional.
DRVL1
DRVL2
30
27
O
I
Low-side MOSFET gate driver outputs. Source 1.3 Ω, sink 0.7 Ω, GND referenced driver.
VREG5 switchover power supply input pin. When EN1 is high, PGOOD1 indicates GOOD and V5SW voltage
is higher than 4.8 V, the switchover function is enabled. (Note: when switchover is enabled, VREG5 output
voltage is approximately the same as the V5SW input voltage.)
V5SW
2
5-V, 100-mA low dropout linear regulator output. Bypass to (power) GND using a 10 µF ceramic capacitor.
Runs from VIN supply. Internally connected to VBST and DRVL. Shuts off with EN. Switches over to V5SW
when 4.8V or above is provided. (Note: when switch-over (see V5SW description above) is enabled, VREG5
output voltage is approximately the same as V5SW input voltage.)
VREG5
29
O
VIN
23
28
I
Supply Input for 5-V and 3.3-V linear regulator. Typically connected to VBAT.
Ground
GND
—
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TYPICAL CHARACTERISTICS
VIN SHUTDOWN CURRENT
VIN SHUTDOWN CURRENT
vs
JUNCTION TEMPERATURE
vs
INPUT VOLTAGE
15
12
9
15
12
9
V
= 12 V
IN
RT
6
6
3
0
3
0
-50
0
50
100
150
5
10
15
20
25
30
TJ - Junction Temperature - °C
VIN - VIN Input Voltage - V
Figure 1.
Figure 2.
VIN STANDBY CURRENT
vs
JUNCTION TEMPERATURE
VIN STANDBY CURRENT
vs
INPUT VOLTAGE
120
100
80
120
100
80
60
40
20
0
60
40
20
0
-50
0
50
100
150
5
10
15
20
25
30
TJ - Junction Temperature -° C
VIN - VIN Input Voltage - V
Figure 3.
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
NO LOAD BATTERY CURRENT
NO LOAD BATTERY CURRENT
vs
vs
INPUT VOLTAGE
INPUT VOLTAGE
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
EN = on, EN1 = on, EN2 = on
EN = on, EN1 = off, EN2 = on
5
10
15
20
25
5
10
15
20
25
VIN - Input Voltage - V
VIN - Input Voltage - V
Figure 5.
Figure 6.
BATTERY CURRENT
vs
INPUT VOLTAGE
VREF2 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1
2.02
2.01
2.00
EN = on, EN1 = on, EN2 = off
VIN=12V
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
1.99
1.98
0.1
0
5
10
15
- Input Voltage - V
20
25
-100
-50
0
50
100
V
IN
IREF2 - VREF2 Output Current - μA
Figure 7.
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
VREF3 OUTPUT VOLTAGE
vs
VREF5 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT CURRENT
5.10
5.05
5.00
3.40
3.35
3.30
3.25
3.20
VIN=12V
VIN=12V
4.95
4.90
0
20
40
60
80
100
0
2
4
6
8
10
IREG5 - VREG5 Output Current - mA
IREG3 - VREG3 Output Current - mA
Figure 9.
Figure 10.
SWITCHING FREQUENCY
vs
JUNCTION TEMPERATURE
OVP/UVP THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
330
320
310
300
290
280
270
150
130
110
90
RF = 330 kΩ
OVP
70
UVP
50
-50
-50
0
50
100
150
0
50
100
150
TJ - Junction Temperature - °C
TJ - Junction Temperature -°C
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
FORWARD VOLTAGE OF BOOST SW
VBST LEAKAGE CURRENT
vs
JUNCTION TEMPERATURE
vs
JUNCTION TEMPERATURE
1.5
1.2
0.9
0.6
0.3
0.0
0.25
0.20
0.15
0.10
0.05
0.00
-50
0
50
100
150
-50
0
50
100
150
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 13.
Figure 14.
CURRENT LIMIT THRESHOLD
vs
JUNCTION TEMPERATURE
CURRENT LIMIT THRESHOLD
vs
JUNCTION TEMPERATURE
37
35
66
64
CSN = 1 V
CSN = 1 V
CSN = 5 V
62
60
33
31
29
CSN = 5 V
CSN = 12 V
CSN = 12 V
58
56
54
27
25
-50
0
50
100
- Junction Temperature - ºC
150
-50
0
50
100
150
T
T
- Junction Temperature - ºC
J
J
Figure 15.
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
5-V OUTPUT VOLTAGE
vs
3.3-V OUTPUT VOLTAGE
vs
INPUT VOLTAGE
INPUT VOLTAGE
3.40
3.35
3.30
5.10
5.05
5.00
CCM
CCM
IO = 0A
IO = 3A
IO = 6A
IO = 0A
IO = 3A
IO = 6A
4.95
4.90
3.25
3.20
5
10
15
20
25
5
10
15
20
25
VIN - Input Voltage - V
Figure 17.
VIN - Input Voltage - V
Figure 18.
5-V EFFICIENCY
vs
OUTPUT CURRENT
5-V EFFICIENCY
vs
OUTPUT CURRENT
100
100
90
Auto-skip
VIN = 7 V
80
60
40
OOA
VIN = 12 V
80
VIN = 21 V
70
60
50
20
0
CCM
Auto-skip
VIN = 12 V
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
IOUT1 - 5-V Output Current - A
IOUT1 - 5-V Output Current - A
Figure 19.
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
3.3-V EFFICIENCY
vs
OUTPUT CURRENT
3.3-V EFFICIENCY
vs
OUTPUT CURRENT
100
90
100
80
VIN = 7 V
Auto-skip
VIN = 12 V
80
70
60
50
40
60
VIN = 21 V
OOA
Auto-skip
40
CCM
5-V Switcher ON
(Auto-skip)
20
0
5-V Switcher ON
(Auto-skip)
VIN = 12 V
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
IOUT2 - 3.3-V Output Current - A
IOUT2 - 3.3-V Output Current - A
Figure 21.
Figure 22.
5-V SWITCHING FREQUENCY
3.3-V SWITCHING FREQUENCY
vs
vs
OUTPUT CURRENT
OUTPUT CURRENT
400
400
350
300
250
200
150
100
VIN = 12 V
VIN = 12 V
350
300
250
200
150
100
50
CCM
CCM
OOA
OOA
50
0
Auto-skip
Auto-skip
0
0
0.5
1
1.5
2
0
0.5
1
1.5
2
IOUT2 - 3.3-V Output Current - A
IOUT1 - 5-V Output Current - A
Figure 23.
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
5-V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.3-V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.40
3.35
3.30
5.10
5.05
5.00
VIN = 12 V
OOA
VIN = 12 V
OOA
CCM
Auto-skip
Auto-skip
CCM
3.25
3.20
4.95
4.90
0
1
2
3
4
5
6
0
1
2
3
4
5
6
IOUT2 - 3.3-V Output Current - A
IOUT1 - 5-V Output Current - A
Figure 25.
Figure 26.
5.0-V START-UP WAVEFORMS
3.3-V START-UP WAVEFORMS
EN1 (5 V/div)
EN2 (5 V/div)
VO1 (2 V/div)
VO2 (2 V/div)
PGOOD1 (5 V/div)
PGOOD2 (5 V/div)
VIN = 12 V
Iout = 6 A
VIN = 12 V
Iout = 6 A
t - Time - 1 ms/div
t - Time - 1 ms/div
Figure 27.
Figure 28.
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TYPICAL CHARACTERISTICS (continued)
5.0-V SOFT-STOP WAVEFORMS
3.3-V SOFT-STOP WAVEFORMS
EN1 (5 V/div)
EN2 (5 V/div)
VO1 (5 V/div)
VO2 (5 V/div)
PGOOD1 (5 V/div)
DRVL1 (5 V/div)
PGOOD2 (5 V/div)
DRVL2 (5 V/div)
t - Time - 1 ms/div
t - Time - 1 ms/div
Figure 29.
Figure 30.
5.0-V LOAD TRANSIENT RESPONSSE
3.3-V LOAD TRANSIENT RESPONSSE
VO2 (100 mV/div)
VO1 (100 mV/div)
I
(5 A/div)
IND
I
(5 A/div)
IND
IO1 (5 A/div)
VIN = 12 V, Auto-skip
IO2 (5 A/div)
VIN = 12 V, Auto-skip
t - Time - 100 ms/div
t - Time - 100 ms/div
Figure 32.
Figure 31.
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TYPICAL CHARACTERISTICS (continued)
5.0-V BODE-PLOT GAIN AND PHASE
3.3-V BODE-PLOT GAIN AND PHASE
vs
vs
FREQUENCY
FREQUENCY
80
60
40
20
0
80
60
40
20
0
180
135
180
135
Phase
Phase
Gain
90
45
0
90
45
0
Gain
-20
-40
-45
-90
-20
-40
-45
-90
VIN = 12 V
-60
-80
-135
-180
VIN = 12 V
-60
-80
-135
-180
Current mode
Current mode
100
1K
10K
100K
1M
100
1K
10K
100K
1M
f - Frequency - kHz
f - Frequency - kHz
Figure 33.
Figure 34.
IMON1 VOLTAGE
vs
OUTPUT CURRENT
IMON1 VOLTAGE
vs
OUTPUT CURRENT
3
3
2.5
2
V
= ULV
V
= LV
OCL
OCL
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
0
1
2
3
IOUT1 - 5V Output Current - A
4
5
0
2
4
6
8
10
IOUT1 - 5 V Output Current - A
Figure 35.
Figure 36.
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TYPICAL CHARACTERISTICS (continued)
5.0-V SWITCH-OVER WAVEFORMS
VIN = 12 V
VREG5 (100mV/div)
VO1 (100mV/div)
t - Time - 2 ms/div
Figure 37.
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DETAILED DESCRIPTION
ENABLE AND SOFT START
When EN is Low, the TPS51221 is in the shutdown state; only the 3.3-V LDO stays alive, and consumes 7µA
(typically). When EN becomes High, the TPS51221 is in the standby state. The 2-V reference and the 5-V LDO
become enabled, consume about 80 µA with no load condition, and are ready to turn on SMPS channels. Each
SMPS channel is turned on when ENx becomes High. After ENx is set to high, the TPS51221 begins softstart,
and ramps up the output voltage from zero to the target voltage with 0.96 ms. However, if a slower soft-start is
required, an external capacitor can be tied from the ENx pin to GND. In this case, the TPS51221 charges the
external capacitor with the integrated 2-µA current source. An approximate external soft-start time would be
tEX-SS=CEX / IEN12, it means the time from ENx=1V to ENx=2V. Recommend capacitance is more than 2.2nF.
1) Internal
Soft-start
EN1
Vout1
200 ms
960 ms
EN1<2V
EN1>1V
2) External
Soft-start
EN1
External
Soft-start
time
Vout1
Figure 38. Enable and Soft-Start Timing
Table 1. Enable Logic States
EN
GND
Hi
EN1
EN2
VREG3
ON
VREF2
Off
VREG5
Off
CH1
Off
CH2
Off
Don’t Care
Don’t Care
Lo
Hi
Lo
Hi
Lo
Lo
Hi
Hi
ON
ON
ON
Off
Off
Hi
ON
ON
ON
ON
Off
Off
Hi
ON
ON
ON
ON
ON
Hi
ON
ON
ON
ON
PRE-BIASED START-UP
The TPS51221 supports a pre-biased start up by preventing negative inductor current during soft-start when the
output capacitor holds some charge. The initial DRHV signal waits until the voltage feedback signal becomes
greater than the internal reference ramping up by the soft-start function. After that, the start-up occurs the same
way the the soft-start condition fully discharges, regardless of the SKIPSELx selection.
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3.3 V, 10 mA LDO (VREG3)
A 3.3-V, 10mA, linear regulator is integrated in the TPS51221. This LDO services some of the analog supply rail
for the IC and provides a handy standby supply for 3.3-V Always On voltage in the notebook system. Apply a
2.2-µF (at least 1-µF), high quality X5R or X7R ceramic capacitor from VREG3 to (signal) GND, adjacent to the
IC.
2.0-V, 100 µA Sink/ Source Reference (VREF2)
This voltage is used for the reference of the loop compensation network. Apply a 0.22-µF (at least 0.1-µF), high
quality X5R or X7R ceramic capacitor from VREF2 to (signal) GND, adjacent to the IC.
5.0-V, 100 mA LDO (VREG5)
A 5.0-V, 100-mA linear regulator is integrated in the TPS51221. This LDO services the main analog supply rail
for the IC and provides current for gate drivers until switch-over function becomes enabled. Apply 10-µF (at least
4.7-µF), high quality X5R or X7R ceramic capacitor from VREG5 to (power) GND, adjacent to the IC.
VREG5 SWITCHOVER
When EN1 is high, PGOOD1 indicates GOOD and more than 4.7-V voltage is applied to V5SW, the internal
5V-LDO is shut off and the VREG5 is shorted to V5SW by an internal MOSFET after A 7.7ms delay. When the
V5SW voltage becomes lower than 4.5 V, EN1 becomes low, or PGOOD1 indicates BAD, the internal switch is
turned off and the internal 5V-LDO resumes immediately.
BASIC PWM OPERATIONS
The main control loop of the SMPS is designed as a fixed-frequency, peak current mode pulse width modulation
(PWM) controller. It can achieve stable operation in any type of capacitors, including low ESR capacitor(s) such
as ceramic or specialty polymer capacitors.
The TPS51221 SMPS uses the output voltage information and the inductor current information to regulate the
output voltage. The output voltage information is sensed by VFBx pin. The signal is compared with the internal
1-V reference and the voltage difference is amplified by a transconductance amplifier (VFB-AMP). The inductor
current information is sensed by CSPx and CSNx pins. The voltage difference is amplified by another
transconductance amplifier (CS-AMP). The output of the VFB-AMP indicates the target peak inductor current. If
the output voltage goes down, the TPS51221 increases the target inductor current to raise the output voltage. On
the other hand, if the output voltage goes up the TPS51221 decreases the target inductor current to reduce the
output voltage.
At the beginning of each clock cycle, the high-side MOSFET is turned on, or becomes ON state. The high-side
MOSFET is turned off, or becomes OFF state, after the inductor current reaches the target value—which is
determined by the combination value of the output of the VFB-AMP and a ramp compensation signal. The ramp
compensation signal is used to prevent sub-harmonic oscillation of the inductor current control loop. The
high-side MOSFET is turned on again at the next clock cycle. By repeating the operation in this manner, the
controller regulates the output voltage. The synchronous low-side or the rectifying MOSFET is turned on each
OFF state to keep the conduction loss minimum.
PWM FREQUENCY CONTROL
TPS51221 has a fixed frequency control scheme with 180° phase shift. The switching can be determined by an
external resistor which is connected between RF pin and GND, and can be calculated using Equation 1:
1 105
RF[kW]
ƒ
[kHz] +
sw
(1)
The TPS51221 can also synchronize to the external clock, of more than 2.5-V amplitude, by applying the signal
to RF pin. The set timing of the channel-1 initiates at the raising edge (1.3V typ) of the clock, and channel-2
initiates at the falling edge (1.1V typ). Therefore, the 50% duty signal makes both channels 180° phase shift.
When the external clock synchronization is selected, the following conditions are required.
•
•
Remove RF resistor
Add clock signal before EN1 or EN2 turning on
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The TPS51221 does NOT support switching frequency change on-the-fly. (neither from the switching frequency
set by the RF resistor to the external clock, nor vice versa)
1000
900
800
700
600
500
400
300
200
100
0
100
200
300
400
500
RF - Resistance - kW
Figure 39. Switching Frequency vs RF
LIGHT LOAD OPERATION
The TPS51221 automatically reduces switching frequency at light load condition to maintain high efficiency if
Auto Skip or OOA mode is selected by SKIPSELx. This reduction of frequency is achieved by skipping pulses.
As the output current decreases from heavy load condition, the inductor current is also reduced and eventually
comes to the point that its peak touches a predetermined current, ILL(PEAK), which indicates the boundary between
heavy-load and light-load conditions. Once the top MOSFET is turned on, the TPS51221 does not allow turning it
off until it touches ILL(PEAK). This eventually causes an over-voltage condition to the output, and pulse skipping.
From the next pulse after zero-crossing is detected, ILL(PEAK) is limited by the ramp-down signal which starts from
25% of the over-current limit setting (IOCL(PEAK): see the CURRENT PROTECTION section) toward 5% of
IOCL(PEAK), over one switching cycle to prevent causing a large ripple. The transition load point to the light load
operation ILL(DC) can be calculated as follows;
I
LL(DC) + ILL(PEAK) * 0.5 IIND(RIPPLE)
(2)
ǒ
V
Ǔ
* V
V
IN
OUT OUT
1
I
+
IND(RIPPLE)
L ƒ
V
IN
SW
(3)
where fSW is the PWM switching frequency as determined by RF resistor setting or external clock. Switching
frequency versus output current in the light load condition is a function of L, f, Vin and Vout; but it decreases
almost proportional to the output current from the ILL(DC) given above however, as the switching is synchronized
with clock. Due to the synchronization, the switching waveform in boundary load condition (close to ILL(DC)),
appears as a sub-harmonic oscillation; however, it is the intended operation.
If SKIPSELx is tied to GND, TPS51221 works at the constant frequency of fSW, regardless of its load current.
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Inductor
Current
I
LL(PEAK)
I
I
IND(RIPPLE)
LL(DC)
0
Time
Figure 40. Boundary Between Pulse Skipping and CCM
V
Ramp + ǒ0.25 * 0.2 OUTǓ
ILL(PEAK)
IOCL(PEAK)
VIN
(4)
Inductor
Current
25% of I
OCL(PEAK)
I
Ramp Signal
LL(PEAK)
I
LL(PEAK)
5% of I
OCL(PEAK)
0
Time
Ton
1/f
SW
Figure 41. Inductor Current Limit at Pulse Skipping
Table 2. Skip Mode Selection
SKIPSELx
GND
VREF2
VREG3
VREG5
OOA Skip (max 7 skips,
for <400 kHz)
OOA Skip (max 15 skips, for equal
to or greater than 400kHz)
Operating Mode
Continuous Conduction
Auto Skip
OUT OF AUDIO SKIP OPERATION
Out-Of-Audio™ (OOA) light load mode is a unique control feature that keeps the switching frequency above
acoustic audible frequencies toward virtually no-load condition while maintaining best-of-the-art high conversion
efficiency. When OOA is selected, the switching frequency is kept higher than audible frequency range in any
load condition. The TPS51221 automatically reduces the switching frequency at light-load conditions. OOA
control circuit monitors the states of both MOSFETs and forces an ON state if a predetermined number of pulses
are skipped. This means that the high-side MOSFET is turned on before the output voltage declines down to the
target value, so that eventually an over-voltage condition is caused. The OOA control circuit detects this
over-voltage condition and begins modulating the skip-mode on-time to keep the output voltage.
The TPS51221 supports a wide switching frequency range; therefore, OOA skip mode has two selections; see
Table 2. When 300 kHz switching frequency is selected, max 7 skip (SKIPSEL=3.3V) makes lowest frequency at
37.5kHz. If max 15 skip is chosen, it becomes 18.8kHz; hence, max 7 skip is suitable for less than 400 kHz, and
max 15 skip is for equal to or greater than 400 kHz.
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99% DUTY CYCLE OPERATION
In a low-dropout condition such as 5-V input to 5-V output, the basic control loop attempts to maintain 100% of
the high-side MOSFET ON. However, with the N-channel MOSFET used for the top switch, it is not possible to
use the 100% on-cycle to charge the boot strap capacitor. When high duty is required, the TPS51221 extends
the ON period (by skipping a maximum of three clock cycles and reducing the switching frequency to 25% of the
steady state value) and asserts the OFF state after extended ON.
HIGH-SIDE DRIVER
The high-side driver is designed to drive high current, low rDS(on) N-channel MOSFET(s). The drive capability is
represented by its internal resistance, which is 1.7 Ω for VBSTx to DRVHx, and 1.0 Ω for DRVHx to SWx. When
configured as a floating driver, 5V bias voltage is delivered from VREG5 supply. The instantaneous drive current
is supplied by the flying capacitor between VBSTx and SWx pins. The average drive current is equal to the gate
charge at Vgs=5V times the switching frequency. This gate drive current, as well as the low-side gate drive
current times 5V, produces the driving power which needs to be dissipated from the TPS51221 package. A dead
time to prevent shoot-through is internally generated between high-side MOSFET off to low-side MOSFET on,
and low-side MOSFET off to high-side MOSFET on.
LOW-SIDE DRIVER
The low-side driver is designed to drive high current low RDS(on) N-channel MOSFET(s). The drive capability is
represented by its internal resistance, which is 1.3Ω for VREG5 to DRVLx, and 0.7 Ω for DRVLx to GND. The
5-V bias voltage is delivered from VREG5 supply. The instantaneous drive current is supplied by an input
capacitor connected between VREG5 and GND. The average drive current is also calculated by the gate charge
at Vgs=5V times switching frequency.
CURRENT SENSING SCHEME
In order to provide both good accuracy and cost effective solution, the TPS51221 supports external resistor
sensing and inductor DCR sensing. An RC network with high quality X5R or X7R ceramic capacitor should be
used to extract voltage drop across DCR. A value of 0.1µF is a good design start. CSPx and CSNx should be
connected to positive and negative terminal of the sensing device, respectively. The TPS51221 has an internal
current amplifier. The gain of the current amplifier, Gc, is selected by TRIP terminal. In any setting, the output
signal of the current amplifier becomes 100mV at the OCL setting point. This means that the current sensing
amplifier normalizes the current information signal based on the OCL setting. Attaching an RC network is
recommended even with a resistor sensing scheme to get accurate current sensing; see section EXTERNAL
PARTS SELECTION for detailed configurations.
CURRENT PROTECTION
The TPS51221 has cycle-by-cycle over-current limiting control. If the inductor current becomes larger than the
over-current trip level, TPS51221 turns off the high-side MOSFET, turns on the low-side MOSFET and waits for
the next clock cycle.
IOCL(PEAK) sets peak level of the inductor current. Thus, the DC load current at over-current threshold, IOCL(DC)
,
can be calculated as follows;
I
OCL(DC) + IOCL(PEAK) * 0.5 IIND(RIPPLE)
(5)
V
OCL
I
+
OCL(PEAK)
R
SENSE
(6)
where
•
•
where RSENSE is resistance of the current-sensing device
VOCL is the over-current trip threshold voltage, as determined by TRIP pin voltages (shown in Table 3)
Table 3. OCL Trip and Discharge Selection
TRIP
GND
VOCL-ULV (Ultra Low Voltage)
Enable Disable
VREF2
VREG3
VREG5
VOCL (OCL Trip voltage)
Discharge
VOCL-LV (Low Voltage)
Disable
Enable
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In an over-current condition, the current to the load exceeds the current to the output capacitor; thus, the output
voltage tends to fall down and ultimately crosses the under-voltage protection threshold, resulting in shutdown.
POWER GOOD
The TPS51221 has a power-good output for both switcher channels. The power-good function is activated after
softstart has finished. If the output voltage comes within ±5% of the target value, internal comparators detect
power-good state and the power-good signal becomes high after 1ms internal delay. If the output voltage goes
outside of ±10% of the target value, the power-good signal becomes low after 1.5µs internal delay. Voltage
applied should be less than 6V and the recommended pull-up resistance value is from 100kΩ to 1MΩ.
OUTPUT DISCHARGE CONTROL
The TPS51221 discharges output when ENx is low. The TPS51221 discharges outputs using an internal
MOSFET connected to CSNx and GND. The current capability of these MOSFETs is limited to discharge the
output capacitor slowly. If ENx becomes high during discharge, the MOSFETs are turning off, and some output
voltage remains. SMPS changes over to soft-start. PWM will begin after the target voltage overtakes the
remaining output voltage. This function can be disabled as shown in Table 3.
CURRENT MONITOR
The TPS51221 monitors the output current as the voltage difference between CSPx and CSNx terminal. The
transconductance amplifier (CS-AMP) amplifies this differential voltage 100 times when VOCL is set VOCL_ULV, 50
times when VOCL is set VOCL_LV, and sends out from IMON1 thermal. This function is only for the channel 1
output and adding an RC filter is recommended.
OVER/UNDER VOLTAGE PROTECTION
The TPS51221 monitors the output voltage to detect over- and under-voltage. When the output voltage becomes
15% higher than the target value, the OVP comparator output goes high, and the circuit latches the high-side
MOSFET driver OFF and the low-side MOSFET driver ON, and shuts off another channel.
When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes
high and an internal UVP delay counter begins counting. After 1ms, the TPS51221 latches OFF both high-side
and low-side MOSFETs, and shuts off another channel. This UVP function is enabled after soft start has
completed. The procedures for restarting from these protection states are:
(1) toggle EN,
(2) toggle EN1 and EN2 or
(3) once be hit UVLO
UVLO PROTECTION
TPS51221 has under-voltage lock out protection (UVLO) for VREG5, VREG3 and VREF2. When the voltage is
lower than UVLO threshold voltage, the TPS51221 shuts off each output as shown in Table 4. This is non-latch
protection.
Table 4. UVLO Protection
CH1/ CH2
VREG5
—
VREG3
On
VREF2
On
VREG5 UVLO
VREG3 UVLO
VREF2 UVLO
Off
Off
Off
Off
—
Off
Off
On
—
THERMAL SHUTDOWN
TPS51221 monitors the temperature of itself. If the temperature exceeds the threshold value TPS51221 shuts off
both SMPS, 5V-LDO and decreases VREG3 current limitation to 5 mA (typically). This is non-latch protection.
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APPLICATION INFORMATION
EXTERNAL PARTS SELECTION
A buck converter using TPS51221 consists of linear circuits and a switching modulator. Figure 42 shows basic
scheme.
Voltage divider
VIN
Switching Modulator
Ramp
comp.
R1
DRVH
Lx
VFB
+
Gmv
Rs
PWM
+
Control
logic
&
+
R2
+
DRVL
Driver
1.0V
ESR
Co
RL
COMP
VREF
Gmc
CSP
Rgv
Cc
Rgc
+
+
CSN
2.0V
Error Amplifier
Figure 42. Simplified Current Mode Functional Blocks
The external components can be selected by following manner.
1. Determine output voltage dividing resistors (R1 and R2: shown in Figure 42) using the next equation
R1 + ǒV
Ǔ
* 1.0 R2
OUT
(7)
2. Determine switching frequency. Higher frequency allows smaller output capacitances; however, efficiency
is degraded due to increase of switching loss. Frequency setting resistor for RF-pin can be calculated by;
1 105
ƒsw [kHz]
RF[kW] +
(8)
3. Choose the inductor. The inductance value should be determined to give the ripple current of
approximately 25% to 50% of maximum output current. Recommended ripple current rate is about 30% to
40% at the typical input voltage condition. The next equation uses 33%.
ǒ
Ǔ
V
IN(TYP) * VOUT VOUT
1
L +
0.33 IOUT(MAX) ƒ
VIN(TYP)
SW
(9)
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak
inductor current before saturation.
4. Determine the OCL trip voltage threshold, VOCL, and select the sensing resistor. The OCL trip voltage
threshold is determined by TRIP pin setting. Using a larger value improves the S/N ratio. Determine the
sensing resistor using next equation. IOCL(PEAK) should be approximately 1.5 × IOUT(MAX) to 1.7 × IOUT(MAX)
.
VOCL
IOCL(PEAK)
RSENSE
+
(10)
26
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5. Determine Rgv. Rgv should be determined from preferable droop compensation value and is given by the
next equation, based on the typical number of Gmv=500µS.
I
OUT(MAX)
1
Rgv + 0.1
V
OUT
I
Gmv Vdroop
OCL(PEAK)
(11)
IOUT(MAX)
VOUT[V]
Rgv[kW] + 200
IOCL(PEAK) Vdroop[mV]
(12)
6. Determine output capacitance Co to achieve stable operation using the next equation. The 0 dB frequency;
ƒo should be kept under 1/3 of the switching frequency.
Gmv Rgv ƒsw
5
1
ƒ0 + IOCL(PEAK)
t
p
3
VOUT
Co
(13)
Gmv Rgv
ƒsw
15
p
1
Co u
IOCL(PEAK)
VOUT
(14)
7. Calculate Cc. Purpose of this capacitance is to cancel zero caused by ESR of the output capacitor. When
using ceramic capacitor(s), there is no need for Cc. If a combination of different capacitors are used,
attaching an RC network circuit might be needed instead of single capacitance to cancel zeros and poles
caused by the output capacitors. In the case of a single capacitance, Cc is given in Equation 15.
ESR
Rgv
Cc + Co
(15)
8. Choose MOSFETs. Generally, the on resistance strongly affects efficiency at high load conditions as a
conduction loss. In case of low output voltage application, the duty ratio is not so high so that the on
resistance of high-side MOSFET does not greatly affect efficiency. However, switching speed (Tr and Tf)
affects efficiency as a switching loss. As for low-side MOSFET, usually switching loss is not a main portion of
the total loss.
RESISTOR CURRENT SENSING
For more accurate current sensing with an external resistor, the following technique is recommended. Adding RC
filtering to cancel the parasitic inductance of the resistor; this filter value can be calculated using Equation 16.
Lx
Rs
Cx Rx +
(16)
This equation means the time-constant of Cx and Rx should match the one of Lx (ESL) and Rs.
VIN
Ex-resistor
Lx(ESL)
Rs
DRVH
L
Control
logic
&
DRVL
Driver
Co
CSP
CSN
+
Cx
Rx
Figure 43. External Resistor Current Sensing
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INDUCTOR DCR CURRENT SENSING
To use an inductor DCR as current sensing resistor (Rs), the configuration needs to change, as shown in
Figure 44. However, the equation must be satisfied the same as the one using resistor sensing.
Inductor
Lx
Rs(DCR)
RNTC
Rx
Rc1
Rc2
Co
CSP
+
Cx
CSN
Figure 44. Inductor DCR Current Sensing
VIN
Inductor
DRVH
Lx
Rs(DCR)
Control
logic
&
DRVL
Driver
Co
Rx
CSP
+
Cx
Rc
CSN
Figure 45. Inductor DCR Current Sensing With Voltage Divider
The TPS51221 has a fixed VOCL point (60 mV or 30 mV). In order to adjust for DCR, a voltage divider can be
configured as shown in Figure 45.
For Rx, Rc and Cx can be determined as below, and over-current limitation value can be calculated as follows.
Lx
Rs
ǒ
Ǔ
Cx Rx ńń Rc +
(17)
Rx ) Rc
1
I
OCL(PEAK) + VOCL
Rs
Rc
(18)
Figure 50 shows the compensation technique for the temperature drifts of the inductor DCR value. This scheme
assumes the temperature rise at the thermistor (RNTC) is directly proportional to the temperature rise at the
inductor.
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Inductor
Lx
Rs(DCR)
RNTC
Rx
Rc1
Rc2
Co
CSP
+
Cx
CSN
Figure 46. Inductor DCR Current Sensing With Temperature Compensation
LAYOUT CONSIDERATIONS
Certain points must be considered before starting a PCB layout work using the TPS51221.
Placement
•
•
•
•
•
Place RC filters for CSP1 and CSP2 close to the IC pins.
Place bypass capacitors for VREG5, VREG3 and VREF2 close to the IC pins.
Place frequency-setting resistor close to the IC pin.
Place the compensation circuits for COMP1 and COMP2 close to the IC pins.
Place the voltage setting resistors close to the IC pins.
Routing (sensitive analog portion)
• Use separate traces for: (see Figure 47)
–
–
–
Output voltage sensing from current sensing (negative-side)
Output voltage sensing from V5SW input (when Vout=5V)
Current sensing (positive-side) from switch-node
V5SW
R1
VFB
R2
H-FET
Inductor
Vout
SW
Cout
L-FET
R
CSP
C
CSN
Figure 47. Sensing Trace Routings
•
Use Kelvin sensing traces from the solder pads of the current sensing device (inductor or resistor) to current
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sensing comparator inputs (CSPx and CSNx). (see Figure 48)
Current sensing
Device
RC network
next to IC
Figure 48. Current Sensing Traces
•
•
•
Use small copper space for VFBx, in other words short and narrow traces to avoid noise coupling
Connect VFB resistor trace to the positive node of the output capacitor.
Use signal GND for VREF2 and VREG3 capacitors, RF and VFB resistors and the other sensitive analog
components. Placing signal GND island (underneath the IC and fully covered peripheral components) on the
internal layer for shielding purpose is recommended. (See Figure 49)
•
Use thermal land for PowerPAD™. Five or more vias with 0.33-mm (13-mils) diameter connected from the
thermal land to the internal GND plane should be used to help dissipation. Do NOT connect GND-pin to this
thermal land on the surface layer, underneath the package.
Routing (power portion)
•
•
•
•
Use wider/ shorter traces of DRVL for low-side gate drivers to reduce stray inductance.
Use the parallel traces of SW and DRVH for high-side MOSFET gate drive and keep them away from DRVL.
Connect SW trace to source terminal of the high-side MOSFET.
Use power GND for VREG5, VIN and Vout capacitors and low-side MOSFETs. Power GND and signal GND
should be connected near the IC GND terminal. (See Figure 49)
TPS51221
0W resistor
GND
#28
GND-pin
To inner
Power-GND
layer
To inner
Signal-GND
island
Inner Signal-GND island
Figure 49. GND Layout Example
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APPLICATION CIRCUITS
VREG5
VBAT
VBAT
5V/100 mA
Q11
C22
2x10 mF
C12
2x10 mF
Q21
C01
10 mF
C14
C24
0.1 mF
L1
L2
0.1 mF
4.0 mH
4.0 mH
PGND
PGND
VO2
3.3V/6A
VO1
5.0V/6A
Q12
PGND
GND
PGND
Q22
C21
2x220 mF
C11
2x120 mF
32
31
30
29
28
27
26
25
PGND
PGND
PGND
PGND
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
DRVH1
V5SW
DRVH2
VIN
VBAT
VO1
R01
330 kW
VREG3
3.3V/10 mA
RF
VREG3
EN2
C03
1 mF
GND
EN1
EN2
EN1
TPS51221RTV
(QFN32)
PGOOD1
PGOOD2
PGOOD1
SKIPSEL1
PGOOD2
GND
SKIPSEL1
SKIPSEL2
SKIPSEL2
R14
6.8 kW
R24
6.8 kW
PowerPAD
CSP1
CSN1
CSP2
CSN2
R15
56 kW
R25
56 kW
C23
C13
0.1 mF
0.1 mF
EN
9
10
11
12
13
14
15
16
GND
R02
10 kW
VREG5
VREF2
R21
IMON1
62 kW
C02
VO1
VO2
C04
0.1 mF
0.22 mF
R13
10 kW
R11
120 kW
C25
220 pF
R23
10 kW
R22
27 kW
R12
30 kW
C15
100 pF
VREF2
VREF2
GND
GND
GND
GND
Figure 50. Current Mode, DCR Sensing, 5.0V/5A, 3.3V/5A, 300-kHz
Table 5. Current Mode, DCR Sensing, 5.0V/5A, 3.3V/5A, 300-kHz
SYMBOL
C11
SPECIFICATION
MANUFACTURER
Panasonic
Murata
PART NUMBER
2 × 120 µF/ 6.3 V/15-mΩ
2 × 10 µF/ 25 V
EEFCX0J121R
C12
GRM32DR71E106K
EEFCX0G221R
GRM32DR71E106K
CEP125-4R0MC-H
CEP125-4R0MC-H
IRF7821
C21
2 × 220 µF/ 4.0 V/15-mΩ
2 × 10 µF/ 25 V
Panasonic
Murata
C22
L1
4.0 µH, 10.3 A, 6.6-mΩ
4.0 µH, 10.3A, 6.6-mΩ
30-V, 13.6-A, 9.5-mΩ
30-V, 13.8-A, 5.8-mΩ
Sumida
Sumida
IR
L2
Q11, Q21
Q12, Q22
IR
IRF8113
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VREG5
VBAT
VBAT
5V/100 mA
Q11
C22
2x10 mF
C12
2x10 mF
Q21
C01
10 mF
C14
C24
0.1 mF
L1
L2
3.3 mH
0.1 mF
3.3 mH
R15
6 mW
R25
PGND
PGND
6 mW
VO2
3.3V/6A
VO1
5V/6A
Q12
PGND
GND
PGND
Q22
C21
2x220 mF
C11
2x220 mF
32
31
30
29
28
27
26
25
PGND
PGND
PGND
PGND
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
DRVH1
V5SW
DRVH2
VIN
VBAT
VO1
R01
270 kW
VREG3
3.3V/10mA
RF
VREG3
EN2
C03
1 mF
GND
EN1
EN2
EN1
TPS51221RTV
(QFN32)
PGOOD1
PGOOD2
PGOOD1
SKIPSEL1
PGOOD2
GND
SKIPSEL1
SKIPSEL2
SKIPSEL2
PowerPAD
CSP1
CSN1
CSP2
CSN2
R14
R24
1.2 W
C13
0.1 mF
C23
1.2 W
0.1 mF
EN
9
10
11
12
13
14
15
16
GND
R02
10 kW
VREF2
R21
IMON1
62 kW
C02
GND
VO2
VO1
C04
0.1 mF
0.22 mF
R13
10 kW
R11
C25
220 pF
R23
10 kW
R22
27 kW
R12
30 kW
C15
220 pF
120 kW
VREF2
VREF2
GND
GND
GND
GND
Figure 51. Current Mode, Ex-Resistor Sensing, 5.0V/5A, 3.3V/5A, 370-kHz
Table 6. Current Mode, DCR sensing, 5.0V/5A, 3.3V/5A, 370-kHz
SYMBOL
C11
SPECIFICATION
MANUFACTURER
Panasonic
Murata
PART NUMBER
2 x 220 µF/ 6.3 V/12-mΩ
2 x 10 µF/ 25 V
EEFUE0J221R
C12
GRM32DR71E106K
EEFUE0G221R
GRM32DR71E106K
FDA1055-3R3M
FDA1055-3R3M
IRF7821
C21
2 x 220 µF/ 4.0 V/12-mΩ
2 x 10 µF/ 25 V
Panasonic
Murata
C22
L1
3.3 µH, 10.3 A, 5.9-mΩ
3.3 µH, 10.3 A, 5.9-mΩ
30-V, 13.6-A, 9.5-mΩ
30-V, 13.8-A, 5.8-mΩ
TOKO
L2
TOKO
Q11, Q21
Q12, Q22
IR
IR
IRF8113
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
TPS51221RTVR
TPS51221RTVT
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
WQFN
WQFN
RTV
32
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS
51221
ACTIVE
RTV
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
51221
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS51221RTVR
TPS51221RTVT
WQFN
WQFN
RTV
RTV
32
32
3000
250
330.0
180.0
12.4
12.4
5.3
5.3
5.3
5.3
1.5
1.5
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Aug-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS51221RTVR
TPS51221RTVT
WQFN
WQFN
RTV
RTV
32
32
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
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