TPS5211PWP [TI]
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC REGULATOR CONTROLLER; 高频可编程迟滞DC控制器型号: | TPS5211PWP |
厂家: | TEXAS INSTRUMENTS |
描述: | HIGH FREQUENCY PROGRAMMABLE HYSTERETIC REGULATOR CONTROLLER |
文件: | 总32页 (文件大小:469K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
PWP PACKAGE
(TOP VIEW)
700 KHz Operation
1.25 MHz Operation With External Driver
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1.5% Reference Over Full Operating
Temperature Range
IOUT
DROOP
OCP
VHYST
VREFB
VSENSE
ANAGND
SLOWST
BIAS
LODRV
LOHIB
DRVGND
LOWDR
DRV
PWRGD
VID0
VID1
VID2
VID3
2
3
Synchronous Rectifier Driver for Greater
Than 90% Efficiency
4
5
Programmable Reference Voltage Range of
1.3 V to 3.5 V
6
VID4
7
INHIBIT
IOUTLO
LOSENSE
HISENSE
BOOTLO
HIGHDR
BOOT
8
User–Selectable Hysteretic Type Control
9
Droop Compensation for Improved Load
Transient Regulation
10
11
12
13
14
Adjustable Overcurrent Protection
Programmable Softstart
V
CC
Overvoltage Protection
Active Deadtime Control
Power Good Output
Internal Bootstrap Schottky Diode
Low Supply Current . . . 3-mA Typ
Reduced System Component Count and
Size
description
The TPS5211 is a hysteretic regulator controller which provides an accurate, programmable supply voltage to
microprocessors. An internal 5-bit DAC is used to program the reference voltage to within a range of 1.3 V to
3.5 V. The output voltage can be set to equal the reference voltage or some multiple of the reference voltage.
A hysteretic controller with user-selectable hysteresis and programmable droop compensation is used to
dramatically reduce overshoot and undershoot caused by load transients. Propagation delay from the
comparator inputs to the output drivers is less than 250 ns. Overcurrent shutdown and crossover protection for
the output drivers combine to eliminate destructive faults in the output FETs. The softstart current source is
proportional to the reference voltage, thereby eliminating variation of the softstart timing when changes are
made to the output voltage. PWRGD monitors the output voltage and pulls the open-collector output low when
the output drops 7% below the nominal output voltage. An overvoltage circuit disables the output drivers if the
output voltage rises 15% above the nominal value. The inhibit pin can be used to control power sequencing.
Inhibit and undervoltage lockout assures the 12-V supply voltage and system supply voltage (5 V or 3.3 V) is
within proper operating limits before the controller starts. Single-supply (12 V) operation is easily accomplished
using a low-current divider for the required 5-V signals. The output driver circuits include 2-A drivers with internal
8-V gate-voltage regulators. The high-side driver can be configured either as a ground-referenced driver or as
a floating bootstrap driver. The TPS5211 is available in a 28-pin TSSOP PowerPAD package. It operates over
a junction temperature range of 0°C to 125°C.
AVAILABLE OPTIONS
PACKAGE
T
J
TSSOP
(PWP)
0°C to 125°C
TPS5211PWPR
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V
ANAGND
7
PWRGD
28
LOSENSE
20
IOUTLO HISENSE
CC
VID0
VID1
VID2
VID3
VID4
15
21
19
11111
Decode
NOCPU
UVLO
2 V
+
1
22
3
IOUT
INHIBIT
OCP
–
2x
Shutdown
10 V
S
R
Q
V
CC
Fault
Rising
Edge
Delay
Deglitch
+
100 mV
HIGHDR
Deglitch
V
PGD
HIGHIN
0.93 V
ref
V
OVP
1.15 V
V
CC
ref
VSENSE
Analog Bias
Analog
Bias
PREREG
DRV REG
8
9
SLOWST
Bandgap
BIAS
DRV
I
VREFB
14
Slowstart
Comp
5
–
+
+
–
Shutdown
VID
MUX
and
16
17
CM Filters
BOOT
HIGHDR
VREF
+
Σ
+
–
200 kΩ
18
–
Decoder
Hysteresis
Comp
BOOTLO
200 kΩ
+ –
VREFB
Shutdown
Hysteresis
Setting
13
12
I
LOWDR
DRVGND
27 26
25
24 23
5
2
4
6
11
10
LODRV
VID0 VID1 VID2 VID3 VID4 VREFB DROOP VHYST VSENSE
LOHIB
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
7
ANAGND
BIAS
Analog ground
9
O
I
Analog BIAS pin. A 1-µF ceramic capacitor should be connected from BIAS to ANAGND.
Bootstrap. Connect a 1-µF low-ESR capacitor from BOOT to BOOTLO.
BOOT
16
18
BOOTLO
O
Bootstrap low. Connect BOOTLO to the junction of the high-side and low-side FETs for floating drive
configuration. Connect BOOTLO to PGND for ground reference drive configuration.
DROOP
2
I
Droop voltage. Voltage input used to set the amount of output-voltage set-point droop as a function of load
current. The amount of droop compensation is set with a resistor divider between IOUT and ANAGND.
DRV
14
12
17
19
O
Drive regulator for the FET drivers. A 1-µF ceramic capacitor should be connected from DRV to DRVGND.
Drive ground. Ground for FET drivers. Connect to FET PWRGND.
DRVGND
HIGHDR
HISENSE
O
I
High drive. Output drive to high-side power switching FETs
High current sense. For current sensing across high-side FETs, connect to the drain of the high-side FETs; for
optional resistor sensing scheme, connect to power supply side of current-sense resistor placed in series with
high-side FET drain.
INHIBIT
IOUT
22
1
I
Disables the drive signals to the MOSFET drivers. Can also serve as UVLO for system logic supply (either 3.3 V
or 5 V).
O
Current out. Output voltage on this pin is proportional to the load current as measured across the Rds(on) of the
high-side FETs. The voltage on this pin equals 2×Rds(on)×IOUT. In applications requiring very accurate
current sensing, a sense resistor should be connected between the input supply and the drain of the high-side
FETs.
IOUTLO
21
O
Current sense low output. This is the voltage on the LOSENSE pin when the high-side FETs are on. A ceramic
capacitor should be connected from IOUTLO to HISENSE to hold the sensed voltage while the high-side FETs
are off. Capacitance range should be between 0.033 µF and 0.1 µF.
LODRV
LOHIB
10
11
I
I
Low drive enable. Normally tied to 5 V. To activate the low-side FETs as a crowbar, pull LODRV low.
Low side inhibit. Connect to the junction of the high and low side FETs to control the anti-cross-conduction and
eliminate shoot-through current. Disabled when configured in crowbar mode.
LOSENSE
20
I
Low current sense. For current sensing across high-side FETs, connect to the source of the high-side FETs; for
optional resistor sensing scheme, connect to high-side FET drain side of current-sense resistor placed in series
with high-side FET drain.
LOWDR
OCP
13
3
O
I
Low drive. Output drive to synchronous rectifier FETs
Over current protection. Current limit trip point is set with a resistor divider between IOUT and ANAGND.
PWRGD
28
O
Power good. Power good signal goes high when output voltage is within 7% of voltage set by VID pins.
Open-drain output.
SLOWST
8
O
I
Slowstart (soft start). A capacitor from SLOWST to ANAGND sets the slowstart time.
Slowstart current = I
/5
VREFB
V
15
4
12-V supply. A 1-µF ceramic capacitor should be connected from V
CC
to DRVGND.
to ANAGND.
CC
VHYST
HYSTERESIS set pin. The hysteresis is set with a resistor divider from V
REFB
The hysteresis window = 2 × (V
Voltage identification input 0
Voltage identification input 1
Voltage identification input 2
Voltage identification input 3
– V
)
REFB
HYST
VID0
VID1
VID2
VID3
VID4
27
26
25
24
23
I
I
I
I
I
Voltage Identification input 4. Digital inputs that set the output voltage of the converter. The code pattern for
settingthe output voltage is located in Table 1. Internally pulled up to 5 V with a resistor divider biased from V
.
CC
VREFB
5
6
O
I
Buffered reference voltage from VID network
VSENSE
Voltage sense input. To be connected to converter output voltage bus to sense and control output voltage. It is
recommended an RC low pass filter be connected at this pin to filter noise.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
detailed description
V
REF
The reference/voltage identification (VID) section consists of a temperature-compensated bandgap reference
and a 5-bit voltage selection network. The 5 VID terminals are inputs to the VID selection network and are
TTL-compatible inputs internally pulled up to 5 V by a resistor divider connected to V . The VID codes conform
CC
to the Intel VRM 8.3 DC-DC Converter Specification for voltage settings between 1.8 V and 3.5 V, and they are
decrementedby50mV,downto1.3V,forthelowerVIDsettings.VoltageshigherthanV
usinganexternaldivider. RefertoTable1fortheVIDcodesettings. TheoutputvoltageoftheVIDnetwork, V
canbeimplemented
REF
,
REF
iswithin±1.5%ofthenominalsettingovertheVIDrangeof1.3 Vto2.5V, includingajunctiontemperaturerange
of 5°C to +125°C, and a V supply voltage range of 11.4 V to 12.6 V. The output of the reference/VID network
CC
is indirectly brought out through a buffer to the V
pin. The voltage on this pin will be within 5mV of V
.
REFB
REF
It is not recommended to drive loads with V
because the current drawn from V
, other than setting the hysteresis of the hysteretic comparator,
sets the charging current for the slowstart capacitor. Refer to the
REFB
REFB
slowstart section for additional information.
hysteretic comparator
The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is
set by 2 external resistors and is centered on V . The 2 external resistors form a resistor divider from V
REF
REFB
to ANAGND, with the output voltage connecting to the VHYST pin. The hysteresis of the comparator will be
equal to twice the voltage difference between the VREFB and VHYST pins. The propagation delay from the
comparator inputs to the driver outputs is 250 ns (maximum). The maximum hysteresis setting is 60 mV.
low-side driver
The low-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
2 A, source and sink. The bias to the low-side driver is internally connected to the DRV regulator.
high-side driver
The high-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
2 A, source and sink. The high-side driver can be configured either as a ground-referenced driver or as a floating
bootstrap driver. When configured as a floating driver, the bias voltage to the driver is developed from the DRV
regulator. The internal bootstrap diode, connected between the DRV and BOOT pins, is a Schottky for improved
drive efficiency. The maximum voltage that can be applied between BOOT and DRVGND is 30 V. The driver
can be referenced to ground by connecting BOOTLO to DRVGND, and connecting BOOT to eitherDRV or V
.
CC
The rms current through the drivers output should not exceed 110 mA. Refer to the application information
section to determine how to calculate an operating frequency to meet this requirement.
deadtime control
Deadtime control prevents shoot-through current from flowing through the main power FETs during switching
transitions by actively controlling the turnon times of the MOSFET drivers. The high-side driver is not allowed
to turn on until the gate-drive voltage to the low-side FETs is below 2 V; the low-side driver is not allowed to turn
on until the voltage at the junction of the high-side and low-side FETs (Vphase) is below 2 V.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
detailed description (continued)
current sensing
Current sensing is achieved by sampling and holding the voltage across the high-side power FETs while the
high-side FETs are on. The sampling network consists of an internal 60-Ω switch and an external ceramic hold
capacitor. Recommended value of the hold capacitor is between 0.033 µF and 0.1 µF. Internal logic controls
the turnon and turnoff of the sample/hold switch such that the switch does not turn on until the Vphase voltage
transitions high, and the switch turns off when the input to the high-side driver goes low. The sampling will occur
only when the high-side FETs are conducting current. The voltage on the IOUT pin equals 2 times the sensed
high-side voltage. In applications where a higher accuracy in current sensing is required, a sense resistor can
be placed in series with the high-side FETs, and the voltage across the sense resistor can be sampled by the
current sensing circuit.
droop compensation
The droop compensation network reduces the load transient overshoot/undershoot on V , relative to V
. V
O
O
REF
is programmed to a voltage greater than V
by an external resistor divider from V to VSENSE to reduce the
REF
O
undershoot on V during a low-to-high load transient. The overshoot during a high-to-low load transient is
O
reduced by subtracting the voltage on DROOP from V
resistor divider, and connected to DROOP.
. The voltage on IOUT is divided with an external
REF
inhibit
INHIBIT is a TTL-compatible digital input used to enable the controller. When INHIBIT is low, the output drivers
are low and the slowstart capacitor is discharged. When INHIBIT goes high, the short across the slowstart
capacitor is released and normal converter operation begins. When the system-logic supply is connected to
INHIBIT, it also controls power sequencing by locking out controller operation until the system-logic supply
exceeds the input threshold voltage of the inhibit circuit. The 12-V supply and the system logic supply (either
5 V or 3.3 V) must be above UVLO thresholds before the controller is allowed to start up. The start threshold
is 2.1 V and the hysteresis is 100 mV for the INHIBIT comparator.
V
undervoltage lockout (UVLO)
CC
The undervoltage lockout circuit disables the controller while the V
supply is below the 10-V start threshold
CC
during power up. When the controller is disabled, the output drivers will be low and the slowstart capacitor is
discharged. When V exceeds the start threshold, the short across the slowstart capacitor is released and
CC
normal converter operation begins. There is a 2-V hysteresis in the undervoltage lockout circuit for noise
immunity.
slowstart
The slowstart circuit controls the rate at which V powers up. A capacitor is connected between SLOWST and
O
ANAGND and is charged by an internal current source. The current source is proportional to the reference
voltage, so that the charging rate of C
is proportional to the reference voltage. By making the charging
SLOWST
currentproportionaltoV
, thepower-uptimeforV willbeindependentofV
. Thus, C
canremain
REF
O
REF
SLOWST
the same value for all VID settings. The slowstart charging current is determined by the following equation:
I
= I(VREFB) / 5 (amps)
slowstart
Where I(VREFB) is the current flowing out of VREFB.
It is recommended that no additional loads be connected to VREFB, other than the resistor divider for setting
thehysteresisvoltage. ThemaximumcurrentthatcanbesourcedbytheVREFBcircuitis500 µA. Theequation
for setting the slowstart time is:
t
= 5 × C
× R
(seconds)
SLOWST
SLOWST
VREFB
Where R
is the total external resistance from V
to ANAGND.
REFB
VREFB
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
detailed description (continued)
power good
The power-good circuit monitors for an undervoltage condition on V . If V is7%belowV , thenthePWRGD
REF
O
O
pin is pulled low. PWRGD is an open-drain output.
overvoltage protection
The overvoltage protection (OVP) circuit monitors V for an overvoltage condition. If V is 15% above V ,
REF
O
O
then a fault latch is set and both output drivers are turned off. The latch will remain set until V
goes below the
CC
undervoltage lockout value. A 3-µs deglitch timer is included for noise immunity. Refer to the LODRV section
for information on how to protect the microprocessor against overvoltages due to a shorted fault across the
high-side power FET.
overcurrent protection
The overcurrent protection (OCP) circuit monitors the current through the high-side FET. The overcurrent
threshold is adjustable with an external resistor divider between IOUT and ANAGND, with the divider voltage
connected to the OCP pin. If the voltage on OCP exceeds 100 mV, then a fault latch is set and the output drivers
are turned off. The latch will remain set until V
goes below the undervoltage lockout value. A 3-µs deglitch
CC
timer is included for noise immunity. The OCP circuit is also designed to protect the high-side power FET against
a short-to-ground fault on the terminal common to both power FETs.
drive regulator
The drive regulator provides drive voltage to the output drivers. The minimum drive voltage is 7 V. The minimum
short circuit current is 100 mA. Connect a 1-µF ceramic capacitor from DRV to DRVGND.
LODRV
TheLODRVcircuitisdesignedtoprotectthemicroprocessoragainstovervoltagesthatcanoccurifthehigh-side
power FETs become shorted. External components to sense an overvoltage condition are required to use this
feature. When an overvoltage fault occurs, the low-side FETs are used as a crowbar. LODRV is pulled low and
the low-side FET will be turned on, overriding all control signals inside the TPS5211 controller. The crowbar
action will short the input supply to ground through the faulted high-side FETs and the low-side FETs. A fuse
in series with V should be added to disconnect the short-circuit.
in
Table 1. Voltage Identification Codes
VID TERMINALS
(0 = GND, 1 = floating or pull-up to 5 V)
V
REF
VID4
0
VID3
1
VID2
1
VID1
1
VID0
1
(Vdc)
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
0
1
1
1
0
0
1
1
0
1
0
1
1
0
0
0
1
0
1
1
0
1
0
1
0
0
1
0
0
1
0
1
0
0
0
0
0
1
1
1
0
0
1
1
0
0
0
1
0
1
0
0
1
0
0
0
0
0
1
1
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
Table 1. Voltage Identification Codes (Continued)
VID TERMINALS
(0 = GND, 1 = floating or pull-up to 5 V)
V
REF
VID4
0
VID3
0
VID2
0
VID1
1
VID0
0
(Vdc)
1.95
2.00
2.05
No CPU
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
3.40
3.50
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
0
1
1
0
0
1
1
1
0
0
0
1
0
1
1
1
1
0
1
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
1
1
1
0
0
1
0
1
0
0
0
1
1
0
0
0
0
†
absolute maximum ratings over operating virtual junction temperature (unless otherwise noted)
Supply voltage range, V
(see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 14 V
CC
Input voltage range: BOOT to DRVGND (High-side Driver ON) . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 30 V
BOOT to HIGHDRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
BOOT to BOOTLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
INHIBIT, VIDx, LODRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7.3 V
PWRGD, OCP, DROOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
LOHIB, LOSENSE, IOUTLO, HISENSE . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 14 V
VSENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 5 V
Voltage difference between ANAGND and DRVGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V
Output current, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 mA
REFB
Short circuit duration, DRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 125°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Unless otherwise specified, all voltages are with respect to ANAGND.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T = 85°C
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
PWP
1150 mW
11.5 mW/°C
630 mW 460 mW
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
recommended operating conditions
MIN
11.4
0
MAX
13
UNIT
V
Supply voltage, V
CC
Input voltage, BOOT to DRVGND
28
V
Input voltage, BOOT to BOOTLO
0
13
V
Input voltage, INHIBIT, VIDx, LODRV, PWRGD, OCP, DROOP
Input voltage, LOHIB, LOSENSE, IOUTLO, HISENSE
Input voltage, VSENSE
0
6
V
0
13
V
0
4.5
±0.2
0.4
V
Voltage difference between ANAGND and DRVGND
0
V
†
Output current, V
0
mA
REFB
Not recommended to load V
†
other than to set hystersis since I
VREFB
sets slowstart time.
REFB
electrical characteristics over recommended operating virtual junction temperature range,
= 12 V, I = 0 A (unless otherwise noted)
V
CC
DRV
reference/voltage identification
PARAMETER
TEST CONDITIONS
= 11.4 to 12.6 V, 1.3 V ≤ V ≤ 3.5 V
REF
MIN
–0.015
TYP
MAX
UNIT
Cumulative reference accuracy
(see Note 2)
V
REF
V
CC
0.015
V/V
VIDx
VIDx
High-level input voltage
Low-level input voltage
Output voltage
2.25
V
V
1
I
= 50 µA
V
REF
–5mV
V
V +5mV
REF
V
VREFB
REF
2
V
REFB
Output regulation
10 µA ≤ I ≤ 500 µA
mV
kΩ
V
O
Input resistance
VIDx = 0 V
36
73
95
5
VIDx
Input pull-up voltage divider
4.8
4.9
NOTES: 2. Cumulative reference accuracy is the combined accuracy of the reference voltage and the input offset voltage of the hysteretic
comparator. Cumulative accuracy equals the average of the high-level and low-level thresholds of the hysteretic comparator.
3. This parameter is ensured by design and is not production tested.
power good
PARAMETER
Undervoltage trip threshold
TEST CONDITIONS
MIN
TYP
93
MAX
UNIT
REF
90
95 %V
V
Low-level output voltage
High-level input current
Hysteresis voltage
I
= 5 mA
0.5
1
0.75
V
OL
O
I
V
= 6 V
µA
OH
PWRGD
V
hys
1.3
2.9
4.5 %V
REF
slowstart
PARAMETER
TEST CONDITIONS
MIN
TYP
13
3
MAX
UNIT
V
= 0.5 V,
= 65 µA
V
= 1.3 V,
SLOWST
VREFB
Charge current
10.4
15.6
µA
I
VREFB
Discharge current
V
= 1 V
mA
mV
nA
SLOWST
Comparator input offset voltage
Comparator input bias current
Comparator hysteresis
10
100
7.5
See Note 3
10
–7.5
mV
NOTE 3: This parameter is ensured by design and is not production tested.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
electrical characteristics over recommended operating virtual junction temperature range,
V
= 12 V, I
= 0 A (unless otherwise noted) (continued)
CC
DRV
hysteretic comparator
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.5
UNIT
mV
nA
Input offset voltage
Input bias current
Hysteresis accuracy
V
= 0 V (see Note 3)
–2.5
DROOP
See Note 3
– V
500
3.5
V
= 15 mV
REFB HYST
(Hysteresis window = 30 mV)
–3.5
mV
Maximum hysteresis setting
V
REFB
– V = 30 mV
60
mV
HYST
NOTE 3: This parameter is ensured by design and is not production tested.
high-side VDS sensing
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Gain
2
V/V
V
= 12 V,
V
= 11.9 V,
LOSENSE
HISENSE
Differential input to V sensing amp = 100 mV
Initial accuracy
Sink current
194
206
250
mV
nA
µA
ds
≤ 13 V
IOUTLO
IOUT
5 V ≤ V
IOUTLO
= 0.5 V,
V
V
V
= 12 V,
IOUT
IOUTLO
HISENSE
Source current
500
50
= 11.5 V
V
V
= 0.05 V, V
= 12 V,
HISENSE
IOUT
IOUTLO
IOUT
Sink current
µA
= 12 V
V
V
V
= 11 V, R
= 10 kΩ
= 10 kΩ
0
0
2
1.5
V
V
V
V
V
HISENSE
HISENSE
HISENSE
IOUT
= 4.5 V, R
Output voltage swing
IOUT
= 3 V, R
= 10 kΩ
0
0.75
IOUT
High-level input voltage
Low-level input voltage
2.85
LOSENSE
V
= 4.5 V (see Note 3)
HISENSE
2.4
80
11.4 V ≤ V
≤ 12.6 V,
HISENSE
LOSENSE connected to HISENSE,
– V = 0.15 V
50
62
60
85
V
HISENSE
4.5 V ≤ V
IOUTLO
≤ 5.5 V,
HISENSE
LOSENSE connected to HISENSE,
123
144
Sample/hold resistance
Ω
V
– V
= 0.15 V
HISENSE
IOUTLO
3 V ≤ V
≤ 3.6 V,
HISENSE
LOSENSE connected to HISENSE,
67
69
95
75
V
– V
= 0.15 V
HISENSE
IOUTLO
V
V
= 12.6 V to 3 V,
HISENSE
HISENSE
CMRR
dB
– V
= 100 mV
OUTLO
NOTE 3. This parameter is ensured by design and is not production tested.
inhibit
PARAMETER
Start threshold
Hysteresis
TEST CONDITIONS
MIN
1.9
TYP
2.1
MAX
2.35
0.12
UNIT
V
V
V
0.08
1.85
0.1
Stop threshold
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
electrical characteristics over recommended operating virtual junction temperature range,
V
= 12 V, I
= 0 A (unless otherwise noted) (continued)
CC
DRV
overvoltage protection
PARAMETER
Overvoltage trip threshold
Hysteresis
TEST CONDITIONS
MIN
TYP
115
10
MAX
UNIT
112
120 %V
REF
See Note 3
mV
NOTE 3: This parameter is ensured by design and is not production tested.
overcurrent protection
PARAMETER
TEST CONDITIONS
TEST CONDITIONS
MIN
TYP
MAX
110
UNIT
mV
OCP trip threshold
Input bias current
90
100
100
nA
deadtime
PARAMETER
MIN
TYP
MAX
1.4
UNIT
High-level input voltage
LOHIB
2.4
V
Low-level input voltage
High-level input voltage
LOWDR
See Note 3
See Note 3
3
V
Low-level input voltage
1.7
NOTE 3: This parameter is ensured by design and is not production tested.
LODRV
PARAMETER
TEST CONDITIONS
MIN
TYP
TYP
MAX
UNIT
High-level input voltage
LODRV
1.85
V
Low-level input voltage
0.95
droop compensation
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Initial accuracy
V
= 50 mV
46
54
mV
DROOP
drive regulator
PARAMETER
Output voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
11.4 V ≤ V
≤ 12.6 V,
≤ 50 mA
I
= 120 mA
7
9
CC
DRV
Output regulation
1 mA ≤ I
100
mV
mA
DRV
Short-circuit current
120
bias regulator
PARAMETER
Output voltage
TEST CONDITIONS
≤ 12.6 V, See Note 4
MIN
TYP
MAX
UNIT
11.4 V ≤ V
6
V
CC
NOTE 4: The bias regulator is designed to provide a quiet bias supply for the TPS5211 controller. External loads should not be driven by the bias
regulator.
input undervoltage lockout
PARAMETER
Start threshold
TEST CONDITIONS
MIN
9.25
1.9
TYP
10 10.75
2.2
MAX
UNIT
V
V
V
Hysteresis
2
Stop threshold
7.5
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
electrical characteristics over recommended operating virtual junction temperature range,
V
= 12 V, I
= 0 A (unless otherwise noted) (continued)
CC
DRV
output drivers
PARAMETER
TEST CONDITIONS
Duty cycle < 2%, < 100 µs,
T = 125°C,
MIN
TYP
MAX
UNIT
t
V
pw
High-side sink
High-side source
Low-side sink
2
– V
= 6.5 V,
BOOTLO
J
BOOT
= 1.5 V (source) or 6 V (sink),
V
HIGHDR
See Note 3
2
2
2
Peak output
current
(see Note 5)
A
Duty Cycle < 2%,
T = 125°C,
t
V
< 100 µs,
= 6.5 V,
pw
J
DRV
= 1.5 V (source) or 5 V (sink),
V
LOWDR
See Note 3
Low-side source
High-side sink
High-side source
Low-side sink
3
45
T = 125°C,
V
– V
= 6.5 V,
BOOTLO
J
BOOT
= 6 V (source) or 0.5 V (sink)
Output
resistance
(see Note 5)
V
HIGHDR
Ω
5.7
45
T = 125°C,
V
= 6.5 V,
J
DRV
= 6 V (source) or 0.5 V (sink)
V
LOWDR
Low-side source
NOTES: 3. This parameter is ensured by design and is not production tested.
5. The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors. The output resistance is the R
the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
of the MOSFET transistor when
ds(on)
supply current
PARAMETER
TEST CONDITIONS
MIN
11.4
TYP
MAX
UNIT
Supply voltage
range
V
12
13
V
CC
CC
V
V
= 5 V,
> 10.75 V at startup,
VID code ≠ 11111,
INHIBIT
CC
3
5
10
V
= 0 V
BOOTLO
Quiescent
current
V
V
C
= 5 V,
> 10.75 V at startup,
= 50 pF,
HIGHDR
= 200 kHz,
VID code ≠ 11111,
INHIBIT
CC
V
mA
V
C
= 0 V,
= 50 pF,
LOWDR
BOOTLO
f
See Note 3
SWX
V
V
= 0 V or VID code = 11111 or V
< 9.25 V at startup,
CC
INHIBIT
BOOT
80
µA
High-side
driver
quiescent
= 13 V,
V
= 0 V
BOOTLO
V
V
C
= 5 V,
VID code ≠ 11111, V
> 10.75 V at startup,
CC
INHIBIT
BOOT
= 13 V,
= 50 pF,
V
= 0 V,
2
mA
BOOTLO
f = 200 kHz (see Note 3)
SWX
current
HIGHDR
NOTE 3: This parameter is ensured by design and is not production tested.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
switching characteristics over recommended operating virtual-junction temperature range,
V
= 12 V, I
= 0 A (unless otherwise noted)
CC
DRV
PARAMETER
TEST CONDITIONS
≤ 3.5 V, 10 mV overdrive
MIN
TYP
MAX
UNIT
1.3 V ≤ V
VREF
150
250
(see Note 3)
VSENSE to HIGHDR or
LOWDR (excluding dead-
time)
1.3 V ≤ V
≤ 3.5 V, 20 mV overdrive
≤ 3.5 V, 30 mV overdrive
≤ 3.5 V, 40 mV overdrive
200
190
180
VREF
ns
1.3 V ≤ V
1.3 V ≤ V
VREF
VREF
Propagation delay
OCP comparator
1
1
OVP comparator
See Note 3
µs
PWRGD comparator
SLOWST comparator
1
Overdrive = 10 mV (see Note 3)
560
900
8
ns
C
C
C
C
C
C
C
C
= 50 pF,
= 3 nF
V
= 0 V
= 0 V
L
L
L
L
L
L
L
L
BOOTLO
HIGHDR output
LOWDR output
HIGHDR output
LOWDR output
35
Rise time
Fall time
ns
= 50 pF
= 3 nF
8
40
= 50 pF,
= 3 nF
V
TBD
35
BOOTLO
ns
= 50 pF
= 3 nF
TBD
40
Deglitch time (Includes
comparator propagation
delay)
OCP
OVP
2
2
5
5
See Note 3
µs
V
V
= 12 V,
HISENSE
pulsed from 12 V to 11.9 V,
2
3
3
IOUTLO
100 ns rise/fall times
(see Note 3)
V
V
= 4.5 V,
HISENSE
pulsed from 4.5 V to 4.4 V,
Response time
High-side VDS sensing
µs
IOUTLO
100 ns rise/fall times (see Note 3)
V
V
= 3 V,
HISENSE
pulsed from 3 V to 2.9 V,
IOUTLO
100 ns rise/fall times (see Note 3)
Short-circuit protection
rising-edge delay
SCP
LOSENSE = 0 V (see Note 3)
300
30
500
100
100
ns
ns
ns
V
sensing sample/hold
3 V ≤ V
≤ 11 V,
HISENSE
DS
Turnon/turnoff delay
Crossover delay time
switch
V
= V
(see Note 3)
LOSENSE
HISENSE
LOWDR to HIGHDRV, and
LOHIB to LOWDR
See Note 3
30
Prefilter pole frequency
Propagation delay
Hysteretic comparator
LODRV
See Note 3
See Note 3
5
MHz
ns
400
NOTE 3: This parameter is ensured by design and is not production tested.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
SLOWSTART TIME
vs
SLOWSTART CAPACITANCE
SLOWSTART TIME
vs
SUPPLY CURRENT (VREFB)
100
10
1000
100
V
I
= 2 V
= 100 µA
(VREFB)
(VREFB)
V
= 2 V
= 0.1 µF
(VREFB)
C
S
J
T
J
= 25°C
T
= 25°C
1
0.1
0
10
1
0.0001
0.0010
0.0100
0.1000
1
1
10
100
1000
Slowstart Capacitance – µF
I
– Supply Current (VREFB) – µA
CC
Figure 1
Figure 2
DRIVER
OUTPUT RISE TIME
vs
DRIVER
OUTPUT FALL TIME
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
1000
100
10
1000
Tj = 27 °C
Tj = 27 °C
100
10
1
High Side
High Side
Low Side
Low Side
1
0.01
0.10
1.00
10.00
100.0
0.01
0.10
1.00
10.00
100.0
C
– Load Capacitance – nF
C
– Load Capacitance – nF
L
L
Figure 3
Figure 4
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
OVP THRESHOLD
vs
JUNCTION TEMPERATURE
OCP THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
118
117
105
103
101
99
116
115
114
97
113
112
95
0
25
50
75
100
125
0
25
50
75
100
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 5
Figure 6
INHIBIT START THRESHOLD VOLTAGE
INHIBIT HYSTERESIS VOLTAGE
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
2.1
150
125
2.05
2
100
75
1.95
1.9
50
0
25
50
75
100
125
0
25
50
75
100
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 7
Figure 8
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
UVLO START THRESHOLD VOLTAGE
UVLO HYSTERESIS
vs
JUNCTION TEMPERATURE
vs
JUNCTION TEMPERATURE
10.5
2.5
V = 12 V
I
V = 12 V
I
2.3
2.1
1.9
1.7
1.5
10
9.5
9
0
25
50
75
100
125
0
25
50
75
100
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 9
Figure 10
QUIESCENT CURRENT
vs
JUNCTION TEMPERATURE
POWERGOOD THRESHOLD
vs
JUNCTION TEMPERATURE
6
4
2
95
V = 12 V
I
94
93
92
91
90
0
0
25
50
75
100
125
0
25
50
75
100
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 11
Figure 12
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
DRIVER
REGULATOR VOLTAGE
vs
SLOWSTART CHARGE CURRENT
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
15
14
13
8.5
V
R
= 1.3 V
= 20 kΩ
(VREFB)
(VREFB)
8.25
8
7.75
7.5
12
11
10
0
25
50
75
100
125
0
25
50
75
100
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 13
Figure 14
DRIVER
DRIVER
HIGH-SIDE OUTPUT RESISTANCE
vs
LOW-SIDE OUTPUT RESISTANCE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
5
4
3
6
4
2
1
0
2
0
0
25
50
75
100
125
0
25
50
75
100
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 15
Figure 16
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
SENSING SAMPLE/HOLD RESISTANCE
vs
JUNCTION TEMPERATURE
100
V
= 12 V
(HISENSE)
75
50
25
0
0
25
50
75
100
125
T
J
– Junction Temperature – °C
Figure 17
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
APPLICATION INFORMATION
The following figure is a typical application schematic. The circuit can be divided into the power-stage section
and the control-circuit section. The power stage must be tailored to the input/output requirements of the
application. The control circuit is basically the same for all applications with some minor tweaking of specific
values. Table 2 shows the values of the power stage components for various output-current options.
L102
L101
Q101
12V
Vo
R103
Q102
R102
+
C103
C102
C104
C101
R101
GND
RTN
Power Stage
Control Section
C2
1 uF
R2
150
C1
1 uF
VCC
DRV
14
13
12
11
10
9
C3
15
16
17
18
19
20
21
22
23
24
25
26
27
28
R11
10.0 k
BOOT
LOWDR
DRVGND
LOHIB
C4
1 uF
HIGHDR
BOOTLO
HISENSE
LOSENSE
IOUTLO
INHIBIT
VID4
1 uF
R1
3.40 k
LODRV
BIAS
C5
1%
0.1 uF
C7
1000pF
C6
SLOWST
ANAGND
VSENSE
VREFB
VHYST
OCP
0.033 uF
8
R3 10.0 k
(see Note A)
7
ENABLE
R5
6
R6
VID3
5
100
20.0 k
VID2
R4
2.55 k
1%
C8
2200 pF
4
R7
3.92 k
R8
1.00 k
VID1
3
VID0
DROOP
IOUT
2
PWRGD
1
R9
4.32 k
R10
1.00 k
TPS5211
U1
NOTE A: VID0 – VID4 User – selected to set output voltage.
Figure 18. Standard Application Schematic
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
APPLICATION INFORMATION
Table 2. Power Stage Components
12-V–Input Power Stage Components
8–A Out 12–A Out
muRata, muRata,
Reference Designation
Function
4–A Out
muRata,
20–A Out
muRata,
C101
Input capacitor
GRM235Y106Z016A,
2 x 10–uF, 16–V, Y5V
GRM235Y106Z016A,
4 x 10–uF, 16–V, Y5V
GRM235Y106Z016A,
6 x 10–uF, 16–V, Y5V
GRM235Y106Z016A,
10 x 10–uF, 16–V, Y5V
muRata,
muRata,
muRata,
muRata,
C102
C103
C104
L101
Snubber capacitor
GRM39X7R102K050A,
1000–pF, 50–V, X7R
GRM39X7R102K050A,
1000–pF, 50–V, X7R
GRM39X7R102K050A,
2 x 1000–pF, 50–V, X7R
GRM39X7R102K050A,
3 x 1000–pF, 50–V, X7R
Sanyo,
4TPC150M,
150–uF, 4–V, 20%
Sanyo,
4TPC150M,
2 x 150–uF, 4–V, 20%
Sanyo,
4TPC150M,
3 x 150–uF, 4–V, 20%
Sanyo,
4TPC150M,
4 x 150–uF, 4–V, 20%
Output bulk
capacitor
muRata,
GRM235Y106Z016A,
2 x 10–uF, 16–V, Y5V
muRata,
GRM235Y106Z016A,
4 x 10–uF, 16–V, Y5V
muRata,
GRM235Y106Z016A,
6 x 10–uF, 16–V, Y5V
muRata,
GRM235Y106Z016A,
8 x 10–uF, 16–V, Y5V
Output hi–freq
bypass capacitor
CoilCraft,
DO1607C–152,
1.5–uH, 2.1–A
CoilCraft,
DO1813HC–122,
1.2–uH, 4.4–A
CoilCraft,
DO1813HC–122,
1.2–uH, 4.4–A
CoilCraft,
DO3316P–152HC,
1.5–uH, 9.0–A
Input filter
inductor
Vishay–Dale,
Vishay–Dale,
CoilCraft,
DO1813HCP–561,
0.56–uH, 6–A
CoilCraft,
DO3316P–681HC,
0.68–uH, 12–A
Output filter
inductor
IHLP–5050CE–XX,
0.82–uH, 16–A,
New product
IHLP–5050CE–XX,
0.5–uH, 25–A,
New product
L102
High–side gate
resistor
10.0–Ohm,
1/16–W, 5%
10.0–Ohm,
1/16–W, 5%
2 x 10.0–Ohm,
1/16–W, 5%
2 x 10.0–Ohm,
1/16–W, 5%
R101
R102
R103
Q101
Q102
Lo–side gate
resistor
3.3–Ohm,
1/16–W, 5%
3.3–Ohm,
1/16–W, 5%
2 x 3.3–Ohm,
1/16–W, 5%
3 x 3.3–Ohm,
1/16–W, 5%
2.7–Ohm,
1/10–W, 5%
2.7–Ohm,
1/10–W, 5%
2 x 2.7–Ohm,
1/10–W, 5%
3 x 2.7–Ohm,
1/10–W, 5%
Snubber resistor
Power switch
IR, IRF7811,
NMOS, 11–mOhm
IR, IRF7811,
NMOS, 11–mOhm
IR, 2 x IRF7811,
NMOS, 11–mOhm
IR, 2 x IRF7811,
NMOS, 11–mOhm
IR, IRF7811,
NMOS, 11–mOhm
IR, IRF7811,
NMOS, 11–mOhm
IR, 2 x IRF7811,
NMOS, 11–mOhm
IR, 2 x IRF7811,
NMOS, 11–mOhm
Synchronous switch
†
Nominal frequency
Hysteresis window
700 KHz
20 mV
†
Nominal frequency measured with Vo set to 2 V.
The values listed above are recommendations based on actual test circuits. Many variations of the above are
possible based upon the desires and/or requirements of the user. Performance of the circuit is equally, if not
more, dependent upon the layout than on the specific components, as long as the device parameters are not
exceeded. Fast-response, low-noise circuits require critical attention to the layout details. Even though the
operating frequencies of typical power supplies are relatively low compared to today’s microprocessor circuits,
the power levels and edge rates can cause severe problems both in the supply and the load. The power stage,
having the highest current levels and greatest dv/dt rates, should be given the greatest attention.
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
APPLICATION INFORMATION
frequency calculation
The simplified equation shown below can be used for a preliminary frequency calculation:
V
x (V
V
)
I
REF
REF
(1)
f
x 0.85
s
V
R11 C7 x Hysteresis Window
I
High frequency operations require special attention not to exceed maxium current through the controller
(120mA), and the maximum total power dissipation.
1400
1300
1200
1100
1000
Fmax With
900
800
700
600
500
400
300
200
100
0
Fmax(D)
kHz
External Driver
Fm(D)
kHz
Fmax With
Internal Driver
0
0.1
0.2
0.3
0.4
0.5
D
0.6
0.7
0.8
0.9
1
Figure 19
Another restriction relates to the maximum rms current through the output of the highside driver, (110mA.) The
maximum allowable operating frequency can be defined by the following equation:
2
(
)
110mA)
Qg x V
60ohm
Vdrv
Fmax
(2)
I
Where Qg = Total gate charge of the upper FETs in the hysteretic converter (in nanocoulombs)
Vdrv = 8 V and is the drive regulator voltage of the TPS5211 controller
V = Input voltage
I
Fmax = Maximum switching frequency in kHz
Figure 19 and equation (2) should be used to determine the maximum operating frequency of a converter. The
operating frequency should not exceed the lower of the two values determined by Figure 19 and equation (2).
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
APPLICATION INFORMATION
Control Section
Below are the equations needed to select the various components within the control section.
output voltage selection
The most important function of the power supply is to regulate the output voltage to a specific value. Values
between 1.3 V and 3.5 V can be easily set by shorting the correct VID inputs to ground. Values above the
maximum reference voltage (3.5 V) can be set by setting the reference voltage to any convenient voltage within
its range and selecting values for R2 and R3 to give the correct output. Select R3:
R3 << than V
/I
; a recommended value is 10 kΩ
REF BIAS(VSENSE)
Then, calculate R2 using:
R3
V
V
V
R2
R3
O
REF
V
V
1
or
R2
O
REF
REF
These equations are accurate if R2<<R11. If this condition is not fullfilled, the following equation must be used:
R2 x R11
V
V
1
O
REF
R3 x (R2
R11)
Another soultion is to use 0.1-µF DC decoupling capacitor in series with R11. In such a case, R11 does not
influence the output voltage value.
R2 and R3 can also be used to make small adjusts to the output voltage within the reference-voltage range
and/or to adjust for load-current active droop compensation. If there is no need to adjust the output voltage, R3
can be eliminated. R2, R3 (if used), and C7 are used as a noise filter; calculate using:
150 ns
C7
R2 R3
slowstart timing
Slowstart reduces the startup stresses on the power-stage components and reduces the input current surge.
Slowstart timing is a function of the reference-voltage current (determined by R6) and is independent of the
reference voltage. The first step in setting slowstart timing will be to determine R6:
R6 should be between 7 kΩ and 300 kΩ, a recommended value is 20 kΩ.
Set the slowstart timing using the formula:
t
t
SS
SS
)
R6
C5
(
5
5
R
VREFB
Where C5 = Slowstart capacitance in µF
= Slowstart timing in µs
t
R
SS
VREFB
= Resistance from VREFB to GND in ohms (≈ R6)
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
APPLICATION INFORMATION
hysteresis voltage
A hysteretic controller regulates by self-oscillation, thus requiring a small ripple voltage on the VSENSE pin
which the input comparator uses for sensing. Once selected, the TPS5211 hysteresis is proportional to the
reference voltage; programming Vref to a new value automatically adjusts the hysteresis to be the same
percentageofVref. SincetheoutputcurrentfromVREFBshouldbelessthan500µA, thetotaldividerresistance
(R5 + R6) should be greater than 7 KΩ. The hysteresis voltage should be no greater than 60 mV so R6 will
dominate the divider.
VREFB
Hysteresis Window = 2 × V
R5
R6
R5
VHSYT
Figure 20. Hysteresis Divider Circuit
The upper divider resistor, R5, is calculated using:
0
( )
)
Hysteresis Window
VHYST
(
0
R5 =
× R6
× R6
(
)
2 × VREFB – Hysteresis Window
2 × 100
Where Hysteresis Window = The desired peak-to-peak hysteresis voltage
VREFB = Selected reference voltage
V
(%) = [(Hysteresis Window)/VREFB] * 100 < V
(%)
HYST
O(Ripple)(P–P)
current limit
Current limit can be implemented using the on-resistance of the upper FETs as the sensing elements. Select
R8:
0.1V
100 × 100nA
VOCP
R8 <<
≤
≤ 10 kΩ
(
)
IBias(OCP)
(A recommended value is 1 kΩ)
The IOUT signal is used to drive the current limit and droop-circuit dividers. The voltage at IOUT at the output
current trip point will be:
(
)
2 ×
× TF
RDS(ON)
NumFETs
Where NumFETS = Number of upper FETS in parallel
TF = R temperature correction factor
=
×
IO(Trip)
VIOUT(Trip)
DS(ON)
I
= Desired output current trip level (A)
O(Trip)
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
APPLICATION INFORMATION
Calculate R7 using:
V
IOUT(Trip)
R7
1
R8
0.1 V
NotethatsinceR
ofMOSFETscanvaryfromlottolotandwithtemperature,tightcurrent-limitcontrol(less
DS(ON)
than 1.5 x I ) using this method is not practical. If tight control is required, an external current-sense resistor
O
in series with the drain of the upper FET can be used with HISENSE and LOSENSE connected across the
resistor.
droop compensation
Active voltage droop positioning is used to reduce the output voltage range during load transients by increasing
the output voltage setpoint toward the upper tolerance limit during light loads and decreasing the voltage
setpoint toward the lower tolerance limit during heavy loads. This allows the output voltage to swing a greater
amount and still remain within the tolerance window. The maximum droop voltage is set with R9 and R10.
Select R10:
VDROOP(Min)
0.01V
100 × 100 nA
R10 <<
≤
≤ 1 kΩ
(
)
IBias(DROOP,Max)
(Again, a value of 1 kΩ is recommended)
The voltage at IOUT during normal operation (0 to 100% load) will vary from 0 V up to:
(
)
2 ×
× TF
RDS(ON)
NumFETs
= Maximum output load current (A).
=
×
IO(Max)
VIOUT(Max)
Where I
O(Max)
droop compensation (continued)
Then, calculate R9:
V
IOUT(Max)
R9
1
R10
V
DROOP
Where V
= Desired droop voltage
DROOP
At full load, the output voltage will be:
R2
R3
V
V
1
V
O
REF
DROOP
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
APPLICATION INFORMATION
using the TPS5211 when both 12 V and 5 V are available
When both 12 V and 5 V are available, several components can be removed from the basic schematic shown
in Figure 18. R1, R4, and C9 are no longer required if 5 V is brought in directly to INHIBIT and LODRV. However,
if undervoltage lockout for the 5-V input is desired, R1 and R4 can be used to set the startup setpoint. The
INHIBIT pin trip level is 2.1 V. Select R4:
2.1V
100 × 100nA
VINH
R4 <<
≤
≤ 210k Ω
(
)
IINH(Max)
Then, set the 5-V UVLO trip level with R1:
(
)
× R4
– 2V
5VTrip
R1 =
2V
LODRV
INHIBIT
R1
5 V IN
R4
Figure 21. 5-V Input With UVLO
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
APPLICATION INFORMATION
using the TPS5211 when only 5 V is available
The TPS5211 controller requires 12 V for internal control of the device. If an external source for 12 V is not
available, a small onboard source must be included in the design. A simple boost circuitry is described in TIs
application report AN452 Providing a DSP Power Solution from +5 V or +3.3 V only Systems. Total 12-V current
depends on switching frequency and power FETs gate charge characteristics. For reliable operation, this
current should not exceed 120 mA. The power stage is not voltage dependent, but component values must be
selected for 5-V inputs. The frequency of operation is dependent upon the power stage input voltage. A typical
5-V only application circuit is shown in Figure 22.
L101
L102
Q101
5V
V
O
R103
Q102
+
C103 C104
C102
C101
R101
R102
RTN
GND
Power Stage
Control Section
C2
1 uF
R2
150
C1
1 uF
12V
15
16
17
18
19
20
21
22
23
24
25
26
27
28
14
DRV
VCC
C3
13
12
11
10
9
R11
7.5k
LOWDR
DRVGND
LOHIB
BOOT
C4
1 uF
1 uF
HIGHDR
BOOTLO
HISENSE
LOSENSE
IOUTLO
INHIBIT
VID4
LODRV
BIAS
R1
C5
10.0 k
1%
R4
0.1 uF
C7
1000pF
C6
0.033 uF
8
SLOWST
ANAGND
VSENSE
VREFB
VHYST
OCP
7
ENABLE
(see Note A)
R3 10.0 k
R6
20.0 k
6
R5
5
VID3
4
100
VID2
C8
2200 pF
11.0 k
1%
3
R8
1.00 k
VID1
R7 3.92 k
2
DROOP
IOUT
VID0
1
PWRGD
R9 4.32 k
R10
1.00 k
TPS5211
U1
NOTE A: VID0 – VID4 User – selected to set output voltage.
Figure 22. Typical 5-V-Only Application Circuit
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
APPLICATION INFORMATION
controller operation
Operation of the TPS5211 controller differs from a regular hysteretic controller. The additional ramp signal
through the input of the hysteretic comparator is formed by R11 and C7. The two signals are summed through
the inputs of the comparator. The two signals are the ramp signal from R11 - C7 circuitry and the signal from
the output converter. By proper selection of R11 and C7, one can get the amplitude of an additional ramp signal
which is greater than the output ripple of the converter. As a result, the switching frequency is greater while the
output ripple becomes lower. The additional ramp signal and output ripple waveforms are shown in Figure 23.
The switching frequency now depends on R11 and C7 values and does not depend on the output filter
characteristics including ESR, ESL, and C of the output capacitor (see frequency calculation section).
The dc feedback signal from the output of the converter through resistor R2 controls the dc level of the output
voltage. Because the switching frequency of TPS5211 is high and it does not depend on output capacitor
characteristics, low cost cermic or film capacitors can be used in a dc to dc converter while having the same
load current transient response characteristics.
(V – V ) – Hysteresis Window
HI
(V
LO
– V
) – Overshoot
MIN
MAX
Because of Delays
V
HC
V
MAX
V
HI
V
O (P–P)
V
REF
V
LO
V
MIN
Additional Ramp-Signal
Output Ripple
t
Figure 23. The Additional Ramp-Signal and Output Voltage Ripple Waveforms
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
APPLICATION INFORMATION
application examples
Below are waveforms and test results measured on the EVM for a 12-V input and a 2-V, 20-A output application.
The output voltage ripple and power switches midpoints are shown in Figure 24. The converter operates at 450
kHz. The peak to peak output ripple is 9.6 mV, while the hysteresis window is set at 20 mV. Therefore, the output
ripple for converter with TPS5211 is much lower than the hysteresis window.
Output Voltage
Ripple (20 mV/div)
Low FET
Drain-Source
Voltage (5 V/div)
Figure 24. The Output Voltage Ripple ans Low FET Drain-Source Voltage Waveforms
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
APPLICATION INFORMATION
The load current transient response waveforms are shown in Figure 25 to illustrate the excellent load current
transient response characteristics of TPS5211.
Output Voltage
(100 mV/div)
Load Current
(10 A/div)
Low FET
Drain-Source Voltage
(10 V/div)
Figure 25
The output voltage transient response of the converter with TPS5211 controller. The load current has 14 A step
with slew rate of 30 A/µS.
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
APPLICATION INFORMATION
Comparison of TPS5210 and TPS5211 controller applications
The TPS5210 and TPS5211 hysteretic controllers have excellent load current transient response
characteristics, which is one of the most important advantages of hysteretic mode. There are specific
application areas where one of the hysteretic controllers is preferable over the other. The table below gives a
comparative view on application areas for the TPS5210 and TPS5211 controllers
comparison of TPS5210 and TPS5211 applications
Controller
Switching frequency, kHz
TPS5210
100 – 400
TPS5211
400 – 700
Independent of output filter and easy to
evaluate
Frequency variation
Output current, A
Depends on outout filter characteristics
up to 18 – 20 (can be increased in multi-
phase configuration)
up to 40
85 – 95
Efficiency, % (depends on frequency, output cur-
rent, Vin, Vout, components, etc.)
75 – 85
Surface-mount ceramic and POSCAP
type capacitors and 40% – 65% smaller
inductors.
Requires bulk electrolytic capacitors espe-
cially if Iout > 12A and larger inductor
Input and output filter
Component Cost
20% – 40% lower for TPS5211
System cost including reliability, power losses,
cooling, etc.
Can be estimated only during design for a given specific application.
Special attention not to exceed frequency
Special attention to the noise sensitive
places such as the hysteresis comparator
and the sample hold circuitry.
and lcc limits. The high frequency dc –
dc converter design rules should be
used.
Layout and design
A dc – dc converter can be placed close
to the microprocessor or DSP to de-
crease the number of decoupling capaci-
tors.
For high current applications, it is difficult to
meet high density minimum size require-
ments.
Compatibility with the whole system
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
APPLICATION INFORMATION
layout guidelines
Goodpowersupplyresultswillonlyoccurwhencareisgiventoproperdesignandlayout. Layout willaffectnoise
pickup and generation and can cause a good design to perform with less than expected results. With a range
of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult
than most general PCB design. The general design should proceed from the switching node to the output, then
back to the driver section, and, finally, to placing the low-level components. Below are several specific points
to consider before layout of a TPS5211 design begins.
1. All sensitive analog components should be referenced to ANAGND. These include components connected
to SLOWST, DROOP, IOUT, OCP, VSENSE, VREFB, VHYST, BIAS, and LOHIB.
2. Analogground and drive ground should be isolated as much as possible. Ideally, analog ground will connect
to the ground side of the bulk storage capacitors on V , and drive ground will connect to the main ground
O
plane close to the source of the low-side FET.
3. Connections from the drivers to the gate of the power FETs, should be as short and wide as possible to
reduce stray inductance. This becomes more critical if external gate resistors are not being used.
4. The bypass capacitor for the DRV regulator should be placed close to the TPS5210 and be connected to
DRVGND.
5. The bypass capacitor for V
should be placed close to the TPS5210 and be connected to DRVGND.
CC
6. When configuring the high-side driver as a floating driver, the connection from BOOTLO to the power FETs
should be as short and as wide as possible. The other pins that also connect to the power FETs, LOHIB
and LOSENSE, should have a separate connection to the FETS since BOOTLO will have large peak
currents flowing through it.
7. When configuring the high-side driver as a floating driver, the bootstrap capacitor (connected from BOOT
to BOOTLO) should be placed close to the TPS5210.
8. When configuring the high-side driver as a ground-referenced driver, BOOTLO should be connected to
DRVGND.
9. The bulk storage capacitors across V should be placed close to the power FETS. High-frequency bypass
I
capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the
high-side FET and to the source of the low-side FET.
10. High-frequency bypass capacitors should be placed across the bulk storage capacitors on V .
O
11. HISENSE and LOSENSE should be connected very close to the drain and source, respectively, of the
high-side FET. HISENSE and LOSENSE should be routed very close to each other to minimize
differential-mode noise coupling to these traces. Ceramic decoupling capacitors should be placed close to
where HISENSE connects to Vin, to reduce high-frequency noise coupling on HISENSE.
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
MECHANICAL DATA
PWP (R-PDSO-G**)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
20-PIN SHOWN
0,30
0,19
0,65
20
M
0,10
11
Thermal Pad
(See Note D)
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
1
10
0,25
A
0°–8°
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
28
DIM
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4073225/E 03/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusions.
D. Thepackagethermalperformancemaybeenhancedbybondingthethermalpadtoanexternalthermalplane.Thispadiselectrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments Incorporated.
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
相关型号:
TPS5300DAPG4
3.3A SWITCHING CONTROLLER, 500kHz SWITCHING FREQ-MAX, PDSO32, GREEN, PLASTIC, HTSSOP-32
TI
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