TPS53632GRSMR_技术文档

Sample &

Buy

Support &

Community

Product

Folder

Tools &

Software

Technical

Documents

TPS53632G

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

TPS53632G D-CAP+™ Half-Bridge PWM Controller

Optimized for GaN-based 48-V DC/DC Converter with I²C Interface

1 Features

3 Description

The TPS53632G device is

a half-bridge PWM

1

•

Valley Current Mode with Constant ON Time

Control

controller with D-CAP+™ architecture that provides

fast transient response, lowest output capacitance

and high efficiency in single stage conversion directly

from 48-V bus. The TPS53632G device supports the

standard I²C Rev 3.0 interface for dynamic control of

the output voltage and current monitor telemetry.

Paired with TI GaN power stages and drivers, the

TPS53632G can switch up to 1 MHz to minimize

magnetic component size and reduce overall board

space. The LMG5200 GaN power stage is designed

specifically for this controller to achieve high

frequency and efficiency as high as 92% with 48-V to

1-V conversion.

•

Lossless Current Sensing Scheme

I²C Interface for VID Control and Telemetry

Programmable I²C Addresses up to Eight Devices

Switching Frequency up to 1 MHz

Digital Current Monitor

7-Bit, DAC Output Range: 0.50-V to 1.52-V with

10-mV Step

•

Accurate, Adjustable Voltage Positioning or Zero

Slope Load-Line

•

Selectable, 8-Level Current Limit

Adjustable Output Slew Rate Control

Default Boot Voltage: 1.00 V

Other features include adjustable control of output

slew rate and voltage positioning. In addition, the

TPS53632G device can be used along with other TI

discrete power MOSFETs and drivers for silicon-

based half bridge solutions. The TPS53632G device

is packaged in a space saving, thermally enhanced,

32-pin VQFN package and is rated to operate at a

range between –10°C and 105°C.

Small, 4-mm × 4-mm, 32-Pin, VQFN, PowerPAD

Package

2 Applications

•

48-V Point-of-Load (POL) for Data Center and

Telecommunication

Device Information

PART NUMBER

PACKAGE

BODY SIZE

•

Wide Input Range Power Supplies for Industrial

TPS53632G

VQFN

4 mm × 4 mm

WHITESPACE

Simplified Schematic

TPS53632G

PWM_H

I²C BUS

HS

3

HB

2

VIN

SW

1

8

9

PWM_L

HI

LI

HS

HB

4

5

HI

LI

HO

LO

GaN Driver

UCC27523

VCC

AGND

PGND

INA

OUTA

INB

OUTB

LMG5200

6

7

VCC

AGND

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS53632G

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

www.ti.com

Table of Contents

7.3 Feature Description................................................. 11

7.4 Device Functional Modes........................................ 18

7.5 Configuration and Programming ............................. 18

7.6 Register Maps ........................................................ 19

Applications and Implementation ...................... 21

8.1 Application Information............................................ 21

8.2 Typical Application .................................................. 21

Power Supply Recommendations...................... 31

1

2

3

4

5

6

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 Timing Requirements................................................ 7

6.7 Switching Characteristics.......................................... 8

6.8 Typical Characteristics (Half-Bridge Operation)........ 9

Detailed Description ............................................ 10

7.1 Overview ................................................................. 10

7.2 Functional Block Diagram ....................................... 10

8

9

10 Layout................................................................... 31

10.1 Layout Guidelines ................................................. 31

10.2 Layout Example .................................................... 34

11 Device and Documentation Support ................. 34

11.1 Trademarks........................................................... 34

11.2 Electrostatic Discharge Caution............................ 35

11.3 Glossary................................................................ 35

7

12 Mechanical, Packaging, and Orderable

Information ........................................................... 35

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (April 2016) to Revision A

Page

•

Updated document status from Product Preview to Production Data.................................................................................... 1

2

Submit Documentation Feedback

Product Folder Links: TPS53632G

TPS53632G

www.ti.com

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

5 Pin Configuration and Functions

RSM Package

32-Pin QFN

Top View

VFB

SDA

1

24

23

22

21

20

19

18

17

GFB

NC

VDD 2

PGOOD 3

NC 4

PU3

TPS53632G

CSP2

CSN2

CSN1

CSP1

PWM-LO 5

PWM-HI 6

SKIP 7

EN 8

Pin Functions

I/O

DESCRIPTION

NAME

NO.

Error amplifier summing node. Resistors between the VREF pin and the COMP pin (R_COMP) and

between the COMP pin and the DROOP pin (R_DROOP) set the droop gain.

COMP

26

I

CSP1

CSP2

17

20

Positive current sense inputs. Connect to the most positive node of current sense resistor or

inductor DCR sense network. Tie CSP2 or CSP1 (in that order) to a 3.3-V supply to disable the

phase.

I

PU3

21

18

Connect to 3.3-V supply.

CSN1

Negative current sense inputs. Connect to the most negative node of current sense resistor or

inductor DCR sense network. CSN1 has a secondary OVP comparator and includes the soft-stop,

pull-down transistor.

I

CSN2

NC

19

22

–

No connect.

Error amplifier output. A resistor pair between this pin and the VREF pin and between the COMP

DROOP

EN

25

8

O

pin and this pin sets the droop gain. A_DROOP= 1 + R_DROOP/ R_COMP

.

Enable. 100-ns de-bounce. Regulator enters low-power mode, but retains start-up settings when

brought low.

I

A resistor between this pin and GND sets the per-phase switching frequency. Add a resistor to

VREF to disable dynamic phase add and drop operation.

FREQ-P

GFB

10

23

Voltage sense return. Tie to GND on PCB with a 10-Ω resistor to provide feedback when the

microprocessor is not populated.

GND

29

13

–

Analog circuit reference. Tie this pin to a quiet point on the ground plane.

IMON

O

Analog current monitor output. V_IMON= ΣV_ISENSE× (1 + R_IMON/R_OCP).

Voltage divider to IMON. Resistor ratio sets the IMON gain (see IMON pin). A resistor between this

pin and GND (R_OCP) selects 1 of 8 OCP levels (per phase, latched at start-up).

OCP-I

12

I/O

PU

9

3

I

Pull-up to VREF through 10-kΩ resistor.

PGOOD

PWM-HI

PWM-LO

NC

O

Power good output. Open-drain.

6

PWM controls for the external driver; 5-V logic level. Controller forces signal to the tri-state level

when needed.

O

–

5

4

No connect.

30

32

NC

–

Submit Documentation Feedback

3

Product Folder Links: TPS53632G

TPS53632G

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

www.ti.com

Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

Voltage divider to VREF. A resistor to GND sets the ramp setting voltage. The RAMP setting can

be used to override the factory ramp setting.

RAMP

11

I

SCL

SDA

31

1

I

Serial digital clock line.

Serial digital I/O line.

I/O

When high, the driver enters FCCM mode; otherwise, the driver is in DCM mode. Driving the tri-

state level on this pin puts the drivers into a low power sleep mode.

SKIP

7

O

The voltage sets the 3 LSBs of the I²C address. The resistance to GND selects 1 of 8 slew rates.

The start-up slew rate (EN transitions high) is SLEWRATE/2. The ADDRESS and SLEWRATE

values are latched at start-up.

SLEWA

15

I

VINTF

V5A

14

28

I

Input voltage to interface logic. Voltage level can be between 1.62 V and 3.5 V.

5-V power input for analog circuits; connect through resistor to 5-V plane and bypass to GND with

ceramic capacitor with a value of at least 1 µF.

VBUS

VDD

16

2

I

The VBUS pin provides input voltage information to the on-time circuits for both converters.

3.3-V digital power input. Bypass this pin to GND with a capacitor with a value of at least 1 µF.

Voltage sense line. Tie directly to V_OUTsense point of processor. Tie to V_OUTon PCB with a 10-Ω

resistor to provide feedback when the microprocessor is not populated. The resistance between

VFB and GFB is > 1 MΩ

VFB

24

I

VREF

PAD

27

O

–

1.7-V, 500-µA reference. Bypass to GND with a 0.22-µF ceramic capacitor.

Thermal pad Tie to the ground plane with multiple vias.

GND

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

–0.3

MAX

6.0

UNIT

V5A

VBUS

30.0

3.6

VDD

Input voltage

V

COMP, CSP1, CSP2, CSN1, CSN2, DROOP, EN, FREQ-P, IMON, OCP-I, O-

USR, RAMP, SCL, SDA, SLEWA, VFB, VINTF, VREF

–0.3

3.6

GFB

–0.2

–0.3

–40

0.2

3.6

PGOOD

Output voltage

V

PWM-LO, PWM-HI, SKIP

6.0

Operating junction temperature, T_J

Storage temperature, T_stg

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

±2000

±750

UNIT

V

Human body model (HBM) ESD stress voltage⁽¹⁾

Charged device model (CDM) ESD stress voltage⁽²⁾

Electrostatic

discharge

V_(ESD)

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4

Submit Documentation Feedback

Product Folder Links: TPS53632G

TPS53632G

www.ti.com

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

MAX

5.5

UNIT

V5A

VBUS

VDD

–0.1

3.1

28

3.5

V_I

Input voltage

V

CSN1, CSN2, CSP1, CSP2, IMON, OCP-I, O-USR, RAMP, SCL,

SDA, VFB, VINTF, VREF

–0.1

3.5

COMP, DROOP, EN, FREQ-P, SLEWA

–0.1

–10

5.5

0.1

3.5

5.5

105

GFB

PGOOD

V_O

T_A

Output voltage

V

PWM-LO, PWM-HI, SKIP

Operating ambient temperature

°C

6.4 Thermal Information

TPS53632G

THERMAL METRIC⁽¹⁾

RSM (VQFN)

32 PINS

37.2

UNITS

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

°C/W

R_θJCtop

R_θJB

31.9

Junction-to-board thermal resistance

8.1

R_ψJT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.4

R_ψJB

7.9

R_θJCbot

2.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

Submit Documentation Feedback

5

Product Folder Links: TPS53632G

TPS53632G

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

www.ti.com

6.5 Electrical Characteristics

over recommended free-air temperature range, V_V5A= 5.0 V, V_VDD= 3.3 V, V_GFB= GND, V_VFB= V_CORE(unless otherwise

noted)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLY: CURRENTS, UVLO AND POWER-ON-RESET

I_V5-3P

V5A supply current

VDD supply current

V_DAC< V_VFB< (V_DAC+ 100 mV), EN = ‘HI’

3.6

0.2

6.0

0.8

mA

V_DAC< V_VFB< (V_DAC+ 100 mV), EN = ‘HI’, digital

buses idle

I_VDD-3P

I_V5STBY

V5A standby current

VDD standby current

VINTF supply current

EN = ‘LO’

125

23

200

40

I_VDDSTBY

I_VDD-1P8

EN = ‘LO’

µA

All conditions, digital buses idle

1.7

5.0

V_VFB< 200 mV, Ramp up, V_VDD> 3 V, EN = ’HI’,

switching begins.

V_UVLOH

V5A UVLO ‘OK’ threshold

V5A UVLO fault threshold

4.2

4.4

4.2

4.52

4.35

Ramp down, EN = ’HI’, V_VDD> 3 V, V_VFB= 100 mV,

restart if 5-V falls below V_PORthen rises > V_UVLOH

V_UVLOL

,

4.00

or EN is toggled w/ V_V5A> V_UVLOH

Ramp down, EN = ‘HI’, V_VDD> 3 V. Can restart if 5-

V rises to V_UVLOHand no other faults present.

V_POR

V5A fault latch reset threshold

VDD UVLO ‘OK’ threshold

1.2

2.5

1.9

2.8

2.5

3.0

V_VFB< 200 mV. Ramp up, V_V5A> 4.5 V, EN = ’HI’,

Switching begins.

V_3UVLOH

V

Ramp down, EN = ’HI’, V5A > 4.5V, VFB = 100 mV,

restart if 5-V dips below V_PORthen rises > V_UVLOH

or EN is toggled with 5 V > V_UVLOH

V_3UVLOL

Fault threshold

VDD fault latch

2.4

1.2

2.6

1.9

2.8

2.5

Ramp down, EN = ‘HI’, V_V5A> 4.5 V, can restart if

5-V supply rises to V_UVLOHand no other faults

present.

V_POR

V_INTFUVLOH

V_INTFUVLOL

VINTF UVLO OK

Ramp up, EN = ’HI’, V_V5A> 4.5 V, V_VFB= 100 mV

1.4

1.3

1.5

1.4

1.6

1.5

Ramp down, EN = ’HI’, V_V5A> 4.5 V, V_VFB= 100

mV

VINTF UVLO falling

REFERENCES: DAC, VREF, VFB DISCHARGE

V_VIDSTP

V_DAC1

VID step size

VFB tolerance

Change VID0 HI to LO to HI

10

No load active, 1.36 V ≤ V_VFB≤ 1.52 V, I_OUT= 0 A

No load medium, 1.0 V ≤ V_VFB≤ 1.35 V, I_OUT= 0 A

No load medium, 0.5 V ≤ V_VFB≤ 0.99 V, I_OUT= 0 A

VREF output 4.5 V ≤ V_V5A≤ 5.5 V, I_VREF= 0 A

0 A ≤ I_REF≤ 500 µA, HP-2

–9

–8

9

8

mV

V_DAC2

VFB tolerance

-7

7

V_VREF

VREF output

1.66

–4

1.700

-3

1.74

V

mV

V

V_VREFSRC

V_VREFSNK

V_VBOOT

VREF output source

VREF output sink

–500 A ≤ I_REF≤ 0 A, HP-2

3

4

Internal VFB initial boot voltage Initial DAC boot voltage

0.99

1.00

1.01

RAMP SETTINGS

R_RAMP= 30 kΩ

60

120

160

40

R_RAMP= 56 kΩ

Compensation ramp

V_RAMP

mV

R_RAMP= 100 kΩ

R_RAMP≥ 150 kΩ

VOLTAGE SENSE: VFB AND GFB

Not in fault, disable or UVLO, V_VFB= V_DAC= 1.5 V,

V_GFB= 0 V, measure from VFB to GFB

R_VFB

VFB/GFB Input resistance

1

MΩ

V_DELGND

GFB Differential

GND to GFB

±100

mV

CURRENT MONITOR

∑∆CS = 0 mV, A_IMON= 3.867

∑∆CS = 1.5 mV, A_IMON= 3.867

∑∆CS = 7.5 mV, A_IMON= 3.867

∑∆CS = 15 mV, A_IMON= 3.867

Each phase, CSPx – CSNx

00h

19h

80h

FFh

VAL_ADC

IMON ADC output

LR_IMON

IMON linear range

50

mV

6

Submit Documentation Feedback

Product Folder Links: TPS53632G

TPS53632G

www.ti.com

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

Electrical Characteristics (continued)

over recommended free-air temperature range, V_V5A= 5.0 V, V_VDD= 3.3 V, V_GFB= GND, V_VFB= V_CORE(unless otherwise

noted)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

CURRENT SENSE: OVER CURRENT PROTECTION, PHASE ADD AND DROP, AND PHASE BALANCE

R_OCP-I= 20 kΩ

R_OCP-I= 24 kΩ

R_OCP-I= 30 kΩ

3.7

6.6

7.6

10.5

14.5

19.5

25.4

32.5

40.5

49.3

0.2

11.4

14.1

18.0

23.0

29.0

36.2

44.0

53.0

500

10.6

15.4

21.3

28.4

36.3

45.0

–500

R_OCP-I= 39 kΩ

OCP voltage (valley current

limit)

V_OCPP

mV

R_OCP-I= 56 kΩ

R_OCP-I= 75 kΩ

R_OCP-I= 100 kΩ

R_OCP-I= 150 kΩ

I_CS

CS pin input bias current

CSPx and CSNx

VFB to DROOP

nA

dB

Error amplifier total voltage

gain⁽¹⁾

A_V-EA

80

I_{EA_SR}

I_{EA_SK}

Error amplifier source current

Error amplifier sink current

I_DROOP, V_VFB= V_DAC+ 50 mV, R_COMP= 1 kΩ

I_DROOP, V_VFB= V_DAC– 50mV, R_COMP= 1 kΩ

1

mA

V/V

–1

Gain from CSPx – CSNx to PWM comparator,

R_SKIP= Open

A_CSINT

Internal current sense gain

5.8

10

6.0

6.2

R_SFTSTP

Soft-stop transistor resistance

Connected to CSN1

EN = HI

100

350

200

600

Ω

kΩ

MΩ

R_VIN

VIN resistance

EN = LOW or STBY

PROTECTION: OVP, UVP, PGOOD AND THERMAL SHUTDOWN

V_OVPH

V_PGDH

Fixed OVP voltage

V_CSN1> V_OVPHfor 1 µs

1.60

190

1.70

0.15

1.80

245

V

Measured at the VFB pin w/r/t VID code, device

latches OFF

PGOOD high threshold

mV

Measured at the VFB pin w/r/t VID code, device

latches OFF

V_PGDL

PGOOD low threshold

-348

-280

0.3

PWM AND SKIP OUTPUTS: I/O VOLTAGE AND CURRENT

V_{P-S_L}

V_{P-S_H}

PWMx/SKIP - Low

PWMx/SKIP - High

PWM_ILOAD= ± 1 mA, SKIP_ILOAD= ± 100 µA

V

4.2

4

LOGIC INTERFACE: VOLTAGE AND CURRENT

R_VRTTL

V_SDA= 0.31

15

50

2

Pull-down resistance

R_VRPG

Ω

µA

V

V_PGOOD= 0.31

36

I_VRTTLK

V_IL

Logic leakage current

Low-level Input voltage

High-level Input voltage

I/O leakage, EN

V_SCL= 1.8 V, V_SDA= 1.8 V, V_PGOOD= 3.3 V

-2

0.2

0.6

SCL, SDA; V_VINTF= 1.8 V

V_IH

1.2

I_ENH

Leakage current , V_EN= 1.8 V

24

40

µA

(1) Specified by design. Not production tested.

6.6 Timing Requirements

The TPS53632G requires the ENABLE signal on Pin 8 to go from low to high only after the V5A (5V), the VDD

(3.3V) and the VIN rails have gone high.

Submit Documentation Feedback

7

Product Folder Links: TPS53632G

TPS53632G

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

www.ti.com

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Controller minimum OFF

time

t_OFF(min)

t_ON(min)

Fixed value

20

ns

Controller minimum ON

time

R_CF= 150 kΩ, V_VIN= 20 V, V_VFB= 0 V

20

TIMERS: SLEW RATE, ADDR, SLEEP EXIT, ON TIME AND I/O TIMING

t_START-CB

t_STBY-E

Cold boot time⁽¹⁾

Standby exit time⁽²⁾

V_BOOT> 0V , EN = high, C_REF= 0.33 µF

V_VID= 1.28 V, R_SLEW= 39 kΩ

R_SLEW= 20 kΩ

1.2

ms

µs

250

6

12

18

24

30

12

R_SLEW= 24 kΩ

Slew rate setting for VID

change

SL_SET

R_SLEW= 30 kΩ

mV/µs

R_SLEW= 39 kΩ

R_SLEW= 56 kΩ

(3)

SL_START

ADDR

Slew rate setting for start-up EN goes high, R_SLEW= 39 kΩ

V_SLEWA≤ 0.30 V (Addr = 100 0xxx)

Address setting 3 LSB of

0.75 V ≤ V_SLEWA≤ 0.85 V

I²C address

000b

011b

101b

1.15 V ≤ V_SLEWA≤ 1.25 V

PGOOD deglitch time

(over)⁽⁴⁾

t_PGDDGLTO

t_PGDDGLTU

1

µs

ns

PGOOD deglitch time

(under)⁽⁵⁾

31

295

230

R_CF= 20 kΩ

R_CF= 24 kΩ, V_VIN= 12 V, V_VFB= 1 V, f_SW

400 kHz

=

R_CF= 39 kΩ, V_VIN= 12 V, V_VFB= 1 V, f_SW

600 kHz

164

140

128

t_ON

On time

R_CF= 75 kΩ, V_VIN= 12 V, V_VFB= 1 V, f_SW

800 kHz

R_CF= 150 kΩ, V_VIN= 12 V, V_VFB= 1 V, f_SW

1 MHz

=

PWM AND SKIP OUTPUTS

PWMx/SKIP H-L transition

time

(3)

t_{P-S_H-L}

10% to 90%, both edges

7

20

ns

µs

PROTECTION: OVP, UVP, PGOOD AND THERMAL SHUTDOWN

t_PG2PGOOD low Low state time after EN goes low.

225

250

275

(1) Cold boot time is defined as the time from UVLO detection to V_OUTramp.

(2) Standby exit time is defined as the time from EN assertion until PGOOD goes high

(3) Specified by design. Not production tested.

(4) PGOOD deglitch time (over) is defined as the time from when the VFB pin rises above the 250-mV V_DACboundary to when the PGOOD

pin goes low.

(5) PGOOD deglitch time (under) is defined as the time from when the VFB pin falls below the –300-mV V_DACboundary to when the

PGOOD pin goes low.

8

Submit Documentation Feedback

Product Folder Links: TPS53632G

TPS53632G

www.ti.com

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

6.8 Typical Characteristics (Half-Bridge Operation)

V_IN= 48 V

Load = 1 A

V_OUT= 1 V

V_IN= 48 V

V_OUT= 1 V

Load = 10 A

Figure 1. Startup

Figure 2. Switching Waveform

V_IN= 48 V

V_OUT= 1 V

V_IN= 48 V

V_OUT= 1 V

Load transient from 10 A to 40 A

Load transient from 40 A to 10 A

Figure 3. Load Transient

Figure 4. Load Transient

Submit Documentation Feedback

9

Product Folder Links: TPS53632G

TPS53632G

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

www.ti.com

7 Detailed Description

7.1 Overview

The TPS53632G device is a DCAP+ mode half-bridge PWM controller optimized for high frequency operation

using GaN switchers. The DAC outputs a reference in accordance with the 7-bit VID code as defined in Table 1.

This DAC sets the output voltage.

In adaptive on-time converters, the controller varies the on-time as a function of input and output voltage to

maintain a nearly constant frequency during steady-state conditions. With conventional voltage-mode constant

on-time converters, each cycle begins when the output voltage crosses to a fixed reference level. However, in

the TPS53632G device, the cycle begins when the current feedback reaches an error voltage level which

corresponds to the amplified difference between the DAC voltage and the feedback output voltage. In the case of

half bridge operation, the device sums the current feedback from secondary current and doubles the output of

the internal current-sense amplifiers.

This approach has two advantages:

•

The amplifier DC gain sets an accurate linear load-line slope, which is required for certain V_COREapplications.

The device filters the error voltage input to the PWM comparator to improve the noise performance.

During a steady-state condition, the phases of the TPS53632G switch are 180° phase-displacement. The phase

displacement is maintained both by the architecture (which does not allow the high-side gate drive outputs of

more than one phase to be ON in any condition except transients) and the current ripple (which forces the pulses

to be spaced equally). The controller forces current-sharing by adjusting the ON-time of each phase. Current

balancing requires no user intervention, compensation, or extra components.

7.2 Functional Block Diagram

COMP

DROOP

VDD

V5A

GND

VBAT

VREF

Clamp

Differential

Amplifier

PWM1

PWM2

Ramp

Comparator

PWM1

PWM2

On-Time

1

VFB

GFB

PWM-HI

PWM-LO

+

CLK1

CLK2

Voltage

Amplifier

+

CLK

Phase

Manager

DAC

On-Time

2

Error

Amplifier

Integrator

CSP1

+

IS1

BLANK

I_AMP

ISUM

CSN1

CSP2

USR

ISUM

DROOP

OSR/USR

OSR

ILIM

+

IS2

I_AMP

ISHARE

ADDR

Current

Sharing

Circuitry

⁺S

CSN2

+

OCP

CPU

Logic, Protection,

SKIP

EN

PGOOD

SCL

VD

ISUM

IS1

and Status Circuitry

DAC

IS2

I2C

Interface

SDA

FSEL

VREF

10

Submit Documentation Feedback

Product Folder Links: TPS53632G

TPS53632G

www.ti.com

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

7.3 Feature Description

7.3.1 Current Sensing

The TPS53632G device provides independent channels of current feedback for secondary side current

doublers . These independent channels increase the system accuracy and reduce the dependence of circuit

performance on layout compared to an externally summed architecture. The design can use inductor DCR

sensing to yield the best efficiency or resistor current sensing to yield the most accuracy across wide

temperature ranges. DCR sensing can be optimized by using a NTC thermistor to reduce the variation of current

sense with temperature.

The pins CSP1, CSN1, CSP2 and CSN2 are the current sensing pins.

7.3.2 Load Transients

When the load increases suddenly, the output voltage immediately drops. This voltage drop is reflected as a

rising voltage on the DROOP pin. This rising voltage forces the PWM to pulse sooner and more frequently which

causes the inductor current to rapidly increase. As the inductor current reaches the new load current, a steady-

state operating condition is reached and the PWM switching resumes the steady-state frequency. Similarly, when

the load releases suddenly, the output voltage rises. This rise is reflected as a falling voltage on the COMP pin.

This rising voltage forces a delay in the PWM pulses until the inductor current reaches the new load current,

when the switching resumes and steady-state switching continues.

7.3.3 PWM and SKIP Signals

The PWM and SKIP signals are outputs of the controller and serve as input to the driver or DrMOS type devices.

Both are 5-V logic signals. The PWM signals are logic high when the high-side driver turns ON. The PWM signal

must be low for the low-side drive to turn ON. When both the drive signals are OFF, the PWM is in tri-state.

7.3.4 5-V, 3.3-V and 1.8-V Undervoltage Lockout (UVLO)

The TPS53632G device continuously monitors the voltage on the V5A, VDD and VINTF pins to ensure a value

high enough to bias the device properly and provide sufficient gate drive potential to maintain high efficiency. The

converter starts with a voltage of approximately 4.4 V and has a nominal 200 mV of hysteresis. After the 5VA,

VDD or VINTF pins go below the V_UVLOLlevel, the corresponding voltage must fall below V_POR(1.5 V) to reset

the device.

The input voltage (V_VIN) does not include a UVLO function, so the circuit runs with power inputs as low as

approximately 3 x V_OUT

.

7.3.5 Output Undervoltage Protection (UVP)

Output undervoltage protection works in conjunction with the current protection described in the Overcurrent

Protection (OCP) section. If the output voltage drops below the low PGOOD voltage threshold, then the drivers

are turned OFF until the EN pin power is cycled.

7.3.6 Overcurrent Protection (OCP)

The TPS53632G device uses a valley current limiting scheme, so the ripple current must be considered. The DC

current value at OCP (I_OCP) is the OCP limit value plus half of the ripple current. Current limiting occurs on a

phase-by-phase and pulse-by-pulse basis. If the voltage between the CSPx and CSNx pins is above the OCP

value, the converter delays the next ON pulse until that voltage difference drops below the OCP limit. For

inductor current sensing circuits, the voltage between the CSPx and CSNx pins is the inductor DCR value

multiplied by the resistor divider which is part of the NTC compensation network. As a result, a wide range of

OCP values can be obtained by changing the resistor divider value. In general, use the highest OCP setting

possible with the least attenuation in the resistor divider to provide as much signal to the device as possible. This

provides the best performance for all parameters related to current feedback.

In OCP mode, the voltage drops until the UVP limit is reached. Then the converter sets the PGOOD to inactive,

and the drivers are turned OFF. The converter remains in this state until the device is reset by the V5A, VDD or

VINTF rails.

Submit Documentation Feedback

11

Product Folder Links: TPS53632G

TPS53632G

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

www.ti.com

Feature Description (continued)

7.3.7 Overvoltage Protection

An OVP condition is detected when the output voltage is greater than the PGDH voltage, and greater than V_DAC

.

V_OUT> + V_PGDHgreater than V_DAC. In this case, the converter sets PGOOD inactive, and turns ON the drive for

the low-side MOSFET. The converter remains in this state until the device is reset by cycling the V5A, VDD or

VINTF pin. However, the OVP threshold is blanked much of the time. In order to provide protection to the

processor 100% of the time, there is a second OVP level fixed at V_OVPHwhich is always active. If the fixed OVP

condition is detected, the PGOOD are forced inactive and the low-side MOSFETs are tuned ON. The converter

remains in this state until the V5A, VDD or VINTF pin is reset.

7.3.8 Analog Current Monitor, IMON and Corresponding Digital Output Current

The TPS53632G device includes a current monitor function. The current monitor supplies an analog voltage,

proportional to the load current, on the IMON pin.

The current monitor function is related to the OCP selection resistors. The R_OCPis the resistor between the OCP-

I pin and GND and R_CIMONis the resistor between the IMON pin to the OCP-I pin that sets the current monitor

gain. Equation 1 shows the calculation for the current monitor gain.

:

;

ìÜØß×æ

H Í 8_¼Ìá1ÛÛÛ. 8

4_ÂÆÈÇ

8

ÂÆÈÇ

L sr H s E

:

;

4_È¼É

where

•

Σ V_CSis the sum of the DC voltages at the inputs to the current sense amplifiers

(1)

To ensure stable current monitor operation and at the same time provide a fast dynamic response, connect a

capacitor with a value between 4.7-nF and 10-nF between the IMON pin and GND.

Set the analog current monitor so that at the maximum processor current (I_CC(max)) level, the IMON voltage is 1.7

V. This corresponds to a digital output current value of ‘FF’ in register 03H.

7.3.9 Addressing

The TPS53632G device can be configured for three different base addresses by setting a voltage on the SLEWA

pin. Configure a resistor divider on SLEWA from VREF to GND. A resistor between the SLEWA pin and GND

sets the slew rate. Once the slew rate resistor is selected, the resistor from the VREF pin to the SLEWA pin can

be chosen based on the required base address. For a base address of 0, the VREF to SLEWA resistor can be

left open.

7.3.10 I²C Interface Operation

The TPS53632G device includes a slave I²C interface accessed via the SCL (serial clock) and SDA (serial data)

pins. The interface sets the base VID value, receives current monitor telemetry, and controls functions described

in this section. It operates when EN = low, with the bias supplies in regulation. It is compliant with I²C

specification UM10204, Revision 3.0. The characteristics are:

•

Addressing

–

7-bit addressing; address range is 100 0xxx (binary)

Last three bits are determined by the SLEWA pin at start-up

•

Byte read / byte write protocols only (See figures in Protocol Examples section)

Frequency

–

100 kHz

400 kHz

1 MHz

3.4 MHz

•

Logic inputs are 1.8-V logic levels (3.3-V tolerant)

12

Submit Documentation Feedback

Product Folder Links: TPS53632G

TPS53632G

www.ti.com

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

Feature Description (continued)

7.3.10.1 Key for Protocol Examples

Master Drives SDA

Slave Drives SDA

NAK

S

P

Start

Stop

W

R

Write

A

ACK

A

Read

UDG-13045

7.3.10.2 Protocol Examples

The good byte read transaction the controller ACKs and the master terminates with a NAK/stop.

S

Slave Address

W

A

Reg Address

A

S

Slave Address

R

A

Reg data

A

P

UDG-13046

Figure 5. Good Byte Read Transaction

The controller issues a NAK to the read command with an invalid register address.

S

Slave Address

W

A

Reg Address

A

UDG-13047

Figure 6. NAK Invalid Register Address

Figure 7 illustrates a good byte write.

S

Slave Address

W

A

Reg Address

A

Reg Data

A

P

UDG-13048

Figure 7. Good Byte Write

The controller issues a NAK to a write command with an invalid register address.

Slave Address Reg Address

S

W

A

UDG-13049

Figure 8. Invalid NAK Register Address

The controller issues a NAK to a write command for the condition of invalid data.

Slave Address Reg Address Reg Data

S

W

A

P

UDG-13050

Figure 9. Invalid NAK Register Data

The device executes the master code sequence shown in Figure 10 to enter Hs (3.4-MHz SCL) mode.

Submit Documentation Feedback

13

Product Folder Links: TPS53632G

TPS53632G

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

www.ti.com

Feature Description (continued)

S

8'b00001xxx

A

UDG-13051

Figure 10. Master Code Sequence

7.3.11 Start-Up Sequence

The TPS53632G initializes when all of the supply voltages rise above the UVLO thresholds. This function is also

know as a cold boot. The device then reads all of the various settings (such as frequency and overcurrent

protection). This process takes less than 1.2 ms. During this time, the VSR pin initializes to the BOOT voltage.

The output voltage rises to the voltage select register (VSR) level when the EN pin (enable) goes high. As soon

as the BOOT sequence completes, PGOOD is HIGH and the I²C interface can be used to change the voltage

select register. The current VSR value is held when EN goes low and returns to a high state This function is also

know as a warm boot). The VSR can be changed when EN is low, however, this is not recommended prior to

completion of the cold boot process.

7.3.12 Power Good Operation

PGOOD is an open-drain output pin that is designed to be pulled up with an external resistor to a voltage 3.6 V

or less. Normal PGOOD operation (exclusive of OC or MAXVID interrupt action) is shown in Figure 11. On initial

power-up, a power good status occurs within 6 µs of the DAC reaching its target value. When EN is brought low,

the PGOOD pin is also brought low for 250 µs and then is allowed to float. The TPS53632G device pulls down

the PGOOD signal when the EN signal subsequently goes high and returns high again within 6 µs of the end of

the DAC ramp. The delay period between the EN pin going high and the PGOOD pin going low in this case is

less than 1 µs.

Figure 11 shows the power good operation at initial start up and with falling and rising EN.

VBIAS

VOUT

EN

1 ms

PGOOD

1.2 ms

6 ms

250 ms

UDG-13096

Figure 11. Power Good Operation

14

Submit Documentation Feedback

Product Folder Links: TPS53632G

TPS53632G

www.ti.com

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

Feature Description (continued)

7.3.13 Fault Behavior

The TPS53632G device has a complete suite of fault detection and protection functions, including input

undervoltage lockout (UVLO) on all power inputs, overvoltage and overcurrent limiting and output undervoltage

detection. The protection limits are summarized in Table 1. The converter suspends switching when the limits are

exceeded and the PGOOD pin goes low. In this state, the fault register 14h is readable. To exit fault protection

mode, power must be cycled.

Table 1. TPS53632G VID Table

VID6

0

1

VID5

0

1

0

VID4

1

0

1

0

VID3

1

0

1

0

1

0

VID2

0

1

0

1

0

1

0

1

0

1

0

VID1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

HEX

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

40

VOLTAGE

0.5000

0.5100

0.5200

0.5300

0.5400

0.5500

0.5600

0.5700

0.5800

0.5900

0.6000

0.6100

0.6200

0.6300

0.6400

0.6500

0.6600

0.6700

0.6800

0.6900

0.7000

0.7100

0.7200

0.7300

0.7400

0.7500

0.7600

0.7700

0.7800

0.7900

0.8000

0.8100

0.8200

0.8300

0.8400

0.8500

0.8600

0.8700

0.8800

0.8900

Submit Documentation Feedback

15

Product Folder Links: TPS53632G

TPS53632G

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

www.ti.com

Table 1. TPS53632G VID Table (continued)

VID6

1

VID5

0

1

VID4

0

1

0

VID3

0

1

0

1

0

1

VID2

0

1

0

1

0

1

0

1

0

1

0

1

VID1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VID0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

HEX

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

VOLTAGE

0.9000

0.9100

0.9200

0.9300

0.9400

0.9500

0.9600

0.9700

0.9800

0.9900

1.0000

1.0100

1.0200

1.0300

1.0400

1.0500

1.0600

1.0700

1.0800

1.0900

1.1000

1.1100

1.1200

1.1300

1.1400

1.1500

1.1600

1.1700

1.1800

1.1900

1.2000

1.2100

1.2200

1.2300

1.2400

1.2500

1.2600

1.2700

1.2800

1.2900

1.3000

1.3100

1.3200

1.3300

1.3400

1.3500

1.3600

16

Submit Documentation Feedback

Product Folder Links: TPS53632G

TPS53632G

www.ti.com

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

Table 1. TPS53632G VID Table (continued)

VID6

1

VID5

1

VID4

1

VID3

0

VID2

0

VID1

0

VID0

0

HEX

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

VOLTAGE

1.3700

1.3800

1.3900

1.4000

1.4100

1.4200

1.4300

1.4400

1.4500

1.4600

1.4700

1.4800

1.4900

1.5000

1.5100

1.5200

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Submit Documentation Feedback

17

Product Folder Links: TPS53632G

TPS53632G

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

www.ti.com

7.4 Device Functional Modes

7.4.1 PWM Operation

The Functional Block Diagram and Figure 12 show how the converter operates in continuous conduction mode

(CCM).

V

CORE

I

SUM

V

DROOP

SW_CLK

Phase 1

Phase 2

Time

UDG-13007

Figure 12. D-CAP+™ Mode Basic Waveforms

Starting with the condition that the high-side FETs are off and the low-side FETs are on, the summed current

feedback (I_SUM) is higher than the error amplifier output (V_COMP). I_CMPfalls until it hits V_COMP, which contains a

component of the output ripple voltage. The PWM comparator senses where the two waveforms cross and

triggers the on-time generator, which generates the internal SW_CLK signal. Each SW_CLK signal corresponds

to one switching ON pulse for one phase.

During single-phase operation, every SW_CLK signal generates a switching pulse on the same phase. Also, I_SUM

voltage corresponds to a single-phase inductor current only.

During multi-phase operation, the controller distributes the SW_CLK signal to each of the phases in a cycle.

Using the summed inductor current and cyclically distributing the ON pulses to each phase automatically gives

the required interleaving of 360/n, where n is the number of phases.

7.5 Configuration and Programming

After the 5-V, 3.3-V, or V_INTFpower is applied to the controller (all are above UVLO level), the following

information is latched and cannot be changed anytime during operation. The Electrical Characteristics table

defines the values of the selections.

7.5.1 Operating Frequency

The resistor between the FREQ-P pin and GND sets the switching frequency. See the Electrical Characteristics

table for the resistor settings corresponding to each frequency selection.

NOTE

The operating frequency is a quasi-fixed frequency in the sense that the ON time is fixed

based on the input voltage (at the VIN pin) and output voltage (set by VID). The OFF time

varies based on various factors such as load and power-stage components.

7.5.2 Overcurrent Protection (OCP) Level

The resistor from OCP-I to GND sets the OCP level of the CPU channel. See the Electrical Characteristics table

for the resistor settings corresponding to each OCP level.

18

Submit Documentation Feedback

Product Folder Links: TPS53632G

TPS53632G

www.ti.com

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

Configuration and Programming (continued)

7.5.3 IMON Gain

The resistors from IMON to OCP-I and OCP-I to GND set the DC load current monitor (IMON) gain.

7.5.4 Slew Rate

The SetVID fast slew rate is set by the resistor from SLEWA pin to GND. See the Electrical Characteristics table

for the resistor settings corresponding to each slew rate setting.

7.5.5 Base Address

The voltage on SLEWA pin sets the device base address.

7.5.6 Ramp Selection

The resistor from RAMP to GND sets the ramp compensation level. See the Electrical Characteristics table for

the resistor settings corresponding to each ramp level.

7.5.7 Active Phases

Normally, the controller is configured to operate in 3-phase mode. To enable 2-phase mode, tie the CSP3 pin to

a 3.3-V supply and the CSN3 pin to GND. To enable 1-phase mode, tie the CSP2 and CSP3 pins to a 3.3-V

supply and tie the CSN2 and CSN3 pins to GND.

7.6 Register Maps

The I²C interface can support 400-kHz, 1-MHz, and 3.4-MHz clock frequencies. The I²C interface is accessible

even when EN is low. The following registers are accessible via I²C.

7.6.1 Voltage Select Register (VSR) (00h)

•

Type: Read and write

Power-up value: 48h. This value can be changed before the rising edge of EN to change BOOT voltage.

EN rising (after power-up): prior programmed value

See Table 1 for exact values

A command to set VSR < 19h (minimum VID) generates a NAK and the VSR remains at the prior value

b7

b6

b5

b4

b3

b2

b1

b0

–

VID[6:0]

7.6.2 IMON Register (03h)

•

Type: Read only

Power-up value: 00h

EN rising (after power-up):00h

b7

b6

b5

b4

b3

b2

b1

b0

MSB

–

LSB

7.6.3 VMAX Register (04h)

•

Type: Read / write (see below)

Power-up value: 1.28 V (OTP value)

EN rising (after power-up): Last written value

b7

b6

b5

b4

b3

b2

b1

b0

Lock

MSB

–

LSB

Submit Documentation Feedback

19

Product Folder Links: TPS53632G

TPS53632G

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

www.ti.com

Bit definitions:

BIT

NAME

DEFINITION

0 - 6

VMAX

Maximum VID setting

Access protection of the VMAX register

0: No protection, R/W access to bits 0-6

7

Lock

1: Access is read only; reset after UVLO event.

7.6.4 Power State Register (06h)

•

Type: Read and write

Power-up value: 00h

EN rising (after power-up): 00h

b7

b6

b5

b4

b3

b2

b1

b0

–

MSB

LSB

Bit definitions:

VALUE

DEFINITION

0

1

2

Multi-phase CCM

Single-phase CCM

Single-phase DCM

7.6.5 SLEW Register (07h)

•

Type: Read and write (see below)

Power-up value: Defined by SLEWA pin at power-up

EN rising (after power-up): Last written value

Write only a single ‘1’ for the SLEW rate desired

b7

b6

b5

b4

b3

b2

b1

b0

48 mV/µs

42mV/µs

36 mV/µs

30 mV/µs

24 mV/µs

18 mV/µs

12 mV/µs

6 mV/µs

7.6.6 Lot Code Registers (10-13h)

•

Type: 8-bits; read only

Power-up value: Programmed at factory

7.6.7 Fault Register (14h)

•

Type: 8-bits; read only

Power-up value: 00h

b7

b6

b5

b4

b3

b2

b1

b0

–

Device thermal

shutdown

OVP

UVP

OCP

20

Submit Documentation Feedback

Product Folder Links: TPS53632G

TPS53632G

www.ti.com

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

8 Applications and Implementation

8.1 Application Information

The TPS53632G device has a very simple design procedure. A Microsoft Excel^®-based component value

calculation tool is available. Please contact your local TI representative to get a copy of the spreadsheet.

8.2 Typical Application

Submit Documentation Feedback

21

Product Folder Links: TPS53632G

TPS53632G

www.ti.com

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

8.2.1.1 Design Requirements

Design example specifications:

•

Input voltage range: 36 V to 72 V

V_OUT= 1.0 V

I_CC(max)= 50 A

Slew rate (minimum): 12 mV/µs

No Load Line

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Step 1: Select Switching Frequency

The switching frequency is selected by a resistor (R_F) between the FREQ_P pin and GND. The frequency is

approximate and expected to vary based on load and input voltage.

Table 2. TPS53632G Device Frequency Selection Table

SELECTION

RESISTOR (R_F) VALUE (kΩ)

OPERATING FREQUENCY

(f_SW) (kHz)

20

24

300

400

500

600

700

800

900

1000

30

39

56

75

100

150

For this design, choose a switching frequency of 300 kHz. So, R_F= 20 kΩ.

8.2.1.2.2 Step 2: Set The Slew Rate

A resistor to GND (R_SLEWA) on SLEWA pin sets the slew rate. For a minimum 12 mV/µs slew rate, the resistor

R_SLEWA= 24 kΩ.

Table 3. Slew Rate Versus Selection Resistor

SELECTION RESISTOR

MINIMUM SLEW RATE

(mV/µs)

R_SLEWA(kΩ)

20

24

6

12

18

24

30

36

42

48

30

39

56

75

100

150

NOTE

The voltage on the SLEWA pin also sets the base address. For a base address of 00, the

SLEWA pin should have only one resistor, R_SLEWto GND. For other base addresses, a

resistor can be connected between the SLEWA pin and the VREF pin (1.7 V). This

resistor can be calculated to set the corresponding voltage for the required address listed

in Table 4.

Submit Documentation Feedback

23

Product Folder Links: TPS53632G

TPS53632G

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

www.ti.com

Table 4. Address Selection

SLEWA

BASE

VOLTAGE

ADDRESS

V_SLEWA≤ 0.30 V

0

1

2

3

4

5

6

7

0.35 V ≤ V_SLEWA≤ 0.45 V

0.55 V ≤ V_SLEWA≤ 0.65 V

0.75 V ≤ V_SLEWA≤ 0.85 V

0.95 V ≤ V_SLEWA≤ 1.05 V

1.15 V ≤ V_SLEWA≤ 1.25 V

1.35 V ≤ V_SLEWA≤ 1.45 V

1.55 V ≤ V_SLEWA≤ 1.65 V

8.2.1.2.3 Step 3: Determine Inductor Value And Choose Inductor

Applications with smaller inductor values have better transient performance but also have higher voltage ripple

and lower efficiency. Applications with higher inductor values have the opposite characteristics. It is common

practice to limit the ripple current between 20% and 40% of the maximum current per phase. In this case, use

30%.

80 A

( )

3

I_P-P

=

´ 0.4 = 10.6 (A)

(2)

(3)

V ´ dT

L =

I

P-P

In this equation,

V = V

- V_OUT= 13V

IN max

(

)

(4)

(5)

V_OUT

f ´ V

dT =

= 238ns

)

(

IN max

(

)

So, calculating, L = 0.29 µH.

Choose an inductance value of 0.3 µH. The inductor must not saturate during peak loading conditions.

I

æ

ç

ö

÷

CC max

(

I

)

P-P

I

=

+

´1.2 = 38.4A

SAT

ç

è

÷

ø

n

2

where

•

n is the number of phases

(6)

The factor of 1.2 allows for current sensing and current limiting tolerances.

The chosen inductor should have the following characteristics:

•

As flat as an inductance versus current curve as possible. Inductor DCR sensing is based on the idea L /

DCR is approximately a constant through the current range of interest

•

Either high saturation or soft saturation

Low DCR for improved efficiency, but at least 0.6 mΩ for proper signal levels

DCR tolerance as low as possible for load-line accuracy

For this application, choose a 0.3-µH, 0.29-mΩ inductor.

8.2.1.2.4 Step 4: Determine Current Sensing Method

The TPS53632G device supports both resistor sensing and inductor DCR sensing. Inductor DCR sensing is

chosen. For resistor sensing, substitute the resistor value for R_CS(eff)in the subsequent equations.

24

Submit Documentation Feedback

Product Folder Links: TPS53632G

TPS53632G

www.ti.com

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

8.2.1.2.5 Step 5: DCR Current Sensing

Design the thermal compensation network and selection of OCP. In most designs, NTC thermistors are used to

compensate thermal variations in the resistance of the inductor winding. This winding is generally copper, and so

has a resistance coefficient of 3900 PPM/°C. NTC thermistors, as an alternative, have very non-linear

characteristics and need two or three resistors to linearize them over the range of interest. A typical DCR circuit

is shown in Figure 14.

L

R_DCR

I

R_SEQU

R_NTC

R_SERIES

R_PAR

C_SENSE

CSP

CSN

UDG-12199

Figure 14. Typical DCR Sensing Circuit

In this design example, the voltage across the C_SENSEcapacitor exactly equals the voltage across R_DCRwhen:

L

- C

´R

EQ

SENSE

R

DCR

(7)

æ

ç

ö

÷

R_{P _N}´R_SEQU

R_EQ

=

ç

R

_SEQU+ R_{P _N}

(

)

è

ø

where

•

R_EQis the series (or parallel) combination of R_SEQU, R_NTC, R_SERIESand R_PAR

(8)

(9)

R

´ R

(

+ R

)

PAR

NTC

SERIES

R

=

P _N

R

+ R

PAR

Ensure that C_SENSEis a capacitor type which is stable over temperature. Use X7R or better dielectric (C0G

preferred).

Because calculating these values by hand is difficult, TI offers a spreadsheet using the Excel solver function

available to calculate them for you. Contact a TI representative to get a copy of the spreadsheet.

In this design, the following values are input to the spreadsheet.

•

L = 0.3 µH

R_DCR= 0.29 mΩ

Minimum Overcurrent Limit = 110 A

Thermistor R25 = 10 kΩ and “B” value = 3380 kΩ

The spreadsheet then calculates the OCP setting and the values of R_SEQU, R_SERIES, R_PAR, and C_SENSE. In this

case, the OCP setting is the value of the resistor that is conencted between the OCP-I pin and GND. (100 kΩ )

The nearest standard component values are:

•

R_SEQU= 1.47 kΩ

R_SERIES= 1.65 kΩ

R_PAR= 30.1 kΩ

C_SENSE= 680 nF

Submit Documentation Feedback

25

Product Folder Links: TPS53632G

TPS53632G

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

www.ti.com

Consider the effective divider ratio for the inductor DCR. Equation 10 shows the effective current sense

resistance (R_CS(eff)calculation.

R_{P _N}

R_{CS eff}= R_DCR

´

( )

R

_SEQU+ R_{P _N}

where

•

R_{P_N}is the series and parallel combination of R_NTC, R_SERIES, and R_PAR

(10)

(11)

R

´ R

+ R

(

)

PAR

NTC

SERIES

R

=

P _N

R

+ R

PAR

where

•

R_CS(eff)is 0.244 mΩ

8.2.1.2.6 Step 6: Select OCP Level

Set the OCP threshold level that corresponds to Equation 12.

I

_VALLEY´R_{CS eff}= V_{CS ocp}

( )

(

)

(12)

(13)

I

OCP

I

=

- 0.5 -I

RIPPLE

VALLEY

N

PH

Table 5. OCP Selection⁽¹⁾

SELECTION RESISTOR

TYPICAL V_CS(OCP)

(mV)

R_OCP(kΩ)

20

24

4

8

30

13

19

25

32

40

49

39

56

75

100

150

(1) If a corresponding match is not found, then select the next higher

setting.

8.2.1.2.7 Step 7: Set the Load-Line Slope

The load-line slope is set by resistor, R_DROOP(between the DROOP pin and the COMP pin) and resistor R_COMP

(between the COMP pin and the VREF pin). The gain of the DROOP amplifier (A_DROOP) is calculated in

Equation 14.

æ

ç

è

ö

R

(

_CS(eff)´ A_CS

æ

ö

÷

ø

)

æ

ç

è

ö

÷

ø

R_DROOP

0.244m´ 6

1.0m

÷

A_DROOP= 1+

=

= 1.46

ç

è

÷

ø

R_COMP

R_LL

(14)

(15)

Set the value of R_DROOPto 10 kΩ, R_COMPas shown in Equation 15.

R_DROOP

R_COMP

=

= 21.5kW

A

-1

(

)

DROOP

Based on measurement, this value is adjusted to 9.75 kΩ.

NOTE

See Loop Compensation for Zero Load-Line for zero-load line.

26

Submit Documentation Feedback

Product Folder Links: TPS53632G

TPS53632G

www.ti.com

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

8.2.1.2.8 Step 8: Current Monitor (IMON) Setting

Set the analog current monitor so that at I_CC(max)the IMON pin voltage is 1.7 V. This corresponds to a digital I_OUT

value of ‘FF’ in I²C register 03H. The voltage on the IMON pin is shown in Equation 16.

:

;

ìÜØß×æ

H Í 8_¼Ìá1ÛÛÛ. 8

4_ÂÆÈÇ

8

ÂÆÈÇ

L sr H s E

:

;

4_È¼É

(16)

So,

æ

ö

÷

ø

R

IMON

1.7 = 10´ 1+

´R

´I

ç

CS eff

CC max

(

( )

)

R

OCP

è

where

•

I_CC(max)is 80 A

R_CS(eff)is 0.244 mΩ

R_OCPis 24 kΩ

(17)

Solving, R_IMON= 169 kΩ. R_IMONis connected from IMON pin to OCP-I pin.

Submit Documentation Feedback

27

Product Folder Links: TPS53632G

TPS53632G

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

www.ti.com

8.2.1.3 Application Performance Plots

1.005

1

96

93

90

87

84

81

78

75

72

69

66

63

60

57

36V Input

48V Input

60V Input

75V Input

0.995

0.99

0.985

0.98

0.975

0.97

0.965

36V Input

48V Input

60V Input

75V Input

0

5

10

15

20

25

30

35

40

45

50

0

5

10 15 20 25 30 35 40 45 50 55

Output Current (A)

D001

V_OUT= 1 V

Figure 15. Output Voltage vs Output Current

Figure 16. Efficiency vs Output Current

660

656

652

648

644

640

636

632

628

624

620

1.6

1.4

1.2

1

36V Input

48V Input

60V Input

75V Input

0.8

0.6

0.4

0.2

0

36V Input

75V Input

0

5

10

15

20

25

30

35

40

0

5

10

15

20

25

30

35

40

Output Current (A)

D001

V_OUT= 1 V

Figure 17. Switching Frequency vs Output Current

Figure 18. IMON Voltage vs Output Current

28

Submit Documentation Feedback

Product Folder Links: TPS53632G

TPS53632G

www.ti.com

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

8.2.1.4 Loop Compensation for Zero Load-Line

The TPS53632G device control architecture (current mode, constant on-time) has been analyzed by the Center

for Power Electronics Systems (CPES) at Virginia Polytechnic and State University. The following equations are

from the presentation: Equivalent Circuit Representation of Current-Mode Control from November 21, 2008.

A simplified control loop diagram is shown in Figure 19. One of the benefits of this technology is the lack of the

sample and hold effect that limits the bandwidth of fixed frequency current mode controllers and causes sub-

harmonic oscillations.

The open loop gain, G_OL, is the gain of the error amplifier, multiplied by the control-to-output gain and is

calculated in Equation 18.

G

= G

´ G

OL

COMP CO

(18)

The control-to-output gain circuitry is shown in Figure 19.

COMP

DROOP

Current Sense

Amplifier

R1

DAC

+

Voltage

Amplifier

C2

ESR

C1

I_SUM

C1

R_LOAD

R2

VREF

Figure 19. Control To Output Gain Circuitry

The control-to-output gain is calculated in Equation 19.

w´R_ESR´ C_OUT+1

v_O

v_C

(

)

1

= K_C

´

2

æ

ö

÷

ø

æ

ç

è

ö

÷

ø

w

w_a

æ

ç

è

ö

÷

ø

w

+1

1+

+ ç

2

w₁

ç

Q₁´ w₁

è

where

æ

ç

è

ö

R_LOAD

÷

R_i

ø

K_C

=

æ

ç

è

ö

÷

ø

t_ON´R_LOAD

2´L_S

1+

•

p

w =

1

t

ON

2

Q =

1

p

V

OUT

t

=

ON

V

´ f

SW

•

IN

Submit Documentation Feedback

29

Product Folder Links: TPS53632G

TPS53632G

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

www.ti.com

æ

ç

è

ö

÷

ø

t_ON´R_LOAD

2´L_S

1+

w_a=

æ

ö

÷

ø

æ

ç

è

ö

÷

ø

t_ON´R_LOAD

2´L_S

R_LOAD´ C_OUT´ 1+

ç

è

•

(19)

For this converter, R_i= R_CS(eff)× A_CS

The theoretical control-to-output transfer function shows 0-dB bandwidth is approximately 20 kHz and the phase

margin is greater than 90°. As a result, creating the desired loop response is a matter of adding an appropriate

pole-zero or pole-zero-pole compensation for the high-gain system.

The loop compensation is designed to meet the following criteria:

1. Phase margin ≥ 60°

(a) More stable and settles more quickly for repetitive transients

f

SW

³ BW ³

2. Bandwidth:

5

3

(a) High-enough BW for good transient response.

(b) If too high, the response for the voltage changes gets very “bumpy”, as each voltage step causes several

pulses very quickly.

3. The phase angle of the compensation at the switching frequency needs to be very near to 0 degrees

(resistive)

(a) Otherwise, there is a phase shift between DROOP and ISUM

(b) Practically, this means the zero frequency should be < f_SW/ 2, and any high-frequency pole (for noise

rejection) needs to be > 2 × f_SW

.

The voltage error amplifier is used in the design. The compensation technique used here is a type II

compensator. Equation 20 describes the transfer function, which has a pole that occurs at the origin. The type II

amplifier also has a 0 (f_Z) that can be programmed by selecting R1 and C1 values. In addition, the type II

compensation network has a pole (f_P) that can be programmed by selecting R1 and C2.

s´R1´ C1+1

(

)

1

G

=

´

COMP

s´ C1+ C2 ´R2

C1´ C2

C1+ C2

æ

ö

(

)

s´R1´

+1

ç

è

÷

ø

(20)

(21)

1

f

=

Z

2p´R1´ C1

1

f =

P

C1´ C2

æ

ö

2p´R1´

ç

÷

C1+ C2

è

ø

(22)

R1 sets the loop crossover to correct for the gain at control to output function. In this design, select R2 = 2 kΩ.

-G

æ

ö

CO fc

( )

-10dB

20

æ

ö

ç

è

÷

ø

-

ç

è

÷

ø

20

R1= R2´10

= 2kW´10

(23)

Capacitor C1 adds phase margin at crossover frequency and can be set between 10% and 20% of the switching

frequency.

1

C1=

2p´ f

´ 0.1´R1

SW

(24)

The last consideration for the voltage loop compensation design is C2. The purpose of C2 is to cancel the phase

gain caused by the ESR of the output capacitor in the control-to-output function after the loop crossover. To

ensure the gain continues to roll off after the voltage loop crossover, the C2 is selected to meet Equation 25.

C_OUT´ESR

C2 =

R1

(25)

30

Submit Documentation Feedback

Product Folder Links: TPS53632G

TPS53632G

www.ti.com

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

9 Power Supply Recommendations

This device is designed to operate from a supply voltage at the V5A pin (5-V power input for analog circuits) from

4.5 V to 5.5 V and a supply voltage at the VDD pin (3.3-V digital power input) from 3.1 V to 3.5 V, and a supply

voltage at the VINTF pin from 1.7 V to 3.5 V. Use only a well-regulated supply. The VIN pin input must be

connected to the conversion input voltage and must not exceed 28 V. Proper bypassing of the V5A and VDD

input supplies is critical for noise performance, as is PCB layout and grounding scheme. See the

recommendations in the Layout section.

10 Layout

10.1 Layout Guidelines

10.1.1 PCB Layout

•

Check the pinout of the controller on schematic against the pinout of the datasheet.

Have a component value calculator tool ready to check component values.

Carefully check the choice of inductor and DCR.

Carefully check the choice of output capacitors.

Because the voltage and current feedback signals are fully differential, double check their polarity.

–

CSP1 / CSN1

CSP2 / CSN2

VOUT_SENSE to VFB / GND_SENSE to GFB

•

Make sure the pull-up on the SDA, and SCL lines are correct. Ensure there is a bypass capacitor close to the

device on the pull-up VINTF rail to GND of the device.

TI strongly recommends that the device GND be separate from the system and Power GND.

Most Critical Layout Rule

Make sure to separate noisy driver interface lines.

The driver is outside of the device. All gate-drive and switch-node traces must be local to the inductor and

MOSFETs.

10.1.2 Current Sensing Lines

Given the physical layout of most systems, the current feedback (CSPx and CSNx) may have to pass near the

power chain.

Submit Documentation Feedback

31

Product Folder Links: TPS53632G

TPS53632G

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

www.ti.com

Layout Guidelines (continued)

boisy

vuiet

Lnductor

hutline

[[_x

ë_/hw9

/{bx

/{ꢁx

w

{9v

w

{9wL9{

Çꢀermistor

UDG-12198

Figure 20. Kelvin Connections To The Inductor For DCR Sensing

Good load-line, current sharing, and current limiting performance of the TPS53632G device requires clean

current feedback, so take the following precautions:

•

Ensure all vias in the CSPx and CSNx traces are isolated from all other signals.

TI recommends dotted signal traces be run in internal planes.

If possible, change the name of the CSNx trace if possible to prevent automatic ties to the V_COREplane.

Put R_SEQUat the boundary between noisy and quiet areas.

Run CSPx and CSNx as a differential pair in a quiet layer.

Place the capacitor as near to the device pins as possible.

Make a Kelvin connection to the pads of the resistor or inductor used for current sensing. See Figure 20 for a

layout example.

•

Run the current feedback signals as a differential pair to the device.

Run the lines in a quiet layer. Isolate the lines from noisy signals by a voltage or ground plane.

Put the compensation capacitor for DCR sensing (C_SENSE) as close to the CS pins as possible.

Place any noise filtering capacitors directly under or near the TPS53632G device and connect to the CS pins

with the shortest trace length possible.

10.1.3 Feedback Voltage Sensing Lines

The voltage feedback coming from the CPU socket must be routed as a differential pair all the way to the VFB

and GFB pins of the TPS53632G device. Avoid routing over switch-node and gate-drive traces.

10.1.4 PWM And SKIP Lines

The PWM and SKIP lines should be routed from the TPS53632G device to the driver without crossing any

switch-node or the gate drive signals.

10.1.4.1 Minimize High Current Loops

Figure 21 shows the primary current loops in each phase, numbered in order of importance.

32

Submit Documentation Feedback

Product Folder Links: TPS53632G

TPS53632G

www.ti.com

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

Layout Guidelines (continued)

V_BAT

C_IN

C_B

1

Q1

4b

DRVH

4a

L

V_CORE

LL

2

Q2

C_D

DRVL

3a

C_OUT

3b

PGND

UDG-12191

Figure 21. Major Current Loops To Minimize

The most important loop to minimize the area of is loop 1, the path from the input capacitor through the high and

low-side FETs, and back to the capacitor through ground.

Loop 2 is from the inductor through the output capacitor, ground, and Q2. The layout of the low-side gate drive

(Loops 3a and 3b) is important. The guidelines for the gate drive layout are:

•

Make the low-side gate drive as short as possible (1 in or less preferred).

Make the DRVL width to length ratio of 1:10, wider (1:5) if possible.

If changing layers is necessary, use at least two vias.

10.1.5 Power Chain Symmetry

The TPS53632G device does not require special care in the layout of the power chain components because

independent isolated current feedback is provided. Lay out the phases in a symmetrical manner, if possible. The

rule is: the current feedback from each phase needs to be clean of noise and have the same effective current-

sense resistance.

10.1.6 Component Location

Place components as close to the device in the following order.

1. CS pin noise filtering components

2. COMP pin and DROOP pin compensation components

3. Decoupling capacitors for VREF, VDD, V5A, and VINTF

4. Decoupling capacitor for VINTF rail, which is pullup voltage for the digital lines. This decoupling should be

placed near the device to have good signal integrity.

5. OCP-I resistors, FREQ_P resistors, SLEWA resistors, and RAMP resistors

10.1.7 Grounding Recommendations

The TPS53632G device has an analog ground and a thermal pad. The usual procedure for connecting these is:

•

Keep the analog GND of the device and the power GND of the power circuit separate. The device analog

GND and the power circuit power GND can be connected at one single quiet point in the layout.

•

The thermal pad does not have an electrical connection to device. But the thermal pad must be connected to

GND pin (pin 29) of the device to give good ground shielding. Do not connect the thermal pad to system

GND.

•

Tie the thermal pad to a ground island with at least 4 vias. All the analog components can connect to this

analog ground island.

The analog ground can be connected to any quiet spot on the system ground. A quiet spot is defined as a

Submit Documentation Feedback

33

Product Folder Links: TPS53632G

TPS53632G

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

www.ti.com

Layout Guidelines (continued)

spot where no power supply switching currents are likely to flow. Use a single point connection from analog

ground to the system ground.

•

Ensure that the low-side MOSFET source connection and the input decoupling capacitors have a sufficient

number of vias.

10.1.8 Decoupling Recommendations

•

Decouple V5A and VDD to GND with a ceramic capacitor (with a value of at least 1 µF) .

Decouple VINTF to GND with a capacitor (with a value of at least 0.1 µF) to GND.

10.1.9 Conductor Widths

•

Follow TI guidelines with respect to the voltage feedback and logic interface connection requirements.

Maximize the widths of power, ground, and drive signal connections.

For conductors in the power path, be sure there is adequate trace width for the amount of current flowing

through the traces.

•

Make sure there are sufficient vias for connections between layers. Use 1 via minimum per ampere of current.

10.2 Layout Example

1.8 V and IMON to GND

decoupling capacitor

PWM

signals

Differential routing

of CSP and CSN in

quiet internal layers.

V5A, VREF, VCCIO

and VDD decoupling

capacitor to analog GND

Differential routing

of VFB and GFB

I²C Interface

signals

Compensation

Network

Figure 22. Example Layout

11 Device and Documentation Support

11.1 Trademarks

D-CAP+ is a trademark of Texas Instruments.

Excel is a registered trademark of Microsoft Corporation.

All other trademarks are the property of their respective owners.

34

Submit Documentation Feedback

Product Folder Links: TPS53632G

TPS53632G

www.ti.com

SLUSCJ3A –APRIL 2016–REVISED JUNE 2016

11.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.3 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Documentation Feedback

35

Product Folder Links: TPS53632G

GENERIC PACKAGE VIEW

RSM 32

4 x 4, 0.4 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224982/A

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS53632GRSMR
厂家：	TEXAS INSTRUMENTS
描述：	用于 48V GaN 直流/直流转换器的半桥 D-CAP+ 控制器 \| RSM \| 32 \| -10 to 105 控制器开关转换器
文件：	总39页 (文件大小：2150K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS53632GRSMR [TI]

相关型号：

TPS53632GRSMT

TPS53632RSMR

TPS53632RSMT

TPS53640

TPS53640A

TPS53640ARSBR

TPS53640ARSBT

TPS53640RSBR

TPS53640RSBT

TPS53641

TPS53641RSBR

TPS53641RSBT