TPS53667_技术文档

Support &

Community

Product

Folder

Order

Now

Tools &

Software

Technical

Documents

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

TPS53667 6 相 D-CAP+ 降压控制器，具有 NVM

和 PMBus™ 接口，适用于 ASIC 电源和高电流负载点

1 特性

3 说明

1

•

通过引脚设置或 NVM 实现的 8 位可选启动电

TPS53667 是一款高电流多相位降压控制器。该器件

压：0.5V 至 2.5V（步长低至 5mV）

提供内置非易失性存储器 (NVM) 和 PMBus 接口。此

款产品与 NexFET 功率级 (CSD9549x) 兼容。

TPS53667 提供 8 位启动电压选择，输出电压范围为

0.5V 到 2.5V，步长低至 5mV，非常适合具备精确输

出电压设置的高电流应用。具有 D-CAP+ 架构等高级

特性，支持下冲衰减 (USR) 和过冲衰减 (OSR)，可实

现快速瞬态响应、最小的输出电容和高效率。

•

1 相、2 相、3 相、4 相、5 相或 6 相操作

PMBus™用于电压、电流、功率、温度和故障条件

遥测的系统接口

•

兼容 1.8V 和 3.3V PMBus 偏置电压

故障报告：输出电压、输出电流和温度

可通过非易失性存储器 (NVM) 或电阻引脚设置来配

置

TPS53667 还提供新型相位交错策略和动态相位减少

功能，可有效提升轻负载条件下的效率。此

•

可通过引脚设置或 NVM 编程设定 16个等级各相

OCL

外，TPS53667 支持 PMBus 通信接口，适用于电压、

电流、功率、温度和故障条件遥测系统。部分配置可通

过引脚设置或 PMBus 编程设定并存储在非易失性存储

器中，这样可尽量减少外部组件的数量。

•

快速瞬态响应， DCAP+™控制

优化了轻负载与重负载条件下的效率

支持预偏置启动

相电流不均衡检测和报告

TPS53667 采用节省空间、耐热增强型 40 引脚 QFN

封装，额定运行温度介于 -40°C 至 125°C 之间。

8 级独立的过冲衰减 (OSR) 和下冲衰减 (USR)

无驱动器配置，有助于实现高效的高频开关

与 CSD9549x NexFET™功率级完全兼容

精确的可调电压配置

器件信息⁽¹⁾

器件型号

封装

封装尺寸（标称值）

300kHz 至 1MHz 频率选择，采用闭环频率控制

已获专利 AutoBalance™相位均衡

使用 TI 的Fusion Digital Power Designer GUI

可编程电流阈值的动态相位减少功能

转换电压范围：4.5V 至 17V

TPS53667

QFN (40)

6.00mm x 6.00mm

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

简化电路原理图

TPS53667

小型 6mm x 6mm、40 引脚 QFN PowerPAD™封

装

PWM1

Power

Stage

CSP1

2 应用范围

•

通信设备专用集成电路 (ASIC) 电源

高密度电源解决方案

服务器电源

PWM2

PMBus

Power

Stage

CSP2

智能电源系统

PWM6

Power

Stage

CSP6

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLUSC40

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

4 修订历史记录

Changes from Revision A (September 2016) to Revision B

Page

•

Updated V3R3 LDO section ................................................................................................................................................. 20

已添加 temperature default value VR_HOT and VR_FAULT Indication section................................................................. 33

Corrected factory default value of VOUT_OV_FAULT_RESPONSE command in 表 7 ...................................................... 40

Corrected factory default value of VIN_OV_FAULT_LIMIT command in 表 7 ..................................................................... 40

Corrected factory default value of MFR_ID command in 表 7.............................................................................................. 41

Corrected factory default value of MFR_SPECIFIC_44 command in 表 7........................................................................... 42

Changes from Original (July 2016) to Revision A

Page

•

已更改将数据表的状态从产品预览改为生产数据 ................................................................................................................... 1

已添加接收文档更新通知部分........................................................................................................................................... 117

已添加社区资源部分 ......................................................................................................................................................... 117

2

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

5 Pin Configuration and Functions

RTA Package

40-Pin QFN

Top View

40 39 38 37 36 35 34 33 32 31

1

2

30

29

28

27

26

25

24

23

22

21

OCL-R

IMON

CSP1

CSP2

CSP3

CSP4

CSP5

CSP6

VSP

O-USR

SLEW-MODE

ADDR-TRISE

VR_FAULT

PMB_DIO

PMB_ALERT

PMB_CLK

ENABLE

3

4

5

TPS53667

6

7

Thermal Pad

8

9

GND

10

VSN

RESET

11 12 13 14 15 16 17 18 19 20

Pin Functions

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

Voltage divider to VREF pin. A resistor (R_ADDR-TRISE) connected between this pin and GND sets the

3-bits. Bit 2 and bit 1 set the rise slew rate. Bit 0 Selects the LSB of BOOT voltage. The voltage

(V_ADDR-TRISE) sets 4 bits PMBus address. The device latches these settings when V3R3 powers up.

ADDR-TRISE

28

I

Output of the g_Merror amplifier. Resistors and capacitors connected between this pin and the VREF

pin set the compensation.

COMP

11

O

CSP1

CSP2

CSP3

CSP4

CSP5

CSP6

ENABLE

3

4

Positive current sense inputs. Connect to the IOUT pin of TI smart power stages (ex: CSD9549x). Tie

CSP6, CSP5, CSP4, CSP3, or CSP2 to the V3R3 pin according to 表 3 to disable the corresponding

phase.

5

I

6

7

8

23

I

VR enable. 1-V I/O level; 100-ns debounce.

Voltage divider to VREF pin. A resistor (R_F-IMAX) connected between this pin and GND sets the

operating frequency of the controller. The voltage level (V_F-IMAX) sets the maximum operating current

of the converter. The IMAX value is an 8-bit A/D where V_F-IMAX= V_VREF× I_MAX/ 255. Both are latched

at V3R3 power-up.

F-IMAX

32

GND

17

20

22

G

Ground pin.

Connect these pins to GND. Note this is not IC ground pin.

(1) I = Input, O = Output, P = Power, I/O = Bi-directional, GND = ground

3

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

Pin Functions (continued)

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

I ´ 5mW ´R

O

IMON

2

O

V

=

IMON

Analog current monitor output.

35kW

A resistor (R_ISUM) connected between this pin and VREF pin determines the droop.

I_O´ 5mW ´ g_{M isum}´R_ISUM

(

)

ISUM

12

V

=

+ V_REF

ISUM

n

(where n is the number of phases)

A resistor (R_OCL-R) connected between this pin and GND and the voltage level (V_OCL-R) select 1 of 16

OCL levels (per phase current-limit). V_OCL-Ralso sets one of four RAMP levels. The device latches

these settings when V3R3 powers up.

OCL-R

O-USR

1

I

Voltage divider to VREF pin. A resistor (R_O-USR) connected between this pin and GND selects one of

seven OSR thresholds or OFF. The voltage level (V_O-USR) sets one of seven USR levels or OFF. The

device latches these settings when V3R3 powers up.

30

PMB_ALERT

PMB_CLK

PMB_DIO

PWM1

25

24

26

38

37

36

35

34

33

O

I

I²C PMBus interrupt line. Open drain. 3.3-V and 1.8-V logic level.

I²C PMBus clock. 3.3-V and 1.8-V logic level.

I²C PMBus digital I/O line. 3.3-V and 1.8-V logic level.

I/O

PWM2

PWM3

O

PWM signals for each phase

PWM4

PWM5

PWM6

Reset pin. If this pin is low for more than 1000 ns, the controller pulls the output voltage to the V_BOOT

level.

RESET

21

I

A resistor (R _SKIP-NVM) connected between this pin and GND sets either pinstrap or NVM configuration

mode. This pin can also connect to the FCCM pin of TI smart power stages (ex: CSD9549x) for SKIP

or FCCM operation.

SKIP-NVM

39

O

Voltage divider to VREF pin. A resistor (R_SLEW-MODE) connected between this pin and GND sets 8

slew rates. The voltage level (V_SLEW-MODE) sets 4-bit operation modes. Bit 7 for DAC mode (1 for

VR12.0; 0 for VR12.5). Bit 6 for the 4-phase interleaving mode (1 for 1/3 and 2/4 two phase

interleaving; 0 for 4 phase interleaving individually). Bit 4 for enabling dynamic phase add or drop (1

for enable; 0 for disable). Bit 3 sets zero load-line (1 for zero load-line; 0 for non-zero load-line) The

device latches these settings when V3R3 powers up.

SLEW-MODE

29

I

Connect to the TAO/FAULT pin of TI smart power stages (ex: CSD9549x) to sense the highest

temperature of the power stages and to sense the fault signal from the power stages.

TSEN

V3R3

V5

40

14

15

I

O

P

3.3-V LDO output. Bypass this pin to GND with a ceramic capacitor with a value of 1-µF or larger.

5-V power input. Bypass this pin to GND with a ceramic capacitor with a value of 1-µF or larger. This

pin is used to power all internal analog circuits.

Voltage divider to VREF pin. A resistor (R_VBOOT) connected between this pin and GND sets 3 bits

(B[3:1]). The voltage level (V_VBOOT) sets 4 bits (B[7:4]). The total 7 bits set 7 of 8 bits of VID of boot

voltage (B[7:1]). The device latches these settings when V3R3 powers up.

VBOOT

31

I

Input voltage supply. This pin is also used for input voltage sensing for on-time control and input

undervoltage lockout (UVLO).

VIN

16

18

P

Power good open-drain output for the controller. This pin is typically pulled up to V3R3 pin through a

resistor with a value of 3-kΩ or larger.

VR_RDY

O

VR fault indicator (open-drain). The failures include shorts of the high-side FETs, over temperature,

output overvoltage, and overcurrent conditions of the input. The fault signal should be used on the

platform to remove the power source either by firing a shunting SCR to blow a fuse or by turning off

the AC power supply. When the failure occurs, the VR_FAULT pin is LOW. This pin is typically pulled

up to V3R3 pin through a resistor with a value of 3-kΩ or larger. Leave this pin floating if not used.

VR_FAULT

VR_HOT

27

19

O

Thermal flag open drain output. Active low. This pin is typically pulled up to V3R3 pin through a

resistor with a value of 3-kΩ or larger. Leave this pin floating if not used.

4

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

Pin Functions (continued)

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

1.7-V, 500-µA, LDO reference voltage. Bypass this pin to GND with a ceramic capacitor with a value

of 0.33 µF. Connect the VREF pin to the REFIN pin of TI smart power stages (ex: CSD9549x) as the

current-sense reference voltage.

VREF

13

O

VSN

10

9

I

Negative input of the remote voltage sense amplifier. Connect this pin directly to the GND of the load.

Positive input of the remote voltage sense amplifier. Connect this pin directly to the load.

VSP

Thermal Pad

GND Thermal pad. Connect the thermal pad to the ground plane with multiple vias.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1) (2)

MIN

–0.3

MAX

19

UNIT

VIN

V5

6

ADDR-TRISE, CSP1, CSP2, CSP3, CSP4, CSP5, CSP6, ENABLE, F-IMAX, OCL-

R, O-USR, PMB_CLK, PMB_DIO, RESET, SLEW-MODE, VBOOT, VSP

Input Voltage

–0.3

3.6

V

TSEN

–0.3

6

0.3

1.8

GND, VSN

VREF

IMON, ISUM,PMB_ALERT, PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, SKIP-

NVM, V3R3, VR_RDY, VR_FAULT, VR_HOT

Output Voltage

–0.3

3.6

V

COMP

–0.3

–40

6

Operating Junction Temperature, T_J

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to the network ground terminal GND unless otherwise noted.

6.2 Handling Ratings

MIN

–55

-2.5

MAX

150

2.5

UNIT

T_stg

Storage temperature range

°C

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

Electrostatic

discharge

V_(ESD)

kV

Charged device model (CDM), per JEDEC specification JESD22-C101,

all pins⁽²⁾

-1.5

1.5

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

NOM

MAX

UNIT

VIN

12

17

5.5

TSEN

-0.1

4.5

V5

5

5.5

ADDR-TRISE, F-IMAX, OCL-R, O-USR, SLEW-MODE,

VBOOT

0.1

V_VREF

V_I

Input voltage

V

CSP1, CSP2, CSP3, CSP4, CSP5, CSP6, VSP

–0.1

-0.1

2.5

3.5

ENABLE, PMB_CLK, PMB_DIO

GND, VSN

VREF

0.1

1.72

3.5

V3R3

3.3

V_O

Output voltage

V

IMON, ISUM, PMB_ALERT, PWM1, PWM2, PWM3, PWM4,

PWM5, PWM6, SKIP-NVM, VR_RDY, VR_FAULT, VR_HOT

–0.1

3.5

COMP

–0.1

–40

5.5

T_A

Operating free air temperature

125

°C

6.4 Thermal Information

TPS53667

THERMAL METRIC⁽¹⁾

RTA (QFN)

40 PINS

30.6

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

R_θJC(top)

R_θJB

14.2

Junction-to-board thermal resistance

6.9

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

6.8

R_θJC(bot)

1.8

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

6.5 Electrical Characteristics

over recommended free-air temperature range, V_VIN= 12 V, V_V5= 5 V, V_VSN= GND, V_VSP= V_OUT(unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY: CURRENTS, UVLO, AND POWER-ON RESET

I_VIN

VIN supply current, 6-phase active

V5 supply current

V_VDAC< V_VSP< V_VDAC+ 100 mV, ENABLE = HI

PMBus Idle, ENABLE = HI

ENABLE = LO

115

7

µA

mA

V

I_V5

6.1

2

I_V5SBY

V5 standby current

2.6

3.4

100

4.5

4.25

0.3

4.7

7.45

8.2

10.7

V_V3R3

V3R3 output voltage

I_V3R3= 0 A

3.2

3.3

V_{V3R3(dropout)}

V_V5UVLOH

V_V5UVLOL

V_HYS(V5)

V3R3 load regulation

V5 UVLO OK threshold

V5 UVLO fault threshold

V5 UVLO hysteresis

I_V3R3= 5 mA

mV

V

Ramp up

4.1

3.95

0.15

4.2

4.25

4.05

0.23

4.5

Ramp down

V

Hysteresis

V

MFR_SPEC_16[1:0] = 00

MFR_SPEC_16[1:0] = 01

MFR_SPEC_16[1:0] = 10

MFR_SPEC_16[1:0] = 11

Hysteresis voltage

6.9

7.25

7.9

V_VINUVLO

VIN UVLO voltage

V

7.6

9.8

10.3

1.05

V_HYS(VIN)

VIN UVLO hysteresis voltage

REFERENCES: DAC AND VREF

VR12.5: Change VID0 HI to LO to HI

10

5

mV

%

V_VIDSTP

VID Step size

VR12.0: Change VID0 HI to LO to HI

V_DAC1

V_DAC2

V_DAC3

Closed Loop VSP tolerance

VR12.0: 0.61 V ≤ V_VSP≤ 0.995 V, I_OUT= 0 A , 0 °C ≤ T_A≤ 85 °C

VR12.0: 1 V ≤ V_VSP≤ 1.52 V, I_COUT= 0 A, 0 °C ≤ T_A≤ 85 °C

VR12.5: 1.50V ≤ V_VSP≤ 2.50 V, I_OUT= 0 A, 0 °C ≤ T_A≤ 85 °C

–6

–0.6

–1

6.5

0.6

1

%

VR12.0: 0.61 V ≤ V_VSP≤ 0.995 V, I_OUT= 0 A, –40°C ≤ T_A≤ 125

°C

V_DAC4

Closed Loop VSP tolerance

–8

8

mV

V_DAC5

Closed Loop VSP tolerance

VREF output

VR12.0: 1.0 V ≤ V_VSP≤ 1.52 V, I_OUT= 0 A, –40 °C ≤ T_A≤ 125 °C

VR12.5: 1.50 V ≤ V_VSP≤ 2.50V, I_OUT= 0 A, –40°C ≤ T_A≤ 125 °C

4.5 ≤ V_V5≤ 5.5 V, I_VREF= 0 A

-0.8

-1.1

0.8

1.0

%

V_DAC6

V_VREF

1.685

–4

1.70

-1

1.717

V

V_VREFSRC

V_VREFSNK

VREF output source

VREF output sink

I_VREF= 0 to 500 µA

mV

I_VREF= –500 to 0 µA

1

4

CURRENT SENSE: AMPLIFIER AND PHASE BALANCING

G_CSINTInternal current sense gain

COMPENSATOR: VOLTAGE POSITIONING AND AMPLIFIER

Gain from (CSPx – VREF ) to PWM comparator

1.0

V/V

g_M(isum)

ISUM amplifier transconductance

COMP amplifier transconductance

COMP amplifier negative clamp voltage

COMP amplifier positive clamp voltage

V_VSP= 1.7 V

500

1000

µS

mV

V

g_M(comp)

V_CCLAMPN

V_CCLAMPP

(V_VREF– V_COMP

)

V_RAMP+ 20

2.2

(V_COMP– V_VREF

2.1

-30

2.3

VOLTAGE SENSE: VSP AND VSN

Not in fault, disable or UVLO,

V_VSP= V_VDAC= 2.3 V, V_VSN= 0 V

I_VSP

VSP input bias current

300

µA

Not in fault, disable or UVLO,

V_VSP= V_VDAC= 2.3 V, V_VSN= 0 V

I_VSN

VSN input bias current

Transistor resistance

-23

10

µA

R_SFTSTP

Connect to VSP

kΩ

LOGIC ( RESET, VR_RDY, VR_FAULT, VR_HOT, AND ENABLE) INTERFACE PINS: I/O VOLTAGE AND CURRENT

R_RPGDL

I_VRTTLK

V_RSTL

V_RSTH

T_RSTTDLY

V_ENL

Open drain pull-down resistance

Open drain leakage current

RESET logic low

VR_RDY, pulldown resistance at 0.31 V

36

50

2

Ω

µA

V

VR_HOT, VR_RDY, hi-Z leakage, apply 3.3 V in off state

–2

0.2

RESET Pin

0.8

RESET logic high

1.2

V

RESET Delay Time

ENABLE logic low

1

µs

V

0.3

25

V_ENH

ENABLE logic high

0.8

V

I_ENH

I/O 1.1- V leakage

Leakage current , V_ENABLE= 1.1 V

µA

PMBUS INTERFACE PINS: I/O VOLTAGE AND CURRENT

V_PMBL

V_PMBH

I_PMBL

PMBus pins logic low

PMBus pins logic high

Logic low input current

Logic high input current

0.8

V

1.2

-10

V_PMBus=0 V

10

µA

I_PMBH

V_PMBus=1.8 V

7

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

Electrical Characteristics (continued)

over recommended free-air temperature range, V_VIN= 12 V, V_V5= 5 V, V_VSN= GND, V_VSP= V_OUT(unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADDR-TRISE PIN: PMBUS ADDRESS, SOFT START RISE TIME SETTING

R

_ADDR-TRISE≤ 20 kΩ or R_ADDR-TRISE= 24 kΩ or

1

1/2

1/4

1/8

0

MFR_SPEC_12<1:0> = 00b

R_ADDR-TRISE= 30 kΩ or R_ADDR-TRISE= 39 kΩ or

MFR_SPEC_12<1:0> = 01b

Soft start rise slew rate in terms of V_OUT

slew rate

SL_RISE

R_ADDR-TRISE= 56 kΩ or R_ADDR-TRISE= 75 kΩ or

MFR_SPEC_12<1:0> = 10b

R_ADDR-TRISE= 100 kΩ or R_ADDR-TRISE= 150 kΩ or

MFR_SPEC_12<1:0> = 11b

R_ADDR-TRISE≤ 20 kΩ or R_ADDR-TRISE= 30 kΩ or R_ADDR-TRISE= 56

kΩ or R_ADDR-TRISE= 100 kΩ, or MFR_SPEC_11 [0] = 0b

BOOT

BOOT voltage set (B0)

R_ADDR-TRISE= 24 kΩ or R_ADDR-TRISE= 39 kΩ or R_ADDR-TRISE= 75

kΩ or R_ADDR-TRISE= 150 kΩ, or MFR_SPEC_11 [0] = 1b

1

V

_ADDR-TRISE≤ 0.053 V with ±20 mV tolerance

1100000

1100001

1100010

1100011

1100100

1100101

1100110

1100111

1110000

1110001

1110010

1110011

1110100

1110101

1110110

1110111

V_ADDR-TRISE= 0.159 V with ±20 mV tolerance

V_ADDR-TRISE= 0.266 V with ±20 mV tolerance

V_ADDR-TRISE= 0.372 V with ±20 mV tolerance

V_ADDR-TRISE= 0.478 V with ±20 mV tolerance

V_ADDR-TRISE= 0.584 V with ±20 mV tolerance

V_ADDR-TRISE= 0.691 V with ±20 mV tolerance

V_ADDR-TRISE= 0.797 V with ±20 mV tolerance

V_ADDR-TRISE= 0.903 V with ±20 mV tolerance

V_ADDR-TRISE= 1.009 V with ±20 mV tolerance

V_ADDR-TRISE= 1.116 V with ±20 mV tolerance

V_ADDR-TRISE= 1.222 V with ±20 mV tolerance

V_ADDR-TRISE= 1.328 V with ±20 mV tolerance

V_ADDR-TRISE= 1.434 V with ±20 mV tolerance

V_ADDR-TRISE= 1.541 V with ±20 mV tolerance

V_ADDR-TRISE= 1.615 V with ±10 mV tolerance

PADDR

PMBus address bits set (11P₄0P₂P₁P₀)

8

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

Electrical Characteristics (continued)

over recommended free-air temperature range, V_VIN= 12 V, V_V5= 5 V, V_VSN= GND, V_VSP= V_OUT(unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OCL-R PIN: OVERCURRENT THRESHOLDS AND RAMP SETTINGS

R_OCL-R= 20 kΩ and V_OCL-R≤ 0.85 V or

MFR_SPEC_00[3:0] = 0000b

21

25

28

31

34

37

40

43

46

49

52

55

58

61

64

24

27

30

33

36

39

42

45

48

51

54

57

60

63

66

27

30

33

36

39

42

45

48

51

54

57

60

63

66

69

R_OCL-R= 24 kΩ and V_OCL-R≤ 0.85 V or

MFR_SPEC_00[3:0] = 0001b

R_OCL-R= 30 kΩ and V_OCL-R≤ 0.85 V or

MFR_SPEC_00[3:0] = 0010b

R_OCL-R= 39 kΩ and V_OCL-R≤ 0.85 V or

MFR_SPEC_00[3:0] = 0011b

R_OCL-R= 56 kΩ and V_OCL-R≤ 0.85 V or

MFR_SPEC_00[3:0] = 0100b

R_OCL-R= 75 kΩ and V_OCL-R≤ 0.85 V or

MFR_SPEC_00[3:0] = 0101b

R_OCL-R= 100 kΩ and V_OCL-R≤ 0.85 V or

MFR_SPEC_00[3:0] = 0110b

R_OCL-R≥ 150 kΩ and V_OCL-R≤ 0.85 V or

MFR_SPEC_00[3:0] = 0111b

Phase OCL level (CSPx-VREF)

(valley current-limit)

I_OCLx

A

R_OCL-R= 20 kΩ and V_OCL-R≥ 0.95 V or

MFR_SPEC_00[3:0] = 1000b

R_OCL-R= 24 kΩ and V_OCL-R≥ 0.95 V or

MFR_SPEC_00[3:0] = 1001b

R_OCL-R= 30 kΩ and V_OCL-R≥ 0.95 V or

MFR_SPEC_00[3:0] = 1010b

R_OCL-R= 39 kΩ and V_OCL-R≥ 0.95 V or

MFR_SPEC_00[3:0] = 1011b

R_OCL-R= 56 kΩ and V_OCL-R≥ 0.95 V or

MFR_SPEC_00[3:0] = 1100b

R_OCL-R= 75 kΩ and V_OCL-R≥ 0.95 V or

MFR_SPEC_00[3:0] = 1101b

R_OCL-R= 100 kΩ and V_OCL-R≥ 0.95 V or

MFR_SPEC_00[3:0] = 1110b

R

_OCL-R≥ 150 kΩ and V_OCL-R≥ 0.95 V or

67

30

69

40

72

50

MFR_SPEC_00[3:0] = 1111b

V_RAMP

Ramp setting

V_OCL-R= 0.2 V ±50mV or V_OCL-R= 1.0 V ±50mV or

MFR_SPEC_14[2:0] = 001b

mV_{P_P}

V_OCL-R= 0.4 V ±50mV or V_OCL-R= 1.2 V ±50mV or

MFR_SPEC_14[2:0] = 011b

70

135

180

80

145

190

90

155

205

V_OCL-R= 0.6 V ±50mV or V_OCL-R= 1.4 V ±50mV or

MFR_SPEC_14[2:0] = 110b

V_OCL-R= 0.8 V ±50mV or V_OCL-R= 1.6 V ±50mV or

MFR_SPEC_14[2:0] = 111b

F-IMAX PIN: FREQUENCY AND IMAX SETTINGS

Switching frequency (See Switching

Characteristics)

f_SW

V_F-IMAX(min)= 0.136V

I_MAX=(V_F-IMAX/V_VREF× 256)-0.5

18

78

20

80

22

82

V_F-IMAX(min)= 0.535 V

I_MAX=(V_F-IMAX/V_VREF× 256)-0.5

I_MAX

IMAX values

A

V_F-IMAX(min)= 0.800 V

I_MAX=(V_F-IMAX/V_VREF× 256)-0.5

118

178

120

180

122

182

V_F-IMAX(min)= 1.198 V

I_MAX=(V_F-IMAX/V_VREF× 256)-0.5

9

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

Electrical Characteristics (continued)

over recommended free-air temperature range, V_VIN= 12 V, V_V5= 5 V, V_VSN= GND, V_VSP= V_OUT(unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SLEW-MODE PIN: SLEW RATES and MODE SELECTIONS

R

_SLEW-MODE≤ 20 kΩ

0.28

0.60

0.91

1.22

1.53

1.85

2.16

0.34

0.68

1.02

1.36

1.7

or MFR_SPEC_13[2:0] = 000b and MFR_SPEC_07[2] = 0b

R_SLEW-MODE= 24 kΩ

or MFR_SPEC_13[2:0] = 001b and MFR_SPEC_07[2] = 0b

R_SLEW-MODE= 30 kΩ

or MFR_SPEC_13[2:0] = 010b and MFR_SPEC_07[2] = 0b

R_SLEW-MODE= 39 kΩ

or MFR_SPEC_13[2:0] = 011b and MFR_SPEC_07[2] = 0b

R_SLEW-MODE= 56 kΩ

or MFR_SPEC_13[2:0] = 100b and MFR_SPEC_07[2] = 0b

R_SLEW-MODE= 75 kΩ

or MFR_SPEC_13[2:0] = 101b and MFR_SPEC_07[2] = 0b

2.04

2.38

R_SLEW-MODE= 100 kΩ

or MFR_SPEC_13[2:0] = 110b and MFR_SPEC_07[2] = 0b

R

_SLEW-MODE≥ 150 kΩ

2.48

1.53

2.74

1.7

or MFR_SPEC_13[2:0] = 111b and MFR_SPEC_07[2] = 0b

SL_SET

Slew rate setting

mV/µs

R_SLEW-MODE≤ 20 kΩ

or MFR_SPEC_13[2:0] = 000b and MFR_SPEC_07[2] = 1b

R_SLEW-MODE= 24 kΩ

or MFR_SPEC_13[2:0] = 001b and MFR_SPEC_07[2] = 1b

1.85

2.16

2.48

2.79

3.10

3.41

3.73

2.04

2.38

2.74

3.08

3.43

3.76

4.13

R_SLEW-MODE= 30 kΩ

or MFR_SPEC_13[2:0] = 010b and MFR_SPEC_07[2] = 1b

R_SLEW-MODE= 39 kΩ

or MFR_SPEC_13[2:0] = 011b and MFR_SPEC_07[2] = 1b

R_SLEW-MODE= 56 kΩ

or MFR_SPEC_13[2:0] = 100b and MFR_SPEC_07[2] = 1b

R_SLEW-MODE= 75 kΩ

or MFR_SPEC_13[2:0] = 101b and MFR_SPEC_07[2] = 1b

R_SLEW-MODE= 100 kΩ

or MFR_SPEC_13[2:0] = 110b and MFR_SPEC_07[2] = 1b

R_SLEW-MODE≥ 150 kΩ

or MFR_SPEC_13[2:0] = 111b and MFR_SPEC_07[2] = 1b

10

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

Electrical Characteristics (continued)

over recommended free-air temperature range, V_VIN= 12 V, V_V5= 5 V, V_VSN= GND, V_VSP= V_OUT(unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

_SLEW-MODE≤ 0.053 V with ±20 mV tolerance,

0000

or MFR_SPEC_13[7:3] = 00x00

V_SLEW-MODE= 0.159 V with ±20 mV tolerance,

MFR_SPEC_13[7:3] = 00x01b

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

V_SLEW-MODE= 0.266 V with ±20 mV tolerance,

MFR_SPEC_13[7:3] = 00x10b

V_SLEW-MODE= 0.372V with ±20 mV tolerance,

MFR_SPEC_13[7:3] = 00x11b

V_SLEW-MODE= 0.478 V with ±20 mV tolerance,

MFR_SPEC_13[7:3] = 01x00b

V_SLEW-MODE= 0.584V with ±20 mV tolerance,

MFR_SPEC_13[7:3] = 01x01b

V_SLEW-MODE= 0.691 V with ±20 mV tolerance,

MFR_SPEC_13[7:3] = 01x10b

V_SLEW-MODE= 0.797 V with ±20 mV tolerance,

MFR_SPEC_13[7:3] = 01x11b

MODE bits set⁽¹⁾

(M₃M₂M₁M₀)

MODE

V_SLEW-MODE= 0.903 V with ±20 mV tolerance,

MFR_SPEC_13[7:3] = 10x00b

V_SLEW-MODE= 1.009 V with ±20 mV tolerance,

MFR_SPEC_13[7:3] = 10x01b

V_SLEW-MODE= 1.116 V with ±20 mV tolerance,

MFR_SPEC_13[7:3] = 10x10b

V_SLEW-MODE= 1.222 V with ±20 mV tolerance,

MFR_SPEC_13[7:3] = 10x11b

V_SLEW-MODE= 1.328 V with ±20 mV tolerance,

MFR_SPEC_13[7:3] = 11x00b

V_SLEW-MODE= 1.434 V with ±20 mV tolerance,

MFR_SPEC_13[7:3] = 11x01b

V_SLEW-MODE= 1.541 V with ±20 mV tolerance,

MFR_SPEC_13[7:3] = 11x10b

V_SLEW-MODE= 1.615 V with ±10 mV tolerance,

MFR_SPEC_13[7:3] = 11x11b

O-USR PIN: OVERSHOOT AND UNDERSHOOT REDUCTION THRESHOLD SETTING

R

_O-USR≤ 20 kΩ or MFR_SPEC_09 [2:0] = 000b

20

30

40

50

R_O-USR= 24 kΩ or MFR_SPEC_09 [2:0] = 001b

R_O-USR= 30 kΩ or MFR_SPEC_09 [2:0] = 010b

R_O-USR= 39 kΩ or MFR_SPEC_09 [2:0] = 011b

R_O-USR= 56 kΩ or MFR_SPEC_09 [2:0] = 100b

R_O-USR= 75 kΩ or MFR_SPEC_09 [2:0] = 101b

R_O-USR= 100 kΩ or MFR_SPEC_09 [2:0] = 110b

50

60

70

80

90

V_OSR

OSR voltage setting

mV

90

100

120

140

OFF

110

130

150

110

130

R_O-USR≥ 150 kΩ or MFR_SPEC_09 [2:0] = 111b

V_O-USR= 0.2 V with ±50 mV tolerance

or MFR_SPEC_09 [6:4] = 000b

10

20

30

40

V_O-USR= 0.4 V with ±50 mV tolerance

or MFR_SPEC_09 [6:4] = 001b

V_O-USR= 0.6 V with ±50 mV tolerance

or MFR_SPEC_09 [6:4] = 010b

50

60

70

V_O-USR= 0.8 V with ±50 mV tolerance

or MFR_SPEC_09 [6:4] = 011b

70

80

90

V_USR

USR voltage setting

mV

V_O-USR= 1.0 V with ±50 mV tolerance

or MFR_SPEC_09 [6:4] = 100b

90

100

120

140

OFF

110

130

150

V_O-USR= 1.2 V with ±50 mV tolerance

or MFR_SPEC_09 [6:4] = 101b

110

130

V_O-USR= 1.4 V with ±50 mV tolerance

or MFR_SPEC_09 [6:4] = 110b

1.55 V ≤ V_O-USR≤ 1.6 V

or MFR_SPEC_09 [6:4] = 111b

V_OSRHYS

V_USRHYS

OSR voltage hysteresis⁽¹⁾

USR voltage hysteresis⁽¹⁾

All settings

10

mV

(1) Specified by design. Not production tested.

11

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

Electrical Characteristics (continued)

over recommended free-air temperature range, V_VIN= 12 V, V_V5= 5 V, V_VSN= GND, V_VSP= V_OUT(unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VBOOT PIN: BOOT VOLTAGE SETTING

R_VBOOT≤ 20 kΩ, or MFR_SPEC_11 [3:1] = 000b

R_VBOOT= 24 kΩ, or MFR_SPEC_11 [3:1] = 001b

R_VBOOT= 30 kΩ, or MFR_SPEC_11 [3:1] = 010b

R_VBOOT= 39 kΩ, or MFR_SPEC_11 [3:1] = 011b

R_VBOOT= 56 kΩ, or MFR_SPEC_11 [3:1] = 100b

R_VBOOT= 75 kΩ, or MFR_SPEC_11 [3:1] = 101b

R_VBOOT= 100 kΩ, or MFR_SPEC_11 [3:1] = 110b

R_VBOOT≥ 150 kΩ, or MFR_SPEC_11 [3:1] = 111b

000

001

010

011

100

101

110

111

0000

BOOT voltage setting (B₃B₂B₁)

V_VBOOT≤ 0.053 V with ±20 mV tolerance, or MFR_SPEC_11

[7:4] = 0000b

V_VBOOT= 0.159 V with ±20 mV tolerance, or MFR_SPEC_11

[7:4] = 0001b

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

V_VBOOT= 0.266 V with ±20 mV tolerance, or MFR_SPEC_11

[7:4] = 0010b

V_VBOOT= 0.372 V with ±20 mV tolerance, or MFR_SPEC_11

[7:4] = 0011b

V_VBOOT= 0.478 V with ±20 mV tolerance, or MFR_SPEC_11

[7:4] = 0100b

V_VBOOT= 0.584 V with ±20 mV tolerance, or MFR_SPEC_11

[7:4] = 0101b

(1)

V_BOOT

V_VBOOT= 0.691 V with ±20 mV tolerance, or MFR_SPEC_11

[7:4] = 0110b

V_VBOOT= 0.797 V with ±20 mV tolerance, or MFR_SPEC_11

[7:4] = 0111b

BOOT voltage setting (B₇B₆B₅B₄)

V_VBOOT= 0.903 V with ±20 mV tolerance, or MFR_SPEC_11

[7:4] = 1000b

V_VBOOT= 1.009 V with ±20 mV tolerance, or MFR_SPEC_11

[7:4] = 1001b

V_VBOOT= 1.116 V with ±20 mV tolerance, or MFR_SPEC_11

[7:4] = 1010b

V_VBOOT= 1.222 V with ±20 mV tolerance, or MFR_SPEC_11

[7:4] = 1011b

V_VBOOT= 1.328 V with ±20 mV tolerance, or MFR_SPEC_11

[7:4] = 1100b

V_VBOOT= 1.434 V with ±20 mV tolerance, or MFR_SPEC_11

[7:4] = 1101b

V_VBOOT= 1.541 V with ±20 mV tolerance, or MFR_SPEC_11

[7:4] = 1110b

V_VBOOT= 1.615 V with ±10 mV tolerance, or MFR_SPEC_11

[7:4] = 1111b

PROTECTION: OVP, UVP, VR_RDY

V_OVPFP

Pre-bias OVP voltage threshold⁽¹⁾

V_OVPF5Fixed OVP voltage threshold (VR12.5)

ENABLE is low and V_VSP> V_OVPFP, PWM → LO

2.75

2.2

V

ENABLE is high and (V_VSP–V_VSN) > V_OVPH5for 1 μs, PWM →

LO,

V_OUT(max)≤ 1.8 V

1.8 V < V_OUT(max)≤ 2.0 V

2.0 V < V_OUT(max)≤ 2.2 V

V_OUT(max)> 2.2 V

2.4

2.6

2.8

V_OVPF0

V_RDYH5

Fixed OVP voltage threshold (VR12.0)

ENABLE is high and (V_VSP–V_VSN) > V_OVPH5for 1 μs, PWM →

LO,

1.7

300

400

500

600

1.75

1.8

400

500

600

700

VR_RDY High Threshold (VR 12.5)

Measured at the VSP pin wrt/VID code. IC latches

OFF.MFR_SPEC_21<4:3>=00b

350

450

550

650

mV

(Tracking OVP Threshold)

Measured at the VSP pin wrt/VID code. IC latches

OFF.MFR_SPEC_21<4:3>=01b (Default)

Measured at the VSP pin wrt/VID code. IC latches

OFF.MFR_SPEC_21<4:3>=10b

Measured at the VSP pin wrt/VID code. IC latches

OFF.MFR_SPEC_21<4:3>=11b

12

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

Electrical Characteristics (continued)

over recommended free-air temperature range, V_VIN= 12 V, V_V5= 5 V, V_VSN= GND, V_VSP= V_OUT(unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_RDYH0

VR_RDY High Threshold (VR 12.0)

(Tracking OVP Threshold)

Measured at the VSP pin wrt/VID code. IC latches

OFF.MFR_SPEC_21<4:3>=00b

150

175

200

mV

Measured at the VSP pin wrt/VID code. IC latches

OFF.MFR_SPEC_21<4:3>=01b (Default)

200

250

300

175

225

235

325

250

300

350

235

Measured at the VSP pin wrt/VID code. IC latches

OFF.MFR_SPEC_21<4:3>=10b

Measured at the VSP pin wrt/VID code. IC latches

OFF.MFR_SPEC_21<4:3>=11b

V_RDYL

VR_RDY low (UVP) threshold

VR_RDY deglitch time

Measured at the VSP pin w/r/t VID code, device latches OFF

Time from VSP out of overvoltage threshold to VR_RDY low

207

1

mV

µs

t_RDYDGLTO

Time from VSP out of undervoltage threshold to VR_RDY low,

(ƒ_SW= 500 kHz)

t_RDYDGLTU

t_HICCUP

VR_RDY deglitch time

32

22

µs

Hiccup delay after UVP and OCP

ms

13

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

Electrical Characteristics (continued)

over recommended free-air temperature range, V_VIN= 12 V, V_V5= 5 V, V_VSN= GND, V_VSP= V_OUT(unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TSEN PIN AND THERMAL SHUTDOWN: THERMAL VOLTAGE LEVELS

T_J= 90°C

T_J= 95°C

T_J= 100°C

T_J= 105°C

1.32

1.36

1.4

V

1.44

1.48

1.52

1.56

1.6

V_TSEN

Thermal voltage definition

T_J= 110°C

T_J= 115°C

T_J= 120°C

T_J= 125°C

Leakage current

I_TSEN

TSEN current

–3

3

µA

°C

Based on the temperature measured on TSEN pin, default

value

125

15

OTP_THLD

OTP_HYS

Over temperature protection threshold

Over temperature protection hysteresis

°C

PWM and SKIP-NVM OUTPUT: I/O VOLTAGE AND CURRENT°C

V_PWML

PWMx output low level

I_LOAD= -1 mA

0.15

0.3

V

V_PWMH

PWMx output high Level

I_LOAD= +1 mA

2.5

V _{SKIP-NVM_L}

V _{SKIP-NVM_H}

R_{P-S_UV}

SKIP-NVM output low Level

SKIP-NVM output high Level

PWMx//SKIP-NVM resistance⁽¹⁾

I_LOAD= –1 mA

V

I_LOAD= +1 mA

2.5

10

V

ENABLE = LOW, or UVLO

MΩ

DYNAMIC PHASE SHEDDING: THRESHOLDS

MFR_SPEC_15 [3] = 0b

MFR_SPEC_15 [3] = 1b

N.A

Dynamic phase add/drop low threshold

current

I_DPSTHL

A

10% × 4 ×

I_OCLx

15% × 4 ×

I_OCLx

MFR_SPEC_15 [2:0] = 000b

MFR_SPEC_15 [2:0] = 001b

MFR_SPEC_15 [2:0] = 010b

MFR_SPEC_15 [2:0] = 011b

MFR_SPEC_15 [2:0] = 1xxb

20% × 4 ×

I_OCLx

Dynamic phase add/drop high threshold

voltage

25% × 4 ×

I_OCLx

I_DPSTHH

30% × 4 ×

I_OCLx

35% × 4 ×

I_OCLx

Dynamic phase add/drop 4-6 threshold

voltage

60% × 4 ×

I_OCLx

I_DPSTH46

I_DPSHYS

A

Dynamic phase add/drop high hysteresis

voltage

Hysteresis

5% × 4 × I_OCLx

Dynamic phase add/drop 6-4 hysteresis

voltage

10% × 4 ×

I_OCLx

I_DPSHYS46

PROGRAMMABLE DROOP SETTING

MFR_SPEC_08 [7:0] = 00h

MFR_SPEC_08 [7:0] = 01h

MFR_SPEC_08 [7:0] = 02h

MFR_SPEC_08 [7:0] = 03h

MFR_SPEC_08 [7:0] = 04h (Default Setting)

MFR_SPEC_08 [7:0] = 10h

MFR_SPEC_08 [7:0] = 20h

MFR_SPEC_08 [7:0] = 30h

MFR_SPEC_08 [7:0] = 40h

MFR_SPEC_08 [7:0] = 50h

MFR_SPEC_08 [7:0] = 60h

MFR_SPEC_08 [7:0] = 70h

MFR_SPEC_08 [7:0] = 80h

MFR_SPEC_08 [7:0] = 90h

MFR_SPEC_08 [7:0] = A0h

0

25

50

75

100

80

85

DROOP

Droop percentage settings

90

%

95

105

110

115

120

125

150

CURRENT SHARING FAULT: THRESHOLDS

14

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

Electrical Characteristics (continued)

over recommended free-air temperature range, V_VIN= 12 V, V_V5= 5 V, V_VSN= GND, V_VSP= V_OUT(unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MFR_SPEC_19<2:0>000b;

3

MFR_SPEC_19<2:0>001b;

MFR_SPEC_19<2:0>010b;

MFR_SPEC_19<2:0>011b;

MFR_SPEC_19<2:0>100b;

MFR_SPEC_19<2:0>101b;

MFR_SPEC_19<2:0>110b;

MFR_SPEC_19<2:0>111b;

5

7

9

I_PHFLT

Current Sharing Faa=ult Threshold

A

11

15

20

OFF

SKIP-NVM PIN: PROGRAM MODE SETTING (NVM OR PINSTRAP)

R

_SKIP-NVM≤ 20 kΩ

_SKIP-NVM≥ 100 kΩ

Pinstrap

NVM

Program

Mode

PGRM

Program mode for the configurations

R

15

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

Electrical Characteristics (continued)

over recommended free-air temperature range, V_VIN= 12 V, V_V5= 5 V, V_VSN= GND, V_VSP= V_OUT(unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IMON PIN: CURRENT MONITOR

I_IMON4LK

I_IMON4LO

I_IMON4MID

I_IMON4HI

0% IMAX level current output

20% IMAX level current output

100% IMAX level current output

125% IMAX level current output

6 phase, IMAX=120A, Σ i_L= 0 A, R_IMON=49.9kΩ

6 phase, IMAX=120A, Σ i_L= 24 A, R_IMON=49.9kΩ

6 phase, IMAX=120A, Σ i_L= 120 A, R_IMON=49.9kΩ

6 phase, IMAX=120A, Σ i_L= 150 A, R_IMON=49.9kΩ

0

20

4

28

A

24

120.8

151

115.8

145

125.8

157

VOUT MEASUREMENT: READ_VOUT

M_VOUT(rng)

V_OUTmeasurement range

0.5

-2

2.1

+2

V

0.5 V ≤ V_OUT< 0.7 V, VR12.0 mode

0.7V ≤ V_OUT≤ 1.0 V, VR12.0 mode

-1

+1

READ_VOUT

accuracy

VID

1.0V < V_OUT≤ 1.52 V, VR12.0 mode

-2

+2

0.5 V ≤ V_OUT≤ 2.1V, VR12.5 mode, (T_a=0°C to 85°C)

0.5 V ≤ V_OUT< 0.7 V, VR12.0 mode

-1

+1

-12.5

-7.5

-10

-12.5

12.5

7.5

10

0.7V ≤ V_OUT≤ 1.0 V, VR12.0 mode

MFR_READ_VOU

T accuracy

mV

1.0V < V_OUT≤ 1.52 V, VR12.0 mode

0.5 V ≤ V_OUT≤ 2.1V, VR12.5 mode, (T_a=0°C to 85°C)

12.5

6.6 I/O Timing Requirements

MIN

TYP

MAX

UNIT

V_BOOT> 0 V, no faults, time from

V3R3 high to VOUT ramp, C_VREF

1 µF

t_STARTUP1

Startup time

=

1.2

ms

V_BOOT> 0 V, no faults, time from

V3R3 high until the controller

responds to PMBus commands,

C_VREF= 1 µF

t_STARTUP2

1.5

ms

t_{RDY_POD}

t_{OFF_MIN}

t_{EN_RDY}

t_{RDY_VSP}

VR_RDY power-on-delay time⁽¹⁾

Controller minimum OFF time⁽¹⁾

ENABLE low to VR_RDY low

VR_RDY low to VSP change⁽¹⁾

DAC settled to VR_RDY going high

Fixed value

1

ms

ns

20

50

80

100

(1) Specified by design. Not production tested.

16

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

6.7 Switching Characteristics

T_A= 25°C. (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

F-IMAX PIN: FREQUENCY

V_VIN= 12 V, V_VSP= 1.7 V

R_F-IMAX= 20 kΩ and MFR_SPEC_12[7] =

0b ; or MFR_SPEC_12[7:4] = 0000b

270

360

450

540

630

720

810

300

400

500

600

700

800

900

330

440

550

660

770

880

990

V_VIN= 12 V, V_VSP= 1.7 V

R_F-IMAX= 24 kΩ and MFR_SPEC_12[7] =

0b ; or MFR_SPEC_12[7:4] = 0001b

V_VIN= 12 V, V_VSP= 1.7 V

R_F-IMAX= 30 kΩ and MFR_SPEC_12[7] =

0b ; or MFR_SPEC_12[7:4] = 0010b

V_VIN= 12 V, V_VSP= 1.7 V

R_F-IMAX= 39 kΩ and MFR_SPEC_12[7] =

0b ; or MFR_SPEC_12[7:4] = 0011b

V_VIN= 12 V, V_VSP= 1.7 V

R_F-IMAX= 56 kΩ and MFR_SPEC_12[7] =

0b ; or MFR_SPEC_12[7:4] = 0100b

V_VIN= 12 V, V_VSP= 1.7 V

R_F-IMAX= 75 kΩ and MFR_SPEC_12[7] =

0b ; or MFR_SPEC_12[7:4] = 0101b

V_VIN= 12 V, V_VSP= 1.7 V

R_F-IMAX= 100 kΩ and MFR_SPEC_12[7] =

0b ; or MFR_SPEC_12[7:4] = 0110b

V_VIN= 12 V, V_VSP= 1.7 V

R_F-IMAX= 150 kΩ and MFR_SPEC_12[7] =

0b ; or MFR_SPEC_12[7:4] = 0111b

900

315

1000

350

1100

385

f_SW

Switching frequency

kHz

V_VIN= 12 V, V_VSP= 1.7 V

R_F-IMAX= 20 kΩ and MFR_SPEC_12[7] =

1b ; or MFR_SPEC_12[7:4] = 1000b

V_VIN= 12 V, V_VSP= 1.7 V

R_F-IMAX= 24 kΩ and MFR_SPEC_12[7] =

1b ; or MFR_SPEC_12[7:4] = 1001b

405

495

585

675

765

855

900

450

550

650

750

850

950

1000

495

605

V_VIN= 12 V, V_VSP= 1.7 V

R_F-IMAX= 30 kΩ and MFR_SPEC_12[7] =

1b ; or MFR_SPEC_12[7:4] = 1010b

V_VIN= 12 V, V_VSP= 1.7 V

R_F-IMAX= 39 kΩ and MFR_SPEC_12[7] =

1b ; or MFR_SPEC_12[7:4] = 1011b

715

V_VIN= 12 V, V_VSP= 1.7 V

R_F-IMAX= 56 kΩ and MFR_SPEC_12[7] =

1b ; or MFR_SPEC_12[7:4] = 1100b

825

V_VIN= 12 V, V_VSP= 1.7 V

R_F-IMAX= 75 kΩ and MFR_SPEC_12[7] =

1b ; or MFR_SPEC_12[7:4] = 1101b

935

V_VIN= 12 V, V_VSP= 1.7 V

R_F-IMAX= 100 kΩ and MFR_SPEC_12[7] =

1b ; or MFR_SPEC_12[7:4] = 1110b

1045

1100

V_VIN= 12 V, V_VSP= 1.7 V

R_F-IMAX= 150kΩ and MFR_SPEC_12[7] =

1b ; or MFR_SPEC_12[7:4] = 1111b

17

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

6.8 Typical Characteristics

100

5.5

5.3

5.1

4.9

4.7

4.5

90

80

70

60

50

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Junction Temperature (èC)

D001

图 1. VIN Supply Current vs Junction Temperature

图 2. V5 Supply Current vs Junction Temperature

7.5

7

4.35

4.25

4.15

4.05

3.95

3.85

RAMP UP

RAMP DOWN

6.5

6

RAMP UP

RAMP DOWN

5.5

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Junction Temperature (èC)

D001

V_UVLO= 7.25V

图 4. V5 UVLO Voltage vs Junction Temperature

图 3. VIN UVLO Voltage vs Junction Temperature

2.4

2.1

1.8

1.5

1.2

0.9

0.6

0.3

0

1.71

1.705

1.7

1.695

1.69

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Junction Temperature (èC)

D001

I_LOAD= 5 mA

图 5. Reference Voltage vs Junction Temperature

图 6. V3R3 Load Regulation vs Junction Temperature

18

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

7 Detailed Description

7.1 Overview

The TPS53667 device is a DCAP+ mode adaptive on-time controller.

The output voltage is set using a DAC that outputs a reference in accordance with the 8-bit VID code defined in

表 1. In adaptive on-time converters, the controller varies the on-time as a function of input and output voltage to

maintain a nearly constant frequency during steady-state conditions. In conventional voltage-mode constant on-

time converters, each cycle begins when the output voltage crosses to a fixed reference level. However, in the

TPS53667 device, the cycle begins when the current feedback reaches an error voltage level which corresponds

to the amplified voltage difference between the DAC voltage and the feedback output voltage with droop. In the

case of multi-phase operations, the current feedback from all the phases is summed, and is amplified using the

ISUM pin to adjust the load-line. Also zero-load line operation can be easily configured with external resistor or

internal NVM selection.

7.2 Functional Block Diagram

COMP

O-USR

ISUM

VDAC

VCOMP

VFBDRP

OSR

and

USR

OSR

USR

LL

Differential

Amplifier

VSP

Detection

VDIFF

+

Loadline

Control

FREQ

CK1

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6

VSN

VDAC

VRAMPP

Ramp

Gen

+

VFBDRP

On-Time

1

VRAMPN

VCM

ISUM

PWM1

PWM2

Error

Amplifier

V_ISUM(tc)

Droop

Amplifier

ISUM

+

VCOMP

VISUMA

Current

CLK_ON

+

CK2

CK3

CK4

CK5

CK6

On-Time

2

Sum Amplifier

IS1

CSP1

CSP2

CSP3

AISUM

IS2

IS3

Mode

Control

and

Phase

Manager

On-Time

3

PWM3

PWM4

VCOMP

CLK_FF

I_AVG

On-Time

4

ꢀ

IS4

IS5

CSP4

CSP5

VDAC

Current-Mode

Control

and

Current Sharing

Circuitry

On-Time

5

PWM5

IS6

CSP6

On-Time

6

PWM6

IS1

IS2

IS3

IS4

IS5

IS6

VDIFF

IMON

VIN

SKIP-NVM

PHASE

ISHARE

ADC

TEMP

ILIM

O-USR

FREQ

LL

OCP

VDIFF

ISUM

V3R3

VIN

V5

RESET

PMB_CLK

SVID/I²C Interface

CPU Logic,

Protection,

and

IS1

IS2

IS3

IS4

IS5

IS6

PMB_ALERT

PMB_DIO

DAC0

VDAC

Status Circuitry

AFE

GND

19

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

7.3 Feature Description

7.3.1 V3R3 LDO

V3R3 is an LDO output generated from V5. It is used as internal digital circuit supply and 1-uF to 4.7-uF ceramic

decoupling capacitor to GND pin is recommended.

When V5 exceeds V_V5UVLOH(4.25 V typically), V3R3 begins to ramp up. The startup time for V3R3 is

approximately 600 µs as shown in 图 7.

4.25 V

V

V5

600 µs

V

V3R3

Time

图 7. V3R3 Startup Waveform

After V3R3 has reached its operational level, the TPS53667 begins to initialize the internal circuit and reads the

pinstrap configurations. This pinstrap reading completes in approximately 1.2 ms, and can communicate to the

PMBus 1.5 ms after V3R3 powers up.

注

This device does not require a high ENABLE signal in order for the V3R3 LDO to start up.

Use V3R3 as pull-up voltage for CSPx (to disable phases), ENABLE, VR_RDY, VR_HOT, and VR_FAULT.

Because the V3R3 maximum current capability is approximately 5 mA, choose pull-up resistances carefully.

Directly tie CSP6,CSP5, CSP4, CSP3 or CSP2 to the V3R3 pin according to to disable the corresponding phase.

20

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

Feature Description (接下页)

7.3.2 PWM Operation

As shown in the Functional Block Diagram, in 6-phase continuous conduction mode, the device operates as

described in 图 8.

V_OUT

I_SUM

V_COMP+ V_RAMP

SW_CLK

Phase 1

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Time

图 8. D-CAP+ Mode Basic Waveforms

Starting with the condition that the high-side FETs are off and the low-side FETs are on, the summed current

feedback (V_ISUM) is higher than the summed error amplifier output (V_COMP) and the internal ramp signal (V_RAMP).

I_SUMfalls until it hits V_COMP+V_RAMP,which contains a component of the output ripple voltage. The PWM

comparator senses where the two waveforms cross and triggers the on-time generator. This generates the

internal SW_CLK. Each SW_CLK corresponds to one switching ON pulse for one phase.

In case of single-phase operation, every SW_CLK generates a switching pulse on the same phase. Also, V_ISUM

corresponds to just a single-phase inductor current.

In case of multi-phase operation, the SW_CLK gets distributed to each of the phases in a cycle. This approach of

using the summed inductor current and cyclically distributing the ON pulses to each phase automatically gives

the required interleaving of 360 / n, where n is the number of phases.

7.3.3 Current Sense and IMON Calculation

The TPS53667 device provides independent channels of current feedback for every phase to increase the

system accuracy and reduce the dependence of circuit performance on layout compared to an externally

summed architecture. The current sensing signals are from TI smart power stages (at 5mV/A) (ex: CSD9549x)

and are already temperature-compensated. The pins CSP1, CSP2, CSP3, CSP4, CSP5, and CSP6 are used for

the individual phases of the phase current sensing.

The sensed currents are then summed together and generate a current output to IMON pin. A resistor is

connected to IMON pin to generate the V_IMONvoltage.

Ã₁^∏=Æ

6_#30∏

2_)-/.

6

)-/.

= F

F 6_2%&G × Æ ×

Æ

ꢀ5 ´À

where

•

V_CSPxis the voltage of CSPx pin

n is the number of active phases

R_IMONis the value of resistor between the IMON pin and GND in kΩ

(1)

21

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

Feature Description (接下页)

Then the V_IMONvoltage translates to a digital IMON reading as shown in 公式 2.

)

× 6

)-/.

-!8

)

=

)-/.

0ꢀꢁ5

where

•

0.85 is the voltage correlated to I_MAX

(2)

When V_IMONis 0.85 V, the IMON reading should be equal to I_MAX

.

The digital IMON then can be reported to the system by using PMBus command READ_IOUT.

7.3.4 Setting the Load-Line (DROOP)

V

DAC

Slope of Loadline R

LL

V

= R x I

DROOP LL OUT

DROOP

I

OUT

图 9. Load Line

A resistor between the ISUM pin and the VREF pin sets the load line in non-zero load line mode.

1

6_$2//0= 2_,,× )_/54= ß_{- ©≥µ≠}_;× 2

× 2_#3× × )_/54

:

)35-

ꢀ

where

•

g_M(isum)is the gain of the internal I_SUMamplifier, (500 µS typical)

R_ISUMis the value of resistor between the ISUM pin and the VREF pin to adjust the load line

R_CSis the effective current sense resistance of TI smart power stages, (5 mΩ for CSD9549x)

I_OUTis the load current

(3)

A desired zero load-line can be implemented by putting a 0 Ω between ISUM and VREF pins or by shorting the

ISUM and VREF pins directly.

7.3.5 Load Transitions

When there is a sudden load increase, the output voltage immediately drops. The TPS53667 device reacts to

this drop in a rising voltage on the COMP pin. This rise forces the PWM pulses to come in sooner and more

frequently which causes the inductor current to rapidly increase. As the inductor current reaches the new load

current, the device reaches a steady-state operating condition and the PWM switching resumes the steady-state

frequency.

When there is a sudden load release, the output voltage flies high. The TPS53667 device reacts to this rise in a

falling voltage on the COMP pin. This drop forces the PWM pulses to be delayed until the inductor current

reaches the new load current. At that point, the switching resumes and steady-state switching continues.

Please note in 图 10 and 图 11, the ripples on V_OUT, V_RAMP, and V_COMPvoltages are not shown for simplicity.

22

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

Feature Description (接下页)

LOAD

V_OUT

V_ISUM

V_COMP+ V_RAMP

V_ISUM

V_COMP+ V_RAMP

SW_CLK

Phase 1

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

SW_CLK

Phase 1

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

图 10. Load Insertion

7.3.6 Overshoot Reduction (OSR)

图 11. Load Release

The problem of overshoot in low duty-cycle synchronous buck converters is well known, and results from the

output inductor having a small voltage (V_OUT) with which to respond to a transient load release.

For simplicity, 图 12 shows a single phase converter. In an ideal converter, with typical input voltage of 12 V and

a 1.0-V output, the inductor has 11.0 V (12 V – 1.0 V) to respond to a transient load increase, but only 1.0 V to

respond once the load releases.

12 V

+ 11.0V œ

1.0 V

L

œ 1.0 V +

C

图 12. Representative Schematic of Synchronous Buck Converter Circuit

With the Overshoot Reduction (OSR) feature enabled, when the summed voltage of V_OUTand V_DROOPexceeds

the DAC voltage V_DACby the OSR value specified in the Electrical Characteristics table, the PWM pulses

immediately become tri-state to turn off both the high-side and low-side FETs. When the low-side FETs are

turned OFF, the energy in the inductor is partially dissipated by the body diodes. Please note the ON pulse width

can be also truncated immediately regardless of the load transient timing, and this feature can further reduce the

overshoot when compared to the conventional constant on-time controllers as shown in 图 13 .

23

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

Feature Description (接下页)

Threshold

Hysteresis

V

OUT

V

DAC

OSRThreshold

OSR

V

OUT

FBDRP

+

I

LOAD

+

OSR

Comparator

+

OSR

V

OSR

V

DROOP

OSR Threshold

OSR

Phase 1

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Time

图 13. Performance for a Load Transient Release with OSR Enabled

7.3.7 Undershoot Reduction (USR)

When the transient load increase becomes quite large, it becomes difficult to meet the energy demanded by the

load especially at lower input voltages. Then it is necessary to quickly increase the energy in the inductors during

the transient load increase. This is achieved in TPS53667 by enabling pulse overlapping. In order to maintain the

interleaving of the multi-phase configuration and yet be able to have pulse-overlapping during load-insertion, the

Undershoot Reduction (USR) mode is entered only when necessary. This mode is entered when the difference

between DAC voltage and the summed voltage of V_OUTand V_DROOPexceeds the USR voltage level specified in

the Electrical Characteristics table.

The waveforms in 图 14 indicate the performance with USR. It can be seen that it is possible to eliminate

undershoot by enabling USR. This allows reduced output capacitance to be used and still meets the

specification.

When the transient condition is over, the interleaving of the phases is resumed.

24

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

Feature Description (接下页)

Threshold

V

DAC

Hysteresis

V

OUT

DAC

USR

+

USR Threshold

V

OUT

V

FBDRP

+

I_LOAD

USR

Comparator

+

V

DROOP

V

USR

USR Threshold

USR

Phase 1

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Time

图 14. Performance for a Load Transient Step-up With USR Enabled

7.3.8 AutoBalance™ Current Sharing

The basic mechanism for current sharing is to sense the average phase current, then adjust the pulse width of

each phase to equalize the current in each phase as shown in 图 15. The PWM comparator (not shown) starts a

pulse when the feedback voltage meets the reference. The V_INvoltage charges C_t(on)through R_t(on). The pulse

terminates when the voltage at C_t(on)matches the on-time reference, which normally equals the DAC voltage

(V_DAC).

The circuit operates in the following fashion. First assume that the 5-µs averaged value from each phase current

are equal. In this case, the PWM modulator terminates at V_DAC, and the normal pulse width is delivered to the

system. If instead, I1 > I_AVG, then an offset is subtracted from V_DAC, and the pulse width for Phase 1 is shortened

to reduce the phase current in Phase 1 for balancing. If I1 < I_AVG, then a longer pulse is generated to increase

the phase current in Phase 1 to achieve current balancing.

25

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

Feature Description (接下页)

VDAC

+

I1

+

K X (I1 œ I_AVG

)

5 µs

CSP1

Filter

œ

+

R_T(on)

PWM1

PWM2

PWM3

PWM4

œ

VIN

I_AVG

VDAC

C_T(on)

+

I2

K X (I2 œ I_AVG

5 µs

CSP2

Filter

+

VIN

I_AVG

VDAC

+

C_T(on)

I3

K X (I3 œ I_AVG

5 µs

CSP3

Filter

œ

+

I_AVG

VIN

VDAC

+

C_T(on)

I4

K X (I4 œ I_AVG

5 µs

CSP4

Filter

+

I_AVG

VIN

VDAC

C_T(on)

+

I5

+

K X (I5 œ I_AVG

)

5 µs

CSP5

Filter

œ

+

R_T(on)

œ

PWM5

PWM6

I_AVG

VIN

VDAC

C_T(on)

+

I6

K X (I6 œ I_AVG)

5 µs

CSP6

Filter

+

R_T(on)

œ

I_AVG

VIN

Averaging Circuit

C_T(on)

图 15. AutoBalance Current Sharing Circuit Detail

7.3.9 Phase Overlap

In TPS53667, phase overlap is allowed during both steady state and transient operation. The duty cycle is

not limited to 1/n (where n is the phase number) unlike TPS53647

7.3.10 VID

The DAC voltage V_DACcan be changed according to 表 1.

The slew rate for a change is set by the resistor at SLEW-MODE pin, as defined in the Electrical Characteristics

table.

26

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

表 1. VID Table

表 1. VID Table (接下页)

VID Hex

VALUE

VR12.0 VOLTAGE

(V)

VR12.5 VOLTAGE

(V)

VID Hex

VALUE

VR12.0 VOLTAGE

(V)

VR12.5 VOLTAGE

(V)

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

0

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

0.48

0.485

0.49

0.96

0.97

0.98

0.99

1.00

1.01

1.02

1.03

1.04

1.05

1.06

1.07

1.08

1.09

1.10

1.11

1.12

1.13

1.14

1.15

1.16

1.17

1.18

1.19

1.20

1.21

1.22

1.23

1.24

1.25

1.26

1.27

1.28

1.29

1.30

1.31

1.32

1.33

1.34

1.35

1.36

1.37

1.38

1.39

1.40

1.41

1.42

0.25

0.50

0.51

0.52

0.53

0.54

0.55

0.56

0.57

0.58

0.59

0.60

0.61

0.62

0.63

0.64

0.65

0.66

0.67

0.68

0.69

0.70

0.71

0.72

0.73

0.74

0.75

0.76

0.77

0.78

0.79

0.80

0.81

0.82

0.83

0.84

0.85

0.86

0.87

0.88

0.89

0.90

0.91

0.92

0.93

0.94

0.95

0.255

0.26

0.495

0.50

0.265

0.27

0.505

0.51

0.275

0.28

0.515

0.52

0.285

0.29

0.525

0.53

0.295

0.30

0.535

0.54

0.305

0.31

0.545

0.55

0.315

0.32

0.555

0.56

0.325

0.33

0.565

0.57

0.335

0.34

0.575

0.58

0.345

0.35

0.585

0.59

0.355

0.36

0.595

0.60

0.365

0.37

0.605

0.61

0.375

0.38

0.615

0.62

0.385

0.39

0.625

0.63

0.395

0.40

0.635

0.64

0.405

0.41

0.645

0.65

0.415

0.42

0.655

0.66

0.425

0.43

0.665

0.67

0.435

0.44

0.675

0.68

0.445

0.45

0.685

0.69

0.455

0.46

0.695

0.70

0.465

0.47

0.705

0.71

0.475

27

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

表 1. VID Table (接下页)

VID Hex

VALUE

VR12.0 VOLTAGE

(V)

VR12.5 VOLTAGE

(V)

VID Hex

VALUE

VR12.0 VOLTAGE

(V)

VR12.5 VOLTAGE

(V)

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

0.715

0.72

1.43

1.44

1.45

1.46

1.47

1.48

1.49

1.50

1.51

1.52

1.53

1.54

1.55

1.56

1.57

1.58

1.59

1.60

1.61

1.62

1.63

1.64

1.65

1.66

1.67

1.68

1.69

1.70

1.71

1.72

1.73

1.74

1.75

1.76

1.77

1.78

1.79

1.80

1.81

1.82

1.83

1.84

1.85

1.86

1.87

1.88

1.89

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

0.95

0.955

0.96

1.90

1.91

1.92

1.93

1.94

1.95

1.96

1.97

1.98

1.99

2.00

2.01

2.02

2.03

2.04

2.05

2.06

2.07

2.08

2.09

2.10

2.11

2.12

2.13

2.14

2.15

2.16

2.17

2.18

2.19

2.20

2.21

2.22

2.23

2.24

2.25

2.26

2.27

2.28

2.29

2.30

2.31

2.32

2.33

2.34

2.35

2.36

0.725

0.73

0.965

0.97

0.735

0.74

0.975

0.98

0.745

0.75

0.985

0.99

0.755

0.76

0.995

1.00

0.765

0.77

1.005

1.01

0.775

0.78

1.015

1.02

0.785

0.79

1.025

1.03

0.795

0.80

1.035

1.04

0.805

0.81

1.045

1.05

0.815

0.82

1.055

1.06

0.825

0.83

1.065

1.07

0.835

0.84

1.075

1.08

0.845

0.85

1.085

1.09

0.855

0.86

1.095

1.10

0.865

0.87

1.105

1.11

0.875

0.88

1.115

1.12

0.885

0.89

1.125

1.13

0.895

0.90

1.135

1.14

0.905

0.91

1.145

1.15

0.915

0.92

1.155

1.16

0.925

0.93

1.165

1.17

0.935

0.94

1.175

1.18

0.945

28

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

表 1. VID Table (接下页)

VID Hex

VALUE

VR12.0 VOLTAGE

(V)

VR12.5 VOLTAGE

VID Hex

VALUE

VR12.0 VOLTAGE

(V)

VR12.5 VOLTAGE

(V)

2.37

2.38

2.39

2.40

2.41

2.42

2.43

2.44

2.45

2.46

2.47

2.48

2.49

2.50

n/a

BC

BD

BE

BF

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

1.185

1.19

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

1.355

1.36

n/a

1.195

1.20

1.365

1.37

1.205

1.21

1.375

1.38

1.215

1.22

1.385

1.39

1.225

1.23

1.395

1.40

1.235

1.24

1.405

1.41

1.245

1.25

1.415

1.42

1.255

1.26

1.425

1.43

n/a

1.265

1.27

n/a

1.435

1.44

n/a

1.275

1.28

n/a

1.445

1.45

n/a

1.285

1.29

n/a

1.455

1.46

n/a

1.295

1.30

n/a

1.465

1.47

n/a

1.305

1.31

n/a

1.475

1.48

n/a

1.315

1.32

n/a

1.485

1.49

n/a

1.325

1.33

n/a

1.495

1.50

n/a

1.335

1.34

n/a

1.505

1.51

n/a

1.345

1.35

n/a

1.515

1.52

n/a

29

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

7.3.11 PWM and SKIP Signals

The PWM and SKIP-NVM signals are output from the controller to drive the TI smart power stages. Both signals

are 3.3-V logic based. The PWM signal is logic high to turn on the high-side MOSFET and logic low to turn on

the low-side MOSFET. When both high-side and low-side MOSFETs are expected to be OFF, the PWM signal is

driven to tri-state condition (1.7 V). The SKIP-NVM pin is asserted low during the soft-start period.

7.3.12 TSEN (Thermal Sense) Pin

TI smart power stage (ex: CSD9549x) senses the die temperature and sends out the temperature information as

a voltage through the TAO pin. In a multi-phase application, the TAO pin of the TI smart power stages are

connected and then tied to the TSEN pin of the TPS53667 device. In this case, the device reports the

temperature of the hottest power stage. The reported temperature can be calculated as shown in 公式 4.

(6_43%.F ꢀꢁꢂ)

4%-0 =

ꢀꢁꢀꢀ8

where

•

TEMP is the sensed temperature in °C

V_TSENis the voltage at TSEN pin

(4)

注

The maximum temperature that can be sensed is 127.9 °C. If the TSEN voltage (V_TSEN) is

higher than the voltage associated to 127.9 °C, the device continues to report 127.9 °C.

TSEN signal is also used as an indicator for power stage fault. When an internal fault occurs in the TI smart

power stage (CSD9549x), the power stage pulls the TAO pin high. In the default configuration, if the TSEN

voltage is higher than 2.5 V, the TPS53667 device senses the fault and turns off both the high-side and the low-

side MOSFETS. There is also an option to disable power stage fault as described in MFR_SPECIFIC_07[3].

Power stage

TAO

Temperature

Sense

Power stage

TPS53667

TAO

TSEN

Temperature

Sense

ADC

Temp

Power stage

TAO

Temperature

Sense

图 16. Temperature Sense

30

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

7.3.13 RESET Function

During adaptive voltage scaling (AVS) operation, the voltage may become falsely adjusted to be out of ASIC

operating range. The RESET function returns the voltage to the VBOOT voltage. When the voltage is out of

ASIC operating range, the ASIC issues a RESET signal to the TPS53667 device, as shown in 图 17. The device

senses this signal and after a delay of greater than 1 µs, it sets an internal RESET_FAULT signal and sets

VOUT_COMMAND to VBOOT. The device pulls the output voltage to the VBOOT level with the slew rate set by

SLEW-MODE pin, as shown in 图 18.

When the RESET pin signal goes high, the internal RESET_FAULT signal goes low.

TPS53667

ASIC Power Stage

ASIC V

RESET

TPS53667 V

RESET

PMB_CLK

PMB_DIO

PMB_CLK

PMB_DIO

Internal

RESET_FAULT

PMB_ALERT

Response Delay

Default VBOOT

Pre-AVS V

.

OUT .

(A)

V

OUT

(C)

(B)

Time

图 17. RESET Pin Connection

7.3.14 Input UVLO

图 18. Reset Function

The TPS53667 device continuously monitors the input voltage through the VIN pin. If the input voltage is lower

than the UVLO low threshold, the device turns off. If V_INrises higher than the UVLO high threshold, the controller

turns on again (if both V5 and ENABLE are high). The hysteresis is approximately 1.05 V.

表 2. Input Undervoltage Lockout (UVLO)

VIN UVLO SETTING

MFR_SPEC_16[1:0] = 00

MFR_SPEC_16[1:0] = 01 (Default)

MFR_SPEC_16[1:0] = 10

MFR_SPEC_16[1:0] = 11

TURN-ON VOLTAGE (V)

TURN-OFF VOLTAGE (V)

4.5

7.25

7.9

3.5

6.25

6.9

10.3

9.3

7.3.15 V5 Pin Undervoltage Lockout (UVLO)

The TPS53667 device also monitors V5 pin voltage. If the voltage is lower than V_V5UVLOL(4.05 V typical), the

controller turns off. If V5 voltage comes back to be higher than V_V5UVLOH(4.25 V typical), the controller turns back

on (if both VIN and ENABLE are high).

7.3.16 Output Undervoltage Protection (UVP)

The output undervoltage protection in the TPS53667 device is called tracking UVP. When the output voltage

drops below (VDAC–V_DROOP–V_RDYL), the controller drives the PWM into a tri-state condition so that both high-

side and low-side MOSFETs turn off. After a hiccup delay (22-ms typical), the device attempts to restart to

VBOOT voltage. If the UVP condition continues, the UVP occurs again and the process repeats.

31

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

7.3.17 Overvoltage Protection (OVP)

The OVP condition is detected when the output voltage V_OUT> V_DAC+ tracking OVP offset (V_OVPT5for VR12.5 or

V_OVPT0for VR12.0) , which is called tracking OVP. In this case the controller drives the VR_RDY pin to inactive

(low state) and drives all PWM signals to logic low which turns on the low-side MOSFET to discharge the output.

However the OVP threshold is blanked during a V_DACchange. In order to continually protect the load, there is

second OVP level (fixed OVP). The second OVP level is fixed at V_OVPH5(VR12.5) or V_OVPH0(VR12.0) is active

during VDAC change. If the fixed OVP condition is detected, the device drives the VR_RDY pin to inactive (logic

low) and drives the PWM signals to logic low in order to turn on the low-side MOSFET. The controller remains in

this state until the ENABLE or V5 is re-cycled.

For both tracking OVP and fixed OVP, the controller will try to restart after a hiccup delay (~22ms). If the OV

condition still exists, the controller will pull PWM signal to logic low and enter into anther hiccup cycle. If after 3

hiccup cycles, the OV condition still exists, the controller will latch PWM signal to logic low until ENABLE or V5 is

re-cycled.

When ENABLE is low, and output voltage is higher than V_OVPFP(2.75 V typical), the OVP condition is detected,

which is called Pre-bias OVP. The device then drives the PWM signals to logic low. The device latches the pre-

bias OVP. The latch can be cleared only by recycling V5.

7.3.18 Overcurrent Limit (OCL) and Overcurrent Protection (OCP)

The TPS53667 device includes a valley-current-based limit function by using a per-phase OCL comparator. A

resistor connected between the OCL-R pin and the VREF pin generates the OCL comparison threshold.

Using the valley current limit, the OCL current level can be selected using 公式 5. To set the per-phase OCL

threshold, subtract half of the ripple current from the maximum average current and select the OCL threshold

specified in the table equal or slight lower than I_OCL

.

I

RIPPLE

æ

ö

æ

ö

MAX

I_OCL= K ´

-

ç

÷

ç

÷

n

2

è

ø

è

ø

where

•

K is the maximum operating margin percentage

n is the number of active phases

I_RIPPLEis the ripple current

(5)

This instantaneous current sense voltage V_CSPxis compared to the OCL threshold. If the current sense voltage at

OCL comparator goes above the OCL threshold, the device delays the next ON pulse until the current sense

voltage drops below the OCL threshold. In this case, the output voltage continues to drop until the UVP threshold

is reached.

Another overcurrent protection (OCP) is based on the current sensed through IMON pin of the device. When the

digitized IMON is higher than OC_FAULT_LIMIT (1.25× IMAX by default), the controller turns off both high-side

and low-side MOSFETS and enters into hiccup mode until the overcurrent condition is removed.

7.3.19 Current Sharing Warning and Phase Fault Detect

TPS53667 can detect faulty phases with the current sharing warning feature. If the current of a certain phase is

lower than the average current by certain threshold (set by MFR_SPECiFIC_19, default is 8A), the controller can

turn off the faulty phase while keeping the other phases in operation (This is also configurable by

MFR_SPECIFIC_19[7]). The faulty phase can be read from STATUS_MFR_SPECIFIC[5:3].

The phase interleaving is not adjusted when the faulty phase is turned off. The controller phase interleaving

operates as if the faulty phase still is still operating. This behavior has the affect of slightly increasing the output

voltage ripple.

When there are only two phases in operation, this feature is disabled. For example, even if one of the phases

has current lower than average, it does not turn off.

7.3.20 Turn off Individual Phase by PMBus

Individual phases can also be turned off by using the PMBus command MFR_SPECIFIC_24(0xE8). Please see

MFR_SPECIFIC_24 (E8h)section for more details.

32

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

The MFR_SPECIFIC_24 setting can be effective before the controller is enabled. For example, when a certain

phase is turned off by MFR_SPECIFIC_24 before Enable goes high, this phase does not turn on after Enable.

7.3.21 Phase Shedding

Phase Shedding is enabled with MFR_SPECIFIC_13[4]. Phase shedding allows the user to optimize efficiency

over a wider range of loads. Using only one or two phases is often more efficient when the load is drawing a

smaller amount of current, than using all six phases.

The points at which phases are shed can be set by MFR_SPECIFIC_15 (Dynamic Phase Shedding Thresholds)

(DFh).

7.3.22 Over Temperature Protection (OTP)

When the sensed temperature through TSEN pin is higher than the over temperature fault threshold

OTP_THLD(125°C by default), the controller turns off high-side and low-side MOSFETS. The power stages cool

down and TSEN voltage drops. When the sensed temperature is 15°C (OTP_HYS) lower than the over temperature

fault threshold, the controller restarts to the VBOOT voltage.

7.3.23 VR_HOT and VR_FAULT Indication

When the sensed temperature is higher than the maximim temperature specification T_MAX,(110°C by default), the

device pulls the VR_HOT pin low. This adjustment provides a warning signal to the load.

注

Only the PMBus interface can establish the maximum temperature (T_MAX) setting. NVM

does not store this setting.

VR_FAULT is used as an indication of severe fault. VR_FAULT wil be pulled low when the below fault occurs:

•

Input Overcurrent Fault

Over Temperature Fault

Overvoltage Fault

Power Stage Fault (V_TSEN> 2.5V)

7.4 Device Functional Modes

表 3. Maximum Operating Phase Numbers

MAXIMUM ACTIVE

PHASES

CSP1

CSP2

CSP3

CSP4

CSP5

CSP6

IOUT1

V3R3

IOUT2

n/a

1

2

3

4

5

6

V3R3

IOUT3

n/a

V3R3

IOUT4

n/a

V3R3

IOUT5

n/a

V3R3

IOUT6

7.5 Programming

7.5.1 User Selections

When SKIP-NVM pin is connected to GND with ≤ 20-kΩ resistor, the resistors connected to O-USR, F-IMAX,

SLEW-MODE, OCL-R, VBOOT and ADDR-TRISE determine the associated configurations. If SKIP-NVM pin is

connected to GND with ≥ 100-kΩ resistor, these configurations are determined by NVM settings. Please note the

address setting is determined only by the resistors on the ADDR-TRISE pin and cannot be set by NVM. When

the V3R3 pin powers up, the following information is latched for normal operations, and can be changed via the

PMBus interface. The Electrical Characteristics table defines the values of the selections.

33

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

Programming (接下页)

In general, the NVM provides more selection than pinstrap configurations. For example, pinstrap for switching

frequency offers 3-bit, 8 selections, which correlates to MFR_SPEC_12<6:4>. Alternatively, NVM provides 4-bit,

16 selections.

7.5.1.1 Switching Frequency

The resistor from F-IMAX pin to GND sets the switching frequency from 300 kHz to 1 MHz. See the Electrical

Characteristics table for the resistor settings corresponding to each frequency selection. Please note that the

operating frequency is a quasi-fixed frequency in the sense that the ON time is fixed based on the input voltage

(at the VIN pin) and output voltage (set by VID). The OFF time varies based on various factors such as load and

power-stage components.

7.5.1.2 IMAX Information

The max current information of the load(IMAX) can be set by the voltage on the F-IMAX pin. See the Electrical

Characteristics table for the details. The default OCP fault trigger level is 125% of IMAX.

7.5.1.3 Boot Voltage

The boot voltage is the controller voltage at start-up to before any output voltage change by the

VOUT_COMMAND. If there is no further output voltage adjustment, the output voltage remains at the boot

voltage level.

The resistor from the VBOOT pin to GND and the voltage level on this pin set 7 high bits of the boot voltage. The

lowest bit is set by the ADDR-TRISE pin. See the Electrical Characteristics table for the resistor settings

corresponding to boot voltage selections.

7.5.1.4 Per-Phase Overcurrent Limit (OCL) Level

The resistor from the OCL-R pin to GND and the voltage level on this pin set the per-phase OCL level. See the

Electrical Characteristics table for the details.

7.5.1.5 Overshoot Reduction (OSR) and Undershoot Reduction (USR) Levels

The resistor from the O-USR pin to GND and the voltage on O-USR pin set the OSR and USR levels. See the

Electrical Characteristics table for details.

7.5.1.6 Slew Rate Selection

The V_OUTchange slew rate is set by the resistor from the SLEW-MODE pin to GND. See the Electrical

Characteristics table for details.

7.5.1.7 Mode Selections

The TPS53667 device supports different operating modes, including VR12.0/VR12.5, phase interleaving mode,

dynamic phase shedding, and zero load-line. The voltage on SLEW-MODE pin sets the desired operating

modes.

7.5.1.8 Soft Start Slew Rate and PMBus Addresses

The resistor from the ADDR-TRISE pin to GND and the voltage on ADDR-TRISE pin set the slew rate of soft

start and the address of PMBus interface. See the Electrical Characteristics table for details.

7.5.1.9 Ramp Selection

The internal ramp can be set by the voltage on the OCL-R pin. See the Electrical Characteristics table for details.

7.5.1.10 Maximum Active Phase Numbers

The maximum active phase numbers can be selected by connecting CSP2, CSP3, CSP4, CSP5 or CSP6 to the

V3R3. See 表 3 for details. The device latches this configuration when V3R3 powers up.

34

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

Programming (接下页)

7.5.1.11 Pinstrap Mode Settings

表 4 summarizes the functions controlled with pin-strap resistors. For details of each setting please refer to the

Electrical Characteristics table. For more information on VID encoding see the VID section.

表 4. Pinstrap Mode Summary

FUNCTION

DESCRIPTION

NAME

NO.

Voltage divider to VREF pin.

Slew Rate

SLEW-MODE

29

A pin-strap resistor (R_SLEW-MODE) connected between this pin and GND sets

one of eight possible slew rates.

The voltage level (V_SLEW-MODE) sets 4-bit operation modes.

-Bit 7 for DAC mode (1 for VR12.0; 0 for VR12.5).

-Bit 6 for the 4-phase interleaving mode (1 for 1/3 and 2/4 two phase

interleaving; 0 for 4 phase interleaving individually).

Mode

SLEW-MODE

29

-Bit 4 for enabling dynamic phase add or drop (1 for enable; 0 for disable).

-Bit 3 sets zero load-line (1 for zero load-line; 0 for non-zero load-line)

The device latches these settings when V3R3 powers up.

Voltage divider to VREF pin.

Overshoot reduction

Undershoot reduction

O-USR

30

A pin-strap resistor (R_O-USR) connected between this pin and GND selects 1

of 7 OSR thresholds or OFF.

The voltage level (V_O-USR) sets 1 of 7 USR levels or OFF.

The device latches these settings when V3R3 powers up.

Voltage divider to VREF pin.

A pin-strap resistor (R_VBOOT) connected between this pin and GND sets 3

bits (B[3:1]).

The voltage level (V_BOOT) sets 4 bits (B[7:4]). The total 7 bit sets 7 of 8 bits of

VID of VBOOT(B[7:1]).

VBOOT

31

28

The device latches these settings when V3R3 powers up.

Voltage divider to VREF pin.

Voltage boot

A pin-strap resistor (R_ADDR-TRISE) connected between this pin and GND sets

3-bits.

-Bit 2 and Bit 1 set the rise slew rate (TRISE).

ADDR-TRISE

-Bit 0 Selects the LSB of BOOT voltage.

The voltage (V_ADDR-TRISE) sets 4 bits PMBus address.

The device latches these settings when V3R3 powers up.

Voltage divider to VREF pin.

A pin-strap resistor (R_ADDR-TRISE) connected between this pin and GND sets

3-bits.

-Bit 2 and Bit 1 set the rise slew rate (TRISE).

Rise slew rate

ADDR-TRISE

28

-Bit 0 Selects the LSB of BOOT voltage.

-The voltage (V_ADDR-TRISE) sets 4 bits PMBus address.

The device latches these settings when V3R3 powers up

Voltage divider to VREF pin.

Frequency

F-IMAX

32

A pin-strap resistor (R_F-IMAX) connected between this pin and GND sets the

operating frequency of the controller.

The voltage level (V_F-IMAX) sets the maximum operating current of the

converter.

Current limit

The IMAX value is an 8-bit A/D where V_F-IMAX= V_VREF× IMAX / 255.

Both are latched at V3R3 power-up.

Voltage divider to VREF pin.

Overcurrent limit

Ramp

OCL-R

1

A pin-strap resistor (R_OCL-R) connected between this pin and GND and the

voltage level (V_OCL-R) selects one of 16 OCL levels (per phase current-limit).

V_OCL-Rsets one of four RAMP levels.

The device latches these settings when the V3R3 pin powers up.

35

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

7.5.1.12 NVM Default Settings

表 5 lists the default settings in NVM where the shaded rows denote register functions that are configured by

associated pins in pinstrap mode.

表 5. NVM Default Settings

DEFAULT VALUES

REGISTER

FUNCTION

Slew Rate

bit 7

bit 6

bit 5

—

0

bit 4

bit 3

bit 2

bit 1

0

bit 0

MFR_SPECIFIC_13 [2:0]

MFR_SPECIFIC_13 [7:3]

MFR_SPECIFIC_09 [2:0]

MFR_SPECIFIC_09 [6:4]

MFR_SPECIFIC_11 [7:0]

MFR_SPECIFIC_12 [1:0]

MFR_SPECIFIC_12[7:4]

MFR_SPECIFIC_10 [7:0]

MFR_SPECIFIC_00 [3:0]

MFR_SPECIFIC_14[2:0]

MFR_SPECIFIC_07 [0]

MFR_SPECIFIC_07 [1]

MFR_SPECIFIC_07 [2]

0

1

Mode

1

0

1

—

1

OSR

—

1

USR

—

1

0

1

—

VBOOT

0

1

0

1

0

TRISE

—

Frequency

IMAX

0

1

0

1

0

1

0

1

0

1

0

1

0

OCL

—

RAMP

—

0

Soft-start slew rate

OSR_TRISTATE

SLEW_FAST

—

0

1

—

0

—

Power Stage Fault

Disable

MFR_SPECIFIC_07 [3]

0

—

MFR_SPECIFIC_07 [4]

MFR_SPECIFIC_16 [1:0]

MFR_SPECIFIC_15 [3]

MFR_SPECIFIC_15 [2:0]

OV Hiccup Disable

VIN UVLO

—

0

—

0

—

0

1

DPS_TH_LOW

DPS_TH_HIGH

—

1

0

Current Sharing

Warning

Response

MFR_SPECIFIC_19 [3]

—

Current Sharing

Warning Threshold

MFR_SPECIFIC_19 [2:0]

MFR_SPECIFIC_21 [4:3]

—

1

Tracking OV

OFFSET

—

0

1

—

MFR_SPECIFIC_21 [2:0]

MFR_SPECIFIC_22 [2:0]

MFR_SPECIFIC_05 [7:0]

MFR_ID

Fixed OV OFFSET

UV OFFSET

—

0

1

0

1

0

1

0

1

0

1

0

1

0

VOUT OFFSET

0

1

0

1

0

MFR_MODEL

0

—

MFR_REVISION [3:0]

MFR_DATE

—

0

36

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

7.5.1.13 6-Phase Application

图 19 shows the diagram for a 6-Phase application with smart power stage (CSD95490Q5MC) and pinstrap

configurations.

12 V

BOOT

VIN

BOOT_R

TAO

V_{CORE_OUT}

Load

TPS53667

VSP

PWM

FCCM

VDD

VSW

PWM 1

Power Stage

VSN

SKIP-NVM

5 V

OCL-R

PGND

REFIN

Enable

AGND

IOUT

COMP

VREF

F-IMAX

CSP1

TSEN

B-TMAX

O-USR

12 V

BOOT

VIN

BOOT_R

TAO

PWM2

PWM

FCCM

VDD

VSW

Power Stage

5 V

PGND

REFIN

ADDR

Enable

AGND

IOUT

SLEW-MODE

CSP2

ISUM

IMON

SCLK

ALERT

To and

From CPU

SDIO

VR_RDY

VR_HOT

PMB_CLK

PMB_ALERT

PMB_DIO

ENABLE

I²C or PMBus

(Optional)

ENABLE

12 V

VR_FAULT

BOOT

VIN

BOOT_R

VR_FAULT

TAO

12 V

VIN

V5

PWM6

PWM

FCCM

VDD

VSW

Power Stage

5 V

PGND

REFIN

5 V

Enable

AGND

IOUT

3.3 V

V3P3

CSP6

GND

图 19. 6-Phase Application with Smart Power Stage (CSD95490Q5MC) and Pinstrap Configuration

37

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

7.5.1.14 6-Phase NVM Application

图 20 shows the diagram for a 6-Phase application with smart power stage (CSD95490Q5MC) and NVM

configurations.

12 V

BOOT

VIN

BOOT_R

TAO

VSW

V_OUT

Load

TPS53667

VSP

PWM

FCCM

VDD

PWM 1

Power Stage

VSN

SKIP-NVM

5 V

OCL-R

Enable

PGND IMON REFIN

COMP

VREF

F-IMAX

CSP1

TSEN

VBOOT

O-USR

12 V

BOOT

BOOT_R

TAO

VSW

VIN

PWM2

PWM

FCCM

VDD

Power Stage

5 V

ADDR-TRISE

SLEW-MODE

Enable

PGND IMON REFIN

CSP2

ISUM

IMON

ENABLE

VR_RDY

VR_HOT

VR_FAULT

PMB_CLK

PMBus

PMB_ALERT

PMB_DIO

RESET

12 V

BOOT

BOOT_R

TAO

VSW

VIN

12 V

5 V

VIN

V5

PWM6

PWM

FCCM

VDD

Power Stage

5 V

Enable

PGND IMON REFIN

V3R3

CSP6

GND

图 20. 6-Phase Application with Smart Power Stage (CSD95490Q5MC) and NVM Configuration

38

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

7.5.2 Supported Protections and Fault Reports

The TPS53667 device supports different types of fault protections, and the warning or fault reports can be found

in the corresponding PMBus registers. The TPS53667 also supports VR_FAULT to indicate catastrophic faults to

the system. If the fault causes the controller to latch-off, then V5 or EN re-cycling is required to clear the latched

faults. Only V5 recycling can clear PRE_OVF .

表 6. Supported Protections and Fault Reports

FAULT NAME

VOLTAGE

DESCRIPTIONS

LATCH-OFF

ALERT

REPORT

VR_FAULT

PMB_ALERT

PRE_OVF

OVF

V_OUT> V_OVPFP

Y

PMBus

VR_FAULT

PMB_ALERT

V_OUT> VID + V_OVPT5/0or V_OUT> V_OVPF5

UVF

V_OUT< VID – V_RDYL– V_DROOP

N

PMB_ALERT

PMBus

VIN_OVF

VIN_UVF

CURRENT

OCF

V_VIN> VIN_OV_FAULT_LIMIT when the controller is enabled

V_VIN< V_INUVLOwhen the controller is enabled

I

_OUT≥ IOUT_OC_FAULT_LIMIT

_O≥ IOUT_OC_WARN_LIMIT

N

PMB_ALERT

PMBus

OCW

I

VR_FAULT

PMB_ALERT

IOCF

I

_IN≥ IIN_OC_FAULT_LIMIT

_IN≥ IIN_OC_WARN_LIMIT

Y

N

PMBus

IOCW

I

PMB_ALERT

TEMPERATURE

VR_FAULT

PMB_ALERT

OTF

T

_sen≥ OT_FAULT_LIMIT

N

PMBus

OTW

T

_sen≥ OT_WARNING_LIMIT

_sen≥ T_MAX

N

Y

PMB_ALERT

VR_HOT

TMAX_F

TS_VREFF

TS_GND

T

TSEN pin short to VREF

TSEN pin short to GND

PMB_ALERT

PMBus

VR_FAULT

PMB_ALERT

TS_PS

V_TSEN> 2.5 V

Y

PMBus

7.5.3 Supported PMBus Address and Commands Summary

7.5.3.1 Address Selection

The TPS53667 device has a dedicated pin (ADDR-TRISE) for determining the address for the PMBus

communication. The device supports a total of 16 possible addresses. See the Electrical Characteristics table for

details.

7.5.3.2 Commands Summary

The TPS53667 device supports only PMBus command sets listed in 表 7. In pinstrap mode, the default state of

all the configuration registers (shaded rows in 表 5) should be detected from pinstrap settings, but users can

overwrite the settings via PMBus after the power-up sequence is complete. In NVM mode, the default values can

be found in the register descriptions.

39

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

7.6 Register Maps

7.6.1 PMBus Description

7.6.1.1 PMBus General

Timing and electrical characteristics of the PMBus can be found in the PMB Power Management Protocol

Specification, Part 1, revision 1.1 available at http://PMBus.org. The TPS53667 device supports both the 100-kHz

and 400-kHz bus timing requirements. The TPS53667 device does not stretch pulses on the PMBus when

communicating with the master device.

Communication over the TPS53667 device PMBus interface can support the packet error checking (PEC)

scheme if desired. If the master supplies CLK pulses for the PEC byte, PEC is used. If the CLK pulses are not

present before a STOP, the PEC is not used.

The TPS53667 device supports a subset of the commands in the PMBus 1.1 specification. Most of the controller

parameters can be programmed using the PMBus and stored as defaults for later use. All commands that require

data input or output use the literal format. The exponent of the data words is fixed at a reasonable value for the

command and altering the exponent is not supported. Direct format data input or output is not supported by the

TPS53667 device. See the Supported PMBus Commands section for specific details.

The TPS53667 device also supports the SMBALERT response protocol. The SMBALERT response protocol is a

mechanism by which a slave (the TPS53667 device) can alert the bus master that it wants to talk. The master

processes this event and simultaneously accesses all slaves on the bus (that support the protocol) through the

alert response address. Only the slave that caused the alert acknowledges this request. The host performs a

modified receive byte operation to get the slave’s address. At this point, the master can use the PMBus status

commands to query the slave that caused the alert. For more information on the SMBus alert response protocol,

see the System Management Bus (SMBus) specification.

The TPS53667 device contains non-volatile memory that is used to store configuration settings and scale factors.

The settings programmed into the device are not automatically saved into this non-volatile memory though. The

STORE_DEFAULT_ALL command must be used to commit the current settings to non-volatile memory as

device defaults. The settings that are capable of being stored in non-volatile memory are noted in their detailed

descriptions.

7.6.1.2 PMBus Connections

The TPS53667 device can operate in either standard mode (100kbit/s) or fast mode (400kbit/s). Connection for

the PMBus interface should follow the High Power DC specifications given in Section 3.1.3 of the System

Management Bus (SMBus) Specification V2.0 for the 400-kHz bus speed or the Low Power DC specifications in

Section 3.1.2. The complete SMBus specification is available from the SMBus website, smbus.org.

7.6.1.3 Supported Data Formats

The TPS53667 device supports both linear and VID data formats. The linear data format is used for all telemetry

reporting data, and VID formatting for certain other commands. (see the Supported PMBus Commands section

for more details on which command supports each data type). Examples of commands that support VID

formatting include VOUT_MODE (Read-only Byte) and VOUT_COMMAND (Read/Write Word). An example of

each can be seen below in Figure 21 and Figure 22.

VOUT_MODE Data Byte .

7

6

5

4

3

2

1

0

Mode = 001b

VID Code Type .

Figure 21. VOUT_MODE Data Byte for VID Mode

43

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

Register Maps (continued)

Data Byte High .

Data Byte Low .

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

VID (Right Justified) .

Figure 22. VOUT_COMMAND Data Bytes for VID Mode

The Linear Data Format is a two byte value with:

•

An 11-bit, two's complement mantissa, and

•

A 5-bit, two's complement exponent (scaling factor).

The format of the two bytes is shown in Figure 23.

Data Byte High .

Data Byte Low .

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

MSB

N.

Y.

Figure 23. Linear Data Format Data Bytes

The relation between Y, N, and the real world value is as shown in Equation 6.

X = Y × 2^N

where

•

X is the real world value

Y is an 11-bit, two's complement integer

N is a 5-bit, two's complement integer

(6)

Note that devices that use the Linear format must accept and be able to process any value of N.

7.6.1.4 PMBus Command Format

The TPS53667 device is a PMBus-compliant device. Figure 24 through Figure 35 show the major communication

protocols used. For full details on the PMBus communication protocols, please visit http://pmbus.org.

1

7

1

8

1

8

1

S

Slave Address

W

A

Command Code

A

Data Byte

A

P

Figure 24. Write Byte Protocol

1

7

1

8

1

8

1

8

1

S

Slave Address

W

A

Command Code

A

Data Byte

A

PEC

A

P

Figure 25. Write Byte Protocol with PEC

44

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

Register Maps (continued)

1

7

1

8

1

7

1

8

1

S

Slave Address

W

A

Command Code

A

S

Slave Address

R

A

Data Byte Low

A

8

1

Data Byte High

A

P

Figure 26. Write Word Protocol

1

7

1

8

1

8

1

8

1

S

Slave Address

W

A

Command Code

A

Data Byte Low

A

Data Byte High

A

P

8

1

PEC

A

P

Figure 27. Write Word Protocol with PEC

1

7

1

8

1

7

1

8

1

S

Slave Address

W

A

Command Code

A

S

Slave Address

R

A

Data Byte

A

P

Figure 28. Read Byte Protocol

1

7

1

8

1

7

1

8

1

S

Slave Address

W

A

Command Code

A

S

Slave Address

R

A

Data Byte

A

8

1

PEC

A

P

Figure 29. Read Byte Protocol with PEC

1

7

1

8

1

7

1

8

1

S

Slave Address

W

A

Command Code

A

S

Slave Address

R

A

Data Byte Low

A

8

1

Data Byte High

A

P

Figure 30. Read Word Protocol

1

7

1

8

1

7

1

8

1

S

Slave Address

W

A

Command Code

A

S

Slave Address

R

A

Data Byte Low

A

8

1

8

1

Data Byte High

A

PEC

A

P

Figure 31. Read Word Protocol with PEC

45

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

Register Maps (continued)

1

7

1

8

1

8

1

8

1

S

Slave Address

W

A

Command Code

A

Byte Count = n

A

Data Byte 1

A

8

1

8

1

Data Byte 2

A

Data Byte n

A

P

Figure 32. Block Write Protocol

1

7

1

8

1

8

1

8

1

S

Slave Address

W

A

Command Code

A

Byte Count = n

A

Data Byte 1

A

8

1

8

1

8

1

Data Byte 2

A

Data Byte n

A

PEC

A

P

Figure 33. Block Write Protocol with PEC

1

7

1

8

1

7

1

8

1

S

Slave Address

W

A

Command Code

A

Sr Slave Address

R

A

Byte Count = n

A

8

1

8

1

8

1

Data Byte 1

A

Data Byte 2

A

Data Byte n

A

P

Figure 34. Block Read Protocol

1

7

1

8

1

7

1

8

1

S

Slave Address

W

A

Command Code

A

Sr Slave Address

R

A

Byte Count = n

A

8

1

8

1

8

1

8

1

Data Byte 1

A

Data Byte 2

A

Data Byte n

A

PEC

A

P

Figure 35. Block Read Protocol with PEC

46

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

Register Maps (continued)

7.6.2 PMBus Functionality

7.6.2.1 PMBus Address

The TPS53667 device has a dedicated pin (ADDR-TRISE) for determining the address for the PMBus

communication. The device supports a total of 16 possible addresses as listed in the Electrical Characteristics

table.

7.6.2.2 Pin Strap Settings

The TPS53667 device supports only PMBus command sets listed in the Electrical Characteristics table. In

pinstrap mode, the default state of all the configuration registers should be detected from pin strap settings, but

users can overwrite the settings via PMBus after the power-up sequence is complete. The pin strap settings can

be found in the Electrical Characteristics table.

7.6.2.3 Supported PMBus Commands

The TPS53667 device supports the following commands from the PMBus 1.1 specification.

7.6.2.3.1 OPERATION (01h)

Format

N/A

Description

The OPERATION command is used to turn the device output on or off in

conjunction with the input from the ENABLE pin. It is also used to set the output

voltage to the upper or lower MARGIN levels.

Default

00h

Figure 36. OPERATION Register

7

6

5

4

3

2

1

0

ON_OFF

R/W

SOFT_OFF

R-0

OPMARGIN

R/W

IIN_OC_VRHOT

R/W

Table 8. OPERATION Register Field Descriptions

Bit

Rese

Field

Type

t

NVM

Description

7

ON_OFF

R/W

0

—

The On/Off bit is used to enable the IC via PMBus. The

necessary condition for this bit to be effective is that the CMD bit

in the ON_OFF CONFIG register is set high. However, the CMD

bit being high is not a sufficient condition to enable the IC via the

On bit, as specified below:

0: (Default) The device output is not enabled via PMBus.

1: The device output is enabled if:

MMMa. The supply voltage VIN is greater than the VIN_UVLO

threshold, the cmd bit is high, and

MMMb. The bit CP in the ON_OFF CONFIG register is low, or

MMMc. The bit CP is high and the ENABLE pin is asserted.

6

SOFT_OFF

R

0

—

This bit is not supported and always set to 0 on this device.

0: No Soft off

1: Not Supported.

5-2

OPMARGIN

R/W

If Margin Low is enabled, load the value from the

VOUT_MARGIN_LOW register. If Margin High is enabled, load

the value from the VOUT_MARGIN_HIGH register.

00xx: Turn off VOUT margin function

0101: Turn on VOUT margin low and ignore fault

0110: Turn on VOUT margin low and act on fault

1001: Turn on VOUT margin high and ignore fault

1010: Turn on VOUT margin high and act on fault

47

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

Table 8. OPERATION Register Field Descriptions (continued)

Bit

Rese

t

Field

Type

NVM

Description

1-0

IIN_OC_VRHOT

R/W

00

—

This bit sets the option of asserting VRHOT when

IIN_OC_WARN_LIMIT is detected.

01: VRHOT assertion ON with IIN_OC_WARN_LIMIT detection

others: VRHOT assertion OFF with IIN_OC_WARN_LIMIT

detection

7.6.2.3.2 ON_OFF_CONFIG (02h)

Format

N/A

Description

The ON_OFF_CONFIG command configures the combination of CONTROL pin

input and serial bus commands needed to turn the unit on and off. This includes

how the unit responds when power is applied.

Default

17h

Figure 37. ON_OFF_CONFIG Register

7

6

5

4

3

2

1

0

Reserved

R-000

PU

R-1

CMD

R/W

CP

R/W

PL

R-1

SP

R-1

Table 9. ON_OFF_CONFIG Register Field Descriptions

Bit

Rese

Field

Type

R

t

NVM

—

Description

7-5

4

Reserved

000

1

Always set to 0.

PU

R

—

This bit is not supported and always set to 1 on this

device.

0: Not supported.

1: Device will act on ENABLE pin assertion and/or

ON_OFF bit (OPERATION<7>).

3

2

CMD

R/W

0

1

—

The CMD bit controls how the device responds to the

OPERATION<7> bit.

0: (Default) Device ignores the ON_OFF

OPERATION<7> bit.

1: Device responds to the ON_OFF OPERATION<7>

bit.

CP

The CP bit controls how the device responds to the

ENABLE pin

0: Device ignores the ENABLE pin, and ON/OFF is

controlled only by the OPERATION command

1: Device responds to the ENABLE pin.

1

0

PL

SP

R

1

—

This bit is not supported and always set to 1 on this

device.

0: Not supported.

1: ENABLE pin has active high polarity.

This bit is not supported and always set to 1 on this

device.

0: Not supported.

1: Turn off output as fast as possible.

48

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

7.6.2.3.3 CLEAR_FAULTS (03h)

Format

N/A

Description

Clears any faults bits that have been set. At the same time, simultaneously clears

all bits in all status registers and negates the PMB_ALERT signal output if it is

asserted.

The CLEAR_FAULTS command does not cause a unit that has latched off for a

condition to restart. If the fault remains present when the bit is cleared, the fault bit

is reset and the host notified by the usual means.

Default

NONE

Figure 38. CLEAR_FAULTS Register

7

6

5

4

3

2

1

0

N/A

—

N/A

—

N/A

—

N/A

—

N/A

—

N/A

—

N/A

—

N/A

—

Table 10. CLEAR_FAULTS Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

7-0

N/A

—

No data bytes are sent, only the command code is

sent.

7.6.2.3.4 WRITE_PROTECT (10h)

Format

N/A

Description

The WRITE_PROTECT command is used to control writing to the PMBus device.

The intent of this command is to provide protection against accidental changes.

This command has one data byte as described below.

NOTE: Invalid data written to WRITE_PROTECT[7:5] causes the ’CML’ bit in the

STATUS_BYTE and the ‘US_DATA’ bit in the STATUS_CML registers to be set.

Invalid data also results in no write protection.

Default

00h

Figure 39. WRITE_PROTECT Register

7

6

5

4

3

2

1

0

bit7

R/W

bit6

R/W

bit5

R/W

Reserved

R-0 0000

Table 11. WRITE_PROTECT Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

7

bit7

R/W

0

—

0: (Default) See Table 12.

1: Disable all writes except for the

WRITE_PROTECT command (bit5 and bit6 must be

0 to be valid).

6

5

bit6

bit5

—

0: (Default) See Table 12.

1: Disable all writes except for the

WRITE_PROTECT and OPERATION commands

(bit5 and bit7 must be 0 to be valid).

0: (Default) See Table 12.

1: Disable all writes except for the

WRITE_PROTECT, OPERATION, and

ON_OFF_CONFIG commands (bit6 and bit7 must

be 0 to be valid).

4:0

Reserved

R

0 0000

—

Always set to 0.

49

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

Table 12. WRITE_PROTECT Data Byte Values

Data Byte Value

1000 0000

Action

Disables all writes except to the WRITE_PROTECT command.

0100 0000

Disables all writes except to the WRITE_PROTECT and OPERATION commands.

Disables all writes to the WRITE_PROTECT, OPERATION, ON_OFF_CONFIG and

VOUT_COMMAND commands.

0010 0000

0000 0000

Others

Enable writes to all commands

Invalid data.

7.6.2.3.5 STORE_DEFAULT_ALL (11h)

Format

N/A

Description

The STORE_DEFAULT_ALL command instructs the PMBus device to copy the

entire contents of the Operating Memory to the matching locations in the non-

volatile Default Store memory. Any items in the Operating Memory that do not

have matching locations in the Default Store are ignored.

Following a STORE_DEFAULT_ALL command, the following registers return to

the default values regardless of the values in the Operating Memory:

•

OC_FAULT_LIMIT returns to 125%×IMAX,

OC_WARN_LIMIT returns to IMAX,

VOUT_COMMAND returns to VBOOT,

VOUT_MAX returns to 00FFh (1.52V in VR12.0 mode and 3.04 V in VR12.5

mode)

Default

NONE

Figure 40. STORE_DEFAULT_ALL Register

7

6

5

4

3

2

1

0

N/A

—

N/A

—

N/A

—

N/A

—

N/A

—

N/A

—

N/A

—

N/A

—

Table 13. STORE_DEFAULT_ALL Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

7:0

N/A

—

No data bytes are sent, only the command code is

sent.

7.6.2.3.6 RESTORE_DEFAULT_ALL (12h)

Format

N/A

Description

The RESTORE_DEFAULT_ALL command instructs the PMBus device to copy the

entire contents of the non-volatile Default Store memory to the matching locations

in the Operating Memory. The values in the Operating Memory are overwritten by

the value retrieved from the Default Store. Any items in Default Store that do not

have matching locations in the Operating Memory are ignored.

Default

NONE

Figure 41. RESTORE_DEFAULT_ALL Register

7

6

5

4

3

2

1

0

N/A

—

N/A

—

N/A

—

N/A

—

N/A

—

N/A

—

N/A

—

N/A

—

50

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

Table 14. RESTORE_DEFAULT_ALL Register Field Descriptions

Bit

Field

N/A

Type

Reset

Description

No data bytes are sent, only the command code is sent.

7:0

—

7.6.2.3.7 CAPABILITY (19h)

Format

N/A

Description

This command provides a way for a host system to determine some key

capabilities of this PMBus device.

Default

B0h

Figure 42. CAPABILITY Register

7

6

5

4

3

2

1

0

PEC

R-1

SPD

R-01

PMBALERT

R-1

Reserved

R-0000

Table 15. CAPABILITY Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

7

PEC

R

1

—

Packet Error Checking is supported.

1: Default

6:5

4

SPD

01

1

—

Maximum supported bus speed is 400 kHz.

01: Default

PMBALERT

This device does have a PMBALERT pin and does

support the SMBus Alert Response Protocol.

1: Default

3:0

Reserved

R

0000

—

Always set to 0.

7.6.2.3.8 VOUT_MODE (20h)

Format

VID

Description

The PMBus specification dictates that the data word for the VOUT_MODE

command is one byte that consists of a 3-bit Mode and 5-bit parameter, as shown

below.

This command is read-only. If the host sends a VOUT_MODE command for

writing, the device will reject the command and declare a communication fault for

invalid data and respond as described in PMBus specification II section 10.2.2.

Default

21h

Figure 43. VOUT_MODE Register

7

6

5

4

3

2

1

0

DATA_MODE

R-001

DATA_PARAMETER

R

Table 16. VOUT_MODE Register Field Descriptions

Bit

7:5

4:0

Field

Type Reset

NVM

—

Description

DATA_MODE

R

001

001: VID mode.

DATA_PARAMETER

0 0001

—

00010: For VR12.5 Mode

00001: For VR12.0 Mode

51

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

7.6.2.3.9 VOUT_COMMAND (21h)

Format

VID

Description

VOUT_COMMAND causes the device to set its output voltage to the commanded

value with two data bytes. These data bytes consist of a right-justified VID code

with VID0 in bit 0 of the lower data byte, VID1 in bit 1 of the lower byte and so

forth. The VID table mapping is determined by the selected VID protocols (VR12.0

or VR12.5) from SLEW_MODE pin or MFR_SPECIFIC_13.

Default

VBOOT

Figure 44. VOUT_COMMAND Register

15

7

14

6

13

5

12

11

10

9

1

8

0

Reserved

R-0000 0000

4

3

2

VOUT

R/W

Table 17. VOUT_COMMAND Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

15:8

Reserved

R

0000

—

Always set to 0.

7:0

VOUT

R/W

—

Used to set the commanded VOUT. Cannot be set

to a level above the value set by VOUT_MAX.

7.6.2.3.10 VOUT_MAX (24h)

Format

VID

Description

The VOUT_MAX command sets an upper limit on the output voltage that the unit

can command regardless of any other commands or combinations. The intent of

this command is to provide a safeguard against a user accidentally setting the

output voltage to a possibly destructive level.

The device detects that an attempt has been made to program the output to a

voltage greater than the value set by the VOUT_MAX command. This will then be

treated as a warning condition and not a fault condition. If an attempt is made to

program the output voltage higher than the limit set by this command, the device

responds as follows:

•

The commanded output voltage is set to VOUT_MAX,

The OTHER bit is set in the STATUS_BYTE,

The VOUT bit is set in the STATUS_WORD,

The VOUT_MAX warning bit is set in the STATUS_VOUT register, and

The device notifies the host (asserts PMBUS_ALERT).

The data bytes are two bytes, which are in right-justified VID format. The VID

table mapping determined by the selected VID protocols (VR12.0 or VR12.5) from

the SLEW_MODE pin or MFR_SPECIFIC_13.

Default

00FFh .

Figure 45. VOUT_MAX Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

Reserved

R-0000 0000

4

3

VOUT_MAX

52

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

R/W

Table 18. VOUT_MAX Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

15:8

Reserved

R

0000

—

Always set to 0.

7:0

VOUT_MAX

R/W

1111

—

Used to set the maximum VOUT of the device.

7.6.2.3.11 VOUT_MARGIN_HIGH (25h)

Format

VID

Description

The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the

output is to be changed when the OPERATION command is set to Margin High.

The data bytes are two bytes, which are in right-justified VID format. The VID

table mapping determined by the selected VID protocols from the SLEW_MODE

pin or MFR_SPECIFIC_13.

Default

0000h

Figure 46. VOUT_MARGIN_HIGH Register

15

7

14

6

13

5

12

11

10

9

1

8

0

Reserved

R-0000 0000

4

3

2

VOUT_MARGIN_HIGH

R/W

Table 19. VOUT_MARGIN_HIGH Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

15:8

Reserved

R

0000

—

Always set to 0.

7:0

VOUT_MARGIN_HIGH

R/W

0000

—

Used to set the value for the VOUT Margin High.

7.6.2.3.12 VOUT_MARGIN_LOW (26h)

Format

VID

Description

The VOUT_MARGIN_LOW command loads the unit with the voltage to which the

output is to be changed when the OPERATION command is set to Margin Low.

The data bytes are two bytes, which are in right-justified VID format. The VID

table mapping determined by the selected VID protocols from the SLEW_MODE

pin or MFR_SPECIFIC_13.

Default

0000h

Figure 47. VOUT_MARGIN_LOW Register

15

7

14

6

13

5

12

11

10

9

1

8

0

Reserved

R-0000 0000

4

3

2

VOUT_MARGIN_LOW

R/W

53

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

Table 20. VOUT_MARGIN_LOW Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

15:8

Reserved

R

0000

—

Always set to 0.

7:0

VOUT_MARGIN_LOW

R/W

0000

—

Used to set the value for the VOUT Margin Low.

7.6.2.3.13 IOUT_CAL_OFFSET (39h)

Format

Linear

Description

The IOUT_CAL_OFFSET command sets the value of compensation for offset

errors in the READ_IOUT command, in amperes.

Default

0000h

Figure 48. IOUT_CAL_OFFSET Register

15

7

14

6

13

IOCAL_OFS_EXPONENT

R/W

12

11

10

9

IOCAL_OFS_MANTISSA

R/W

8

0

5

4

3

2

1

IOCAL_OFS_MANTISSA

R/W

Table 21. IOUT_CAL_OFFSET Register Field Descriptions

Bit

15:11 IOCAL_OFS_EXPONENT

10:0 IOCAL_OFS_MANTISSA

Field

Type Reset

R/W

NVM

—

Description

5-bit, two's complement exponent (scaling factor).

11-bit, two's complement mantissa.

R/W

—

7.6.2.3.14 VOUT_OV_FAULT_RESPONSE (41h)

Format

N/A

Description

The VOUT_OV_FAULT_RESPONSE command instructs the device on what

action to take in response to an output overvoltage fault. Upon triggering the

overvoltage fault, the controller is latched off, and the following actions are taken:

•

Set the VOUT_OV_FAULT bit in the STATUS_BYTE,

Set the VOUT bit in the STATUS_WORD,

Set the VOUT_OV_FAULT bit in the STATUS_VOUT register, and

The device notifies the host (asserts PMB_ALERT).

Default

!~ filter="filter4, filter5"80hfilter="filter6"9Ah!~9Ah

Figure 49. VOUT_OV_FAULT_RESPONSE Register

7

6

5

4

3

2

1

0

VOUT_OV_FAULT_RESPONSE

R-1000 0000

Table 22. VOUT_OV_FAULT_RESPONSE Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

7:0

VOUT_OV_FAULT_RESPO

NSE

R

1000

0000

—

Upon triggering the overvoltage fault, the controller

will shut the device down immediately and will not

attempt to restart. The output remains disabled until

the fault is cleared.

54

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

7.6.2.3.15 VOUT_UV_FAULT_RESPONSE (45h)

Format

N/A

Description

The VOUT_UV_FAULT_RESPONSE instructs the device on what action to take in

response to an output undervoltage fault. Upon triggering the undervotlage fault,

the following actions are taken:

•

Set the OTHER bit in the STATUS_BYTE,

Set the VOUT bit in the STATUS_WORD,

Set the VOUT_UV_FAULT bit in the STATUS_VOUT register, and

The device notifies the host (asserts PMB_ALERT).

Default

BAh

Figure 50. VOUT_UV_FAULT_RESPONSE Register

7

6

5

4

3

2

1

0

VOUT_UV_FAULT_RESPONSE

R-1011 1010

Table 23. VOUT_UV_FAULT_RESPONSE Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

7:0

VOUT_UV_FAULT_RESPON

SE

R

1011

1010

—

Upon triggering the undervoltage fault, the controller

will shut the device down immediately and will

attempt to restart after a 22 ms delay.

7.6.2.3.16 IOUT_OC_FAULT_LIMIT (46h)

Format

Linear

Description

The IOUT_OC_FAULT_LIMIT command sets the value of the output current, in

amperes, that causes an overcurrent fault condition. Upon triggering the

overcurrent fault, the following actions are taken:

•

Set the IOUT_OC_FAULT bit in the STATUS_BYTE,

Set the IOUT bit in the STATUS_WORD,

Set the IOUT_OC_FAULT bit in the STATUS_IOUT register, and

The device notifies the host (asserts PMB_ALERT).

Default

125% IMAX

Figure 51. IOUT_OC_FAULT_LIMIT Register

15

7

14

6

13

OCF_LIMIT_EXPONENT

R/W

12

11

10

9

OCF_LIMIT_MANTISSA

R/W

8

0

5

4

3

2

1

OCF_LIMIT_MANTISSA

R/W

Table 24. IOUT_OC_FAULT_LIMIT Register Field Descriptions

Bit

15:11 OCF_LIMIT_EXPONENT

10:0 OCF_LIMIT_MANTISSA

Field

Type Reset

R/W

NVM

—

Description

5-bit, two's complement exponent (scaling factor).

11-bit, two's complement mantissa.

R/W

—

55

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

7.6.2.3.17 IOUT_OC_FAULT_RESPONSE (47h)

Format

N/A

Description

The IOUT_OC_FAULT_RESPONSE instructs the device on what action to take in

response to an output overcurrent fault. Upon triggering the overcurrent fault, the

controller is latched off, and the following actions are taken:

•

Set the IOUT_OC_FAULT bit in the STATUS_BYTE,

Set the IOUT bit in the STATUS_WORD,

Set the IOUT_OC_FAULT bit in the STATUS_IOUT register, and

The device notifies the host (asserts PMB_ALERT).

Default

FAh

Figure 52. IOUT_OC_FAULT_RESPONSE Register

7

6

5

4

3

2

1

0

IOUT_OC_FAULT_RESPONSE

R-1111 1010

Table 25. IOUT_OC_FAULT_RESPONSE Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

7:0

Upon triggering the overcurrent fault, the controller

immediately shuts down the device and attempts to

restart after a 22 ms delay.

IOUT_OC_FAULT_RESPON

SE

1111

1010

R

—

56

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

7.6.2.3.18 IOUT_OC_WARN_LIMIT (4Ah)

Format

Linear

Description

The IOUT_OC_WARN_LIMIT command sets the value of the output current, in

amperes, that causes an output overcurrent warning condition. Upon triggering the

overcurrent warning, the following actions are taken:

•

Set the OTHER bit in the STATUS_BYTE,

Set the IOUT bit in the STATUS_WORD,

Set the IOUT OC Warning bit in the STATUS_IOUT register, and

The device notifies the host (asserts PMB_ALERT).

Default

IMAX

Figure 53. IOUT_OC_WARN_LIMIT Register

15

7

14

6

13

12

11

10

9

OCW_LIMIT_MANTISSA

R/W

8

0

OCW_LIMIT_EXPONENT

R/W

5

4

3

2

1

OCW_LIMIT_MANTISSA

R/W

Table 26. IOUT_OC_WARN_LIMIT Register Field Descriptions

Bit

15:11 OCW_LIMIT_EXPONENT

10:0 OCW_LIMIT_MANTISSA

Field

Type Reset

R/W

NVM

—

Description

5-bit, two's complement exponent (scaling factor).

11-bit, two's complement mantissa.

R/W

—

57

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

7.6.2.3.19 OT_FAULT_LIMIT (4Fh)

Format

Linear

Description

The OT_FAULT_LIMIT command sets the value of the temperature limit, in

degrees Celsius, that causes an over-temperature fault condition. The default

value is 125C°. Upon triggering the over-temperature fault, the following actions

are taken:

•

Set the TEMPERATURE bit in the STATUS_BYTE,

Set the OT_FAULT bit in the STATUS_TEMPERATURE register, and

The device notifies the host (asserts PMB_ALERT and VR_FAULT).

Default

007Dh

Figure 54. OT_FAULT_LIMIT Register

15

7

14

6

13

OT_LIMIT_EXPONENT

R/W

12

11

10

2

9

OT_LIMIT_MANTISSA

R/W

8

0

5

4

3

1

OT_LIMIT_MANTISSA

R/W

Table 27. OT_FAULT_LIMIT Register Field Descriptions

Bit

15:11 OT_LIMIT_EXPONENT

10:0 OT_LIMIT_MANTISSA

Field

Type Reset

NVM

—

Description

R/W

0000 0

5-bit, two's complement exponent (scaling factor).

11-bit, two's complement mantissa.

000 0111

1101

—

58

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

7.6.2.3.20 OT_FAULT_RESPONSE (50h)

Format

N/A

Description

The OT_FAULT_RESPONSE instructs the device on what action to take in

response to an over-temperature fault. Upon triggering the over-temperature fault,

the controller shuts off and attempts to restart when the temperature reduces by

15C°, and the following actions are taken:

•

Set the TEMPERATURE bit in the STATUS_BYTE,

Set the OT_FAULT bit in the STATUS_TEMPERATURE register, and

The device notifies the host (asserts PMB_ALERT and VR_FAULT).

Default

F8h

Figure 55. OT_FAULT_RESPONSE Register

7

6

5

4

3

2

1

0

OT_FAULT_RESPONSE

R-1111 1000

Table 28. OT_FAULT_RESPONSE Register Field Descriptions

Bit

Field

OT_FAULT_RESPONSE

Type Reset

NVM

Description

7:0

R

1111

1000

—

Upon triggering the over-temperature fault, the

device will shut down immediately (disables the

output), and will restart when the temperature goes

15 degree Celsius below OT _FAULT_LIMIT.

7.6.2.3.21 OT_WARN_LIMIT (51h)

Format

Linear

Description

The OT_WARN_LIMIT command sets the temperature, in degrees Celsius, at

which it should indicate an over-temperature warning condition. The default value

is 95C. Upon triggering the over-temperature warning, the following actions are

taken:

•

Sets the TEMPERATURE bit in the STATUS_BYTE,

Sets the OT Warning bit in the STATUS_TEMPERATURE register, and

The device notifies the host (asserts PMB_ALERT).

Default

005Fh

Figure 56. OT_WARN_LIMIT Register

15

7

14

6

13

OTW_WARN_EXPONENT

R/W

12

11

10

2

9

OTW_WARN_MANTISSA

R/W

8

0

5

4

3

1

OTW_WARN_MANTISSA

R/W

Table 29. OT_WARN_LIMIT Register Field Descriptions

Bit

Field

Type

R/W

Reset

NVM

—

Description

15:11

10:0

OTW_WARN_EXPONENT

OTW_WARN_MANTISSA

0000 0

5-bit, two's complement exponent (scaling factor).

11-bit, two's complement mantissa.

000 0101 1111

—

59

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

7.6.2.3.22 VIN_OV_FAULT_LIMIT (55h)

Format

Linear

Description

The VIN_OV_FAULT_LIMIT command sets the value of the input voltage that

causes an input overvoltage fault condition. The default value is 17 V in NVM

mode and 14 V in pinstrap mode. Upon triggering an input voltage fault, the

following actions are taken:

•

Sets the OTHER bit in the STATUS_BYTE,

Sets the INPUT bit in the upper byte of the STATUS_WORD,

Sets the VIN_OV_FAULT bit in the STATUS_INPUT register, and

The device notifies the host (asserts PMB_ALERT).

Default

!~ 0011h !~0011h

Figure 57. VIN_OV_FAULT_LIMIT Register

15

7

14

6

13

VIN_OVF_EXPONENT

R/W

12

11

10

9

VIN_OVF_MANTISSA

R/W

8

0

5

4

3

2

1

VIN_OVF_MANTISSA

R/W

Table 30. VIN_OV_FAULT_LIMIT Register Field Descriptions

Bit

Field

Type

R/W

Reset

NVM

—

Description

15:11

10:0

VIN_OVF_EXPONENT

VIN_OVF_MANTISSA

0000 0

5-bit, two's complement exponent (scaling factor).

11-bit, two's complement mantissa.

000 0001 0001

—

After a STORE_DEFAULT_ALL command, the controller reads the last two LSB of VIN_OV_FAULT_LIMIT and

convert to decimal, and then adds 14 and converts to save into the VIN_OV_FAULT_LIMIT register. For

example, when the two LSB are 01b, after STORE_DEFAULT_ALL command, the VIN_OV_FAULT_LIMIT reads

000Fh (15 V).

60

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

7.6.2.3.23 IIN_OC_FAULT_LIMIT (5Bh)

Format

Linear

Description

The IIN_OC_FAULT_LIMIT command sets the value of the input current, in

amperes, that the causes an input overcurrent fault condition. Upon triggering the

overcurrent fault, the following actions are taken:

•

Sets the OTHER bit in the STATUS_BYTE,

Sets the INPUT bit in the STATUS_WORD,

Sets the IIN_OC_FAULT bit in the STATUS_INPUT register, and

The device notifies the host (asserts PMB_ALERT).

Default

00FFh

Figure 58. IIN_OC_FAULT_LIMIT Register

15

7

14

6

13

INOCF_LIMIT_EXPONENT

R/W

12

11

10

9

INOCF_LIMIT_MANTISSA

R/W

8

0

5

4

3

2

1

INOCF_LIMIT_MANTISSA

R/W

Table 31. IIN_OC_FAULT_LIMIT Register Field Descriptions

Bit

Field

Type

R/W

Reset

NVM

—

Description

15:11

10:0

INOCF_LIMIT_EXPONENT

INOCF_LIMIT_MANTISSA

0000 0

5-bit, two's complement exponent (scaling factor).

11-bit, two's complement mantissa.

000 1111 1111

—

61

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

7.6.2.3.24 IIN_OC_FAULT_RESPONSE (5Ch)

Format

N/A

Description

The IIN_OC_FAULT_RESPONSE instructs the device on what action to take in

response to an input overcurrent fault. Upon triggering the input overcurrent fault,

the controller is latched off, and the following actions are taken:

•

Sets the OTHER bit in the STATUS_BYTE,

Sets the INPUT bit in the STATUS_WORD,

Sets the IIN_OC_FAULT bit in the STATUS_INPUT register, and

The device notifies the host (asserts PMB_ALERT and VR_FAULT).

Default

C0h

Figure 59. IIN_OC_FAULT_RESPONSE Register

7

6

5

4

3

2

1

0

IIN_OC_FAULT_RESPONSE

R-1100 0000

Table 32. IIN_OC_FAULT_RESPONSE Register Field Descriptions

Bit

Field

Type

Reset

NVM

Description

7:0

IIN_OC_FAULT_RESPONSE

R

1100 0000

—

Upon triggering the input overcurrent fault, the device

will shut down immediately (disables the output), and

will not attempt to restart. The output then remains

disabled until the fault is cleared.

62

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

7.6.2.3.25 IIN_OC_WARN_LIMIT (5Dh)

Format

Linear

Description

The IIN_OC_WARN_LIMIT command sets the value of the input current, in

amperes, that causes the input overcurrent warning condition. The default setting

is 25A. Upon triggering the overcurrent warning, the following actions are taken:

•

Sets the OTHER bit in the STATUS_BYTE,

Sets the INPUT bit in the STATUS_WORD,

Sets the IIN OC Warning bit in the STATUS_INPUT register, and

The device notifies the host (asserts PMB_ALERT).

Default

0019h

Figure 60. IIN_OC_WARN_LIMIT Register

15

7

14

6

13

INOCW_LIMIT_EXPONENT

R/W

12

11

10

9

INOCW_LIMIT_MANTISSA

R/W

8

0

5

4

3

2

1

INOCW_LIMIT_MANTISSA

R/W

Table 33. IIN_OC_WARN_LIMIT Register Field Descriptions

Bit

Field

Type

R/W

Reset

NVM

—

Description

15:11

10:0

INOCW_LIMIT_EXPONENT

INOCW_LIMIT_MANTISSA

0000 0

5-bit, two's complement exponent (scaling factor).

11-bit, two's complement mantissa.

000 0001 1001

—

63

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

7.6.2.3.26 STATUS_BYTE (78h)

Format

N/A

Description

The STATUS_BYTE command returns a single byte of information with the a

summary of critical faults. The STATUS_BYTE command is the same register as

the low byte of the STATUS_WORD command. It should be noted that all faults

and warnings trigger the assertion of PMB_ALERT.

Default

00h

Figure 61. STATUS_BYTE Register

7

6

OFF

R

5

VOUT_OV

R

4

IOUT_OC

R

3

VIN_UV

R

2

TEMP

R

1

CML

R

0

OTHER

R

BUSY

R-0

Table 34. STATUS_BYTE Register Field Descriptions

Bit

7

Field

BUSY

OFF

Type Reset

NVM

—

Description

Not supported and always set to 0

R

0

6

—

This bit is asserted if the unit is not providing power

to the output, regardless of the reason, including

simply not being enabled.

0: Raw status indicating the IC is providing power to

VOUT.

1: Raw status indicating the IC is not providing

power to VOUT.

5

4

VOUT_OV

IOUT_OC

R

—

Output Over-Voltage Fault Condition

0: Latched flag indicating no VOUT OV fault has

occurred.

1: Latched flag indicating a VOUT OV fault occurred

Output Over-Current Fault Condition

0: Latched flag indicating no IOUT OC fault has

occurred.

1: Latched flag indicating an IOUT OC fault has

occurred.

3

2

1

0

VIN_UV

TEMP

CML

R

—

Input Under-Voltage Fault Condition

0: Latched flag indicating VIN is above the UVLO

threshold.

1: Latched flag indicating VIN is below the UVLO

threshold.

Over-Temperature Fault/Warning

0: Latched flag indicating no OT fault or warning has

occurred.

1: Latched flag indicating an OT fault or warning has

occurred.

Communications, Memory or Logic Fault

0: Latched flag indicating no communication,

memory, or logic fault has occurred.

1: Latched flag indicating a communication,

memory, or logic fault has occurred.

OTHER

Other Fault

This bit is used to flag faults not covered with the

other bit faults. In this case, UVF or OCW faults are

examples of other faults not covered by the bits [6:1]

in this register.

0: No fault has occurred

1: A fault or warning not listed in bits [6:1] has

occurred.

64

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

7.6.2.3.27 STATUS_WORD (79h)

Format

N/A

Description

The STATUS_WORD command returns two bytes of information with a summary

of critical faults, such as over-voltage, overcurrent, over-temperature, etc. It should

be noted that all faults and warnings except VIN_UV trigger the assertion of

PMB_ALERT.

NOTE: The STATUS_WORD low byte is the STATUS_BYTE.

Default

0000h

Figure 62. STATUS_WORD Register

15

VOUT

R

14

IOUT

R

13

INPUT

R

12

MFR

R

11

PGOOD

R

10

FANS

R-0

9

8

OTHER

R-0

UNKNOWN

R-0

7

6

OFF

R

5

VOUT_OV

R

4

IOUT_OC

R

3

VIN_UV

R

2

TEMP

R

1

CML

R

0

OTHER

R

BUSY

R-0

Table 35. STATUS_WORD Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

15

VOUT

R

—

Output Voltage Fault/Warning

0: Latched flag indicating no VOUT fault or warning

has occurred.

1: Latched flag indicating a VOUT fault or warning

has occurred.

14

13

IOUT

R

—

Output Current Fault/Warning

0: Latched flag indicating no IOUT fault or warning

has occurred.

1: Latched flag indicating an IOUT fault or warning

has occurred.

INPUT

Input Voltage/Current Fault/Warning

0: Latched flag indicating no VIN or IIN fault or

warning has occurred.

1: Latched flag indicating a VIN or IIN fault or

warning has occurred.

12

11

MFR

R

—

MFR_SPECIFIC Fault

0: Latched flag indicating no MFR_SPECIFIC fault

has occurred.

1: Latched flag indicating a MFR_SPECIFIC fault

has occurred.

PGOOD

Power Good Status

0: Raw status indicating VRRDY pin is at logic high.

1: Raw status indicating VRRDY pin is at logic low.

10

9

8

7

6

5

4

3

2

1

0

FANS

R

0

—

Not supported and always set to 0.

OTHER

UNKNOWN

BUSY

OFF

VOUT_OV

IOUT_OC

VIN_UV

TEMP

See information in Table 34

CML

OTHER

65

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

7.6.2.3.28 STATUS_VOUT (7Ah)

Format

N/A

Description

The STATUS_VOUT command returns one byte of information relating to the

status of the converter's output voltage related faults.

Default

00h

Figure 63. STATUS_VOUT Register

7

VOUT_OVF

R

6

5

4

VOUT_UVF

R

3

2

1

0

VOUT_TRACK

R-0

VOUT_OVW

R-0

VOUT_UVW

R-0

VOUT_MAXW

R

TON_MAX

R-0

TOFF_MAX

R-0

Table 36. STATUS_VOUT Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

7

VOUT_OVF

R

—

Output Over-Voltage Fault

0: Latched flag indicating no VOUT OV fault has

occurred.

1: Latched flag indicating a VOUT OV fault has

occurred.

6

5

4

VOUT_OVW

VOUT_UVW

VOUT_UVF

R

0

—

Not supported and always set to 0.

Output Under-Voltage Fault

0: Latched flag indicating no VOUT UV fault has

occurred.

1: Latched flag indicating a VOUT UV fault has

occurred.

3

VOUT_MAXW

R

—

VOUT Max Warning

0: Latched flag indicating that no VOUT Max

warning has occurred

1: Latched flag indicating that an attempt has been

made to set the output voltage to a value higher

than allowed by the VOUT_MAX command.

2

1

0

TON_MAX

R

0

—

Not supported and always set to 0.

TOFF_MAX

VOUT_TRACK

7.6.2.3.29 STATUS_IOUT (7Bh)

Format

N/A

Description

The STATUS_IOUT command returns one byte of information relating to the

status of the converter's output current related faults.

Default

00h

Figure 64. STATUS_IOUT Register

7

IOUT_OCF

R

6

5

IOUT_OCW

R

4

3

CUR_SHAREF

R-0

2

1

0

IOUT_OCUVF

R-0

IOUT_UCF

R-0

POW_LIMIT

R-0

POUT_OPF

R-0

POUT_OPW

R-0

Table 37. STATUS_IOUT Register Field Descriptions

Bit

Field

IOUT_OCF

Type Reset

NVM

Description

7

R

—

Output Over-Current Fault

0: Latched flag indicating no IOUT OC fault has

occurred.

1: Latched flag indicating a IOUT OC fault has

occurred .

66

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

Table 37. STATUS_IOUT Register Field Descriptions (continued)

Bit

6

Field

Type Reset

NVM

—

Description

IOUT_OCUVF

IOUT_OCW

R

0

Not supported and always set to 0.

5

—

Output Over-Current Warning

0: Latched flag indicating no IOUT OC warning has

occurred

1: Latched flag indicating a IOUT OC warning has

occurred

4

3

2

1

0

IOUT_UCF

R

0

—

Not supported and always set to 0.

CUR_SHAREF

POW_LIMIT

POUT_OPF

POUT_OPW

7.6.2.3.30 STATUS_INPUT (7Ch)

Format

N/A

Description

The STATUS_INPUT command returns one byte of information relating to the

status of the converter's input voltage and current related faults.

Default

00h

Figure 65. STATUS_INPUT Register

7

VIN_OVF

R

6

5

4

VIN_UVF

R

3

2

IIN_OCF

R

1

IIN_OCW

R

0

VIN_OVW

R-0

VIN_UVW

R-0

VIN_OFF

R-0

PIN_OPW

R-0

Table 38. STATUS_INPUT Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

7

VIN_OVF

R

—

Input Over-Voltage Fault

0: Latched flag indicating no VIN OV fault has

occurred.

1: Latched flag indicating a VIN OV fault has

occurred.

6

5

4

VIN_OVW

VIN_UVW

VIN_UVF

R

0

—

Not supported and always set to 0.

Input Under-Voltage Fault

0: Latched flag indicating no VIN UV fault has

occurred.

1: Latched flag indicating a VIN UV fault has

occurred.

3

2

VIN_OFF

IIN_OCF

R

0

—

Not supported and always set to 0.

Input Over-Current Fault

0: Latched flag indicating no IIN OC fault has

occurred.

1: Latched flag indicating a IIN OC fault has

occurred.

1

0

IIN_OCW

PIN_OPW

R

—

Input Over-Current Warning

0: Latched flag indicating no IIN OC warning has

occurred.

1: Latched flag indicating a IIN OC warning has

occurred.

0

Not supported and always set to 0.

67

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

7.6.2.3.31 STATUS_TEMPERATURE (7Dh)

Format

N/A

Description

The STATUS_ TEMPERATURE command returns one byte of information relating

to the status of the converter's temperature related faults.

Default

00h

Figure 66. STATUS_TEMPERATURE Register

7

OTF

R

6

OTW

R

5

4

3

2

1

0

UTW

R-0

UTF

R-0

Reserved

R-0000

Table 39. STATUS_TEMPERATURE Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

7

OTF

R

—

Over-Temperature Fault

0: Latched flag indicating no temperature fault has

occurred.

1: Latched flag indicating a temperature fault has

occurred.

6

OTW

R

—

Over-Temperature Warning

0: Latched flag indicating no temperature warning

has occurred.

1: Latched flag indicating a temperature warning has

occurred.

5

4

UTW

R

0

—

Not supported and always set to 0.

Always set to 0.

UTF

0

3-0

Reserved

0000

68

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

7.6.2.3.32 STATUS_CML (7Eh)

Format

N/A

Description

The STATUS_ CML command returns one byte with contents regarding

communication, logic, or memory conditions.

Default

00h

Figure 67. STATUS_CML Register

7

US_CMD

R

6

US_DATA

R

5

PEC_FAIL

R

4

MEM_FAULT

R

3

2

1

COM_FAIL

R

0

PRO_FAULT

R-0

Reserved

R-0

CML_OTHER

R-0

Table 40. STATUS_CML Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

7

US_CMD

US_DATA

PEC_FAIL

R

—

Invalid or Unsupported Command Received

0: Latched flag indicating no invalid or unsupported

command has received.

1: Latched flag indicating an invalid or unsupported

command has received.

6

5

4

R

—

Invalid or Unsupported Data Received

0: Latched flag indicating no invalid or unsupported

data has received.

1: Latched flag indicating an invalid or unsupported

data has received.

Packet Error Check Failed

0: Latched flag indicating no packet error check has

failed

1: Latched flag indicating a packet error check has

failed

MEM_FAULT

Memory Error

0: Latched flag indicating that there is no memory

error.

1: Latched flag indicating that a memory error, i.e.

PMBus controller is trying to write into registers

when NVM memory is being programmed.

3

2

1

PRO_FAULT

Reserved

R

0

—

Not supported and always set to 0.

Always set to 0.

COM_FAIL

Other Communication Faults

0: Latched flag indicating no communication fault

other than the ones listed in this table has occurred.

1: Latched flag indicating a communication fault

other than the ones listed in this table has occurred.

0

CML_OTHER

R

0

—

Not supported and always set to 0.

69

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

7.6.2.3.33 STATUS_MFR_SPECIFIC (80h)

Format

N/A

Description

The STATUS_ MFR_SPECIFIC command returns one byte containing

manufacturer-specific faults or warnings.

Default

00h

Figure 68. STATUS_MFR_SPECIFIC Register

7

6

5

4

3

2

1

0

MFR_FAULT_P

S

MFR_PBF

CUR_SH_WARN

RST_VOUT

VOUT_MIN

PHFLT

R

Table 41. STATUS_MFR_SPECIFIC Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

7

MFR_FAULT_PS

R

—

Power State Fault

0: Latched flag indicating no fault from TI power

stage has occurred.

1: Latched flag indicating a fault from TI power

stage has occurred.

6

MFR_PBF

R

—

Pre-Bias Fault

0: Latched flag indicating no pre-bias fault (V_OUT

2.75V at startup) has occurred.

>

1: Latched flag indicating a pre-bias fault (V_OUT

2.75V at startup) has occurred.

>

5:3

2

CUR_SH_WARN

RST_VOUT

R

000

—

not supported and alwats set to 0

RST_VOUT Fault

0: Latched flag indicating no RST_VOUT fault has

occurred.

1: Latched flag indicating a RST_VOUT fault has

occurred.

1

0

VOUT_MIN

PHFLT

R

—

VOUT_MIN Fault

0: Latched flag indicating no VOUT_MIN fault has

occurred.

1: Latched flag indicating a VOUT_MIN fault has

occurred.

Phase Fault

0: Latched flag indicating no phase fault (no phase

pulse detected) has occurred.

1: Latched flag indicating a phase fault (no phase

pulse detected) has occurred.

70

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

7.6.2.3.34 READ_VIN (88h)

Format

Linear

Description

The READ_VIN command returns the input voltage in volts. Refer to Equation 6 to

get the real world value.

Default

Figure 69. READ_VIN Register

15

7

14

6

13

12

11

10

2

9

8

0

READ_VIN_EXPONENT

R

READ_VIN_MANTISSA

R

5

4

3

1

READ_VIN_MANTISSA

R

Table 42. READ_VIN Register Field Descriptions

Bit

15:11 READ_VIN_EXPONENT

10:0 READ_VIN_MANTISSA

Field

Type Reset

NVM

—

Description

R

5-bit, two's complement exponent (scaling factor).

11-bit, two's complement mantissa.

—

71

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

7.6.2.3.35 READ_IIN (89h)

Format

Linear

Description

The READ_IIN command returns the input current in amperes. Refer to

Equation 6 to get the real world value.

Default

Figure 70. READ_IIN Register

15

7

14

6

13

12

11

10

2

9

8

0

READ_IIN_EXPONENT

R

READ_IIN_MANTISSA

R

5

4

3

1

READ_IIN_MANTISSA

R

Table 43. READ_IIN Register Field Descriptions

Bit

15:11 READ_IIN_EXPONENT

10:0 READ_IIN_MANTISSA

Field

Type Reset

NVM

—

Description

R

5-bit, two's complement exponent (scaling factor).

11-bit, two's complement mantissa.

—

72

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

7.6.2.3.36 READ_VOUT (8Bh)

Format

VID

The READ_VOUT command returns the actual, measured output voltage.

Description

Default

Another command, MFR_READ_VOUT (D4h), returns the measured output voltage in linear format.

Figure 71. READ_VOUT Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

READ_VOUT_VID

R

4

3

READ_VOUT_VID

R

Table 44. READ_VOUT Register Field Descriptions

Bit

Field

READ_VOUT_VID

Type Reset

NVM

Description

15:0

R

—

16-bit, VID format

7.6.2.3.37 READ_IOUT (8Ch)

Format

Linear

Description

The READ_IOUT command returns the output current in amperes. Refer to

Equation 6 to get the real world value.

Default

Figure 72. READ_IOUT Register

15

7

14

6

13

12

11

10

2

9

8

0

READ_IOUT_EXPONENT

R

READ_IOUT_MANTISSA

R

5

4

3

1

READ_IOUT_MANTISSA

R

Table 45. READ_IOUT Register Field Descriptions

Bit

15:11 READ_IOUT_EXPONENT

10:0 READ_IOUT_MANTISSA

Field

Type Reset

NVM

—

Description

R

5-bit, two's complement exponent (scaling factor).

11-bit, two's complement mantissa.

—

73

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

7.6.2.3.38 READ_TEMPERATURE_1 (8Dh)

Format

Linear

Description

The READ_TEMPERATURE_1 command returns the temperature in degrees

Celsius. Refer to Equation 6 to get the real world value.

Default

Figure 73. READ_TEMPERATURE_1 Register

15

7

14

6

13

12

11

10

9

8

0

READ_TEMP_1_EXPONENT

R

READ_TEMP_1_MANTISSA

R

5

4

3

2

1

READ_TEMP_1_MANTISSA

R

Table 46. READ_TEMPERATURE_1 Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

15:11 READ_TEMP_1_EXPONEN

T

R

—

5-bit, two's complement exponent (scaling factor).

10:0

READ_TEMP_1_MANTISSA

R

—

11-bit, two's complement mantissa.

74

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

7.6.2.3.39 READ_POUT (96h)

Format

Linear

Description

The READ_POUT command returns the output power in watts. Refer to

Equation 6 to get the real world value.

Default

Figure 74. READ_POUT Register

15

7

14

6

13

12

11

10

2

9

8

0

READ_POUT_EXPONENT

R

READ_POUT_MANTISSA

R

5

4

3

1

READ_POUT_MANTISSA

R

Table 47. READ_POUT Register Field Descriptions

Bit

15:11 READ_POUT_EXPONENT

10:0 READ_POUT_MANTISSA

Field

Type Reset

NVM

—

Description

R

5-bit, two's complement exponent (scaling factor).

11-bit, two's complement mantissa.

—

75

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

7.6.2.3.40 READ_PIN (97h)

Format

Linear

Description

The READ_PIN command returns the input power in watts. Refer to READ_PIN

(97h) to get the real world value.

Default

Figure 75. READ_PIN Register

15

7

14

6

13

12

11

10

2

9

8

0

READ_PIN_EXPONENT

R

READ_PIN_MANTISSA

R

5

4

3

1

READ_PIN_MANTISSA

R

Table 48. READ_PIN Register Register Field Descriptions

Bit

15:11 READ_PIN_EXPONENT

10:0 READ_PIN_MANTISSA

Field

Type Reset

NVM

—

Description

R

5-bit, two's complement exponent (scaling factor).

11-bit, two's complement mantissa.

—

7.6.2.3.41 PMBus_REVISION (98h)

Format

N/A

Description

The PMBus_REVISION command returns the revision of the PMBus to which the

device is compliant.

Default

11h

Figure 76. PMBus_REVISION Register

7

6

5

4

3

2

1

0

PMBUS_REV

R-0001 0001

Table 49. PMBus_REVISION Register Field Descriptions

Bit

Field

Type

Reset

NVM

Description

Compliant to revision 1.1 of the PMBus specification.

7:0

PMBUS_REV

R

0001 0001

—

7.6.2.3.42 MFR_ID (99h)

Format

N/A

Description

The MFR_ID command loads the unit with the text character that contains the

manufacturer's ID.

Default

!~ NVM: 5401h!~54h

Figure 77. MFR_ID Register

15

7

14

6

13

5

12

4

11

10

2

9

1

8

0

MFR_ID_BW

R/W

3

MFR_ID_HC

R-0000 0001

76

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

Table 50. MFR_ID Register Field Descriptions

Bit

15:8

7:0

Field

Type

R/W

R

Reset

NVM

Yes

—

Description

MFR_ID_BW

MFR_ID_HC

PMBus Block Write

Hard Coded to 01h

0000 0001

7.6.2.3.43 MFR_MODEL (9Ah)

Format

N/A

Description

The MFR_MODEL command loads the unit with the text character that contains

the model number of the manufacturer.

Default

NVM:

Figure 78. MFR_MODEL Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

MFR_MODEL_BW

R/W

4

3

MFR_MODEL_HC

R-0000 0001

Table 51. MFR_MODEL Register Field Descriptions

Bit

Field

Type

R/W

R

Reset

NVM

Yes

—

Description

15:8

7:0

MFR_MODEL_BW

MFR_MODEL_HC

PMBus Block Write

Hard Coded to 01h

0000 0001

7.6.2.3.44 MFR_REVISION (9Bh)

Format

N/A

Description

The MFR_REVISION command loads the unit with the text character that contains

the revision number of the manufacturer. This is typically done once at the time of

manufacture.

Default

Figure 79. MFR_REVISION Register

15

7

14

13

12

11

10

9

8

0

MFR_REVISION_HC1

R-0000

MFR_REVISION_BW

R/W

6

5

4

3

2

1

MFR_REVISION_HC2

R-0000 0001

Table 52. MFR_REVISION Register Field Descriptions

Bit

Field

Type Reset

NVM

—

Description

15:12 MFR_REVISION _HC1

R

0001

Hard Coded to 0h

PMBus Block Write

Hard Coded to 01h

11:8

7:0

MFR_REVISION

R/W

R

Yes

—

MFR_REVISION_HC2

0000

0001

77

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

7.6.2.3.45 MFR_DATE (9Dh)

Format

N/A

Description

The MFR_DATE command loads the unit with the text character that identifies the

device's date of manufacture. This is typically done once at the time of

manufacture.

Default

Figure 80. MFR_DATE Register

15

7

14

6

13

5

12

MFR_DATE_BW

R/W

11

10

2

9

1

8

0

4

3

MFR_DATE_HC

R-0000 0001

Table 53. MFR_DATE Register Field Descriptions

Bit

15:8

7:0

Field

Type

R/W

R

Reset

NVM

Yes

—

Description

MFR_DATE_BW

MFR_DATE_HC

PMBus Block Write

Hard Coded to 01h.

0000 0001

7.6.2.3.46 MFR_VOUT_MIN (A4h)

Format

VID

Description

The MFR_VOUT_MIN command sets an lower limit on the output voltage that the

unit can command regardless of any other commands or combinations. The intent

of this command is to provide a safeguard against a user accidentally setting the

output voltage to a possibly non-operational level.

The device detects that an attempt has been made to program the output to a

voltage lower than the value set by the MFR_VOUT_MIN command. The device

treats this detection as a warning condition and not a fault condition. If an attempt

is made to program the output voltage lower than the limit set by this command,

the device responds as follows:

•

The commanded output voltage is set to MFR_VOUT_MIN,

The OTHER bit is set in the STATUS_BYTE,

The VOUT bit is set in the STATUS_WORD,

The MFR_VOUT_MIN warning bit is set in the STATUS_VOUT register, and

The device notifies the host (asserts PMBUS_ALERT).

The data bytes are two bytes, which are in right-justified VID format. The VID

table mapping determined by the selected VID protocols (VR12.0 or VR12.5) from

the SLEW_MODE pin or MFR_SPECIFIC_13.

Default

0000h

Figure 81. MFR_VOUT_MIN Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R-0000 0000

4

3

MFR_VOUT_MIN

R/W

78

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

Table 54. MFR_VOUT_MIN Register Field Descriptions

Bit

15:8

7:0

Field

Type

R

Reset

NVM

—

Description

RESERVED

0000 0000

Hard coded to 00h

MFR_VOUT_MIN

R/W

—

Minimum value for VID

7.6.2.3.47 MFR_SPECIFIC_00 (Per-Phase Overcurrent Limit) (D0h)

Format

N/A

Description

The MFR_SPECIFIC_00 command sets the valley-current threshold for the per-

phase overcurrent limit. The settings can override the default setting form the

OCL-R pin.

Default

Pin strap: OCL-R pin

NVM: 08h

Figure 82. MFR_SPECIFIC_00 (Per-Phase Overcurrent Limit) Register

7

6

5

4

3

2

1

0

Reserved

R-0000

OCL

R/W

Table 55. MFR_SPECIFIC_00 (Per-Phase Overcurrent Limit) Register Field Descriptions

Bit

7:4

3:0

Field

Type Reset

NVM

—

Description

Reserved

OCL

R

R-0000

Always set to 0.

R/W

Yes

0000: 24A

0001: 27A

0010: 30A

0011: 33A

0100: 36A

0101: 39A

0110: 42A

0111: 45A

1000: 48A

1001: 51A

1010: 54A

1011: 57A

1100: 60A

1101: 63A

1110: 66A

1111:69A

79

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

7.6.2.3.48 MFR_SPECIFIC_01 (Telemetry Averaging Time) (D1h)

Format

Description

Default

The MFR_SPECIFIC_01 command sets the averaging time for telemetry

reporting.

50h

Figure 83. MFR_SPECIFIC_01 (Telemetry Averaging Time) Register

7

6

5

4

3

2

1

0

Reserved

R-0

FILTER_PIN

R/W

Reserved

R-00

FILTER_IV

R/W

Table 56. MFR_SPECIFIC_01 (Telemetry Averaging Time) Register Field Descriptions

Bit

7

Field

Type Reset

NVM

—

Description

Reserved

FILTER_PIN

R

0

Always set to 0.

6:4

R/W

101

—

Averaging Time for Input Power Reporting

000: Bypass.

001: 2 ms

010: 5.5 m

011: 11.5 m

100: 19 ms

101: 50 ms

110: 100 ms

111: 225 ms

3:2

1:0

Reserved

R

00

—

Always set to 0.

FILTER_IV

R/W

Averaging Time for Current and Voltage Reporting

00: Bypass.

01: .5 ms

10: 1 ms

11: 2.5 ms

7.6.2.3.49 MFR_SPECIFIC_04 (Read VOUT) (D4h)

Format

Linear

Description

The MFR_SPECIFIC_04 command returns the actual, measured output voltage in

volts. Refer to Equation 6 to get the real world value, where n= -9.

Default

Figure 84. MFR_SPECIFIC_04 (Read VOUT) Register

15

7

14

6

13

12

11

10

9

1

8

0

MFR_SPEC_04_MANTISSA

R

5

4

3

2

MFR_SPEC_04_MANTISSA

R

Table 57. MFR_SPECIFIC_04 (Read VOUT) Register Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

15:0

MFR_SPEC_04_MANTISSA

R

—

Unsigned 16-bit mantissa with an exponent value of

n=-9.

80

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

7.6.2.3.50 MFR_SPECIFIC_05 (VOUT Trim) (D5h)

Format

Signed Two's Complement

Description

The MFR_SPECIFIC_05 command is used to trim the VR output voltage in volts.

LSB resolution is 5 mV/10 mV based on the selected VR12.0/VR12.5.

Default

NVM: 00h

Figure 85. MFR_SPECIFIC_05 (VOUT Trim) Register

7

6

5

4

3

2

1

0

VOUT_VID_OFFSET

R/W

Table 58. MFR_SPECIFIC_05 (VOUT Trim) Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

7:0

VOUT_VID_OFFSET

R/W

Yes

Sets the VR output trim voltage.

01111111: 0.635 V in VR12.0 and 1.27V in VR12.5

01111110: 0.630 V in VR12.0 and 1.26 V in VR12.5

...........................

00000001: 0.005 V in VR12.0 and 0.01 V in VR12.5

00000000: 0 V

11111111: –0.005 V in VR12.0 and –0.01 V in

VR12.5

...........................

10000001: –0.635 V in VR12.0 and –1.27 V in

VR12.5

10000000: –0.640 V in VR12.0 and –1.28 V in

VR12.5

81

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

7.6.2.3.51 MFR_SPECIFIC_07 (Additional Function Bits) (D7h)

Format

N/A

Description

Default

The MFR_SPECIFIC_07 command sets the additional function bits.

NVM: 02h

Figure 86. MFR_SPECIFIC_07 (Additional Function Bits) Register

7

6

5

4

3

2

1

0

Reserved

OVFLT_MODE_SE

L

PS_FLT_DIS

SLEW_FAST

OSR_TRISTATE

SST_TIME

R-0000 0

R/W

Table 59. MFR_SPECIFIC_07 (Additional Function Bits) Register Field Descriptions

Bit

7:5

4

Field

Type Reset

NVM

—

Description

Reserved

R

000

Always set to 0.

OVFLT_MODE_SEL

R/W

No

0: Tracking OVP and Fixed OVP is 3 cycle hiccup

then latch off 1: Tracking OVP and Fixed OVP is

latch off from first occurrence.

3

2

PS_FLT_DIS

SLEW_FAST

R/W

No

0: Power stage fault is active 1: Power stage fault is

disabled

Yes

Fast Slew Mode Enable/Disable

0: Default slew rate selected by

MFR_SPECIFIC_13[2:0]

1: Add 1.36 mV/µs to the selected slew rate

1

0

OSR_TRISTATE

SST_TIME

R/W

Yes

Body Braking Enable/Disable

0: Enable OSR pulse truncation without body

braking

1: Enable OSR pulse truncation with body braking

Soft Slew Rate Selection

0: soft start slew rate dependent on TRISE

1: 1/16 of the selected slew rate for soft-start

82

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

7.6.2.3.52 MFR_SPECIFIC_08 (Droop) (D8h)

Format

N/A

Description

The MFR_SPECIFIC_08 command sets the load line as percentage of the default

one. For example, if slope is set as 1mohm = 100%, then 0.5mohm = 50%

Default

04h

Figure 87. MFR_SPECIFIC_08 (Droop) Register

7

6

5

4

3

2

1

0

DROOP

R/W

Table 60. MFR_SPECIFIC_08 (Droop) Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

7:0

DROOP

R/W

0000

0100

—

0000 0000: 0%

0000 0001: 25%

0000 0010: 50%

0000 0011: 75%

0000 0100: 100%

0001 0000: 80%

0010 0000: 85%

0011 0000: 90%

0100 0000: 95%

0101 0000: 105%

0110 0000: 110%

0111 0000: 115%

1000 0000: 120%

1001 0000: 125%

1010 0000: 150%

1011 0000: 175%

Others: 100%

83

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

7.6.2.3.53 MFR_SPECIFIC_09 (OSR/USR) (D9h)

Format

N/A

Description

The MFR_SPECIFIC_09 command sets the threshold for OSR and USR control.

The setting can override the default setting from the O-USR pin.

Default

Pin strap: O-USR pin

NVM: 77h

Figure 88. MFR_SPECIFIC_09 (OSR/USR) Register

7

6

5

4

3

2

1

0

Reserved

R-0

USR

R/W

Reserved

R-0

OSR

R/W

Table 61. MFR_SPECIFIC_09 (OSR/USR) Register Field Descriptions

Bit

7

Field

Type Reset

NVM

—

Description

Reserved

USR

R

0

Always set to 0.

6:4

R/W

Yes

Undershoot Reduction

000: 20 mV

001: 30 mV

010: 60 mV

011: 80 mV

100: 100 mV

101: 120 mV

110: 140 mV

111: USR off

3

Reserved

OSR

R

0

—

Always set to 0.

2:0

R/W

Yes

Overshoot Reduction

000: 30 mV

001: 40 mV

010: 60 mV

011: 80 mV

100: 100 mV

101: 120 mV

110: 140 mV

111: OSR off

84

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

7.6.2.3.54 MFR_SPECIFIC_10 (Maximum Operating Current) (DAh)

Format

N/A

Description

The MFR_SPECIFIC_10 command sets the maximum operating current (IMAX,

unit: A) of the converter. The setting can override the default setting from the F-

IMAX pin

Default

Pin strap: F-IMAX pin

NVM:

Figure 89. MFR_SPECIFIC_10 (Maximum Operating Current) Register

7

6

5

4

3

2

1

0

IMAX

R/W

Table 62. MFR_SPECIFIC_10 (Maximum Operating Current) Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

7:0

IMAX

R/W

Yes

Set maximum operating current.

7.6.2.3.55 MFR_SPECIFIC_11 (VBOOT) (DBh)

Format

VID

Description

The MFR_SPECIFIC_11 command sets the boot voltage in 8-bit VID format. The

setting can override the default setting from the VBOOT pin.

Default

Pin strap: VBOOT pin

NVM: 97h

Figure 90. MFR_SPECIFIC_11 (VBOOT) Register

7

6

5

4

3

2

1

0

VBOOT

R/W

Table 63. MFR_SPECIFIC_11 (VBOOT) Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

7:0

VBOOT

R/W

Yes

Set the boot voltage according to the selected VID

table.

85

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

7.6.2.3.56 MFR_SPECIFIC_12 (Switching Frequency and TRISE) (DCh)

Format

N/A

Description

The MFR_SPECIFIC_12 command sets the switching frequency and the soft start

rise slew rate. The settings can override the default setting from the F-IMAX.

Default

Pin strap: F-IMAX pin

NVM: 20h

Figure 91. MFR_SPECIFIC_12 (Switching Frequency and TRISE) Register

7

6

5

4

3

2

1

0

FSW

R/W

Reserved

R-0

TRISE

R/W

Table 64. MFR_SPECIFIC_12 (Switching Frequency and TRISE) Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

7:4

FSW

R/W

Yes

Switching Frequency

0000: 300 kHz

0001: 400 kHz

0010: 500 kHz

0011: 600 kHz

0100: 700 kHz

0101: 800 kHz

0110: 900 kHz

0111: 1000 kHz

1000: 350 kHz

1001: 450 kHz

1010: 550 kHz

1011: 650 kHz

1100: 750 kHz

1101: 850 kHz

1110: 950 kHz

1111: 1000 kHz

3:2

1:0

Reserved

TRISE

R

0

—

Always set to 0.

R/W

Yes

Soft start rise slew rate in terms of VOUT slew rate

00: 1

01: 1/2

10: 1/4

11: 1/8

7.6.2.3.57 MFR_SPECIFIC_13 (Slew Rate and Other Operation Modes) (DDh)

Format

N/A

Description

The MFR_SPECIFIC_13 command sets the slew rates and the operation modes.

The settings can override the default setting from the SLEW-MODE pin.

Default

Pin strap: SLEW-MODE pin

NVM: 89h

Figure 92. MFR_SPECIFIC_13 (Slew Rate and Other Operation Modes) Register

7

6

5

4

3

2

1

0

VR12_MODE

R/W

PI_SET

R/W

Reserved

R/W

DPS_EN

R/W

ZLL_SET

R/W

SLEW

R/W

86

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

Table 65. MFR_SPECIFIC_13 (Slew Rate and Other Operation Modes) Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

7

VR12_MODE

R/W

Yes

VR12 Mode

0: VR12.5.

1: VR12.0.

6

PI_SET

R/W

Yes

Phase Interleaving

0:

1: 1/3, 2/4 and 5/6 phase interleaving

5

4

Reserved

DPS_EN

R/W

Yes

Not used, write or read has no effect

Dynamic Phase Shedding Enable

0: Disable dynamic phase shedding.

1: Enable dynamic phase shedding.

3

ZLL_SET

SLEW

R/W

Yes

Load Line

0: Non-zero load line

1: Zero load line

2:0

Slew Rate

000: 0.34 mV/µs

001: 0.68 mV/µs

010: 1.02 mV/µs

011: 1.36 mV/µs

100: 1.7 mV/µs

101: 2.04 mV/µs

110: 2.38 mV/µs

111: 2.74 mV/µs

87

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

7.6.2.3.58 MFR_SPECIFIC_14 (Ramp Height) (DEh)

Format

N/A

Description

The MFR_SPECIFIC_14 command sets the ramp amplitude for compensations.

The settings can override the default setting from the OCL-R pin.

Default

Pin strap: OCL-R pin

NVM: 06h

Figure 93. MFR_SPECIFIC_14 Register

7

6

5

4

3

2

1

0

Reserved

R-0000 0

RAMP

R/W

Table 66. MFR_SPECIFIC_14 Register Field Descriptions

Bit

7:3

2:0

Field

Type Reset

NVM

—

Description

Reserved

RAMP

R

0

Always set to 0.

R/W

Yes

Ramp Amplitude

000: 20 mV_PP

001: 40 mV_PP

010: 60 mV_PP

011: 80 mV_PP

100: 100 mV_PP

101: 120 mV_PP

110: 150 mV_PP

111: 200 mV_PP

88

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

7.6.2.3.59 MFR_SPECIFIC_15 (Dynamic Phase Shedding Thresholds) (DFh)

Format

N/A

Description

The MFR_SPECIFIC_15 command sets the threshold for the dynamic phase

shedding. Use 4 × overcurrent limit (OCL) as 100% load condition

Default

NVM: 01h

Figure 94. MFR_SPECIFIC_15 (Dynamic Phase Shedding Thresholds) Register

7

6

5

4

3

2

1

0

Reserved

R-0000

DPS_TH_LOW

R/W

DPS_TH_HIGH

R/W

Table 67. MFR_SPECIFIC_15 (Dynamic Phase Shedding Thresholds) Register Field Descriptions

Bit

7:4

3

Field

Type Reset

NVM

—

Description

Reserved

DPS_TH_LOW

R

0000

Always set to 0.

R/W

Yes

Switch from 2 Phase to 1 Phase Operation

0: Disable decreasing to 1 phase operation.

1: 10% load.

2:0

DPS_TH_HIGH

R/W

Yes

Switch from 6 Phase to 2 Phase Operation

000: 15% load.

001: 20% load.

010: 25% load.

011: 30% load.

Others: 35% load.

7.6.2.3.60 MFR_SPECIFIC_16 (VIN UVLO) (E0h)

Format

N/A

Description

The MFR_SPECIFIC_16 command sets the threshold for the VIN Undervoltage

Lockout (UVLO).

Default

NVM: 01h

Figure 95. MFR_SPECIFIC_16 (VIN UVLO) Register

7

6

5

4

3

2

1

0

Reserved

R-00 0000

VIN_UVLO

R/W

Table 68. MFR_SPECIFIC_16 (VIN UVLO) Register Field Descriptions

Bit

7:2

1:0

Field

Type Reset

NVM

—

Description

Reserved

VIN_UVLO

R

00 0000

01

Always set to 0.

R/W

Yes

Input Voltage UVLO

00:4.25V

01: 6.0V

10: 8.1V

11: 10.2V

7.6.2.3.61 MFR_SPECIFIC_19 (E3h)

Format

N/A

Description

The MFR_SPECIFIC_19 command sets the thresholds for determining the current

sharing warning. Once the difference between any phase current and the average

current is larger than the pre-defined threshold, the STATUS_IOUT [3] will be set

while asserting PMB_ALERT#.

89

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

Default

0003h

Figure 96. MFR_SPECIFIC_19 Register

15

14

6

13

12

11

10

9

8

0

Reserved

R- 0000 0000

7

5

4

3

2

1

PHFLT_DIS_S

EL

Reserved

R- 0000

CUR_SHARE_TH

R/W

Table 69. MFR_SPECIFIC_19 Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

15:8

Reserved

R

0000

__

Always set to 0.

7

PHFLT_DIS_SEL

R/W

0

Yes

0: Phase with Current Share Warning will be turned

off.

1: Phase with Current Share Warning will NOT be

turned off.

6:3

2:0

Reserved

R

0000

011

—

Always set to 0.

000: 2 Amps

CUR_SHARE_TH

R/W

Yes

001: 4 Amps

010: 6 Amps

011: 8 Amps

000: 10 Amps

001: 15 Amps

010: 20 Amps

011: OFF

7.6.2.3.62 MFR_SPECIFIC_20 (Maximum Operational Phase Number) (E4h)

Format

N/A

Description

The MFR_SPECIFIC_20 command sets the maximum operational phase numbers

on-the-fly. If the maximum operational phase number is set higher than the

available phase numbers specified by hardware, then the operational phase

number remains unchanged, and the STAUTS_MFR_SPECIFIC<3> is set while

asserting PMB_ALERT.

Default

Hardware Specific

Figure 97. MFR_SPECIFIC_20 (Maximum Operational Phase Number) Register

7

6

5

4

3

2

1

0

Reserved

R-0 0000

PHASE_NUM

R/W

Table 70. MFR_SPECIFIC_20 (Maximum Operational Phase Number) Register Field Descriptions

Bit

7:3

2:0

Field

Type Reset

NVM

—

Description

Reserved

PHASE_NUM

R

0 0000

Always set to 0.

R/W

—

Phase Number

000: 1-phase operation.

001: 2-phase operation.

010: 3-phase operation.

011: 4-phase operation.

100: 5-phase operation.

101: 6-phase operation.

Others: Not allowed

90

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

7.6.2.3.63 MFR_SPECIFIC_21 (VIN UVLO) (E5h)

Format

N/A

Description

The MFR_SPECIFIC_21 command programs the over-voltage thresholds.

Tracking OV threshold: VOUT_COMMAND + OV_TRACK_OFFSET

Fixed OV threshold: VOUT_MAX + FIX_OV_OFFSET

Default

0Fh

Figure 98. MFR_SPECIFIC_21 Register

7

6

5

4

3

2

1

0

Reserved

R-000

OV_TRACK_OFFSET

R/W

FI_OV_OFFSET

R/W

Table 71. MFR_SPECIFIC_21 Register Field Descriptions

Bit

7:5

4:3

Field

Type Reset

R 000

NVM

—

Description

Always set to 0.

00:175mV

Reserved

OV_TRACK_OFFSET

Yes

01:225mV

10:275mV

11:325 mV

000: 50mV

2:0

FIX_OV_OFFSET

Yes

001: 100mV

010: 150mV

011: 200mV

100: 250mV

101: 300mV

110: 350mV

111: 400mV

7.6.2.3.64 MFR_SPECIFIC_22 ( VOUT_UV_FAULT_threshold) (E6h)

Format

N/A

Description

The MFR_SPECIFIC_22 command sets the value of VOUT undervoltage

threshold.

UVP threshold = VOUT_COMMAND - Load Line * Iout - VOUT_UVF_OFFSET

NVM: 03h

Default

Figure 99. MFR_SPECIFIC_22 (VOUT_UV_FAULT_threshold) Register

7

6

5

4

3

2

1

VOUT_UVF_THRESHOLD

R/W

0

Reserved

R-0 0000

91

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

Table 72. MFR_SPECIFIC_22 (VOUT_UV_FAULT_threshold) Register Field Descriptions

Bit

7:3

2:0

Field

Type Reset

NVM

—

Description

Reserved

R

0 0000

Always set to 0.

VOUT_UVF_OFFSET

R/W

Yes

VOUT UVF threshold

000: 50 mV

001: 100 mV

010: 150 mV

011: 200 mV

100: 250 mV

101: 300 mV

110: 325 mV

111: 400 mV

7.6.2.3.65 MFR_SPECIFIC_23 (E7h)

Format

N/A

Description

The MFR_SPECIFIC_23 command sets the boot voltage in 8-bit VID format.

(Same as MFR_SPECIFIC_11) The two data bytes contain of a right-justified VID

code with VID0 in bit 0 of the lower data byte, VID1 in bit 1 of the lower byte and

so forth.

Default

Figure 100. MFR_SPECIFIC_23 Register

15

7

14

6

13

12

11

10

9

1

8

0

Reserved

R- 0000 0000

5

4

3

2

BOOT_CODE

R/W

Table 73. MFR_SPECIFIC_23 Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

15:8

Reserved

R

0000

__

Always set to 0.

7:0

BOOT_CODE

R/W

Yes

Set the boot voltage according to the selected VID

table.

7.6.2.3.66 MFR_SPECIFIC_24 (E8h)

Format

N/A

Description

The MFR_SPECIFIC_24 command set is used to enable/disable the Phases in

Analog along with some other settings/logic.

Default

Figure 101. MFR_SPECIFIC_24 (VIN UVLO) Register

7

6

5

4

3

2

1

0

Reserved

R-00

PH5_DIS

PH4_DIS

PH3_DIS

PH2_DIS

PH1_DIS

PH0_DIS

R/W

92

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

Table 74. MFR_SPECIFIC_24 (VIN UVLO) Register Field Descriptions

Bit

7:6

5

Field

Type Reset

NVM

—

Description

Reserved

PH5_DIS

R

00

0

Always set to 0.

R/W

No

1: Phase5 is disabled.

0: Phase5 is not disabled.

1: Phase4 is disabled.

0: Phase4 is not disabled.

1: Phase3 is disabled.

0: Phase3 is not disabled.

1: Phase2 is disabled.

0: Phase2 is not disabled.

1: Phase1 is disabled.

0: Phase1 is not disabled.

1: Phase0 is disabled.

0: Phase0 is not disabled.

4

3

2

1

0

PH4_DIS

PH3_DIS

PH2_DIS

PH1_DIS

PH0_DIS

R/W

0

No

7.6.2.3.67 MFR_SPECIFIC_44 (DEVICE_CODE) (FCh)

Format

Description

Default

The MFR_SPECIFIC_44 command reads back the DEVICE_CODE information.

!~ 01F0h!~01F8h

Figure 102. MFR_SPECIFIC_44 (DEVICE_CODE) Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

DEVICE_CODE

R-0000 0001

4

3

DEVICE_CODE

R-1111 0000

Table 75. MFR_SPECIFIC_44 (DEVICE_CODE) Register Field Descriptions

Bit

Field

Type Reset

NVM

Description

15:0

DEVICE_CODE

R

0000

0001

1111

0000

—

Device Code

93

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

8 Application and Implementation

8.1 Application Information

The TPS53667 device has a very simple design procedure. Please contact your local Texas Instruments

representative to get a copy of our excel-based design tool spreadsheet. This design describes a typical output

application with pinstrap mode.

8.2 Typical Application

R16

R17

26.7 kΩ

39.2 kΩ

SKIP-NVM

VREF

TSEN

R1

20 kΩ

R14

12.4 kΩ

R15

30.1 kΩ

C1

1 nF

R2

121 kΩ

VREF

R3

4.32 kΩ

VREF

40 39 38 37 36 35 34 33

32 31

R4

R18

9.31 kΩ

R20

R22

20 kΩ

16.5 kΩ 16.5 kΩ

1

2

3

4

5

6

7

8

9

OCL-R

O-USR 30

IMON

CSP1

CSP2

CSP3

CSP4

CSP5

CSP6

VSP

C2

2.2 nF

SLEW-MODE 29

ADDR-TRISE 28

CSP1

R5

33.2 kΩ

CSP2

R19

150 kΩ

R21

R23

CSP3

CSP4

VR_FAULT 27

PMB_DIO 26

PMB_ALERT 25

PMB_CLK 24

ENABLE 23

GND 22

VR_FAULT

PMB_DIO

24.3 kΩ 24.3 kΩ

TPS53667

U1

VOUT

PMB_ALERT

PMB_CLK

CSP5

CSP6

R7

0 Ω

R6 0 Ω

VOUT-SENSE+

ENABLE

C3

1 nF

R8 0 Ω

GND-SENSEœ

10 VSN

RESET 21

RESET

R9

0 Ω

R30

0 Ω

11 12

13 14

15

16 17 18 19 20

R11

2.55 Ω

C4

12 pF

VR_HOT

VR_RDY

R10

8.06kΩ

R13 1 Ω

R12 1 Ω

12-V V_IN

5-V V_IN

C5

1nF

C6

330 nF

VREF

C7

1 mF

C8

4.7 mF

C9

1 mF

V3R3

3.3V

V3R3

R24

10 kΩ

R25

10 kΩ 10 kΩ

R26

C10

0.1 mF

R27

10 kΩ

C11

0.1 mF

R28

10 kΩ

R29

10 kΩ

Figure 103. Controller Schematic for a 6-Phase, 1 V, 180 A Application

94

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

L7

65 nH

P12-V V_IN

12-V V_IN

PC13

270 mF

16 V

PC14

270 mF

16 V

C68

22 mF

C69

22 mF

C66

22 mF

C67

22 mF

Reserve 30 x 100 µF, 1206 ceramic capacitors, populate 20x100uF

VOUT

C71

C72

C73

C74

C75

C76

C77

C78

C79

C80

C81

C82

C83

C84

C85

C86

C87

C88

C70

100 µF

C89

100 µF

100 µF 100 µF 100 µF 100 µF 100 µF 100 µF 100 µF 100 µF 100 µF 100 µF 100 µF 100 µF

100 µF 100 µF 100 µF 100 µF 100 µF 100 µF

PGND

VOUT

C90

C91

C92

C93

C94

C95

C96

C97

C98

C99

DNP DNP DNP DNP DNP DNP DNP DNP DNP DNP

PGND

Figure 105. Input and Output Filter for a 6-Phase, 1 V, 180 A Application

8.2.1 Design Requirements

•

6-phase, 1 V, 180 A output

Number of phases: 6

Input Voltage 10.8 V – 13.2 V

I_max: 180 A

Load-line: Zero Load Line

Boot voltage, V_BOOT: 1.0 V

PMBus Address: 1110001 (bin)

96

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

8.2.2 Detailed Design Procedure

For this design, complete the following steps:

1. Select Switching Frequency

2. Set the Maximum Output Current

3. Select the Soft-Start Slew Rate

4. Select the Operation Mode

5. Choose Inductor

6. Select the Per-Phase Valley Current Limit and Ramp Level

7. Set the Load Line

8. Set the BOOT Voltage

9. Set OSR/USR Thresholds for Improving Load Transient Performance

10. Determine Digital Current Monitor (IMON) Gain and Filter Setting

11. Adjust Compensation Design

12. Set the PMBus Addresses

13. Program the Device with the PMBus

8.2.2.1 Select the Switching Frequency

The value of a resistor (R_F) between the F-IMAX pin and GND selects the switching frequency. The frequency is

an approximate frequency and is expected to vary based on load and input voltage.

Table 76. Frequency Selection Table

SELECTION

RESISTOR (R_F) VALUE (kΩ)

OPERATING FREQUENCY

(f_SW) (kHz)

20

24

300

400

500

600

700

800

900

1000

30

39

56

75

100

150

For this design, choose 500 kHz for the switching frequency. So, R_F= 30 kΩ.

97

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

8.2.2.2 Set the Maximum Output Current (I_MAX

)

The voltage on the F-IMAX pin sets the maximum output current from the value of the resistors connected from

the VREF pin to the F-IMAX pin (R_IMAX). Equation 7 shows the maximum output current calculation.

NOTE

The default total overcurrent threshold is 125% of I_MAX

ꢀ_&

)

= 255 ×

-!8

(ꢀ_&+ ꢀ_)-!8

ꢁ

(7)

(8)

Use Equation 8 to calculate R_IMAX

.

ꢁ

2_&× (ꢀ55 F )_-!8

2_)-!8

=

)

-!8

From Table 76, R_F= 30 kΩ. Selecting the closest standard resistor value, R_IMAX= 12.4 kΩ

NOTE

The tolerance of the R_Fand R_IMAXresistors affect I_IMAXvalue. If the design requires an

accurate I_IMAXis needed, select an R_Fand an R_IMAXvalue with tight tolerance (0.5% or

0.1%).

8.2.2.3 Select the Soft-Start Slew Rate

To select the soft-start slew rate, the first step is to select the output voltage change slew rate. The resistor

(R_SLEW) (connected between the SLEW-MODE pin and GND) sets the output voltage change slew rate when

using VOUT_COMMAND. Table 77 show a summary of these settings. For a minimum 0.68-mV/μs slew rate, the

resistor R_SLEW= 24.3 kΩ.

Table 77. Vout Change Slew Rate Selection

SELECTION RESISTOR

MINIMUM SLEW RATE

( mV/µs)

R_SLEW(kΩ)

20

24

0.34

0.68

1.02

1.36

1.7

30

39

56

75

2.04

2.38

2.74

100

150

After determining the V_OUTchange slew rate, select the ratio of soft-start rate versus V_OUTchange slew rate.

Select a value for resistor R_ADDR(the resistor between ADDR_TRISE pin and GND) to configure this ratio.

Table 78. Soft-Start Slew Rate Selection

SELECTION RESISTOR

MINIMUM SLEW RATE

( mV/µs)

R_ADDR(kΩ)

20 or 24

30 or 39

1

1/2

1/4

1/8

56 or 75

100 or 150

98

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

In this design, the soft-start slew rate is the same as Vout change slew rate. So R_ADDR=20k or 24k is selected.

The LSB of BOOT voltage VID determines the value of R_ADDRas described in Set the BOOT Voltage. If slower

soft start is desired, higher R_ADDRcan be used to set soft-start slew rate to be 1/2, 1/4 or 1/8 of output voltage

change slew rate.

8.2.2.4 Select the Operation Mode

The resistor (R_MODE) is connected between the VREF pin and the SLEW-MODE pin. After selecting the value of

R_SLEW, set the operation mode by choosing the voltage on the SLEW-MODE pin as summarized in Table 79 and

the Electrical Characteristics table. In this design, VR 12.0 mode is selected with individual phase interleaving,

disabled dynamic phase shedding, and zero load-line. As described in the Select the Soft-Start Slew Rate

section, use the value R_SLEW= 24 kΩ, so R_MODE= 16.5 kΩ to select the desired operating modes.

Table 79. Operation Mode with Resistor Selection

OPERATION MODES BIT

BIT DESCRIPTION

0: VR12.5 (Use VR12.5 VID table)

1: VR12.0 (Use VR12.0 VID table)

0: individual phase interleaving

1: 1/3, 2/4, and 5/6 phase interleaving

0: Disable dynamic phase shedding

1: Enable dynamic phase shedding

0: Non-zero load-line

Mode bit M₃

MFR_SPEC_13<7>

MFR_SPEC_13<6>

MFR_SPEC_13<4>

MFR_SPEC_13<3>

VR12_MODE

Mode bit M₂

Mode bit M₁

Mode bit M₀

PI_SET

DPS_EN

ZLL_SET

1: Zero load-line

8.2.2.5 Choose Inductor

Smaller inductance values yield better transient performance, but also have a higher ripple and lower efficiency.

Higher inductance values have the opposite characteristics. It is common practice to limit the ripple current to

between 20% and 50% of the maximum per-phase current. In this design example, 40% of the maximum per-

phase current is used.

)

1ꢁꢂ

ꢃ

)

0_0

= l ^-!8p × %6_2)00,ꢀ= l

p × ꢂ.4 = 1ꢄ !

Æ

(9)

6_/54

k¶₃₇× 6_{).(≠°∏ ꢀ}o

k6_{).(≠°∏ ꢀ}F 6_/54o ×

6 × §4

, =

=

= 1ꢁꢂ Æꢃ

)

0_0

(10)

The inductor with a value of 150 nH and saturation current of I_SAT= 61 A at 100°C is selected for this application.

This saturation current level can be used to determine the OCL level. So the I_OCLis selected to be 48 A to use in

the OCL resistor calculation in Equation 11.

)

/#,

= )_3!4F )₀

= 61 F 12.ꢀ2 = ꢁ8.68 !

;

:

0 °£¥µ°¨

(11)

8.2.2.6 Select the Per-Phase Valley Current Limit And Ramp Level

The per-phase, valley current limit is selected by the resistor (R_OCL) from OCL-R pin to GND as shown in

Table 80. The RAMP is set by the voltage on OCL_R pin with resistor (R_RAMP) from OCL_R pin to VREF. The

current limit is selected so that the output current OCL is higher than the maximum per-phase current to allow

sufficient room for current increase during load transient while the peak inductor current is still lower saturation

current level.

99

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

Table 80. Per-Phase Valley Current Limit vs Resistor

Selection

PER-PHASE

VALLEY

CURRENT LIMIT

(A)

V_OCL(V)

R_OCL-R(kΩ)

20

24

27

30

33

36

39

42

45

30

39

≤ 0.85

56

75

100

150

20

24

48

51

54

57

60

63

66

69

30

39

≥ 0.95

56

75

100

150

Table 81. Ramp Level vs OCL_R Pin Voltage Selection

V_OCL-R(V)

RAMP LEVEL ( mV_p-p)

0.2 ±50 mV or 1.0 ±50 mV

0.4 ±50 mV or 1.2 ±50 mV

0.6 ±50 mV or 1.4 ±50 mV

0.8 ±50mV or 1.6 ±50mV

40

80

150

200

In this design example, a 48-A valley current limit is selected, so R_OCLis chosen as 20 kΩ.

In this example, a ramp voltage of 150 mV is chosen. The user may chose a lower ramp value to improve

transient performance if jitter performance is less of a concern. This value depends on the board layout and

individual layout requirements.

Table 80 notes that V_OCLmust be ≥ 1.0 V. Table 81 shows that for a 150- mV ramp, V_OCLmust be 1.4 V,

therefore the value of the resistor placed between the OCL-R pin and the VREF pin (R_OCL-R) should be 4.32 kΩ.

8.2.2.7 Set the Load-Line

The load-line is set by the resistor, R_ISUM, from ISUM pin to VREF. Please note a 0 Ω resistor will be used since

load line setting is not required for this design example.

The below procedure is provided for applications when a 1.05 mΩ load line is needed.

1

R_ISUM= R_LL

´

= 1.05mW´

= 2.52kW

1

6

g_{M isum}´R_CS´ A_CS

(

)

0.5mS´5mW ´

where

•

R_LLis the desired load-line

g_M(isum)is the ISUM amplifier transconductance

R_CSis the current-sensing gain from the CSD95490

A_CSis the internal gain

(12)

100

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

Because the sensed current from the CSD95490 device is temperature-compensated, a NTC network is not

required to achieve a simple application circuit.

8.2.2.8 Set the BOOT Voltage

The resistor, R_BOOT, placed between the VBOOT pin and GND as shown in Table 82 sets bit 3, 2, and 1 of the

VID of the BOOT voltage. The voltage on VBOOT pin sets bit 7, 6, 5, 4 of the VID of the BOOT voltage. The

resistor between the ADDR_TRISE pin and GND sets bit 0 of VID of the BOOT voltage. The BOOT voltage

selection also depends on the operation mode selected in the Select the Operation Mode section. In this design

example, 1.0 V is selected as the BOOT voltage in VR12.0 mode, and the VID is 1001 0111, so the R_BOOT= 39

kΩ, V_VBOOT= 1.009 V, R_ADDR= 24 kΩ.

Table 82. Boot Voltage VID Selection (Step 1)

BOOT VOLTAGE VID

R_BOOT(kΩ)

B₃B₂B₁

20

24

000

001

010

011

100

101

110

111

30

39

56

75

100

150

Table 83. Boot Voltage VID Selection (Step 2)

BOOT VOLTAGE VID

V_VBOOT(V)

B₇B₆B₅B₄

V_VBOOT≤ 0.053V ± 20 mV

V_VBOOT= 0.159V ± 20 mV

V_VBOOT= 0.226V ± 20 mV

V_VBOOT= 0.372V ± 20 mV

V_VBOOT= 0.478V ± 20 mV

V_VBOOT= 0.584V ± 20 mV

V_VBOOT= 0.691V ± 20 mV

V_VBOOT= 0.797V ± 20 mV

V_VBOOT= 0.903V ± 20 mV

V_VBOOT= 1.009V ± 20 mV

V_VBOOT= 1.116V ± 20 mV

V_VBOOT= 1.222V ± 20 mV

V_VBOOT= 1.328V ± 20 mV

V_VBOOT= 1.434V ± 20 mV

V_VBOOT= 1.541V ± 20 mV

V_VBOOT= 1.615V ± 10 mV

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Table 84. Boot Voltage VID Selection (Step 3)

BOOT VOLTAGE VID

R_ADDR(kΩ)

B₀

20 or 30 or 56 or 100

0

24 or 39 or 75 or 150

1

101

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

8.2.2.9 Set OSR/USR Thresholds to Improve Load Transient Performance

The resistor, R_OSRconnected between the O-USR pin and GND as shown in Table 85 sets the overshoot

reduction (OSR) threshold.

Table 85. OSR Threshold vs Resistor Selection

R_O-USR

(kΩ)

OSR THRESHOLD ( mV)

20

24

30

40

30

60

39

80

56

100

120

140

OFF

75

100

150

The required OSR setting is based on the load-transient performance and the amount of the actual output

capacitance. The suggested method is to start with OSR OFF and perform the load transient per the application

requirement. If the overshoot can meet the specification with the chosen output capacitance, then the OSR can

be kept OFF. So the resistor R_OSRcan be selected as 150 kΩ. Otherwise the OSR threshold can be lowered by

choosing a lower setting from the Table 85 to reduce the overshoot to meet the specifications.

Once R_OSRis selected, the Undershoot Reduction (USR) threshold is set by the voltage on the O-USR pin with

the resistor, R_USR, from the O-USR pin to VREF as shown in Table 86.

Table 86. USR Threshold vs Voltage Selection

V_O-USR

(V)

USR THRESHOLD

( mV)

V

_O-USR≤ 0.3

20

30

0.35 ≤ V_O-USR≤ 0.45

0.55 ≤ V_O-USR≤ 0.65

0.75 ≤ V_O-USR≤ 0.85

0.95 ≤ V_O-USR≤ 1.05

1.15 ≤ V_O-USR≤ 1.25

1.35 ≤ V_O-USR≤ 1.45

1.55 ≤ V_O-USR≤ 1.6

60

80

100

120

140

OFF

The design procedure for the USR threshold is similar to the OSR setting. The initial setting of the USR threshold

is to start with USR OFF, and then perform the load transient test. If the undershoot can meet the requirement,

the USR setting can remain OFF. In this design the USR setting is OFF.

102

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

8.2.2.10 Digital Current Monitor (IMON) Gain and Filter Setting

To correctly monitor digital current values, the gain of the analog current monitor should be determined by setting

the IMON voltage to 0.85 V for maximum output current I_MAX. When PMBus host sends the READ_IOUT

command, the current information is reported.

R_IMONcan be determined by using Equation 13

0ꢀ85 6

2_)-/.

=

= ꢂꢂꢀ0ꢃ ´3

1

)

× 2_#3× 3&

-!ꢁ

180 ! × 5 ≠3 × @

A

ꢂ5 ´3

where

•

R_IMONis the desired impedance on the IMON pin

I_MAXis the total maximum output current

R_CSis the current sense gain from CSD95490

SF is is the internal current gain scaling factor

(13)

In this design example, I_MAX= 180 A, so the resistance, R_IMON, is calculated as 33.05 kΩ. Use the standard value

of 33.2kΩ. A capacitor, C_IMONusually connected in parallel with R_IMONto provide filtering on the IMON signal. In

this design, a C_IMONvalue of 2.2 nF is selected.

8.2.2.11 Compensation Design

A type-II compensator is used with the DCAP+ architecture of TPS53667 as shown in Figure 106. g_M(comp)is the

COMP amplifier transconductance, which is typically 0.5 mS. R_COMPdetermines the gain and the compensation

pole and zero locations. C_COMPSdetermines the compensation zero to increase the phase margin, and C_COMPP

determines the compensation pole to filter out the high-frequency noise. The actual compensator design needs

to be adjusted, based on the experimental test results and the bode plot measurements. In this example, R_COMP

= 8.06 kΩ, C_COMPS= 1 nF, and C_COMPP= 12 pF to put the compensation zero at 19.7 kHz and the compensator

pole at 1.65 MHz.

g_{M_COMP}

COMP

V_DAC

+

V_{FB_DRP}

œ

R_COMP

C_COMPP

V_COMP

V_ISUM

V_RAMP

C_COMPS

Adaptive

On-Time

Modulator

VREF

Figure 106. Compensation Circuitry

8.2.2.12 Set PMBus Addresses

To communicate with system controllers or host with PMBus interfaces, the slave address of the TPS53667

device needs to be set. The voltage on ADDR_TRISE pin sets the PMBus address. Since the resistance of

R_ADDRis already determined (24 kΩ), The resistance between ADDR_TRISE pin and VREF can be calculated. In

this design, PMBUs address of 111 0001 is used. The resistor between ADDR_TRISE and VREF is 16.5 kΩ.

8.2.2.13 Programming the Device with the PMBus

It is optional to use the PMBus interface to program the TPS53667 device since all the settings can be

configured externally by using resistors; however, the system controller can override the configurations or can

program the device to change the operation modes using the PMBus. The supported PMBus command sets

have been introduced in the previous section for the firmware development.

103

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

8.2.3 Application Curves

6-Phase, 180-A, full load application

1.0032

1.0026

1.002

95%

90%

85%

80%

75%

70%

65%

60%

55%

50%

1.0014

1.0008

1.0002

0.9996

0.999

0.9984

0.9978

0

20

40

60

80

100 120 140 160 180

0

20

40

60

80

100 120 140 160 180

Load Current (A)

D001

V_IN= 12.0 V

V_OUT= 1.0 V

V_V5= 5.0 V

V_IN= 12.0 V

V_OUT= 1.0 V

V_V5= 5.0 V

Loadline = 0 mΩ

f_SW= 500 kHz

Figure 107. Load Regulation

Figure 108. Load Current vs. Efficiency

V_IN= 12 V

V_OUT= 1.0 V

I_OUT= 6 A

V_IN= 12 V

V_OUT= 1.0 V

I_OUT= 6 A

Figure 109. Enable Start-Up

Figure 110. Enable Shutdown

104

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

6-Phase, 180-A, full load application

V_IN= 12 V

V_OUT= 1.0 V

I_OUT= 60 A

V_IN= 12 V

V_OUT= 1.0 V

I_OUT= 60 A

Figure 111. PWM Interleaving (Phases 1-4)

Figure 112. PWM Interleaving (Phases 4-6)

V_IN= 12 V

V_OUT= 1.0 V

I_OUT= 160 A

V_VIN= 12 V

V_OUT= 1.0 V

40-A Load Step

Figure 113. Output Ripple

Figure 114. Transient Response

105

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

6-Phase, 180-A, full load application

V_IN= 12 V

I_OUT= 6 A

V_IN= 12 V

V_BOOT=1.0 V

I_OUT= 6 A

V_BOOT=1.0 V

VOUT COMMAND change to

0.8 V

VOUT COMMAND change to

1.2 V

Figure 116. VID Change to 0.8 V

Figure 115. VID Change to 1.2 V

V_IN= 12 V

I_OUT= 6 A

V_IN= 12 V

I_OUT= 6 A

V_BOOT=1.0 V

V_OUT= 1.2 V

V_BOOT=1.0 V

V_OUT= 0.8 V

Figure 118. Reset Function (V_OUT=1.2 V)

Figure 117. RESET Function (V_OUT=0.8 V)

106

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

6-Phase, 180-A, full load application

SW1

SW2

SW3

IOUT

PHASE ADDING

V_IN= 12 V

V_OUT= 1.0 V

I_OUT= 160 A

Figure 120. Phase Adding

OC_FAULT_LIMIT=150 A

Figure 119. Hiccup mode (OCP)

100

80

200

Gain

Phase

160

60

120

80

40

20

40

SW1

SW2

0

-20

-40

-60

-80

-100

-40

-80

-120

-160

-200

SW3

PHASE SHEDDING

IOUT

1000 2000 5000 10000

100000

Frequency (Hz)

1000000

D001

6-Phase

V_IN= 12 V

Operation

Figure 121. Phase Shedding

V_OUT= 1.0 V

I_OUT= 180 A

Figure 122. Bode Plot

107

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

9 Power Supply Recommendations

The TPS53667 device operates from a 5-V supply at the V5 pin, and a 12-V supply on the VIN pin. For best

results, consider the UVLO range for VIN, V5 pin voltages, use well regulated supplies and use the

recommended filter network.

The controller requires 1.2 ms to complete the reading of the pinstrap settings. If the converter is enabled before

pinstrap completion, the controller first completes the pinstrap function and then initiated the start-up sequence.

After the ENABLE pin voltage goes high, the controller waits for approximately 260 µs before V_OUTbegins to

ramp up.

12 V

0 V

VIN

V5

5 V

0 V

3.3 V

1 V

0 V

V3R3

ENABLE

Time

图 123. Power Supply Waveforms

108

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

10 Layout

10.1 Layout Guidelines

10.1.1 Schematic Review Checklist

•

Confirm the pin-out of the controller on schematic to the pin-out of datasheet

Get a closest TI reference design to check for connection and component values

Have a component value design tool ready to check component values.

Carefully confirm the choice of inductor and DCR (see the Detailed Design Procedure section).

Carefully confirm the choice of output capacitors (see the Detailed Design Procedure section).

Confirm the polarity of the differential pair of voltage sensing (VSP/VSN).

Confirm the current sensing feedback and reference voltage of TI smart power stages (ex: CSD95490Q5MC).

A separated IC ground (analog ground) is recommended but not a must.

10.1.2 PCB Design Guidelines

Most Critical Layout Requirement

Separate noisy driver interface lines from sensitive analog lines.

The TPS53667 device makes this separation easy. The power stage (CSD95490) is

outside of the TPS53667 device. So all gate-drive and switch-node traces must be local to

the inductor and the MOSFETs.

10.1.2.1 Layer Stack-up, 8-Layer PCB as example

•

Top Layer: VIN, VOUT, power ground and analog ground

Layer 2: Power ground

Layer 3: VIN, VREF, VOUT, PWM signals, and current sense signals

Layer 4: Power ground, analog ground, and VOUT plane

Layer5: Power ground, V3R3, and VOUT plane

Layer 6: V5, VIN and VOUT plane

Layer 7: Power ground

Bottom Layer: VIN, VOUT, power ground, analog ground, and feedbacks

109

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

Layout Guidelines (接下页)

10.1.2.2 Current Sensing Lines

Given the physical layout of most systems, the current feedback (CSPx) may have to pass near the power chain.

Clean current feedback is required for good load-line, current sharing, and current limiting performance of the

TPS53667, so please take the following precautions:

•

Run the current feedback signals in the VREF plane as shown in 图 124.

Recommended trace width is 8-10 mil

The distance of each trace should be larger than 20 mil

LhÜÇ

([ayer 3)

ëw9C t[!b9

([ayer 3)

图 124. Layout Example of Current Sensing Traces

10.1.2.3 Feedback Voltage Sensing Lines

The voltage feedback coming from the load must be routed as differential pair (distance ≤ 10 mil) all the way to

the TPS53667 VSP and VSN pins. Recommended trace width is 8-10 mil. Care should be taken to avoid routing

over switch-node traces.

110

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

Layout Guidelines (接下页)

ë{ꢀ

(.ottom)

ë{b

(.ottom)

图 125. Layout Example for Feedback Voltage Sensing Traces

10.1.2.4 PWM Lines

The PWM lines should be routed from the (TPS53667) device to the power stage (CSD95490) without crossing

any switch-node signals.

tía6

tía5

tía4

tía3

tía2

tía1

图 126. Layout Example for PWM Traces

10.1.2.5 Power Chain Symmetry

The TPS53667 device does not require special care in the layout of the power chain components. This is

because independent isolated current feedback is provided. If it is possible to lay out the phases in a symmetrical

manner, then please do so. The rule is: the current feedback from each phase needs to be clean of noise and

have the same effective current sense resistance.

111

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

Layout Guidelines (接下页)

10.1.2.6 Placing Analog Signal Components

Place components close to the TPS53667 device in the following order, as shown in 图 127:

1. COMP pin and ISUM pin compensation components must be put on the same side of the controller as

shown in. Recommended trace width is 8-10 mil.

2. Decoupling capacitors for VREF, V3R3, and V5 must be put on the same side of the controller as shown in.

Recommended trace width is 8-10 mil.

–

Decouple VREF to GND with at most 0.47-uF ceramic capacitor.

Decouple V3R3 to GND with at least 1-uF ceramic capacitor.

Decouple V5 to GND with at least 4.7-uF ceramic capacitor. A 1-Ω resistor between 5V supply voltage

and V5 pin is also recommended as a filter.

–

Decouple VIN to GND with at least 1-uF ceramic capacitor. A 1-Ω resistor between 12V supply voltage

and VIN pin is also recommended as a filter.

3. OCL-R resistors, F-IMAX resistors, SLEW-MODE resistors, VBOOT resistors, IMON resistor, and O-USR

resistors. Recommended trace width is 8-10 mil.

/hat9b{!ÇLhb

/hathb9bÇ{

59/hÜt[LbD /!t{

图 127. Layout Example of Decoupling Caps and Compensation Components

112

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

Layout Guidelines (接下页)

10.1.2.7 Grounding Recommendations

The TPS53667 device has a GND pin, and a thermal pad. The normal procedure for connecting these follows:

•

The thermal pad does not have an electrical connection to the TPS53667 device. However, it is suggested to

be connected to GND pin of the TPS53667 device (analog ground) to give good ground shielding as shown in

图 128

•

All the analog components should connect to this analog ground island

Use a single point connection from analog ground to the power ground.

The return path of the decoupling capacitors (V3R3, V5, VREF, Vin) should be as short as possible.

When a separated analog ground is used, it's recommended to have an analog ground shape in layer 3

(assuming controller is on the top layer) to interconnect all the analog ground signals.

!b![hD DwhÜb5

t[!b9

Db5

tLb

图 128. Layout Example for TPS53667 Grounding

113

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

Layout Guidelines (接下页)

10.1.2.8 TI Smart Power Stage CSD95490Q5MC

The following layout recommendations refer to the CSD95490Q5MC.

10.1.2.8.1 Electrical Performance

The CSD95490Q5MC has the ability to switch at voltage rates greater than 10 kV/µs. Special care must be taken

with the PCB layout design and placement of the input capacitors, inductor and output capacitors.

•

The placement of the input capacitors relative to VIN and PGND pins of CSD95490Q5MC device should have

the highest priority during the component placement routine. It is critical to minimize these node lengths. As

such, place ceramic input capacitors as close as possible to the VIN and PGND pins. The example in uses 1

× 3300 pF, 0402, 50-V, X7R ceramic capacitor and 3 × 22 µF, 1206, 25-V ceramic capacitors (TDK part

number C3216X5R1E226M160AB or equivalent). Notice there are ceramic capacitors on both sides of the

board with an appropriate amount of vias interconnecting both layers.

•

Closely connect the bootstrap capacitor (0.1-µF, 0603, 25-V ceramic capacitor) between the BOOT and

BOOT_R pins.

The switching node of the output inductor should be placed relatively close to the Power Stage

CSD95490Q5MC VSW pins. Minimizing the VSW node length between these two components reduces the

PCB conduction losses and actually reduce the switching noise level.

10.1.2.8.2 Thermal Performance

The CSD95490Q5MC has the ability to use the GND planes as the primary thermal path. As such, the use of

thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder

voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount

of solder attach that will wick down the via barrel:

•

Intentionally space out the vias from each other to avoid a cluster of holes in a given area.

Use the smallest drill size allowed in your design. The example in uses vias with a 12 mil drill hole and a 26

mil capture pad.

•

Tent the opposite side of the vias with solder-mask.

In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and

manufacturing capabilities.

10.1.2.8.3 Sensing Performance

The thermal sensing output TAO pin must be properly decoupled for accurate reporting. As discussed above, a

1nF 25V X7R ceramic capacitor should be placed between TAO and PGND as close to the TAO pin as practical.

The integrated current sensing technology built into the driver of the CSD95490Q5MC produces an analog signal

that is proportional to the inductor current with a proportionality constant of 5 mV/A. This signal is referenced to

the voltage applied to REFIN. For optimal performance of this technology a 0.1µF or larger ceramic capacitor

should be placed across the REFIN and PGND pins as close as possible to the device.

In addition the IOUT pin should be routed back to the TPS53667 device in a quiet inner layer. If multiple

CSD95490Q5M’s are used on the same board, the IOUT traces should have at least 20 mils spacing between

them. Capacitive loading of the IOUT pin should be avoided to maintain the integrity of the sensed signal.

114

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

Layout Guidelines (接下页)

10.1.2.9 Power Delivery and Power Density

Power stage layout guidelines:

•

Maximize the widths of power, ground and drive signal connections.

For conductors in the power path, be sure there is adequate trace width for the amount of current flowing

through the traces.

•

Make sure there are sufficient vias for connections between layers. A good rule of thumb is to use 1 minimum

via per ampere of current.

Phase 5

Phase 4

Phase 3

Phase 2

Phase 1

Phase 6

VIN

Power

ground

1"

VOUT

3"

图 129. Layout Example of Power Density

115

TPS53667

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

10.2 Layout Example

图 130. TPS53667 Layout Example

116

TPS53667

www.ti.com.cn

ZHCSFI2B –JULY 2016–REVISED FEBRUARY 2017

11 器件和文档支持

11.1 器件支持

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.1.2 开发支持

如需 Power Stage Designer 工具，请访问 www.ti.com/tool/powerstage-designer。

11.2 文档支持

11.2.1 相关文档


型号：	TPS53667
厂家：	TEXAS INSTRUMENTS
描述：	适用于 ASIC 且具有 NVM 和 PMBus 接口的六相 D-CAP+ 无驱动器降压控制器驱动控制器驱动器
文件：	总126页 (文件大小：3558K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS53667 [TI]

相关型号：

TPS53667RTAR

TPS53667RTAT

TPS53676

TPS53676RSLR

TPS53676RSLT

TPS53679

TPS53679RSBR

TPS53679RSBT

TPS53681

TPS53681RSBR

TPS53681RSBT

TPS53685