TPS53681 [TI]
具有 PMBus 和 NVM 的双通道 6+2/5+3 D-CAP+™ 多相降压控制器;
| 型号： | TPS53681 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 PMBus 和 NVM 的双通道 6+2/5+3 D-CAP+™ 多相降压控制器 控制器 |
| 文件： | 总130页 (文件大小：3634K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
具有 NVM 和 PMBus™ 的TPS53681双通道(6-Phase + 2-Phase) or (5-
Phase + 3-Phase) D-CAP+™ 降压多相控制器
1 特性
3 说明
1
•
•
转换输入电压范围：4.5V 至 17V
TPS53681 是一款多相降压控制器，具有两个通道、
内置非易失性存储器 (NVM) 和 PMBus™接口，且可
与 TINexFET ™功率级完全兼容。高级控制 特性 ，例
如具有下冲减弱 (USR) 功能的 D-CAP+™架构，可提
供快速瞬态响应、低输出电容和高效率。该器件还提供
全新的相位交错策略和动态切相功能，可有效提升轻负
载条件下的效率。该器件通过可调压摆率支持快速动态
电压转换。此外，该器件还支持 PMBus 通信接口，可
向系统报告遥测的电压、电流、功率、温度和故障状
况。所有可编程参数均可通过 PMBus 接口进行配置，
而且可作为新的默认值存储在 NVM 中，以尽可能减少
外部组件数量。
具有可选 5mV 或 10mV 分辨率的 8 位 DAC，两个
通道的输出范围均为 0.25V 至 1.52V 或 0.5V 至
2.8125V。
•
相位配置
–
–
最高（6 相位 + 2 相位）或（5 相位 + 3 相位）
最低（1 相位 + 1 相位）
•
•
无驱动器配置，有助于实现高效的高频开关
可通过 PMBus 接口配置可编程压摆率，从而实现
动态输出电压转换
•
通过闭环频率控制进行频率选择：300kHz 至
1MHz
•
•
可编程内部环路补偿
TPS53681 器件采用热增强型 40 引脚 QFN 封装，额
定工作温度为 –40°C 到 125°C。
可通过非易失性存储器 (NVM) 进行配置，从而减少
外部组件数量
•
•
单独的相电流校准和报告
器件信息(1)
可通过可编程电流阈值实现动态切相，从而优化轻
负载和重负载下的效率
器件型号
TPS53681
封装
QFN (40)
封装尺寸（标称值）
5mm × 5mm
•
•
快速添相以减弱下冲 (USR)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
与 TI NexFET™功率级完全兼容，可实现高密度解
决方案
图 1. 简化应用
•
•
•
•
精确可调电压定位
已获专利 AutoBalance™相位均衡
可选 16 级每相位电流限制
TPS53681
PWM1
Power
PMBus™用于电压、电流、功率、温度和故障条件
遥测的系统接口
Stage
CSP1
•
•
低静态电流
5 mm × 5 mm 40 引脚 QFN PowerPad™封装
PWM2
CSP2
PMBus
Power
Stage
2 应用
•
•
•
•
网络处理器电源（Broadcom®、 Cavium®）
数据中心、园区和分支交换机
PWM6
CSP6
Power
Stage
核心和边缘路由器
高电流 FPGA 电源（Intel®、 Xilinx®)
Copyright © 2017, Texas Instruments Incorporated
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSCT1
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
目录
6.20 Boot Voltage and TMAX Settings ......................... 21
6.21 Protections: OVP and UVP................................... 22
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 7
6.5 Supply: Currents, UVLO, and Power-On Reset........ 7
6.6 References: DAC and VREF .................................... 8
6.22 Protections: ATSEN and BTSEN Pin Voltage Levels
and Fault .................................................................. 22
6.23 PWM: I/O Voltage and Current ............................ 23
6.24 Dynamic Phase Add and Drop.............................. 24
6.25 Typical Characteristics.......................................... 34
Detailed Description ............................................ 35
7.1 Overview ................................................................. 35
7.2 Functional Block Diagram ....................................... 35
7.3 Feature Description................................................. 35
7.4 Device Functional Modes........................................ 43
7.5 Programming........................................................... 43
Applications, Implementation, and Layout ..... 105
8.1 Application Information.......................................... 105
8.2 Typical Application ................................................ 105
Power Supply Recommendations.................... 116
7
6.7 Voltage Sense: AVSP and BVSP, AVSN and
BVSN ......................................................................... 8
8
9
6.8 Telemetry .................................................................. 9
6.9 Input Current Sensing ............................................. 10
6.10 Programmable Loadline Settings.......................... 11
6.11 Current Sense and Calibration.............................. 15
10 Layout................................................................. 117
10.1 Layout Guidelines ............................................... 117
10.2 Layout Examples................................................. 118
11 器件和文档支持 ................................................... 120
11.1 接收文档更新通知 ............................................... 120
11.2 社区资源.............................................................. 120
11.3 商标..................................................................... 120
11.4 静电放电警告....................................................... 120
11.5 术语表 ................................................................. 120
12 机械、封装和可订购信息..................................... 121
6.12 Logic Interface Pins: AVR_EN, AVR_RDY,
BVR_EN, BVR_RDY, RESET, VR_FAULT,
VR_HOT................................................................... 15
6.13 I/O Timing.............................................................. 16
6.14 PMBus Address Setting ........................................ 17
6.15 Overcurrent Limit Thresholds................................ 18
6.16 Switching Frequency............................................. 19
6.17 Slew Rate Settings................................................ 19
6.18 Ramp Selections................................................... 20
6.19 Dynamic Integration and Undershoot Reduction .. 20
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (November 2018) to Revision B
Page
•
Updated the device NVM default values in Supported Commands ..................................................................................... 45
Changes from Original (June 2017) to Revision A
Page
•
•
更新了应用 列表...................................................................................................................................................................... 1
已添加 (21h) VOUT_COMMAND register table in Output Voltage Margin Testing section ................................................. 67
2
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
5 Pin Configuration and Functions
RSB Package
40-Pin QFN
Top View
BPWM1
BPWM2
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
BVSP
BCSP2
APWM6/BPWM3
APWM5
ACSP6/BCSP3
ACSP5
APWM4
ACSP4
Thermal
Pad
ACSP3
APWM3
APWM2
ACSP2
ACSP1
AVSN
APWM1
SMB_DIO
SMB_CLK
AVSP
(Not to scale)
Thermal pad acts as AGND.
NC = not connected
Pin Functions
PIN
I/O(1)
NO.
DESCRIPTION
NAME
ACSP1
ACSP2
ACSP3
ACSP4
ACSP5
23
24
25
Current sense input for the channel A. Connect to the IOUT pin of TI smart power stages. Tie the
ACSP5, ACSP4, ACSP3, or ACSP2 pin to the V3P3 pin according to Table 1 to disable the
corresponding phase.
I
26
27
Current sense inputs for channel A or channel B based on NVM option. Connect to the IOUT pin of
smart power stages. Tie ACSP6/BCSP3 to the 3.3-V supply to disable corresponding phase.
ACSP6/BCSP3
ADDR
28
34
Voltage divider to VREF and GND. The voltage level sets the 7-bit PMBus address with an ADC.
Address is latched at 3.3-V power up.
I
APWM1
APWM2
APWM3
APWM4
APWM5
8
7
6
5
4
O
O
O
O
O
PWM signal for phase 1 of channel A.
PWM signal for phase 2 of channel A.
PWM signal for phase 3 of channel A.
PWM signal for phase 4 of channel A.
PWM signal for phase 5 of channel A.
(1) G = ground, I = input, O = output, P = power input
Copyright © 2017–2019, Texas Instruments Incorporated
3
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
Pin Functions (continued)
PIN
I/O(1)
DESCRIPTION
NAME
NO.
APWM6/BPWM3
3
O
O
PWM signal for phase 6 of channel A, or phase 3 of channel B, based on the NVM option.
Connect to TAO pin of TI smart power stages of Channel A to sense the highest temperature of the
power stages and to sense the built-in fault signal from power stages
ATSEN
36
13
12
Active high enable input for channel A. Asserting the AVR_EN pin activates channel A. Re-cycling
BVR_EN pin clears the faults of channel A.
AVR_EN
AVR_RDY
I
Power good open-drain output signal of channel A. This open drain output requires an external pull-
up resistor. The AVR_RDY pin is pulled low when a shutdown fault occurs.
O
AVSN
AVSP
22
21
I
I
Negative input of the remote voltage sense of channel A.
Positive input of the remote voltage sense of channel A.
Current sense input for channel B. Connect to the IOUT pins of TI smart power stages. If channel B is
not used, then connect the BCSP1 pin to GND.
BCSP1
BCSP2
32
29
I
I
Current sense input for channel B. Connect to the IOUT pins of TI smart power stages. Tie the
BCSP2 pin to the V3P3 pin according to Table 1 to disable the corresponding phase.
BPWM1
BPWM2
1
2
O
O
PWM signal for phase 1 of channel B
PWM signal for phase 2 of channel B
Connect to TAO pin of TI smart power stages of Channel B to sense the highest temperature of the
power stages and to sense the built-in fault signal from power stages
BTSEN
BVR_EN
BVR_RDY
BVSN
35
20
16
31
30
O
I
Active high enable input for channel B. Asserting the BVR_EN pin activates channel B. Re-cycling
BVR_EN pin clears the faults of channel B.
Power good open-drain output signal of channel B. This open drain output requires an external pull-
up resistor. BVR_RDY is pulled low when a shutdown fault occurs.
O
I
Negative input of the remote voltage sense of channel B. If channel B is not used, connect BVSN to
GND.
Positive input of the remote voltage sense of channel B. If channel B is not used, connect BVSP to
GND.
BVSP
I
Input voltage from the positive terminal connecting to the input current sensing shunt. When input
current sensing is not used, short CSPIN to VIN_CSNIN and connect to the converter input voltage
(example: 12 V).
CSPIN
GND
37
I
17
18
19
15
11
10
9
G
Connect to GND
NC
–
No connection.
RESET
I/O
I/O
I
Resets the output voltage to BOOT voltage
SMBus or I2C bi-directional ALERT pin interface. (Open drain)
SMBus or I2C serial clock interface. (Open drain)
SMBus or I2C bi-directional serial data interface. (Open drain)
SMB_ALERT
SMB_CLK
SMB_DIO
I/O
3.3-V power input. Bypass to GND with a ceramic capacitor with a value greater than or equal to 1
µF. Used to power all digital logic circuits.
V3P3
39
P
Input voltage sensing for on-time control and telemetry. Serves as the negative terminal connecting to
the input current sensing shunt. When input current sensing is not used, short VIN_CSNIN to CSPIN
and connect to the converter input voltage (example: 12 V).
VIN_CSNIN
38
P
VR fault indicator. (Open-drain). The failures include the high-side FETs short, over-voltage, over-
temperature, and the input over-current conditions. Use the fault signal on the platform to remove the
power source by turning off the AC power supply. When the failure occurs, the VR_FAULT pin is
LOW, and put the controller into latch-off mode. One NVM bit is used to select whether or not the
faults from channel B asserts the VR_FAULT. pin.
VR_FAULT
VREF
33
O
O
1.7-V LDO reference voltage. Bypass to GND with 1-µF ceramic capacitor. Connect the VREF pin to
the REFIN pin of the TI smart power stages as the current sense common-mode voltage.
40
14
VR_HOT
O
G
Active low external temperature indicator.
Thermal Pad
Analog ground pad. Connect to GND plan with vias.
4
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
Table 1. Current Sense Inputs for Active Phases
Active
Phase
Channel
ACSP1
ACSP2
ACSP3
ACSP4
ACSP5
ACSP6
BSCP1
BSCP2
A
1
B
0
1
1
1
1
0
1
2
2
3
AIOUT1
AIOUT1
AIOUT1
AIOUT1
AIOUT1
AIOUT1
AIOUT1
AIOUT1
AIOUT1
AIOUT1
V3P3
n/a
n/a
n/a
n/a
n/a
GND
V3P3
V3P3
2
AIOUT2
AIOUT2
AIOUT2
AIOUT2
AIOUT2
AIOUT2
AIOUT2
AIOUT2
AIOUT2
V3P3
n/a
n/a
BIOUT1
BIOUT1
BIOUT1
BIOUT1
GND
3
AIOUT3
AIOUT3
AIOUT3
AIOUT3
AIOUT3
AIOUT3
AIOUT3
AIOUT3
V3P3
n/a
n/a
V3P3
4
AIOUT4
AIOUT4
AIOUT4
AIOUT4
AIOUT4
AIOUT4
AIOUT4
V3P3
n/a
V3P3
5
AIOUT5
AIOUT5
AIOUT5
AIOUT5
AIOUT5
AIOUT5
V3P3
AIOUT6
AIOUT6
AIOUT6
V3P3
BIOUT3
V3P3
6
6(1)
V3P3
BIOUT1
BIOUT1
BIOUT1
BIOUT1
V3P3
6
BIOUT2
BIOUT2
BIOUT2
5
5(1)
(1) For n+1 or n+3 applications, the NVM setting must be changed. See also the Phase Configuration for
Channel B section.
Copyright © 2017–2019, Texas Instruments Incorporated
5
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
CSPIN, VIN_CSNIN
–0.3
19
V
ACSP1, ACSP2, ACSP3, ACSP4, ACSP5, ACSP6/BCSP3, ADDR, ATSEN,
AVR_EN, AVSP, BCSP1, BCSP2, BTSEN, BVR_EN, BVSP, RESET, SMB_CLK,
SMB_DIO, V3P3
(1) (2)
Input voltage
–0.3
3.6
V
AGND, AVSN, BVSN
–0.3
–0.3
0.3
3.6
V
V
APWM1, APWM2, APWM3, APWM4, APWM5, APWM6/BPWM3, BPWM2,
AVR_RDY, BPWM1, BVR_RDY, SMB_ALERT, VREF, VR_FAULT, VR_HOT
(1) (2)
Output voltage
Operating junction temperature, TJ
Storage temperature, TSTG
–40
–55
150
150
°C
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal GND unless otherwise noted.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±3000
Electrostatic
discharge
V(ESD)
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
4.5
NOM
12
MAX
17
UNIT
CSPIN, VIN_CSNIN
V3P3
2.97
3.3
3.5
ACSP1, ACSP2, ACSP3, ACSP4, ACSP5, ACSP6/BSCP3, ADDR,
ATSEN, AVR_EN, AVSP, BCSP1, BCSP2, BTSEN, BVR_EN, BVSP,
RESET, SMB_CLK, SMB_DIO, V3P3
Input voltage
V
–0.1
3.5
AGND, AVSN, BVSN
VREF
–0.1
–0.1
0.1
1.72
APWM1, APWM2, APWM3, APWM4, APWM5, APWM6/BPWM3,
BPWM2, AVR_RDY, BPWM1, BVR_RDY, SMB_ALERT, VREF,
VR_FAULT, VR_HOT
Output voltage
V
–0.1
–40
3.5
Ambient temperature, TA
125
°C
6
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
6.4 Thermal Information
TPS53681
THERMAL METRIC(1)
RSB (WQFN)
UNIT
40 PINS
34.1
16.6
5.8
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
5.7
RθJC(bot)
0.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Supply: Currents, UVLO, and Power-On Reset
VVIN_CSNIN = 12.0 V, VV3P3 = 3.3 V, VAVSN = GND, VBVSN = GND, VAVSP = VOUTA, VBVSP = VOUTB (Unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply: Currents, UVLO, and Power-On Reset
VDAC < VSP < VDAC + 100m V, ENABLE =
'HI '
IV3P3
V3P3 supply current
13
9
18
mA
IV3P3SBY
V3NORMAL
V3UVLOH
V3UVLOL
V3P3 standby current
V3P3 normal range
ENABLE = 'LO '
Normal operation
13.5
3.5
mA
V
2.97
2.85
2.65
3.75
5
V3P3 UVLO 'OK ' threshold Ramp up
V3P3 UVLO fault threshold Ramp down
2.95
2.75
4.25
5.5
V
V
VIN_ON = 0xF010
4
5.25
6.25
7.25
8.25
9.25
10.25
11.25
invalid
4.25
5.5
V
VIN_ON = 0xF015
V
VIN_ON = 0xF019
6
6.5
V
VIN_ON = 0xF01D
7
7.5
V
V12ON
V12 UVLO 'OK ' threshold
VIN_ON = 0xF021
8
8.5
V
VIN_ON = 0xF025
9
9.5
V
VIN_ON = 0xF029
10
11
10.5
11.5
V
VIN_ON = 0xF02D
V
VIN_ON = others
VIN_UV_FAULT_LIMIT = 0xF011
VIN_UV_FAULT_LIMIT = 0xF80B
VIN_UV_FAULT_LIMIT = 0xF80D
VIN_UV_FAULT_LIMIT = 0xF80F
VIN_UV_FAULT_LIMIT = 0xF811
VIN_UV_FAULT_LIMIT = 0xF813
VIN_UV_FAULT_LIMIT = 0xF815
VIN_UV_FAULT_LIMIT = 0xF817
VIN_UV_FAULT_LIMIT = others
4
5.25
4.48
5.78
6.78
7.78
8.78
9.78
10.78
11.8
V
V
V
V
V
V
V
V
6.25
6.5
7.25
7.5
V12UVF
V12 UVLO fault threshold
8.25
8.5
9.25
9.5
10.25
11.25
10.5
11.5
invalid
Copyright © 2017–2019, Texas Instruments Incorporated
7
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
6.6 References: DAC and VREF
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
10
5
MAX
UNIT
mV
10 mV DAC: Change VID0 HI to LO to HI
5 mV DAC: Change VID0 HI to LO to HI
VVIDSTP
VDAC0
VID step size
mV
10 mV DAC : 0.50 ≤ VVSP ≤ 0.99 V,
ICORE = 0 A
VSP tolerance
VSP tolerance
VSP tolerance
VSP tolerance
–10
–8
10
8
mV
mV
mV
%
5 mV DAC: 0.25 ≤ VVSP ≤ 0.795 V,
ICORE = 0 A
VDAC1
VDAC2
VDAC3
10 mV DAC: 1.00 V ≤ VVSP ≤ 1.49 V,
ICORE = 0 A
5 mV DAC: 0.8 ≤ VVSP ≤ 0.995 V,
ICORE = 0 A
–5
5
5mV DAC: 1.00V ≤ VSP ≤ 1.52 V,
ICORE = 0 A
–0.5
0.5
10 mV DAC: 1.50 V ≤ VVSP ≤ 2.50 V,
ICORE = 0 A
VVREF
VREF output deeper sleep
VREF output source
VREF output sink
2.97V ≤ VV3P3 ≤ 3.5 V, IVREF = 0 A
0 A ≤ IVREF = 2 mA
1.692
–8
1.7
1.708
8
V
VVREFSRC
VVREFSNK
mV
mV
–2 mA ≤ IVREF = 0 A
VOUT_SCALE_LOOP = 0xe809,
VOUT_SCALE_MONITOR = 0xe809
1.125
1
KRATIO
Voltage divider ratio
VOUT offset LSB
VOUT_SCALE_LOOP = 0xe808,
VOUT_SCALE_MONITOR = 0xe808
VOUT_TRIML
MFR_SPECIFIC_05 = 0x01
MFR_SPECIFIC_05 = 0x1F
MFR_SPECIFIC_05 = 0xA0
MFR_SPECIFIC_05 = 0x5F
MFR_SPECIFIC_05 = 0xE0
0
37.5
1.25
38.75
–40
2.5
40
mV
mV
–43.25
56.25
–63
–37.75
61.25
–57
VOUT_TRIMR
VOUT offset range
58.75
–60
6.7 Voltage Sense: AVSP and BVSP, AVSN and BVSN
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Not in Fault, Disable or UVLO; VVSP = VVDAC
= 2.3 V, VVSN = 0 V
IAVSP
IAVSN
IBVSP
IBVSN
AVSP input bias current
75
µA
Not in Fault, Disable or UVLO; VVSP = VVDAC
= 2.3 V, VVSN = 0 V
AVSN input bias current
BVSP input bias current
BVSN input bias current
–75
µA
µA
µA
Not in Fault, Disable or UVLO; VVSP = VVDAC
= 1.0 V, VVSN = 0 V
75
Not in Fault, Disable or UVLO; VVSP = VVDAC
= 1.0 V, VVSN = 0 V
–75
8
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
6.8 Telemetry
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
5 mV DAC : 0.25 V ≤ VVSP ≤ 1.52 V
10 mV DAC: 0.5 ≤ VVSP ≤ 2.4 V
VREAD_VOUT MFR_READ_VOUT Accuracy
–12
12
mV
VREAD_VIN
READ_VIN Accuracy
4.50 V ≤ VIN ≤ 17 V
–2.25%
–7.3%
–4.2%
–3.1%
–2.5%
–2.3%
–2%
2.25%
7.3%
4.2%
3.1%
2.5%
2.3%
2%
6-phase, ICC(max) = 228 A, IOUT = 22.8 A
6-phase, ICC(max) = 228 A, IOUT = 45.6 A
6-phase, ICC(max) = 228 A, IOUT = 68.4 A
6-phase, ICC(max) = 228 A, IOUT = 91.2 A
6-phase, ICC(max) = 228 A, IOUT = 114 A
6-phase, ICC(max) = 228 A, IOUT = 136.8 A
6-phase, ICC(max) = 228 A, IOUT = 228 A
6-phase, ICC(max) = 228 A, IOUT = 255 A
5-phase, ICC(max) = 228 A, IOUT = 22.8 A
5-phase, ICC(max) = 228 A, IOUT = 45.6 A
5-phase, ICC(max) = 228 A, IOUT = 68.4 A
5-phase, ICC(max) = 228 A, IOUT = 91.2 A
5-phase, ICC(max) = 228 A, IOUT = 114 A
5-phase, ICC(max) = 228 A, IOUT = 136.8 A
5-phase, ICC(max) = 228 A, IOUT = 228 A
4-phase, ICC(max) = 200 A, IOUT = 20 A
4-phase, ICC(max) = 200 A, IOUT = 40 A
4-phase, ICC(max) = 200 A, IOUT = 60 A
4-phase, ICC(max) = 200 A, IOUT = 80 A
4-phase, ICC(max) = 200 A, IOUT = 100 A
4-phase, ICC(max) = 200 A, IOUT = 120 A
4-phase, ICC(max) = 200 A, IOUT = 200 A
3-phase, ICC(max) = 82 A, IOUT = 8.2 A
3-phase, ICC(max) = 82 A, IOUT = 16.4 A
3-phase, ICC(max) = 82 A, IOUT = 24.6 A
3-phase, ICC(max) = 82 A, IOUT = 32.8 A
3-phase, ICC(max) = 82 A, IOUT = 41 A
3-phase, ICC(max) = 82 A, IOUT = 49.2 A
3-phase, ICC(max) = 82 A, IOUT = 82 A
2-phase, ICC(max) = 82 A, IOUT = 8.2 A
2-phase, ICC(max) = 82 A, IOUT = 16.4 A
2-phase, ICC(max) = 82 A, IOUT = 24.6 A
2-phase, ICC(max) = 82 A, IOUT = 32.8 A
2-phase, ICC(max) = 82 A, IOUT = 41 A
2-phase, ICC(max) = 82 A, IOUT = 49.2 A
2-phase, ICC(max) = 82 A, IOUT = 82 A
0.28 V (–40°C) ≤ TSEN ≤ 1.8 V (150°C)
Digital current monitor
accuracy, Rail A (READ_IOUT)
IMON_ACC
–1.6%
–1.5%
–6.4%
–3.7%
–2.9%
–2.3%
–2.1%
–1.9%
–1.5%
–6.5%
–3.7%
–2.8%
–2.3%
–2.1%
–1.9%
–1.5%
–11.4%
–6.1%
–4.6%
–3.4%
–3%
1.6%
1.5%
6.4%
3.7%
2.9%
2.3%
2.1%
1.9%
1.5%
6.5%
3.7%
2.8%
2.3%
2.1%
1.9%
1.5%
11.4%
6.1%
4.6%
3.4%
3%
Digital current monitor
accuracy, Rail A (READ_IOUT)
IMON_ACC
IMON_ACC
IMON_ACC
Digital current monitor
accuracy, Rail A (READ_IOUT)
Digital current monitor
accuracy, Rail B (READ_IOUT)
–2.8%
–2%
2.8%
2%
–8.7%
–4.7%
–3.7%
–2.7%
–2.5%
–2.4%
–1.8%
–2
8.7%
4.7%
3.7%
2.7%
2.5%
2.4%
1.8%
2
Digital current monitor
accuracy, Rail B (READ_IOUT)
IMON_ACC
Temp
READ_TEMP1
0
°C
Copyright © 2017–2019, Texas Instruments Incorporated
9
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
6.9 Input Current Sensing
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(VCSPIN – VCSNIN) = 2.5 mV, IIN = 5 A,
RSENSE = 0.5 mΩ
–10%
10%
6%
(VCSPIN – VCSNIN) = 5 mV, IIN = 10 A,
RSENSE = 0.5 mΩ
IIN
READ_IIN accuracy
–6%
–3%
(VCSPIN – VCSNIN) = 15 mV, IIN = 30 A,
RSENSE = 0.5 mΩ
3%
10
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
6.10 Programmable Loadline Settings
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOUT_DROOP = 0xD000
VOUT_DROOP = 0xD008
VOUT_DROOP = 0xD010
VOUT_DROOP = 0xD014
VOUT_DROOP = 0xD018
VOUT_DROOP = 0xD01C
VOUT_DROOP = 0xD020
VOUT_DROOP = 0xD024
VOUT_DROOP = 0xD028
VOUT_DROOP = 0xD030
VOUT_DROOP = 0xD033
VOUT_DROOP = 0xD034
VOUT_DROOP = 0xD035
VOUT_DROOP = 0xD036
VOUT_DROOP = 0xD037
VOUT_DROOP = 0xD038
VOUT_DROOP = 0xD039
VOUT_DROOP = 0xD03A
VOUT_DROOP = 0xD03B
VOUT_DROOP = 0xD03C
VOUT_DROOP = 0xD03D
VOUT_DROOP = 0xD03E
VOUT_DROOP = 0xD03F
VOUT_DROOP = 0xD040
VOUT_DROOP = 0xD041
VOUT_DROOP = 0xD042
VOUT_DROOP = 0xD043
VOUT_DROOP = 0xD044
VOUT_DROOP = 0xD048
VOUT_DROOP = 0xD050
VOUT_DROOP = 0xD058
VOUT_DROOP = 0xD060
VOUT_DROOP = 0xD068
VOUT_DROOP = 0xD070
VOUT_DROOP = 0xD078
VOUT_DROOP = 0xD07C
VOUT_DROOP = 0xD080
VOUT_DROOP = 0xD084
VOUT_DROOP = 0xD088
VOUT_DROOP = 0xD08C
VOUT_DROOP = 0xD090
VOUT_DROOP = 0xD098
VOUT_DROOP = 0xD09B
VOUT_DROOP = 0xD09C
MIN
TYP
0
MAX
UNIT
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
0.1125
0.2412
0.3031
0.3637
0.4265
0.4875
0.5484
0.6093
0.6855
0.7769
0.7921
0.8073
0.8227
0.8379
0.8531
0.8683
0.8836
0.8988
0.9140
0.9292
0.9445
0.9597
0.975
0.125
0.25
0.1395
0.2587
0.3218
0.3872
0.4484
0.5125
0.5765
0.6406
0.7207
0.8168
0.8328
0.8488
0.8648
0.8808
0.8968
0.9128
0.9289
0.9449
0.9609
0.9769
0.9930
1.0090
1.025
0.3125
0.375
0.4375
0.5
0.5625
0.625
0.7031
0.7969
0.8125
0.8281
0.8438
0.8594
0.875
0.8906
0.9063
0.9219
0.9375
0.9531
0.9688
0.9844
1
DC loadline settings for
Channel A
DCLLChannel A
0.9902
1.0055
1.0207
1.0359
1.0968
1.2187
1.3406
1.4625
1.5843
1.7062
1.8281
1.8890
1.95
1.0156
1.0313
1.0469
1.0625
1.125
1.25
1.0409
1.0570
1.0730
1.0890
1.1531
1.2812
1.4093
1.5375
1.6656
1.7937
1.9218
1.9859
2.05
1.375
1.5
1.625
1.75
1.875
1.9375
2
2.0109
2.0718
2.1328
2.1937
2.2698
2.3612
2.3765
2.0625
2.125
2.1875
2.25
2.1141
2.1781
2.2421
2.3062
2.3862
2.4823
2.4984
2.328
2.4218
2.4375
Copyright © 2017–2019, Texas Instruments Incorporated
11
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
Programmable Loadline Settings (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOUT_DROOP = 0xD09D
VOUT_DROOP = 0xD09E
VOUT_DROOP = 0xD09F
VOUT_DROOP = 0xD0A0
VOUT_DROOP = 0xD0A1
VOUT_DROOP = 0xD0A2
VOUT_DROOP = 0xD0A3
VOUT_DROOP = 0xD0A4
VOUT_DROOP = 0xD0A5
VOUT_DROOP = 0xD0A6
VOUT_DROOP = 0xD0A7
VOUT_DROOP = 0xD0A8
VOUT_DROOP = 0xD0A9
VOUT_DROOP = 0xD0AA
VOUT_DROOP = 0xD0AB
VOUT_DROOP = 0xD0AC
VOUT_DROOP = 0xD0B0
VOUT_DROOP = 0xD0B8
VOUT_DROOP = 0xD0C0
VOUT_DROOP = 0xD0C8
VOUT_DROOP = 0xD000
VOUT_DROOP = 0xD008
VOUT_DROOP = 0xD010
VOUT_DROOP = 0xD014
VOUT_DROOP = 0xD018
VOUT_DROOP = 0xD01C
VOUT_DROOP = 0xD020
VOUT_DROOP = 0xD024
VOUT_DROOP = 0xD028
VOUT_DROOP = 0xD030
VOUT_DROOP = 0xD033
VOUT_DROOP = 0xD034
VOUT_DROOP = 0xD035
VOUT_DROOP = 0xD036
VOUT_DROOP = 0xD037
VOUT_DROOP = 0xD038
MIN
2.3917
2.4069
2.4221
2.4375
2.4527
2.4679
2.4831
2.4984
2.5136
2.5288
2.5437
2.5593
2.5745
2.5897
2.6050
2.6203
2.6812
2.8031
2.925
TYP
2.4531
2.4687
2.4843
2.5
MAX
UNIT
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
2.5144
2.5304
2.5464
2.5625
2.5784
2.5944
2.6104
2.6265
2.6425
2.6585
2.6742
2.6906
2.7066
2.7226
2.7385
2.7546
2.8187
2.9468
3.075
2.5156
2.5312
2.5468
2.5625
2.5781
2.5937
2.609
2.625
2.6406
2.6562
2.6718
2.6875
2.75
DC loadline settings for
Channel A
DCLLChannel A
2.875
3
3.0468
3.125
0
3.2031
0.1125
0.2355
0.297
0.125
0.25
0.1395
0.2625
0.3234
0.395
0.3125
0.375
0.4375
0.5
0.3637
0.4244
0.4875
0.5464
0.6093
0.6855
0.7769
0.7921
0.8073
0.8227
0.8379
0.8531
0.454
0.517
0.5625
0.625
0.7031
0.7969
0.8125
0.8281
0.8438
0.8594
0.875
0.5786
0.648
DC Loadline settings for
Channel B
DCLLChannel B
0.7207
0.8168
0.8335
0.852
0.8648
0.8815
0.8968
12
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
Programmable Loadline Settings (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MFR_SPECIFIC_07 = 0x00
MFR_SPECIFIC_07 = 0x01
MFR_SPECIFIC_07 = 0x02
MFR_SPECIFIC_07 = 0x03
MFR_SPECIFIC_07 = 0x04
MFR_SPECIFIC_07 = 0x05
MFR_SPECIFIC_07 = 0x06
MFR_SPECIFIC_07 = 0x07
MFR_SPECIFIC_07 = 0x08
MFR_SPECIFIC_07 = 0x09
MFR_SPECIFIC_07 = 0x0A
MFR_SPECIFIC_07 = 0x0B
MFR_SPECIFIC_07 = 0x0C
MFR_SPECIFIC_07 = 0x0D
MFR_SPECIFIC_07 = 0x0E
MFR_SPECIFIC_07 = 0x0F
MFR_SPECIFIC_07 = 0x10
MFR_SPECIFIC_07 = 0x11
MFR_SPECIFIC_07 = 0x12
MFR_SPECIFIC_07 = 0x13
MFR_SPECIFIC_07 = 0x14
MFR_SPECIFIC_07 = 0x15
MFR_SPECIFIC_07 = 0x16
MFR_SPECIFIC_07 = 0x17
MFR_SPECIFIC_07 = 0x18
MFR_SPECIFIC_07 = 0x19
MFR_SPECIFIC_07 = 0x1A
MFR_SPECIFIC_07 = 0x1B
MFR_SPECIFIC_07 = 0x1C
MFR_SPECIFIC_07 = 0x1D
MFR_SPECIFIC_07 = 0x1E
MFR_SPECIFIC_07 = 0x1F
MFR_SPECIFIC_07 = 0x20
MFR_SPECIFIC_07 = 0x21
MFR_SPECIFIC_07 = 0x22
MFR_SPECIFIC_07 = 0x23
MFR_SPECIFIC_07 = 0x24
MFR_SPECIFIC_07 = 0x25
MFR_SPECIFIC_07 = 0x26
MFR_SPECIFIC_07 = 0x27
MFR_SPECIFIC_07 = 0x28
MFR_SPECIFIC_07 = 0x29
MFR_SPECIFIC_07 = 0x2A
MFR_SPECIFIC_07 = 0x2B
MIN
TYP
0
MAX
UNIT
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
0.1125
0.2412
0.3031
0.3637
0.4265
0.4875
0.5484
0.6093
0.7312
0.7769
0.7921
0.8073
0.8227
0.8379
0.8531
0.8683
0.8836
0.8988
0.9140
0.9292
0.9445
0.9597
0.975
0.125
0.25
0.1395
0.2587
0.3218
0.3862
0.4484
0.5125
0.5765
0.6406
0.7687
0.8168
0.8328
0.8488
0.8648
0.8808
0.8968
0.9128
0.9289
0.9449
0.9609
0.9769
0.9930
1.0090
1.025
0.3125
0.375
0.4375
0.5
0.5625
0.625
0.75
0.7969
0.8125
0.8281
0.8438
0.8594
0.875
0.8906
0.9063
0.9219
0.9375
0.9531
0.9688
0.9844
1
AC Loadline settings for
both Channel A and
Channel B(1)
ACLL
0.9902
1.0055
1.0207
1.0359
1.0968
1.2187
1.3406
1.4625
1.5843
1.7062
1.8281
1.8890
1.95
1.0156
1.0313
1.0469
1.0625
1.125
1.25
1.0409
1.0570
1.0730
1.0890
1.1531
1.2812
1.4093
1.5375
1.6656
1.7937
1.9218
1.9859
2.05
1.375
1.5
1.625
1.75
1.875
1.9375
2
2.0109
2.0718
2.1328
2.1937
2.3156
2.3612
2.3765
2.0625
2.125
2.1875
2.25
2.1140
2.1781
2.2421
2.3062
2.4343
2.4823
2.4984
2.375
2.4218
2.4375
(1) Specified by design. Not production tested.
Copyright © 2017–2019, Texas Instruments Incorporated
13
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
Programmable Loadline Settings (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MFR_SPECIFIC_07 = 0x2C
MFR_SPECIFIC_07 = 0x2D
MFR_SPECIFIC_07 = 0x2E
MFR_SPECIFIC_07 = 0x2F
MFR_SPECIFIC_07 = 0x30
MFR_SPECIFIC_07 = 0x31
MFR_SPECIFIC_07 = 0x32
MFR_SPECIFIC_07 = 0x33
MFR_SPECIFIC_07 = 0x34
MFR_SPECIFIC_07 = 0x35
MFR_SPECIFIC_07 = 0x36
MFR_SPECIFIC_07 = 0x37
MFR_SPECIFIC_07 = 0x38
MFR_SPECIFIC_07 = 0x39
MFR_SPECIFIC_07 = 0x3A
MFR_SPECIFIC_07 = 0x3B
MFR_SPECIFIC_07 = 0x3C
MFR_SPECIFIC_07 = 0x3D
MFR_SPECIFIC_07 = 0x3E
MFR_SPECIFIC_07 = 0x3F
MFR_SPEC_7<11:8> = 0000b
MFR_SPEC_7<11:8> = 0001b
MFR_SPEC_7<11:8> = 0010b
MFR_SPEC_7<11:8> = 0011b
MFR_SPEC_7<11:8> = 0100b
MFR_SPEC_7<11:8> = 0101b
MFR_SPEC_7<11:8> = 0110b
MFR_SPEC_7<11:8> = 0111b
MFR_SPEC_7<11:8> = 1000b
MFR_SPEC_7<11:8> = 1001b
MFR_SPEC_7<11:8> = 1010b
MFR_SPEC_7<11:8> = 1011b
MFR_SPEC_7<11:8> = 1100b
MFR_SPEC_7<11:8> = 1101b
MFR_SPEC_7<11:8> = 1110b
MFR_SPEC_7<11:8> = 1111b
MIN
2.3917
2.4069
2.4221
2.4375
2.4527
2.4679
2.4831
2.4984
2.5136
2.5288
2.5437
2.5593
2.5745
2.5897
2.6050
2.6203
2.6812
2.8031
2.925
TYP
2.4531
2.4687
2.4843
2.5
MAX
UNIT
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
µs
2.5144
2.5304
2.5464
2.5625
2.5784
2.5944
2.6104
2.6265
2.6425
2.6585
2.6742
2.6906
2.7066
2.7226
2.7385
2.7546
2.8187
2.9468
3.075
2.5156
2.5312
2.5468
2.5625
2.5781
2.5937
2.609
2.625
2.6406
2.6562
2.6718
2.6875
2.75
2.875
3
AC Loadline settings for
both Channel A and
Channel B(1)
ACLL
3.0468
3.125
5
3.2031
10
µs
15
µs
20
µs
25
µs
30
µs
35
µs
40
µs
tINT
Integration time constant(1)
1
µs
2
µs
3
µs
4
µs
5
µs
6
µs
7
µs
8
µs
14
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
6.11 Current Sense and Calibration
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
0
TYP
MAX UNIT
IACSP1
IACSP2
IACSP3
IACSP4
IACSP5
IACSP6
IBCSP1
IBCSP2
ACSP1 leakage current
ACSP2 leakage current
ACSP3 leakage current
ACSP4 leakage current
ACSP5 leakage current
ACSP6 leakage current
BCSP1 leakage current
BCSP2 leakage current
VACSP1 = 2.5 V
VACSP2 = 2.5 V
VACSP3 = 2.5 V
VACSP4 = 2.5 V
VACSP5 = 2.5 V
VACSP6 = 2.5 V
VBCSP1 = 2.5 V
VBCSP2 = 2.5 V
20
20
20
20
20
20
20
20
µA
µA
µA
µA
µA
µA
µA
µA
0
0
0
0
0
0
0
Current monitor calibration offset IOUT_CAL_OFFSET resolution (per-
IMON_CAL_OF1
0.125
1
A
A
A
A
LSB (per-phase)(1)
phase)
IOUT_CAL_OFFSET = 0xE808 (per-
phase)
Current monitor calibration offset
range (per-phase)
IMON_CAL_OF2
IOUT_CAL_OFFSET = 0xEFF9 (per-
phase)
–0.875
0.25
Current monitor calibration offset
LSB (total)(1)
IMON_CAL_OF3
IOUT_CAL_OFFSET resolution (total)
IOUT_CAL_OFFSET = 0xE820 (total)
IOUT_CAL_OFFSET = 0xEFE2 (total)
4
A
A
Current monitor calibration offset
range (total)
IMON_CAL_OF4
–3.75
Current monitor calibration gain
LSB(1)
IMON_CAL_GA_LSB
IMON_CAL_GA_RNG
IOUT_CAL_GAIN resolution
0.3125%
IOUT_CAL_GAIN = 0xD131
IOUT_CAL_GAIN = 0xD150
4.7656
5.25
mΩ
mΩ
Current monitor calibration gain
range
(1) Specified by design. Not production tested.
6.12 Logic Interface Pins: AVR_EN, AVR_RDY, BVR_EN, BVR_RDY, RESET, VR_FAULT,
VR_HOT
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Open-drain pulldown
resistance
RRPGDL
VAVR_RDY = VBVR_RDY = VVR_FAULT = 0.45 V
36
50
Ω
SDIO, VR_HOT, AVR_RDY, BVR_RDY,
VR_FAULT, Hi Z Leakage, apply to 3.3-V
supply in off state
IVRTTLK
Open-drain leakage current
–2
0.2
2
µA
VAENL
Channel A ENABLE logic low
Channel A ENABLE logic high
Channel A ENABLE hysteresis
Channel A ENABLE deglitch(1)
Channel A I/O 1.1-V leakage
Channel B ENABLE logic low
Channel B ENABLE logic high
Channel B ENABLE hysteresis
Channel B ENABLE deglitch(1)
0.7
V
V
VAENH
VAENHYS
tAENDIG
IAENH
0.8
0.028
0.2
0.05
0.07
V
µs
µA
V
VAVR_EN = 1.1 V
25
VBENL
0.7
VBENH
VBENHYS
tBENDIG
0.8
0.028
0.2
V
0.05
0.07
1.5
V
µs
Channel A ENABLE low to
AVR_RDY low
tAENVRRDYF
From AVR_EN low to AVR_RDY low
VBENH = 1.1 V
µs
IBENH
Channel B I/O 1.1-V leakage
25
µA
V
VRSTL
VRSTH
tRSTTDLY
RESET logic low
0.8
RESET logic high(1)
RESET delay time
1.09
V
1
µs
(1) Specified by design. Not production tested.
Copyright © 2017–2019, Texas Instruments Incorporated
15
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
6.13 I/O Timing
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VVBOOT > 0 V, no faults, CREF = 1 µF,
TON_DELAY = 0xB1EC (PAGE 0)
0.38
0.48
0.58
ms
TON_DELAY = 0xB396 (PAGE 0)
TON_DELAY = 0xBAD1 (PAGE 0)
TON_DELAY = 0xC26E (PAGE 0)
TON_DELAY = others
0.8
1.308
2.28
0.9
1.408
2.432
Invalid
1
1.508
2.584
ms
ms
ms
tSTARTUPA Channel A startup time(1)
VVBOOT > 0 V, no faults, CREF = 1 µF,
TON_DELAY = 0xB1EC (PAGE 1)
0.38
0.48
0.58
ms
TON_DELAY = 0xB396 (PAGE 1)
TON_DELAY = 0xBAD1 (PAGE 1)
TON_DELAY = 0xC26E (PAGE 1)
TON_DELAY = others
0.8
1.308
2.28
0.9
1.408
2.432
Invalid
1
1.508
2.584
ms
ms
ms
tSTARTUPB Channel B startup time(2)
ACK of SetVID_x command to start of voltage
ramp
(3)
tVCCVID
VID change to VSP change
500
ns
tVRTDGLT VR_HOT update time
Temperature data update time
MFR_SPEC_09<8:6> = 000b
MFR_SPEC_09<8:6> = 001b
MFR_SPEC_09<8:6> = 010b
MFR_SPEC_09<8:6> = 011b
MFR_SPEC_09<8:6> = 100b
MFR_SPEC_09<8:6> = 101b
MFR_SPEC_09<8:6> = 110b
MFR_SPEC_09<8:6> = 111b
0.3
72
0.5
92
ms
ns
ns
ns
ns
ns
ns
ns
ns
53
58
66
70
78
82
88
91
78
98
86
108
114
125
132
139
145
92
(3)
tON_BLANK Rising-edge blanking time
100
108
114
120
(1) Time from AVR_EN to output voltage ramp up to target voltage.
(2) Time from AVR_EN or BVR_EN to output voltage ramp up to target voltage.
(3) Specified by design. Not production tested.
16
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
6.14 PMBus Address Setting
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ADDR ≤ 0.039 V
MIN
TYP MAX
1011000 (B0h)
UNIT
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
Bin
V
VADDR = 0.073 V with ±15 mV tolerance
VADDR = 0.122 V with ±15 mV tolerance
VADDR = 0.171 V with ±15 mV tolerance
VADDR = 0.219 V with ±15 mV tolerance
VADDR = 0.268 V with ±15 mV tolerance
VADDR = 0.317 V with ±15 mV tolerance
VADDR = 0.366 V with ±15 mV tolerance
VADDR = 0.415 V with ±15 mV tolerance
VADDR = 0.464 V with ±15 mV tolerance
VADDR = 0.513 V with ±15 mV tolerance
VADDR = 0.562 V with ±15 mV tolerance
VADDR = 0.610 V with ±15 mV tolerance
VADDR = 0.660 V with ±15 mV tolerance
VADDR = 0.708 V with ±15 mV tolerance
VADDR = 0.757 V with ±15 mV tolerance
VADDR = 0.806 V with ±15 mV tolerance
VADDR = 0.854 V with ±15 mV tolerance
VADDR = 0.903 V with ±15 mV tolerance
VADDR = 0.952 V with ±15 mV tolerance
VADDR = 1.000 V with ±15 mV tolerance
VADDR = 1.050 V with ±15 mV tolerance
VADDR = 1.098 V with ±15 mV tolerance
VADDR = 1.147 V with ±15 mV tolerance
VADDR = 1.196 V with ±15 mV tolerance
VADDR = 1.245 V with ±15 mV tolerance
VADDR = 1.294 V with ±15 mV tolerance
VADDR = 1.343 V with ±15 mV tolerance
VADDR = 1.392 V with ±15 mV tolerance
VADDR = 1.440 V with ±15 mV tolerance
VADDR = 1.489 V with ±15 mV tolerance
VADDR = 1.540 V with ±15 mV tolerance
1011001 (B2h)
1011010 (B4h)
1011011 (B6h)
1011100 (B8h)
1011101 (BAh)
1011110 (BCh)
1011111 (BEh)
1100000 (C0h)
1100001 (C2h)
1100010 (C4h)
1100011 (C6h)
1100100 (C8h)
1100101 (CAh)
1100110 (CCh)
1100111 (CEh)
1101000 (D0h)
1101001 (D2h)
1101010 (D4h)
1101011 (D6h)
1101100 (D8h)
1101101 (DAh)
1101110 (DCh)
1101111 (DEh)
1110000 (E0h)
1110001 (E2h)
1110010 (E4h)
1110011 (E6h)
1110100 (E8h)
1110101 (EAh)
1110110 (ECh)
1110111 (EEh)
PMBus address bits (7-bit
format)
PADDR
Copyright © 2017–2019, Texas Instruments Incorporated
17
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
6.15 Overcurrent Limit Thresholds
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
12.5
16.5
20.5
24.5
28.5
32.5
36.5
40.5
44.5
48.5
52.5
56.5
60.5
64.5
68.5
72.5
12
TYP
14.5
18.5
22.5
26.5
30.5
34.5
38.5
42.5
46.5
50.5
54.5
58.5
62.5
66.5
70.5
74.5
14
MAX
UNIT
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
MFR_SPEC_00<3:0>, (PAGE0) = 0000b
MFR_SPEC_00<3:0>, (PAGE0) = 0001b
MFR_SPEC_00<3:0>, (PAGE0) = 0010b
MFR_SPEC_00<3:0>, (PAGE0) = 0011b
MFR_SPEC_00<3:0>, (PAGE0) = 0100b
MFR_SPEC_00<3:0>, (PAGE0) = 0101b
MFR_SPEC_00<3:0>, (PAGE0) = 0110b
MFR_SPEC_00<3:0>, (PAGE0) = 0111b
MFR_SPEC_00<3:0>, (PAGE0) = 1000b
MFR_SPEC_00<3:0>, (PAGE0) = 1001b
MFR_SPEC_00<3:0>, (PAGE0) = 1010b
MFR_SPEC_00<3:0>, (PAGE0) = 1011b
MFR_SPEC_00<3:0>, (PAGE0) = 1100b
MFR_SPEC_00<3:0>, (PAGE0) = 1101b
MFR_SPEC_00<3:0>, (PAGE0) = 1110b
MFR_SPEC_00<3:0>, (PAGE0) = 1111b
MFR_SPEC_00<3:0>, (PAGE1) = 0000b
MFR_SPEC_00<3:0>, (PAGE1) = 0001b
MFR_SPEC_00<3:0>, (PAGE1) = 0010b
MFR_SPEC_00<3:0>, (PAGE1) = 0011b
MFR_SPEC_00<3:0>, (PAGE1) = 0100b
MFR_SPEC_00<3:0>, (PAGE1) = 0101b
MFR_SPEC_00<3:0>, (PAGE1) = 0110b
MFR_SPEC_00<3:0>, (PAGE1) = 0111b
MFR_SPEC_00<3:0>, (PAGE1) = 1000b
MFR_SPEC_00<3:0>, (PAGE1) = 1001b
MFR_SPEC_00<3:0>, (PAGE1) = 1010b
MFR_SPEC_00<3:0>, (PAGE1) = 1011b
MFR_SPEC_00<3:0>, (PAGE1) = 1100b
MFR_SPEC_00<3:0>, (PAGE1) = 1101b
MFR_SPEC_00<3:0>, (PAGE1) = 1110b
MFR_SPEC_00<3:0>, (PAGE1) = 1111b
16.5
20.5
24.5
28.5
32.5
36.5
40.5
44.5
48.5
52.5
56.5
60.5
64.5
68.5
72.5
76.5
16
Phase OCL levels for Channel A
(ACSPx-VREF), valley current
limit
IOCLAx
16
18
20
20
22
24
24
26
28
28
30
32
32
34
36
36
38
40
Phase OCL levels for Channel B
(BCSPx-VREF), valley current
limit
40
42
44
IOCLBx
44
46
48
48
50
52
52
54
56
56
58
60
60
62
64
64
66
68
68
70
72
72
74
76
18
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
6.16 Switching Frequency
VIN = 12 V, VAVSP = 1.0 V, VBVSP = 0.8 V, TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
270
315
360
405
450
500
540
585
630
675
720
765
810
855
900
TYP
300
MAX
330
385
440
495
550
600
660
715
770
825
880
935
990
1045
1100
UNIT
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
FREQUENCY_SWITCH = 0x012C
FREQUENCY_SWITCH = 0x015E
FREQUENCY_SWITCH = 0x0190
FREQUENCY_SWITCH = 0x01C2
FREQUENCY_SWITCH = 0x01F4
FREQUENCY_SWITCH = 0x0226
FREQUENCY_SWITCH = 0x0258
FREQUENCY_SWITCH = 0x028A
FREQUENCY_SWITCH = 0x02BC
FREQUENCY_SWITCH = 0x02EE
FREQUENCY_SWITCH = 0x0320
FREQUENCY_SWITCH = 0x0352
FREQUENCY_SWITCH = 0x0384
FREQUENCY_SWITCH = 0x03B6
FREQUENCY_SWITCH = 0x03E8
FREQUENCY_SWITCH = others
350
400
450
500
550
600
650
fSW
Switching frequency
700
750
800
850
900
950
1000
Invalid
6.17 Slew Rate Settings
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
6
MAX
7
UNIT
mV/µs
mV/µs
mV/µs
mV/µs
mV/µs
mV/µs
mV/µs
mV/µs
mV/µs
mV/µs
mV/µs
mV/µs
mV/µs
mV/µs
mV/µs
mV/µs
mV/µs
VOUT_TRANSITION_RATE = 0xE050
VOUT_TRANSITION_RATE = 0xE0A0
VOUT_TRANSITION_RATE = 0xE0F0
VOUT_TRANSITION_RATE = 0xE140
VOUT_TRANSITION_RATE = 0xE190
VOUT_TRANSITION_RATE = 0xE1E0
VOUT_TRANSITION_RATE = 0xE230
VOUT_TRANSITION_RATE = 0xE280
VOUT_TRANSITION_RATE = 0xE005
VOUT_TRANSITION_RATE = 0xE00A
VOUT_TRANSITION_RATE = 0xE00F
VOUT_TRANSITION_RATE = 0xE014
VOUT_TRANSITION_RATE = 0xE019
VOUT_TRANSITION_RATE = 0xE01E
VOUT_TRANSITION_RATE = 0xE023
VOUT_TRANSITION_RATE = 0xE028
VOUT_TRANSITION_RATE = others
5
10
12
18
24
30
36
42
48
14
15
20
25
30
35
40
SLSET Slew rate setting
0.3125
0.625
0.9375
1.25
1.5625
1.875
2.1875
2.5
Invalid data
SLSET
AVSP and BVSP slew rate
SetVID_Fast
SLF
mV/µs
SLSET / 4
SLSET / 2
SLSET / 4
SLSET / 16
mV/µs
mV/µs
mV/µs
mV/µs
SLS1
AVSP and BVSP slew rate slow
MFR_SPEC_13<8> = 0b
MFR_SPEC_13<8> = 1b
AVSP and BVSP slew rate slew
rate soft-start
SLSS
Copyright © 2017–2019, Texas Instruments Incorporated
19
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
6.18 Ramp Selections
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
30
TYP
40
MAX
UNIT
mV
mV
mV
mV
mV
mV
mV
mV
MFR_SPEC_14<2:0> = 000b
MFR_SPEC_14<2:0> = 001b
MFR_SPEC_14<2:0> = 010b
MFR_SPEC_14<2:0> = 011b
MFR_SPEC_14<2:0> = 100b
MFR_SPEC_14<2:0> = 101b
MFR_SPEC_14<2:0> = 110b
MFR_SPEC_14<2:0> = 111b
55
95
70
80
110
150
190
230
270
305
120
160
200
240
280
320
135
175
215
255
300
335
VRAMP
RAMP Setting
6.19 Dynamic Integration and Undershoot Reduction
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MFR_SPEC_12<10:8> = 000b;
MFR_SPEC_12<10:8> = 001b;
MFR_SPEC_12<10:8> = 010b;
MFR_SPEC_12<10:8> = 011b;
MFR_SPEC_12<10:8> = 100b;
MFR_SPEC_12<10:8> = 101b;
MFR_SPEC_12<10:8> = 110b;
MFR_SPEC_12<10:8> = 111b;
MFR_SPEC_12<7:4> = 0000b;
MFR_SPEC_12<7:4> = 0001b;
MFR_SPEC_12<7:4> = 0010b;
MFR_SPEC_12<7:4> = 0011b;
MFR_SPEC_12<7:4> = 0100b;
MFR_SPEC_12<7:4> = 0101b;
MFR_SPEC_12<7:4> = 0110b;
MFR_SPEC_12<7:4> = 0111b;
MFR_SPEC_12<7:4> = 1000b;
MFR_SPEC_12<7:4> = 1001b;
MFR_SPEC_12<7:4> = 1010b;
MFR_SPEC_12<7:4> = 1011b;
MFR_SPEC_12<7:4> = 1100b;
MFR_SPEC_12<7:4> = 1101b;
MFR_SPEC_12<7:4> = 1110b;
MFR_SPEC_12<7:4> = 1111b;
MFR_SPEC_09<14:12> = 000b;
MFR_SPEC_09<14:12> = 001b;
MFR_SPEC_09<14:12> = 010b;
MFR_SPEC_09<14:12> = 011b;
MFR_SPEC_09<14:12> = 100b;
MFR_SPEC_09<14:12> = 101b;
MFR_SPEC_09<14:12> = 110b;
MFR_SPEC_09<14:12> = 111b;
MIN
90
TYP
100
150
200
250
300
350
400
OFF
1
MAX
116
175
230
285
345
400
455
UNIT
mV
mV
mV
mV
mV
mV
mV
mV
µs
135
175
225
270
315
360
Dynamic integration voltage
setting
VDYN
2
µs
3
µs
4
µs
5
µs
6
µs
7
µs
8
µs
Dynamic integration time
constant(1)
tDINT
12
µs
13
µs
14
µs
15
µs
16
µs
17
µs
18
µs
19
µs
120
155
190
230
265
300
335
140
180
220
260
300
340
380
OFF
160
205
245
290
335
375
420
mV
mV
mV
mV
mV
mV
mV
mV
VUSR2
USR level 2 voltage setting
(1) Specified by design. Not production tested.
20
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
Dynamic Integration and Undershoot Reduction (continued)
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MFR_SPEC_09<2:0> = 000b;
MFR_SPEC_09<2:0> = 001b;
MFR_SPEC_09<2:0> = 010b;
MFR_SPEC_09<2:0> = 011b;
MFR_SPEC_09<2:0> = 100b;
MFR_SPEC_09<2:0> = 101b;
MFR_SPEC_09<2:0> = 110b;
MFR_SPEC_09<2:0> = 111b;
MFR_SPEC_09<5> = 0b;
MIN
70
TYP
90
MAX
110
140
170
205
240
270
305
UNIT
mV
100
130
160
185
215
240
120
150
180
210
240
270
OFF
3
mV
mV
mV
VUSR1
USR level 1 voltage setting
mV
mV
mV
mV
phases
phases
mV
Maximum phase added in USR
level 1(1)
PHUSR1
MFR_SPEC_09<5> = 1b;
4
MFR_SPEC_09<4:3> = 00b;
MFR_SPEC_09<4:3> = 01b;
MFR_SPEC_09<4:3> = 10b;
MFR_SPEC_09<4:3> = 11b;
2
5
5
9
15
20
25
10
mV
Dynamic integration/USR voltage
hysteresis
VOUSRHYS
10
15
15
mV
20
mV
6.20 Boot Voltage and TMAX Settings
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
90
MAX
UNIT
°C
°C
°C
°C
°C
°C
°C
°C
V
MFR_SPEC_12<2:0> = 000b
MFR_SPEC_12<2:0> = 001b
MFR_SPEC_12<2:0> = 010b
MFR_SPEC_12<2:0> = 011b
MFR_SPEC_12<2:0> = 100b
MFR_SPEC_12<2:0> = 101b
MFR_SPEC_12<2:0> = 110b
MFR_SPEC_12<2:0> = 111b
MFR_SPEC_11<7:0> = 00h
MFR_SPEC_11<7:0> = 74h
MFR_SPEC_11<7:0> = 79h
MFR_SPEC_11<7:0> = 7Eh
MFR_SPEC_11<7:0> = 00h
MFR_SPEC_11<7:0> = 83h
MFR_SPEC_11<7:0> = 97h
MFR_SPEC_11<7:0> = BFh
95
100
105
110
115
120
125
0
TMAX
Maximum temperature setting
1.65
1.7
1.75
0
V
BOOT voltage setting (10-mV
DAC)
V
V
VBOOT
V
0.9
1
V
BOOT voltage setting (5-mV
DAC)
V
1.2
V
Copyright © 2017–2019, Texas Instruments Incorporated
21
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
6.21 Protections: OVP and UVP
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Measured at the VSP pin wrt VID code.
Device latches OFF.
VRDYH5
VRDYH0
330
400
mV
Tracking OVP
Measured at the VSP pin wrt VID code.
Device latches OFF.
140
200
mV
tRDYDGLTO
tRDYDGLTU
VRDYL
VR_RDY deglitch time(1)
VR_RDY deglitch time(1)
Undervoltage protection(3)
(2)2.5
µs
µs
fSW = 500 kHz
4
(VVSP + VDROOP) with respect to VID
370
400
430
mV
Fixed overvoltage protection,
Channel A(3)
VAVSP > VOVP for 1 µs, ENABLE = HI or LO,
PWM to LO
VOVPA
VOVPB
2.75
2.8
1.9
2.86
V
V
Fixed overvoltage protection,
Channel B(3)
VBVSP > VOVP for 1 µs, ENABLE = HI or LO,
PWM to LO
1.85
1.95
(1) Specified by design. Not production tested.
(2) Time from VSP out of +200 or +400 mV VDAC boundary to VR_RDY low.
(3) Can be programmed with different configurations.
6.22 Protections: ATSEN and BTSEN Pin Voltage Levels and Fault
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VTSEN = 0.28 V
MIN
–42
23
TYP
–40
25
MAX
–38
27
UNIT
°C
VTSEN = 0.8 V
VTSEN = 1.2 V
VTSEN = 1.4 V
VTSEN = 1.6 V
VTSEN = 1.8 V
°C
73
75
77
°C
TSEN
Thermal voltage definition
TSEN leakage current
98
100
125
150
102
127
152
3
°C
123
148
–3
°C
°C
ITSEN
µA
22
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
6.23 PWM: I/O Voltage and Current
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VPWML
VPWMH
PWMx output low-level
PWMx output high-level
ILOAD = 0.5 mA
0.15
0.3
V
V
V
ILOAD = –0.5 mA; VV3P3 = 2.97 V
ILOAD = ± 100 µA
2.8
1.6
VPW-SKLK PWMx tri-state
tP-S_H-L PWMx H-L transition time
tP-S_TRI
(1) Specified by design. Not production tested.
1.7
1.8
10
CLOAD = 10 pF, ILOAD = ± 100 µ A, 10% to
90% both edges
(1)
ns
ns
CLOAD = 10 pF, ILOAD = ± 100 µ A, 10% or
90% to tri-state, both edges
(1)
PWMx tri-state transition
10
Copyright © 2017–2019, Texas Instruments Incorporated
23
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
6.24 Dynamic Phase Add and Drop
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 2 A; (MFR_SPECIFIC_15<4:3> = 00b);
21
23
25
27
29
31
27
29
31
33
29
31
33
35
31
33
35
37
A
VRIPPLE ≈ 18 A (estimation)
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 4 A; (MFR_SPECIFIC_15<4:3> = 01b);
23
25
27
23
25
27
29
25
27
29
31
27
29
31
33
25
27
29
25
27
29
31
27
29
31
33
29
31
33
35
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
VRIPPLE ≈ 18 A (estimation)
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 6 A; (MFR_SPECIFIC_15<4:3> = 10b);
VRIPPLE ≈ 18 A (estimation)
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 8 A; (MFR_SPECIFIC_15<4:3> = 11b);
VRIPPLE ≈ 18 A (estimation)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 2 A; (MFR_SPECIFIC_15<4:3> = 00b);
VRIPPLE ≈ 18 A (estimation)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 4 A; (MFR_SPECIFIC_15<4:3> = 01b);
VRIPPLE ≈ 18 A (estimation)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 6 A; (MFR_SPECIFIC_15<4:3> = 10b);
VRIPPLE ≈ 18 A (estimation)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 8 A; (MFR_SPECIFIC_15<4:3> = 11b);
Dynamic phase
adding threshold, 1 to
2 Phases (Peak
Current)
VRIPPLE ≈ 18 A (estimation)
VDPSTHA1
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 2 A; (MFR_SPECIFIC_15<4:3> = 00b);
VRIPPLE ≈ 18 A (estimation)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 4 A; (MFR_SPECIFIC_15<4:3> = 01b);
VRIPPLE ≈ 18 A (estimation)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 6 A; (MFR_SPECIFIC_15<4:3> = 10b);
VRIPPLE ≈ 18 A (estimation)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 8 A; (MFR_SPECIFIC_15<4:3> = 11b);
VRIPPLE ≈ 18 A (estimation)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 2 A; (MFR_SPECIFIC_15<4:3> = 00b);
VRIPPLE ≈ 18 A (estimation)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 4 A; (MFR_SPECIFIC_15<4:3> = 01b);
VRIPPLE ≈ 18 A (estimation)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 6 A; (MFR_SPECIFIC_15<4:3> = 10b);
VRIPPLE ≈ 18 A (estimation)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 8 A; (MFR_SPECIFIC_15<4:3> = 11b);
VRIPPLE ≈ 18 A (estimation)
24
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
Dynamic Phase Add and Drop (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = -6 A; (MFR_SPECIFIC_15<14:13> =
00b)
4
6
8
A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = -4 A; (MFR_SPECIFIC_15<14:13> =
01b)
6
8
8
10
12
8
10
12
14
10
12
14
16
12
14
16
18
14
16
18
20
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = -2 A; (MFR_SPECIFIC_15<14:13> =
10b)
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 0 A; (MFR_SPECIFIC_15<14:13> =
11b)
10
6
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = -6 A; (MFR_SPECIFIC_15<14:13> =
00b)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = -4 A; (MFR_SPECIFIC_15<14:13> =
01b)
8
10
12
14
10
12
14
16
12
14
16
18
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = -2 A; (MFR_SPECIFIC_15<14:13> =
10b)
10
12
8
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 0 A; (MFR_SPECIFIC_15<14:13> =
11b)
Dynamic phase
shedding threshold, 2
to 1 phase (average
current)
VDPSTHS1
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = -6 A; (MFR_SPECIFIC_15<14:13> =
00b)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = -4 A; (MFR_SPECIFIC_15<14:13> =
01b)
10
12
14
10
12
14
16
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = -2 A; (MFR_SPECIFIC_15<14:13> =
10b)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 0 A; (MFR_SPECIFIC_15<14:13> =
11b)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = -6 A; (MFR_SPECIFIC_15<14:13> =
00b)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = -4 A; (MFR_SPECIFIC_15<14:13> =
01b)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = -2 A; (MFR_SPECIFIC_15<14:13> =
10b)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 0 A; (MFR_SPECIFIC_15<14:13> =
11b)
Copyright © 2017–2019, Texas Instruments Incorporated
25
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
Dynamic Phase Add and Drop (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 4 A; (MFR_SPECIFIC_15<6:5> = 00b);
VRIPPLE = 14 A (estimation)
32.5
35
37.5
39.5
41.5
43.5
41.5
43.5
45.5
47.5
45.5
47.5
49.5
51.5
49.5
51.5
53.5
55.5
A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 6 A; (MFR_SPECIFIC_15<6:5> = 01b);
VRIPPLE = 14 A (estimation)
34.5
36.5
38.5
36.5
38.5
40.5
42.5
40.5
42.5
44.5
46.5
44.5
46.5
48.5
50.5
37
39
41
39
41
43
45
43
45
47
49
47
49
51
53
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 8 A; (MFR_SPECIFIC_15<6:5> = 10b);
VRIPPLE = 14 A (estimation)
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 10 A; (MFR_SPECIFIC_15<6:5> = 11b);
VRIPPLE = 14 A (estimation)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 4 A; (MFR_SPECIFIC_15<6:5> = 00b);
VRIPPLE = 14 A (estimation)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 6 A; (MFR_SPECIFIC_15<6:5> = 01b);
VRIPPLE = 14 A (estimation)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 8 A; (MFR_SPECIFIC_15<6:5> = 10b);
VRIPPLE = 14 A (estimation)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 10 A; (MFR_SPECIFIC_15<6:5> = 11b);
VRIPPLE = 14 A (estimation)
Dynamic phase
adding threshold, 2 to
3 phases (Peak
Current)
VDPSTHA2
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 4 A; (MFR_SPECIFIC_15<6:5> = 00b);
VRIPPLE = 14 A (estimation)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 6 A; (MFR_SPECIFIC_15<6:5> = 01b);
VRIPPLE = 14 A (estimation)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 8 A; (MFR_SPECIFIC_15<6:5> = 10b);
VRIPPLE = 14 A (estimation)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 10 A; (MFR_SPECIFIC_15<6:5> = 11b);
VRIPPLE = 14 A (estimation)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 4 A; (MFR_SPECIFIC_15<6:5> = 00b);
VRIPPLE = 14 A (estimation)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 6 A; (MFR_SPECIFIC_15<6:5> = 01b);
VRIPPLE = 14 A (estimation)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 8 A; (MFR_SPECIFIC_15<6:5> = 10b);
VRIPPLE = 14 A (estimation)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 10 A; (MFR_SPECIFIC_15<6:5> = 11b);
VRIPPLE = 14 A (estimation)
26
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
Dynamic Phase Add and Drop (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = -4 A; (MFR_SPECIFIC_14<9:8> = 00b)
17.5
20
22.5
A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = -2 A; (MFR_SPECIFIC_14<9:8> = 01b)
19.5
21.5
23.5
21.5
23.5
25.5
27.5
25.5
27.5
29.5
31.5
29.5
31.5
33.5
35.5
22
24
26
24
26
28
30
28
30
32
34
32
34
36
38
24.5
26.5
28.5
26.5
28.5
30.5
32.5
30.5
32.5
34.5
36.5
34.5
36.5
38.5
40.5
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 0 A; (MFR_SPECIFIC_14<9:8> = 10b)
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 2 A; (MFR_SPECIFIC_14<9:8> = 11b)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = -4 A; (MFR_SPECIFIC_14<9:8> = 00b)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = -2 A; (MFR_SPECIFIC_14<9:8> = 01b)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 0 A; (MFR_SPECIFIC_14<9:8> = 10b)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 2 A; (MFR_SPECIFIC_14<9:8> = 11b)
Dynamic phase
shedding threshold, 3
to 2 phases (average
current)
VDPSTHS2
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = -4 A; (MFR_SPECIFIC_14<9:8> = 00b)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = -2 A; (MFR_SPECIFIC_14<9:8> = 01b)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 0 A; (MFR_SPECIFIC_14<9:8> = 10b)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 2 A; (MFR_SPECIFIC_14<9:8> = 11b)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = -4 A; (MFR_SPECIFIC_14<9:8> = 00b)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = -2 A; (MFR_SPECIFIC_14<9:8> = 01b)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 0 A; (MFR_SPECIFIC_14<9:8> = 10b)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 2 A; (MFR_SPECIFIC_14<9:8> = 11b)
Copyright © 2017–2019, Texas Instruments Incorporated
27
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
Dynamic Phase Add and Drop (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 6 A; (MFR_SPECIFIC_15<8:7> = 00b);
VRIPPLE = 10 A (estimation)
44
47
50
52
54
56
56
58
60
62
62
64
66
68
68
70
72
74
A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 8 A; (MFR_SPECIFIC_15<8:7> = 01b);
VRIPPLE = 10 A (estimation)
46
48
50
50
52
54
56
56
58
60
62
62
64
66
68
49
51
53
53
55
57
59
59
61
63
65
65
67
69
71
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 10 A; (MFR_SPECIFIC_15<8:7> = 10b);
VRIPPLE = 10 A (estimation)
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 12 A; (MFR_SPECIFIC_15<8:7> = 11b);
VRIPPLE = 10 A (estimation)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 6 A; (MFR_SPECIFIC_15<8:7> = 00b);
VRIPPLE = 10 A (estimation)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 8 A; (MFR_SPECIFIC_15<8:7> = 01b);
VRIPPLE = 10 A (estimation)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 10 A; (MFR_SPECIFIC_15<8:7> = 10b);
VRIPPLE = 10 A (estimation)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 12 A; (MFR_SPECIFIC_15<8:7> = 11b);
VRIPPLE = 10 A (estimation)
Dynamic phase
adding threshold, 3 to
4 Phases (Peak
Current)
VDPSTHA3
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 6 A; (MFR_SPECIFIC_15<8:7> = 00b);
VRIPPLE = 10 A (estimation)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 8 A; (MFR_SPECIFIC_15<8:7> = 01b);
VRIPPLE = 10 A (estimation)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 10 A; (MFR_SPECIFIC_15<8:7> = 10b);
VRIPPLE = 10 A (estimation)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 12 A; (MFR_SPECIFIC_15<8:7> = 11b);
VRIPPLE = 10 A (estimation)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 6 A; (MFR_SPECIFIC_15<8:7> = 00b);
VRIPPLE = 10 A (estimation)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 8 A; (MFR_SPECIFIC_15<8:7> = 01b);
VRIPPLE = 10 A (estimation)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 10 A; (MFR_SPECIFIC_15<8:7> = 10b);
VRIPPLE = 10 A (estimation)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 12 A; (MFR_SPECIFIC_15<8:7> = 11b);
VRIPPLE = 10 A (estimation)
28
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
Dynamic Phase Add and Drop (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = -2 A; (MFR_SPECIFIC_14<11:10> =
00b)
31
34
37
A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 0 A; (MFR_SPECIFIC_14<11:10> =
01b)
33
35
37
37
39
41
43
43
45
47
49
49
51
53
55
36
38
40
40
42
44
46
46
48
50
52
52
54
56
58
39
41
43
43
45
47
49
49
51
53
55
55
57
59
61
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 2 A; (MFR_SPECIFIC_14<11:10> =
10b)
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 4 A; (MFR_SPECIFIC_14<11:10> =
11b)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = -2 A; (MFR_SPECIFIC_14<11:10> =
00b)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 0 A; (MFR_SPECIFIC_14<11:10> =
01b)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 2 A; (MFR_SPECIFIC_14<11:10> =
10b)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 4 A; (MFR_SPECIFIC_14<11:10> =
11b)
Dynamic phase
shedding threshold, 4
to 3 phases (average
current)
VDPSTHS3
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = -2 A; (MFR_SPECIFIC_14<11:10> =
00b)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 0 A; (MFR_SPECIFIC_14<11:10> =
01b)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 2 A; (MFR_SPECIFIC_14<11:10> =
10b)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 4 A; (MFR_SPECIFIC_14<11:10> =
11b)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = -2 A; (MFR_SPECIFIC_14<11:10> =
00b)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 0 A; (MFR_SPECIFIC_14<11:10> =
01b)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 2 A; (MFR_SPECIFIC_14<11:10> =
10b)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 4 A; (MFR_SPECIFIC_14<11:10> =
11b)
Copyright © 2017–2019, Texas Instruments Incorporated
29
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
Dynamic Phase Add and Drop (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 6 A; (MFR_SPECIFIC_15<10:9> = 00b);
VRIPPLE = 8 A (estimation)
54.5
58
61.5
63.5
65.5
67.5
69.5
71.5
73.5
75.5
77.5
79.5
81.5
83.5
85.5
87.5
89.5
91.5
A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 8 A; (MFR_SPECIFIC_15<10:9> = 01b);
VRIPPLE = 8 A (estimation)
56.5
58.5
60.5
62.5
64.5
66.5
68.5
70.5
72.5
74.5
76.5
78.5
80.5
82.5
84.5
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 10 A; (MFR_SPECIFIC_15<10:9> =
10b); VRIPPLE = 8 A (estimation)
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 12 A; (MFR_SPECIFIC_15<10:9> =
11b); VRIPPLE = 8 A (estimation)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 6 A; (MFR_SPECIFIC_15<10:9> = 00b);
VRIPPLE = 8 A (estimation)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 8 A; (MFR_SPECIFIC_15<10:9> = 01b);
VRIPPLE = 8 A (estimation)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 10 A; (MFR_SPECIFIC_15<10:9> =
10b); VRIPPLE = 8 A (estimation)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 12 A; (MFR_SPECIFIC_15<10:9> =
11b); VRIPPLE = 8 A (estimation)
Dynamic phase
adding threshold, 4 to
5 Phases (Peak
Current)
VDPSTHA4
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 6 A; (MFR_SPECIFIC_15<10:9> = 00b);
VRIPPLE = 8 A (estimation)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 8 A; (MFR_SPECIFIC_15<10:9> = 01b);
VRIPPLE = 8 A (estimation)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 10 A; (MFR_SPECIFIC_15<10:9> =
10b); VRIPPLE = 8 A (estimation)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 12 A; (MFR_SPECIFIC_15<10:9> =
11b); VRIPPLE = 8 A (estimation)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 6 A; (MFR_SPECIFIC_15<10:9> = 00b);
VRIPPLE = 8 A (estimation)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 8 A; (MFR_SPECIFIC_15<10:9> = 01b);
VRIPPLE = 8 A (estimation)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 10 A; (MFR_SPECIFIC_15<10:9> =
10b); VRIPPLE = 8 A (estimation)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 12 A; (MFR_SPECIFIC_15<10:9> =
11b); VRIPPLE = 8 A (estimation)
30
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
Dynamic Phase Add and Drop (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = -2 A; (MFR_SPECIFIC_14<13:12> =
00b)
42.5
46
49.5
A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 0 A; (MFR_SPECIFIC_14<13:12> =
01b)
44.5
46.5
48.5
50.5
52.5
54.5
56.5
58.5
60.5
62.5
64.5
66.5
68.5
70.5
72.5
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
51.5
53.5
55.5
57.5
59.5
61.5
63.5
65.5
67.5
69.5
71.5
73.5
75.5
77.5
79.5
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 2 A; (MFR_SPECIFIC_14<13:12> =
10b)
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 4 A; (MFR_SPECIFIC_14<13:12> =
11b)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = -2 A; (MFR_SPECIFIC_14<13:12> =
00b)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 0 A; (MFR_SPECIFIC_14<13:12> =
01b)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 2 A; (MFR_SPECIFIC_14<13:12> =
10b)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 4 A; (MFR_SPECIFIC_14<13:12> =
11b)
Dynamic phase
shedding threshold, 5
to 4 phases (average
current)
VDPSTHS4
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = -2 A; (MFR_SPECIFIC_14<13:12> =
00b)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 0 A; (MFR_SPECIFIC_14<13:12> =
01b)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 2 A; (MFR_SPECIFIC_14<13:12> =
10b)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 4 A; (MFR_SPECIFIC_14<13:12> =
11b)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = -2 A; (MFR_SPECIFIC_14<13:12> =
00b)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 0 A; (MFR_SPECIFIC_14<13:12> =
01b)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 2 A; (MFR_SPECIFIC_14<13:12> =
10b)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 4 A; (MFR_SPECIFIC_14<13:12> =
11b)
Copyright © 2017–2019, Texas Instruments Incorporated
31
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
Dynamic Phase Add and Drop (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 6 A; (MFR_SPECIFIC_15<12:11> =
00b); VRIPPLE = 6 A (estimation)
65
69
73
75
A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 8 A; (MFR_SPECIFIC_15<12:11> =
01b); VRIPPLE = 6 A (estimation)
67
69
71
75
77
79
81
85
87
89
91
95
97
99
101
71
73
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 10 A; (MFR_SPECIFIC_15<12:11> =
10b); VRIPPLE = 6 A (estimation)
77
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 12 A; (MFR_SPECIFIC_15<12:11> =
11b); VRIPPLE = 6 A (estimation)
75
79
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 6 A; (MFR_SPECIFIC_15<12:11> =
00b); VRIPPLE = 6 A (estimation)
79
83
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 8 A; (MFR_SPECIFIC_15<12:11> =
01b); VRIPPLE = 6 A (estimation)
81
85
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 10 A; (MFR_SPECIFIC_15<12:11> =
10b); VRIPPLE = 6 A (estimation)
83
87
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 12 A; (MFR_SPECIFIC_15<12:11> =
11b); VRIPPLE = 6 A (estimation)
85
89
Dynamic phase
adding threshold, 5 to
6 Phases (Peak
Current)
VDPSTHA5
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 6 A; (MFR_SPECIFIC_15<12:11> =
00b); VRIPPLE = 6 A (estimation)
89
93
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 8 A; (MFR_SPECIFIC_15<12:11> =
01b); VRIPPLE = 6 A (estimation)
91
95
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 10 A; (MFR_SPECIFIC_15<12:11> =
10b); VRIPPLE = 6 A (estimation)
93
97
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 12 A; (MFR_SPECIFIC_15<12:11> =
11b); VRIPPLE = 6 A (estimation)
95
99
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 6 A; (MFR_SPECIFIC_15<12:11> =
00b); VRIPPLE = 6 A (estimation)
99
103
105
107
109
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 8 A; (MFR_SPECIFIC_15<12:11> =
01b); VRIPPLE = 6 A (estimation)
101
103
105
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 10 A; (MFR_SPECIFIC_15<12:11> =
10b); VRIPPLE = 6 A (estimation)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 12 A; (MFR_SPECIFIC_15<12:11> =
11b); VRIPPLE = 6 A (estimation)
32
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
Dynamic Phase Add and Drop (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = -2 A; (MFR_SPECIFIC_14<15:14> =
00b)
54
58
62
A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 0 A; (MFR_SPECIFIC_14<15:14> =
01b)
56
58
60
64
66
68
70
74
76
78
80
84
86
88
90
60
62
64
68
70
72
74
78
80
82
84
88
90
92
94
64
66
68
72
74
76
78
82
84
86
88
92
94
96
98
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 2 A; (MFR_SPECIFIC_14<15:14> =
10b)
Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =
00b); Offset = 4 A; (MFR_SPECIFIC_14<15:14> =
11b)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = -2 A; (MFR_SPECIFIC_14<15:14> =
00b)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 0 A; (MFR_SPECIFIC_14<15:14> =
01b)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 2 A; (MFR_SPECIFIC_14<15:14> =
10b)
Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =
01b); Offset = 4 A; (MFR_SPECIFIC_14<15:14> =
11b)
Dynamic phase
shedding threshold, 6
to 5 phases (average
current)
VDPSTHS5
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = -2 A; (MFR_SPECIFIC_14<15:14> =
00b)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 0 A; (MFR_SPECIFIC_14<15:14> =
01b)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 2 A; (MFR_SPECIFIC_14<15:14> =
10b)
Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =
10b); Offset = 4 A; (MFR_SPECIFIC_14<15:14> =
11b)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = -2 A; (MFR_SPECIFIC_14<15:14> =
00b)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 0 A; (MFR_SPECIFIC_14<15:14> =
01b)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 2 A; (MFR_SPECIFIC_14<15:14> =
10b)
Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =
11b); Offset = 4 A; (MFR_SPECIFIC_14<15:14> =
11b)
版权 © 2017–2019, Texas Instruments Incorporated
33
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
6.25 Typical Characteristics
1.9
98
97
96
95
94
93
92
91
90
Load Line
- 1/2 Ripple
+ 1/2 Ripple
Lower Limit (VOUT(min)
Upper Limit (VOUT(max)
1.85
1.8
)
)
1.75
1.7
1.65
1.6
DPS
On
Off
1.55
0
50
100
150
200
250
0
50
100
150
200
250
Output Current (A)
Load Current (A)
D001
D001
VVIN = 12 V
VOUT = 1.82 V
VVIN = 12 V
VOUT = 1.8 V
fSW = 600 kHz
Load Line = 0.9 mΩ
Load Line = 0.9 mΩ
图 2. VOUTA Load Line
图 3. Efficiency
250
225
200
175
150
125
100
75
450
400
350
300
250
200
150
100
50
50
Load Current
Upper Limit
Lower Limit
Input Power
Upper Limit
Lower Limit
25
0
0
0
10
20
30
40
50
60
70
80
90 100
0
50
100 150 200 250 300 350 400 450
Input Power (W)
Load Current (%)
D001
D001
VVIN = 12 V
VOUT = 1.82 V
VVIN = 12 V
VOUT = 1.82 V
Load Line = 0.9 mΩ
Load Line = 0.9 mΩ
图 5. VOUTA Reported Output Current by PMBus
图 4. VOUTA Reported Input Power by PMBus
34
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
7 Detailed Description
7.1 Overview
The TPS53681 is a multiphase step-down controller with dual channels, built-in non-volatile memory (NVM), and
PMBus™ interface, and is fully compatible with TI NexFET ™ power stages. Advanced control features such as
D-CAP+™ architecture with undershoot reduction (USR) provide transient response,
7.2 Functional Block Diagram
DCLLA
COMPA
AVSP
AVSN
Differential
Amplifier
VRAMPA
VCOMPA
VISUMA
+
VDIFFA
VISUMA
VFBDRPA
VDACA
+
+
CLKA_ON
Loadline
Control
Programmable
Loop
FREQA
CK1
TONA
On-Time
A1
APWM1
APWM2
BVSP
BVSN
Differential
Amplifier
VRAMPB
VCOMPB
VISUMB
CK2
CK3
CK4
CK5
On-Time
A2
+
VDIFFB
VISUMB
VFBDRPB
VDACB
+
+
CLKB_ON
Loadline
Control
Programmable
Loop
On-Time
A3
APWM3
APWM4
VIA1
VIA2
VIA3
DCLLB
COMPB
ACSP1
ACSP2
ACSP3
Mode Control
and
Programmable
Phase Manager
On-Time
A4
VISUMA
VISUMB
PHASE
ꢀ
ꢀ
On-Time
A5
VIA4
VIA5
VIA6
VIB1
VIB2
APWM5
ACSP4
ACSP5
VIA1
VIA2
VIA3
VIA4
CK6
On-Time
A6
APWM6/BPWM3
BPWM1
Adaptive
On-Time Control
and
Current Sharing
Circuitry
ACSP6/BCSP3
BCSP1
CKB1
VIA5
VIA6
VIB1
On-Time
B1
TONB
BCSP2
VIB2
VDACA
VDACB
Ramp
Generator
CKB2
On-Time
B2
BPWM2
FREQB
VIA1
VIA2
VIA3
VIA4
CPU Logic,
Protection,
and
IIN
I2C Interface
VIA5
VIA6
VIB1
VIB2
V3P3
GND
Status Circuitry
SMB_CLK
NVM
SMB_ALERT
SMB_DIO
VDACA
VDACB
FAULT
AFE, ADC, and DAC
Copyright © 2017, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Phase Interleaving and PWM Operation
As shown in the Overview section, in 8-phase continuous conduction mode, the device operates as described in
图 6.
版权 © 2017–2019, Texas Instruments Incorporated
35
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
Feature Description (接下页)
VCORE
ISUM
VCOMP+VRAMP
CLKA_ON
APWM1
APWM2
APWM3
APWM4
APWM5
APWM6
Time
图 6. D-CAP+ Mode Basic Waveforms
Starting with the condition that the high-side FETs are off and the low-side FETs are on, the summed current
feedback (VISUM) is higher than the summed error amplifier output (VCOMP) and the internal ramp signal (VRAMP).
ISUM falls until it hits VCOMP+VRAMP, which contains a component of the output ripple voltage. The PWM
comparator senses where the two waveforms cross and triggers the on-time generator. This generates the
internal CLKA_ON signal. Each CLKA_ON signal corresponds to one switching ON pulse for one phase.
In case of single-phase operation, every CLKA_ON signal generates a switching pulse on the same phase. Also,
VISUM corresponds to just a single-phase inductor current.
In case of multi-phase operation, the CLKA_ON signal gets distributed to each of the phases in a cycle. This
approach of using the summed inductor current and cyclically distributing the ON pulses to each phase
automatically gives the required interleaving of 360 / n, where n is the number of phases.
7.3.1.1 Setting the Load-Line (DROOP)
V
DAC
Slope of Loadline R
LL
V
V
= R x I
DROOP LL OUT
DROOP
I
OUT
图 7. Load Line
The loadline can be set with VOUT_DROOP register via PMBus. The programmable range for channel A is
between 0 mΩ and 3.125 mΩ with 64 options, and the range for channel B is between 0 mΩ and 0.875 mΩ with
16 options to fulfill the requirements for different applications.
36
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
Feature Description (接下页)
7.3.1.2 Load Transitions
When there is a sudden load increase, the output voltage immediately drops. The TPS53681 device reacts to
this drop in a rising voltage on the COMP pin. This rise forces the PWM pulses to come in sooner and more
frequently which causes the inductor current to rapidly increase. As the inductor current reaches the new load
current, the device reaches a steady-state operating condition and the PWM switching resumes the steady-state
frequency.
When there is a sudden load release, the output voltage flies high. The TPS53681 device reacts to this rise in a
falling voltage on the COMP pin. This drop forces the PWM pulses to be delayed until the inductor current
reaches the new load current. At that point, the switching resumes and steady-state switching continues.
Please note in 图 8 and 图 9, the ripples on VOUT, VRAMP, and VCOMP voltages are not shown for simplicity.
LOAD
LOAD
VOUT
VOUT
VISUM
VCOMP + VRAMP
VISUM
VCOMP + VRAMP
CLKA_ON
CLKA_ON
APWM1
APWM1
APWM2
APWM2
APWM3
APWM3
APWM4
APWM4
APWM5
APWM5
APWM6
APWM6
图 8. Load Insertion
图 9. Load Release
The TPS53681 achieves fast load transient performance using the inherent variable switching frequency
characteristics.图 8 illustrates the load insertion behavior that the PWM pulses can be generated with faster
frequency than the steady-state frequency to provide more energy to improve the undershoot performance. 图 9
illustrates the load release behavior that PWM pulses can be gated to avoid charging extra energy to the load
until the output voltage reaches the peak overshoot.
7.3.1.2.1 VID Table
The DAC voltage VDAC can be changed via PMBus according to 表 2 . Set the VOUT_SCALE_LOOP command
to 1.125 to achieve output voltages higher than 2.500. The controller will acknowledge all VID codes and ignore
those which are unsupported per the table below.
版权 © 2017–2019, Texas Instruments Incorporated
37
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
表 2. VID Table
表 2. VID Table (接下页)
VID Hex
VALUE
DAC STEP
(5 mV)
DAC STEP
(10 mV)
VID Hex
VALUE
DAC STEP
(5 mV)
DAC STEP
(10 mV)
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
1.04
1.05
1.06
1.07
1.08
1.09
1.10
1.11
1.12
1.13
1.14
1.15
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
1.25
1.26
1.27
1.28
1.29
1.30
1.31
1.32
1.33
1.34
1.35
1.36
1.37
1.38
1.39
1.40
1.41
1.42
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
0
0
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
0.48
0.485
0.49
0.25
0.50
0.51
0.52
0.53
0.54
0.55
0.56
0.57
0.58
0.59
0.60
0.61
0.62
0.63
0.64
0.65
0.66
0.67
0.68
0.69
0.70
0.71
0.72
0.73
0.74
0.75
0.76
0.77
0.78
0.79
0.80
0.81
0.82
0.83
0.84
0.85
0.86
0.87
0.88
0.89
0.90
0.91
0.92
0.93
0.94
0.95
0.255
0.26
0.495
0.50
0.265
0.27
0.505
0.51
0.275
0.28
0.515
0.52
0.285
0.29
0.525
0.53
0.295
0.30
0.535
0.54
0.305
0.31
0.545
0.55
0.315
0.32
0.555
0.56
0.325
0.33
0.565
0.57
0.335
0.34
0.575
0.58
0.345
0.35
0.585
0.59
0.355
0.36
0.595
0.60
0.365
0.37
0.605
0.61
0.375
0.38
0.615
0.62
0.385
0.39
0.625
0.63
0.395
0.40
0.635
0.64
0.405
0.41
0.645
0.65
0.415
0.42
0.655
0.66
0.425
0.43
0.665
0.67
0.435
0.44
0.675
0.68
0.445
0.45
0.685
0.69
0.455
0.46
0.695
0.70
0.465
0.47
0.705
0.71
0.475
38
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
表 2. VID Table (接下页)
表 2. VID Table (接下页)
VID Hex
VALUE
DAC STEP
(5 mV)
DAC STEP
(10 mV)
VID Hex
VALUE
DAC STEP
(5 mV)
DAC STEP
(10 mV)
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
0.715
0.72
1.43
1.44
1.45
1.46
1.47
1.48
1.49
1.50
1.51
1.52
1.53
1.54
1.55
1.56
1.57
1.58
1.59
1.60
1.61
1.62
1.63
1.64
1.65
1.66
1.67
1.68
1.69
1.70
1.71
1.72
1.73
1.74
1.75
1.76
1.77
1.78
1.79
1.80
1.81
1.82
1.83
1.84
1.85
1.86
1.87
1.88
1.89
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
0.95
0.955
0.96
1.90
1.91
1.92
1.93
1.94
1.95
1.96
1.97
1.98
1.99
2.00
2.01
2.02
2.03
2.04
2.05
2.06
2.07
2.08
2.09
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
2.21
2.22
2.23
2.24
2.25
2.26
2.27
2.28
2.29
2.30
2.31
2.32
2.33
2.34
2.35
2.36
0.725
0.73
0.965
0.97
0.735
0.74
0.975
0.98
0.745
0.75
0.985
0.99
0.755
0.76
0.995
1.00
0.765
0.77
1.005
1.01
0.775
0.78
1.015
1.02
0.785
0.79
1.025
1.03
0.795
0.80
1.035
1.04
0.805
0.81
1.045
1.05
0.815
0.82
1.055
1.06
0.825
0.83
1.065
1.07
0.835
0.84
1.075
1.08
0.845
0.85
1.085
1.09
0.855
0.86
1.095
1.10
0.865
0.87
1.105
1.11
0.875
0.88
1.115
1.12
0.885
0.89
1.125
1.13
0.895
0.90
1.135
1.14
0.905
0.91
1.145
1.15
0.915
0.92
1.155
1.16
0.925
0.93
1.165
1.17
0.935
0.94
1.175
1.18
0.945
版权 © 2017–2019, Texas Instruments Incorporated
39
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
表 2. VID Table (接下页)
表 2. VID Table (接下页)
VID Hex
VALUE
DAC STEP
(5 mV)
DAC STEP
(10 mV)
VID Hex
VALUE
DAC STEP
(5 mV)
DAC STEP
(10 mV)
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
BC
BD
BE
BF
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
1.185
1.19
2.37
2.38
2.39
2.40
2.41
2.42
2.43
2.44
2.45
2.46
2.47
2.48
2.49
2.50
n/a
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
1.355
1.36
1.195
1.20
1.365
1.37
1.205
1.21
1.375
1.38
1.215
1.22
1.385
1.39
1.225
1.23
1.395
1.40
1.235
1.24
1.405
1.41
1.245
1.25
1.415
1.42
1.255
1.26
1.425
1.43
n/a
1.265
1.27
n/a
1.435
1.44
n/a
1.275
1.28
n/a
1.445
1.45
n/a
1.285
1.29
n/a
1.455
1.46
n/a
1.295
1.30
n/a
1.465
1.47
n/a
1.305
1.31
n/a
1.475
1.48
n/a
1.315
1.32
n/a
1.485
1.49
n/a
1.325
1.33
n/a
1.495
1.50
n/a
1.335
1.34
n/a
1.505
1.51
n/a
1.345
1.35
n/a
1.515
1.52
n/a
40
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
7.3.1.3 Temperature and Fault Sensing
TI smart power stage senses the die temperature and sends out the temperature information as a voltage
through the TAO pin. In a multi-phase application, the TAO pin of the TI smart power stages are connected
together and then tied to the ATSEN and BTSEN pins of the TPS53681 device. In this case, the device reports
the temperature of the hottest power stage. The reported temperature can be calculated as shown in 公式 1.
(VTSEN F 0.6)
TEMP =
where
•
•
TEMP is the sensed temperature in °C
VTSEN is the voltage at ATSEN and BTSEN pins
(1)
TSEN signal is also used as an indicator for power stage fault. When an internal fault occurs in the TI smart
power stage, the power stage pulls the xTAO pins high. If the TSEN voltage is higher than 2.5 V, the TPS53681
device senses the fault and turns off both the high-side and the low-side MOSFETS.
The TSEN signal is also used to indicate hand-shaking between the controller and the power stages. If the power
stages are not powered, the TAO pin is pulled down to prevent switching, even if the controller is enabled.
A Rail Power Stage
ATAO
Temperature
Sense
A Rail Power Stage
ATAO
Controller
ATSEN
Temperature
Sense
B Rail Power Stage
BTAO
BTSEN
Temperature
Sense
Temp
ADC
Copyright © 2017, Texas Instruments Incorporated
图 10. Temperature Sense
7.3.1.4 AutoBalance™ Current Sharing
The basic mechanism for current sharing is to sense the average phase current, then adjust the pulse width of
each phase to equalize the current in each phase as shown in 图 11. The PWM comparator (not shown) starts a
pulse when the feedback voltage meets the reference. The VIN voltage charges Ct(on) through Rt(on). The pulse
terminates when the voltage at Ct(on) matches the on-time reference, which normally equals the DAC voltage
(VDAC).
The circuit operates in the following fashion. First assume that the 1-µs averaged value from each phase current
are equal. In this case, the PWM modulator terminates at VDAC, and the normal pulse width is delivered to the
system. If instead, I1 > IAVG, then an offset is subtracted from VDAC, and the pulse width for Phase 1 is shortened
to reduce the phase current in Phase 1 for balancing. If I1 < IAVG, then a longer pulse is generated to increase
the phase current in Phase 1 to achieve current balancing.
版权 © 2017–2019, Texas Instruments Incorporated
41
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
VDAC
+
I1
+
+
+
+
K X (I1 œ IAVG
)
)
)
)
1 µs
ACSP1
Filter
œ
œ
+
RT(on)
RT(on)
RT(on)
RT(on)
APWM1
APWM2
APWM3
APWM4
œ
œ
œ
œ
VIN
IAVG
VDAC
CT(on)
+
I2
K X (I2 œ IAVG
1 µs
ACSP2
Filter
+
VIN
IAVG
VDAC
+
CT(on)
I3
K X (I3 œ IAVG
1 µs
ACSP3
Filter
œ
œ
+
IAVG
VIN
VDAC
+
CT(on)
I4
K X (I4 œ IAVG
1 µs
ACSP4
Filter
+
IAVG
VIN
VDAC
CT(on)
+
I5
+
+
K X (I5 œ IAVG
)
1 µs
ACSP5
Filter
œ
œ
+
RT(on)
APWM5
APWM6
œ
IAVG
VIN
VDAC
CT(on)
+
I6
K X (I6 œ IAVG)
1 µs
ACSP6
Filter
+
RT(on)
œ
IAVG
VIN
Averaging Circuit
CT(on)
图 11. AutoBalance Current Sharing Circuit Detail
42
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
7.3.1.5 Phase Configuration for Channel B
By default, the second rail of the TPS53681 is configured for two-phase operation. Two NVM bits, CHB_2PH and
CHB_3PH control the number of phases available to channel B. The CHB_2PH bit is found in
MFR_SPECIFIC_13 (bit 12), and the CHB_3PH bit is found in USER_DATA_11. See 表 3 below, which
describes these bit settings, versus phase configuration for channel B. Refer to the accompanying Technical
Reference Manual for a register map of MFR_SPECIFIC_13 and USER_DATA_11. Refer to Current Sense
Inputs for Active Phases for information about pin configuration of CSP signals for various channel B phase
configuration settings.
表 3. Channel B Phase Configuration
CHB_2PH
MFR_SPECIFIC_13[PAGE0][12]
USER_DATA_11[PAGE0][9]
CHB_3PH
USER_DATA_11[PAGE0][9]
Channel B Phases
1
2
3
1b
0b
0b
0b
0b
1b
7.3.1.6 RESET Function
During adaptive voltage scaling (AVS) operation, the voltage may become falsely adjusted to be out of ASIC
operating range. The RESET function returns the voltage to the VBOOT voltage. When the voltage is out of
ASIC operating range, the ASIC issues a RESET signal to the TPS53681 device, as shown in 图 12. The device
senses this signal and after a delay of greater than 1 µs, it sets an internal RESET_FAULT signal and sets
VOUT_COMMAND to VBOOT. The device pulls the output voltage to the VBOOT level with the slew rate set by
VOUT_TRANSITION_RATE command, as shown in 图 13.
When the RESET pin signal goes high, the internal RESET_FAULT signal goes low.
TPS53681
ASIC Power Stage
ASIC V
RESET
RESET
TPS53681 V
RESET
RESET
PMB_CLK
PMB_DIO
PMB_CLK
PMB_DIO
Internal
RESET_FAULT
PMB_ALERT
PMB_ALERT
Response Delay
Default VBOOT
Pre-AVS V
.
OUT .
(A)
V
OUT
(C)
(B)
Time
图 12. RESET Pin Connection
图 13. Reset Function
7.4 Device Functional Modes
7.5 Programming
7.5.1 PMBus Connections
The TPS53681 device can support either 100kHz class, 400 kHz class or 1 MHz class operation, with 1.8-V or
3.3-V logic levels. Connection for the PMBus interface should follow the DC specifications given in Section 4.3 of
the System Management Bus (SMBus) Specification V3.0 . The complete SMBus specification is available from
the SMBus website, smbus.org.
7.5.2 PMBus Address Selection
The PMBus slave addresses for TPS53681 are selected with a resistor divider from VREF to ADDR.
Copyright © 2017–2019, Texas Instruments Incorporated
43
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
Programming (continued)
The PMBus slave address is set by the voltage on the ADDR pin. Refer to Table 4. With the desired PMBus
address, and RADDRL selected, calculate the RADDRH using Equation 2.
Note that TPS53681 uses 7 bit addressing, per the SMBus specification. Users communicating to the device
using generic I2C drivers should be aware that these 7 bits occupy the most significant bits of the first byte in
each transaction, with the least significant bit being the data direction bit (0 for write operations, 1 for read
operations). That is, for read transactions, the address byte is A6A5A4A3A2A1A01 and for write operations the
address byte is A6A5A4A3A2A1A00. Refer to the SMBus specification for more information.
The general procedure for selecting these resistors is as follows:
1. Determine the desired PMBus slave addresses, per system requirements
2. Select an RADDRL value of 10 kΩ or 20 kΩ
3. Using the desired PMBus address, refer to Table 4 for the desired address pin voltage
4. Use Equation 2 to calculate RADDRH
VREF
RADDRH
ADDR
RADDRL
Figure 14. PMBus Address Selection
Contact your local Texas Instruments representative for a copy of the PMBus address setting design tool
spreadsheet.
VREF
RADDRH = RADDRL
l
F 1p
VADDR
(2)
Table 4. PMBus Slave Address Selection
VADDR (V)
PMBus Address
(7 bit binary)
PMBus Address
(7-bit decimal)
I2C Address Byte
(Write Operation)
I2C Address Byte
(Read Operation)
A6A5A4A3A2A1A0
≤ 0.039 V
1011000b
1011001b
1011010b
1011011b
1011100b
1011101b
1011110b
1011111b
1100000b
1100001b
1100010b
1100011b
1100100b
1100101b
1100110b
88d
89d
90d
91d
92d
93d
94d
95d
96d
97d
98d
99d
100d
101d
102d
B0h
B2h
B4h
B6h
B8h
BAh
BCh
BEh
C0h
C2h
C4h
C6h
C8h
CAh
CCh
B1h
B3h
B5h
B7h
B9h
BBh
BDh
BFh
C1h
C3h
C5h
C7h
C9h
CBh
CDh
0.073 V ± 15 mV
0.122 V ± 15 mV
0.171 V ± 15 mV
0.219 V ± 15 mV
0.268 V ± 15 mV
0.317 V ± 15 mV
0.366 V ± 15 mV
0.415 V ± 15 mV
0.464 V ± 15 mV
0.513 V ± 15 mV
0.562 V ± 15 mV
0.610 V ± 15 mV
0.660 V ± 15 mV
0.708 V ± 15 mV
44
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
Table 4. PMBus Slave Address Selection (continued)
VADDR (V)
PMBus Address
(7 bit binary)
PMBus Address
(7-bit decimal)
I2C Address Byte
(Write Operation)
I2C Address Byte
(Read Operation)
A6A5A4A3A2A1A0
0.757 V ± 15 mV
0.806 V ± 15 mV
0.854 V ± 15 mV
0.903 V ± 15 mV
0.952 V ± 15 mV
1.000 V ± 15 mV
1.050 V ± 15 mV
1.098 V ± 15 mV
1.147 V ± 15 mV
1.196 V ± 15 mV
1.245 V ± 15 mV
1.294 V ± 15 mV
1.343 V ± 15 mV
1.392 V ± 15 mV
1.440 V ± 15 mV
1.489 V ± 15 mV
1.540 V ± 15 mV
1100111b
1101000b
1101001b
1101010b
1101011b
1101100b
1101101b
1101110b
1101111b
1110000b
1110001b
1110010b
1110011b
1110100b
1110101b
1110110b
1110111b
103d
104d
105d
106d
107d
108d
109d
110d
111d
112d
113d
114d
115d
116d
117d
118d
119d
CEh
D0h
D2h
D4h
D6h
D8h
DAh
DCh
DEh
E0h
E2h
E4h
E6h
E8h
EAh
ECh
EEh
CFh
D1h
D3h
D5h
D7h
D9h
DBh
DDh
DFh
E1h
E3h
E5h
E7h
E9h
EBh
EDh
EFh
7.5.3 Supported Commands
The table below summarizes the PMBus commands supported by the TPS53681. Only selected commands,
which are most commonly used during device configuration and usage are reproduced in this document. For a
full set of register maps for this device, refer to the accompanying Technical Reference Manual.
Copyright © 2017–2019, Texas Instruments Incorporated
45
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
Default Value
R/W,
NVM
CMD
Command Name
Description
Default Behavior
Ch. A
Ch. B
(PAGE 0)
PAGE 1
Selects which channel subsequent
PMBus commands address
All commands
address Channel A
00h PAGE
RW
RW
N/A
Conversion
disabled. Margin
None.
Enable or disable each channel,
enter or exit margin.
01h OPERATION
00h
1Bh
00h
1Bh
Configure the combination of
OPERATION, and enable pin
required to enable power conversion
for each channel.
RW,
OPERATION
NVM command only.
02h ON_OFF_CONFIG
Clears all fault status registers to 00h
and releases PMB_ALERT
03h CLEAR_FAULT
04h PHASE
W
Write-only
N/A
00h
Selects which phase of the active
channel subsequent PMBus
commands address
Commands
address all phases.
RW
FFh
FFh
Used to control writing to the volatile
operating memory (PMBus and
restore from NVM).
Writes to all
commands are
allowed
10h WRITE_PROTECT
RW
Stores all current storable register
settings into NVM as new defaults.
11h STORE_DEFAULT_ALL
12h RESTORE_DEFAULT_ALL
W
W
Write-only
Write-only
N/A
N/A
Restores all storable register settings
from NVM.
Provides a way for a host system to
determine key PMBus capabilities of
the device.
1 MHz, PEC,
PMB_ALERT
Supported
19h CAPABILITY
R
D0h
SMBALERT_MASK
1Bh
Selects which faults/status bits may
to assert PMB_ALERT
RW,
All bits may assert
00h
00h
00h
00h
(STATUS_VOUT)
NVM PMB_ALERT
SMBALERT_MASK
1Bh
Selects which faults/status bits may
to assert PMB_ALERT
RW,
All bits may assert
(STATUS_IOUT)
NVM PMB_ALERT
LOW_VIN does not
assert
PMB_ALERT
SMBALERT_MASK
1Bh
Selects which faults/status bits may
to assert PMB_ALERT
RW,
NVM
08h
08h
(STATUS_INPUT)
SMBALERT_MASK
1Bh
Selects which faults/status bits may
to assert PMB_ALERT
RW,
All bits may assert
00h
00h
00h
00h
00h
00h
(STATUS_TEMPERATURE)
NVM PMB_ALERT
SMBALERT_MASK
1Bh
Selects which faults/status bits may
to assert PMB_ALERT
RW,
All bits may assert
(STATUS_CML)
NVM PMB_ALERT
SMBALERT_MASK
1Bh
Selects which faults/status bits may
to assert PMB_ALERT
RW,
All bits may assert
(STATUS_MFR_SPECIFIC)
NVM PMB_ALERT
VID mode.
5 mV Step (Ch A),
20h VOUT_MODE
Read-only output mode indicator
R(1)
21h
21h
5 mV Step (Ch B)
RW,
0.500 V (Ch A)
21h VOUT_COMMAND
24h VOUT_MAX
Output voltage target.
0033h
00FFh
0033h
00FFh
NVM 0.500 V (Ch B)
RW, 1.520 V (Ch A)
NVM 1.520 V (Ch B)
Sets the maximum output voltage
Load the unit with the voltage to
which the output is to be changed
when OPERATION command is set
to “Margin High”.
0.000 V (CH A)
RW
25h VOUT_MARGIN_HIGH
26h VOUT_MARGIN_LOW
27h VOUT_TRANSITION_RATE
0000h
0000h
E019h
0000h
0000h
E019h
0.000 V (Ch B)
Load the unit with the voltage to
which the output is to be changed
when OPERATION command is set
to “Margin Low”.
0.000 V (CH A)
RW
0.000 V (Ch B)
1.5625 mV/µs (Ch
Used to set slew rate settings for
output voltage updates
RW,
A)
NVM 1.5625 mV/µs (Ch
B)
(1) NVM-backed bits in the MFR_SPECIFIC or USER_DATA commands affect the reset value of these commands. Refer to the individual
register maps for more detail.
46
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
CMD
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
Default Value
R/W,
NVM
Command Name
Description
Default Behavior
Ch. A
Ch. B
(PAGE 0)
PAGE 1
The VOUT_DROOP sets the rate, in
mV/A (mΩ) at which the output
voltage decreases (or increases) with
increasing (or decreasing) output
current for use with Adaptive Voltage
Positioning
RW,
0.000 mΩ (Ch A)
28h VOUT_DROOP
D000h
D000h
NVM 0.000 mΩ (Ch B)
RW,
1.000 (Ch A)
29h VOUT_SCALE_LOOP
2Ah VOUT_SCALE_MONITOR
2Bh VOUT_MIN
Used for scaling the VID code
E808h
E808h
0000h
01F4h
E808h
E808h
0000h
01F4h
NVM 1.000 (Ch B)
Used for scaling output voltage
telemetry
RW, 1.000 (Ch A)
NVM 1.000 (Ch B)
RW, 0.000 V (Ch A)
NVM 0.000 V (Ch B)
RW, 500 kHz (Ch A)
Sets the minimum output voltage
Sets the switching frequency
33h FREQUENCY_SWITCH
NVM 500 kHz (Ch B)
Sets value of input voltage at which
the device should start power
conversion.
RW,
35h VIN_ON
6.25 V
NVM
F019h
Sets the ratio of voltage at the current
sense pins to the sensed current.
RW,
5.000 mΩ (Ch A)
38h IOUT_CAL_GAIN
39h IOUT_CAL_OFFSET
D140h
E800h
D140h
E800h
NVM 5.000 mΩ (Ch B)
0.000 A (Ch A)
RW,
Used to null offsets in the output
current sensing circuit
0.000 A (Ch B)
NVM
(All Phases)
Sets the value of the sensed output
voltage which triggers an output
overvoltage fault
1.520 V (Ch A)
1.520 V (Ch B)
40h VOUT_OV_FAULT_LIMIT
41h VOUT_OV_FAULT_RESPONSE
44h VOUT_UV_FAULT_LIMIT
R
00FFh
80h
00FFh
80h
Sets the converter response to an
output overvoltage event
Shutdown, do not
restart
R
Sets the value of the sensed output
voltage which triggers an output
undervoltage fault
0.000 V (Ch A)
0.000 V (Ch B)
R
0000h
0000h
Sets the converter response to an
output undervoltage event
RW,
NVM restart
Shutdown, do not
45h VOUT_UV_FAULT_RESPONSE
46h IOUT_OC_FAULT_LIMIT
80h
0027h
FAh
80h
0027h
FAh
Sets the output Over Current fault
limit
RW,
39 A (Ch A)
NVM(1) 39 A (Ch B)
Define the over-current fault
response.
RW,
NVM Hiccup
Shutdown, and
47h IOUT_OC_FAULT_RESPONSE
Sets the value of the output current
that causes the over current detector
to indicate an over current warning.
RW,
26 A (Ch A)
4Ah IOUT_OC_WARN_LIMIT
001Ah
001Ah
NVM(1) 26 A (Ch B)
Sets the temperature, in degrees
Celsius, of the unit at which it should
indicate an Over temperature Fault.
RW,
135 °C (Ch A)
4Fh OT_FAULT_LIMIT
0087h
80h
0087h
80h
NVM(1) 135 °C (Ch B)
Sets the converter response to an
over temperature fault.
RW,
NVM restart
Shutdown, do not
50h OT_FAULT_RESPONSE
Sets the temperature, in degrees
Celsius, of the unit at which it should
indicate an Over temperature
warning.
105 °C (Ch A)
105 °C (Ch B)
51h OT_WARN_LIMIT
RW
0069h
0069h
Set the voltage, in volts, of the unit at
which it should indicate a Vin Over-
voltage Fault.
RW,
NVM
55h VIN_OV_FAULT_LIMIT
14.000 V
000Eh
Instructs the device on what action to
take in response to an input
overvoltage fault.
Continue
Uninterrupted
56h VIN_OV_FAULT_RESPONSE
R
00h
Sets the value of the input voltage
that causes an Input Under voltage
Fault
RW,
NVM
59h VIN_UV_FAULT_LIMIT
5.500 V
F80Bh
C0h
Sets the converter response to an
input undervoltage event
Shutdown, do not
restart
5Ah VIN_UV_FAULT_RESPONSE
R
Copyright © 2017–2019, Texas Instruments Incorporated
47
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
Default Value
R/W,
NVM
CMD
Command Name
Description
Default Behavior
Ch. A
Ch. B
(PAGE 0)
PAGE 1
Sets the value in amperes that
causes the over current fault
condition of the input current
RW,
NVM
5Bh IIN_OC_FAULT_LIMIT
5Ch IIN_OC_FAULT_RESPONSE
5Dh IIN_OC_WARN_LIMIT
63.5 A
F87Fh
Sets the converter response to input
overcurrent events
Shutdown, do not
restart
R
C0h
Sets the value in amperes that
causes the over current warning
condition of the input current
RW,
NVM
63.5 A
F87Fh
Sets the time, in milliseconds, from
when a start condition is received (as
programmed by the
ON_OFF_CONFIG command) until
the output voltage starts to rise.
RW,
2.43 ms (Ch A)
60h TON_DELAY
C26Eh
C26Eh
NVM 2.43 ms (Ch B)
The PIN_OP_WARN_LIMIT
command sets the value of the input
power, in watts, that causes a
warning that the input power is high
6Bh PIN_OP_WARN_LIMIT
RW
450 W
08E1h
78h STATUS_BYTE
79h STATUS_WORD
7Ah STATUS_VOUT
7Bh STATUS_IOUT
7Ch STATUS_INPUT
7Dh STATUS_TEMPERATURE
7Eh STATUS_CML
PMBus read-only status and flag bits.
PMBus read-only status and flag bits.
PMBus read-only status and flag bits.
PMBus read-only status and flag bits.
PMBus read-only status and flag bits.
PMBus read-only status and flag bits.
PMBus read-only status and flag bits.
PMBus read-only status and flag bits.
Returns the input voltage in volts
RW
RW
RW
RW
RW
RW
RW
RW
R
Current Status
Current Status
Current Status
Current Status
Current Status
Current Status
Current Status
Current Status
Current Status
Current Status
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
80h STATUS_MFR_SPECIFIC
88h READ_VIN
N/A
N/A
89h READ_IIN
Returns the input current in amperes
R
Returns the output voltage in VID
format
8Bh READ_VOUT
R
R
R
Current Status
Current Status
Current Status
N/A
N/A
N/A
N/A
Returns the output current in
amperes
8Ch READ_IOUT
Returns the highest power stage
temperature in °C
8Dh READ_TEMPERATURE_1
N/A
N/A
N/A
N/A
96h READ_POUT
97h READ_PIN
Returns the output power in Watts
Returns the input power in Watts
R
R
Current Status
Current Status
N/A
33h
Returns the version of the PMBus
specification to which this device
complies
PMBus 1.3
Part I, Part II
98h PMBUS_REVISION
R
Loads the unit with bits that contain
the manufacturer’s ID
RW,
NVM user
Arbitrary NVM for
99h MFR_ID
0000h
0000h
0400h
1103h
Loads the unit with bits that contain
the manufacturer’s model number
RW,
NVM user
Arbitrary NVM for
9Ah MFR_MODEL
9Bh MFR_REVISION
Loads the unit with bits that contain
the manufacturer’s model revision
RW,
NVM user
Arbitrary NVM for
Loads the unit with bits that contain
the manufacture date
RW,
NVM
9Dh MFR_DATE
9Eh MFR_SERIAL
ADh IC_DEVICE_ID
March 2017
NVM Checksum
R
NVM checksum
TPS53681
484D2979h
81h
Returns a number indicating the part
number of the device
R
Returns a number indicating the
device revision
AEh IC_DEVICE_REV
B0h USER_DATA_00
B1h USER_DATA_01
R
Rev 1.0
Current
00h
RW
Factory Default
Settings
Used for batch NVM programming.
Used for batch NVM programming.
NVM configuration
RW Current
NVM configuration
Factory Default
Settings
48
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
CMD
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
Default Value
R/W,
NVM
Command Name
Description
Default Behavior
Ch. A
Ch. B
(PAGE 0)
PAGE 1
RW
Current
Factory Default
B2h USER_DATA_02
B3h USER_DATA_03
B4h USER_DATA_04
B5h USER_DATA_05
B6h USER_DATA_06
B7h USER_DATA_07
B8h USER_DATA_08
B9h USER_DATA_09
BAh USER_DATA_10
BBh USER_DATA_11
BCh USER_DATA_12
Used for batch NVM programming.
Used for batch NVM programming.
Used for batch NVM programming.
Used for batch NVM programming.
Used for batch NVM programming.
Used for batch NVM programming.
Used for batch NVM programming.
Used for batch NVM programming.
Used for batch NVM programming.
Used for batch NVM programming.
Used for batch NVM programming.
NVM configuration
RW Current
NVM configuration
RW Current
NVM configuration
RW Current
NVM configuration
RW Current
NVM configuration
RW Current
NVM configuration
RW Current
NVM configuration
RW Current
NVM configuration
RW Current
NVM configuration
RW Current
NVM configuration
RW Current
NVM configuration
Settings
Factory Default
Settings
Factory Default
Settings
Factory Default
Settings
Factory Default
Settings
Factory Default
Settings
Factory Default
Settings
Factory Default
Settings
Factory Default
Settings
Factory Default
Settings
Factory Default
Settings
Configures per-phase overcurrent
levels, current share thresholds, and
other miscellaneous settings.
RW
Misc. configuration,
D0h MFR_SPECIFIC_00
0006h
3006h
NVM See register maps
Returns information regarding current
imbalance warnings for each phase
D3h MFR_SPECIFIC_03
D4h MFR_SPECIFIC_04
R
R
Current status
Current status
0 mV offset
N/A
N/A
Returns the output voltage for the
active channel, in linear format
N/A
00h
N/A
00h
Used to trim the output voltage of the
active channel, by applying an offset
to the currently selected VID code.
RW
D5h MFR_SPECIFIC_05
D6h MFR_SPECIFIC_06
D7h MFR_SPECIFIC_07
D8h MFR_SPECIFIC_08
D9h MFR_SPECIFIC_09
NVM (Ch A and Ch B)
Configures dynamic load line options
for both channels, and selects Auto-
DCM operation.
RW Misc. configuration,
NVM See register maps
0000h
118Fh
00h
0000h
118Fh
00h
Misc. configuration,
See to register
maps
Configures the internal loop
compensation for both channels.
RW
NVM
Used to identify catastrophic faults
which occur first, and store this
information to NVM
RW
Current status
NVM
Used to configure non-linear transient
performance enhancements such as
undershoot reduction (USR)
RW
Misc. configuration,
76C7h
06C7h
NVM See register maps
Used to configure input current
sensing, and set the maximum output
current
RW
Misc. configuration,
DAh MFR_SPECIFIC_10
DBh MFR_SPECIFIC_11
DCh MFR_SPECIFIC_12
C81Ah
33h
001Ah
33h
NVM See register maps
RW
VID 51d (Ch A)
Boot-up VID code for each channel
NVM VID 51d (Ch B)
Used to configure input current
sensing and other miscellaneous
settings
RW
Misc. configuration,
C704h
0700h
NVM See register maps
Used to configure output voltage slew
rates, DAC stepsize, and other
miscellaneous settings.
RW
Misc. configuration,
DDh MFR_SPECIFIC_13
8825h
0025h
NVM See register maps
Copyright © 2017–2019, Texas Instruments Incorporated
49
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
Default Value
R/W,
NVM
CMD
Command Name
Description
Default Behavior
Ch. A
Ch. B
(PAGE 0)
PAGE 1
Used to configure dynamic phase
shedding, and compensation ramp
amplitude, and dynamic ramp
amplitude during USR, and different
power states
RW
Misc. configuration,
DEh MFR_SPECIFIC_14
0005h
0005h
NVM See register maps
Used to configure dynamic phase
shedding.
RW
Misc. configuration,
DFh MFR_SPECIFIC_15
E4h MFR_SPECIFIC_20
F0h MFR_SPECIFIC_32
FAh MFR_SPECIFIC_42
1FFAh
0000h
NVM See register maps
Used to set the maximum operational
phase number, on-the-fly.
RW Misc. configuration,
NVM See register maps
Hardware Configured
00E1h
Used to set the input over-power
warning
RW
450 W
RW
NVM
NVM Security
NVM Security Key
0000h
50
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
7.5.4 Commonly Used PMBus Commands
The following sections describe the most commonly used PMBus commands and their usage in the
configuration, operation and testing of TPS53681 power solutions:
•
•
•
•
•
•
•
•
•
•
•
•
Voltage, Current, Power, and Temperature Readings
Input Current Sense and Calibration
Output Current Sense and Calibration
Output Voltage Margin Testing
Loop Compensation
Converter Protection and Response
Dynamic Phase Shedding
NVM Programming
NVM Security
Black Box Fault Recording
Board Identification and Inventory Tracking
Status Reporting
版权 © 2017–2019, Texas Instruments Incorporated
51
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
7.5.5 Voltage, Current, Power, and Temperature Readings
Using an internal ADC, the TPS53681 provides a full set of telemetry capabilities, allowing the user to read back
critical information about the converter's input voltage, input current, input power, output voltage, output current,
output power and temperature. The table below summarizes the available commands and their formats. Register
maps for each command are included.
表 5. Telemetry Functions
Command
Description
Format
Units
Channel/Phase
Shared, Channel
A and B
READ_VIN
READ_IIN
Input voltage telemetry
Linear
V
Shared, Channel
A and B
Input current telemetry
Linear
VID
A
VID Code
A
READ_VOUT
READ_IOUT
Output voltage telemetry (VID format)
Output current telemetry
Per Channel
Per Channel and Per
Phase
Linear
Per Channel,
Highest phase
temperature only
READ_TEMPERATURE_1
Power stage temperature telemetry
Linear
°C
READ_POUT
READ_PIN
Output power telemetry
Linear
Linear
Linear
W
W
V
Per Channel
Shared, Channel
A and B
Input power telemetry
MFR_SPECIFIC_04
Output voltage telemetry (linear format)
Per Channel
7.5.5.1 (88h) READ_VIN
The READ_VIN command returns the input voltage in volts. The two data bytes are formatted in the Linear Data
format. The refresh rate is 1200 µs. This command should be accessed through Read Word transactions, and is
shared between channel A and channel B.
15
R
14
R
13
12
R
11
R
10
R
9
8
R
R
R
READ_VIN_EXP
READ_VIN_MAN
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
READ_VIN_MAN
LEGEND: R/W = Read/Write; R = Read only
图 15. READ_VIN
表 6. READ_VIN Register Field Descriptions
Bit
Field
Type
Reset
Description
Current
Status
Linear two's complement format exponent.
Linear two's complement format mantissa.
15:11
READ_VIN_EXP
R
Current
Status
10:0
READ_VIN_MAN
R
7.5.5.2 (89h) READ_IIN
The READ_IIN command returns the input current in amperes. The refresh rate is 100 µs. The two data bytes
are formatted in the Linear Data format. This command should be accessed through Read Word transactions,
and is shared between channel A and channel B.
52
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
15
R
14
R
13
12
R
11
R
10
R
9
8
R
R
R
READ_IIN_EXP
READ_IIN_MAN
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
READ_IIN_MAN
LEGEND: R/W = Read/Write; R = Read only
图 16. READ_IIN
表 7. READ_IIN Register Field Descriptions
Bit
Field
Type
Reset
Description
Current
Status
Linear two's complement format exponent.
Linear two's complement format mantissa.
15:11
READ_IIN_EXP
R
Current
Status
10:0
READ_IIN_MAN
R
7.5.5.3 (8Bh) READ_VOUT
The READ_VOUT command returns the actual, measured output voltage. The two data bytes are formatted in
the VID Data format, and the refresh rate is 1200 us. This command should be accessed through Read Word
transactions. READ_VOUT is a paged register. In order to access READ_VOUT command for channel A, PAGE
must be set to 00h. In order to access READ_VOUT register for channel B, PAGE must be set to 01h.
15
R
14
R
13
R
12
R
11
R
10
R
9
R
0
8
R
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
READ_VOUT_VID
LEGEND: R/W = Read/Write; R = Read only
图 17. READ_VOUT
表 8. READ_VOUT Register Field Descriptions
Bit
Field
Type
Reset
Description
Current
Status
Output voltage, VID format
7:0
READ_VOUT_VID
R
7.5.5.4 (8Ch) READ_IOUT
The READ_IOUT command returns the output current in amperes. The update rate is 100us. READ_IOUT is a
linear format command, and must be accessed through Read Word Transactions.
READ_IOUT is a paged register. In order to access READ_IOUT for channel A, PAGE must be set to 00h. In
order to access the READ_IOUT register for channel B, PAGE must be set to 01h. For simultaneous access of
channels A and B, the PAGE command must be set to FFh. READ_IOUT is also a phased register. Depending
on the configuration of the design, for channel A, PHASE must be set to 00h to access Phase 1, 01h to access
Phase 2, etc... PHASE must be set to FFh to access all phases simultaneously. PHASE may also be set to 80h
to readack the total phase current (sum of all active phase currents for the active channel) measurement, as
described in Output Current Sense and Calibration. Note that READ_IOUT is only a phased command for
Channel A (PAGE 0).
版权 © 2017–2019, Texas Instruments Incorporated
53
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
15
R
14
R
13
12
R
11
R
10
R
9
8
R
R
R
READ_IOUT_EXP
READ_IOUT_MAN
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
READ_IOUT_MAN
LEGEND: R/W = Read/Write; R = Read only
图 18. READ_IOUT
表 9. READ_IOUT Register Field Descriptions
Bit
Field
Type
Reset
Description
Current
Status
Linear two's complement format exponent.
Linear two's complement format mantissa.
15:11
READ_IOUT_EXP
R
Current
Status
10:0
READ_IOUT_MAN
R
Attempts to write to this command results in invalid transactions. The device ignores the invalid data, sets the
appropriate flags in STATUS_CML and STATUS_WORD, and asserts the PMB_ALERT signal to notify the
system host of an invalid transaction.
7.5.5.5 (8Dh) READ_TEMPERATURE_1
The READ_TEMPERATURE_1 command returns the temperature in degree Celsius. The refresh rate is 1200
us.
READ_TEMPERATURE_1 is a linear format command. The READ_TEMPERATURE_1 command must be
accessed through Read Word transactions.
READ_TEMPERATURE_1 is a paged register. In order to access READ_TEMPERATURE_1 command for
channel A, PAGE must be set to 00h. In order to access READ_TEMPERATURE_1 register for channel B,
PAGE must be set to 01h. For simultaneous access of channels A and B, the PAGE command must be set to
FFh.
15
R
14
R
13
12
R
11
R
10
R
9
8
R
R
R
READ_TEMP_EXP
READ_TEMP_MAN
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
READ_TEMP_MAN
LEGEND: R/W = Read/Write; R = Read only
图 19. READ_TEMPERATURE_1
表 10. READ_TEMPERATURE_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
Current
Status
Linear two's complement format exponent.
15:11
READ_TEMP_EXP
R
Current
Status
Linear two's complement format mantissa.
10:0
READ_TEMP_MAN
R
54
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
Attempts to write to this command results in invalid transactions. The device ignores the invalid data, sets the
appropriate flags in STATUS_CML and STATUS_WORD, and asserts the PMB_ALERT signal to notify the
system host of an invalid transaction
7.5.5.6 (96h) READ_POUT
The READ_POUT command returns the calculated output power, in watts for the active channel. The refresh
rate is 1200 µs.
READ_POUT is a linear format command. The READ_POUT command must be accessed through Read Word
transactions.
READ_POUT is a paged register. In order to access READ_POUT command for channel A, PAGE must be set
to 00h. In order to access READ_POUT register for channel B, PAGE must be set to 01h. For simultaneous
access of channels A and B, the PAGE command must be set to FFh.
15
R
14
R
13
12
R
11
R
10
R
9
8
R
R
R
READ_POUT_EXP
READ_POUT_MAN
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
READ_POUT_MAN
LEGEND: R/W = Read/Write; R = Read only
图 20. READ_POUT
表 11. READ_POUT Register Field Descriptions
Bit
Field
Type
Reset
Description
Current
Status
Linear two's complement format exponent.
Linear two's complement format mantissa.
15:11
READ_POUT_EXP
R
Current
Status
10:0
READ_POUT_MAN
R
Attempts to write to this command results in invalid transactions. The device ignores the invalid data, sets the
appropriate flags in STATUS_CML and STATUS_WORD, and asserts the PMB_ALERT signal to notify the
system host of an invalid transaction
7.5.5.7 (97h) READ_PIN
The READ_PIN command returns the calculated input power. The refresh rate is 1200 µs.
READ_PIN is a linear format command. The READ_PIN command must be accessed through Read Word
transactions.
The READ_PIN command is shared between Channel A and Channel B. All transactions to this command will
affect both channels regardless of the PAGE command.
15
R
14
R
13
12
R
11
R
10
R
9
8
R
R
R
READ_PIN_EXP
READ_PIN_MAN
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
READ_PIN_MAN
LEGEND: R/W = Read/Write; R = Read only
图 21. READ_PIN
版权 © 2017–2019, Texas Instruments Incorporated
55
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
表 12. READ_PIN Register Field Descriptions
Bit
Field
Type
Reset
Description
Current
Status
Linear two's complement format exponent.
15:11
READ_PIN_EXP
R
Current
Status
Linear two's complement format mantissa.
10:0
READ_PIN_MAN
R
7.5.5.8 (D4h) MFR_SPECIFIC_04
The MFR_SPECIFIC_04 command is used to return the output voltage for the active channel, in the linear
format (READ_VOUT uses VID format).
The MFR_SPECIFIC_04 command must be accessed through Read Word transactions. MFR_SPECIFIC_04 is a
Linear format command.
MFR_SPECIFIC_04 is a paged register. In order to access MFR_SPECIFIC_04 command for channel A, PAGE
must be set to 00h. In order to access the MFR_SPECIFIC_04 register for channel B, PAGE must be set to 01h.
15
R
14
R
13
12
R
11
R
10
R
9
8
R
R
R
VOUT_LIN_EXP
VOUT_LIN_MAN
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
VOUT_LIN_MAN
LEGEND: R/W = Read/Write; R = Read only
图 22. MFR_SPECIFIC_04
表 13. MFR_SPECIFIC_04 Register Field Descriptions
Bit
Field
Type
Reset
Description
Current
Status
Linear format two's complement exponent.
Linear format two's complement mantissa.
15:11
VOUT_LIN_EXP
R
Current
Status
10:0
VOUT_LIN_MAN
R
56
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
7.5.6 Input Current Sense and Calibration
The READ_IIN command reports the total input current to both channels. TPS53681 supports shunt or inductor
DCR sensing. The section below describes how to calibrate the gain and offset of the sensed signal for accurate
input current reporting. When input current sensing is not used, the CSPIN and VIN_CSNIN pins should be
shorted together and connected to the power input voltage.
7.5.6.1 Measured Input Current Calibration
The TPS53681 reports input current via an integrated current sense interface on the CSPIN and VIN_CSNIN
pins. A conceptual block diagram is shown in 图 23. This circuit must be calibrated to the value of the sense
element, RSENSE (e.g. shunt resistance or DCR), chosen. The values of AIIN, IIN_MAX and IIN_OFS may be used
to calibrate input current sensing. These settings are programmed using the MFR_SPECIFIC_10 and
MFR_SPECIFIC_12 commands.
Input Voltage
CSPIN
+
-
+
RSENSE
ADC
READ_IIN
œ
AIIN
IIN_MAX
IIN_OFS
VIN_CSNIN
Input to
Power Stages
图 23. Measured Input Current Interface
The IIN_RGAIN bits in MFR_SPECIFIC_12, and the IIN_GAIN_CTRL bit in MFR_SPECIFIC_10 select AIIN, the
gain of the analog input current sense interface. Refer to 表 18 for a table of supported AIIN values. Note that the
analog gain setting also corresponds to maximum allowed signal level and measured input current according to
表 14.
表 14. AIIN, Input Current Sense Analog Gain
Maximum Supported
(CSPIN–VIN_CSNIN)
Voltage
Maximum Supported
Input Current
IIN_GAIN_CTRL
( MFR_SPECIFIC_10)
IIN_RGAIN
( MFR_SPECIFIC_12)
Effective AIIN
Measurement
0b
0b
0b
0b
1b
1b
1b
1b
00b
01b
10b
11b
00b
01b
10b
11b
0.15 mΩ
0.25 mΩ
0.3 mΩ
0.5 mΩ
1.2 mΩ
2.0 mΩ
2.4 mΩ
4.0 mΩ
7.5 mV
12.5 mV
15.0 mV
25.0 mV
7.5 mV
50.0 A
50.0 A
50.0 A
50.0 A
6.25 A
6.25 A
6.25 A
6.25 A
12.5 mV
15.0 mV
25.0 mV
The IIN_MAX bits in MFR_SPECIFIC_10 may also be used to digitally calibrate the gain of the input current
reporting. Changing IIN_MAX allows the user to achieve fine gain calibration of the input current sense circuit, as
well as support sense element resistor values other than those directly supported using AIIN
.
The nominal value of IIN_MAX is 50d. When the sense element resistance and AIIN are equal, IIN_MAX should
remain set to 50d. Changing IIN_MAX adjusts the current sense gain ratiometrically with respect to the nominal
value of 50d. For example, changing IIN_MAX to 25d, reduces the effective gain by a factor of 2, and changing
IIN_MAX to 10d, reduces the effective gain by a factor of 5. IIN_MAX has a maximum value of 64d. When using
a sense element RSENSE not equal to one of the supported AIIN values, the IIN_MAX register must be adjusted
according to 公式 3 to achieve accurate gain calibration.
版权 © 2017–2019, Texas Instruments Incorporated
57
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
AIIN
IIN_MAX = 50d ×
RSENSE
(3)
The IIN_OFS bits in MFR_SPECIFIC_10 may also be used to apply an offset to the sensed current in amperes.
Example #1: 0.5 mΩ RSENSE
With a 0.5 mΩ sense element value, for example, (VCSPIN - VVIN_CSNIN) = 10 mV corresponds to 20 A current.
Select the analog interface gain, AIIN =0.5 mΩ, since this selection is available in 表 18, and do not apply any
scaling via IIN_MAX (set it to 50d).
1. Select the value of AIIN that most closely matches the target sense resistance. In this case, AIIN = 0.5 mΩ is
available, which gives IIN_RGAIN = 11b, and IIN_GAIN_CTRL = 0b.
2. Set IIN_MAX = 50d × (0.5 mΩ / 0.5 mΩ) = 50d
3. Set IIN_OFS = 0 A to start with, and tune as needed based on measurements.
Example #2: 1.0 mΩ RSENSE
With a 1.0 mΩ sense element value, for example, (VCSPIN - VVIN_CSNIN) = 10 mV corresponds to 10 A current.
With the analog interface gain, AIIN set to 0.5 mΩ, 10 mV would be interpreted as 20 A. Therefore apply IIN_MAX
= 50*(0.5 mΩ / 1 mΩ) to reduce the effective gain by a factor of 2, so 10 mV is interpreted as 10 A.
1. Select the value of AIIN that most closely matches the target sense resistance. In this case, 1.0 mΩ is not
directly available. Select AIIN = 0.5 mΩ , which gives IIN_RGAIN = 11b, and IIN_GAIN_CTRL = 0b.
2. Set IIN_MAX = 50d × (0.5 mΩ / 1.0 mΩ) = 25d
3. Set IIN_OFS = 0 A to start with, and tune as needed based on measurements.
7.5.6.2 (DAh) MFR_SPECIFIC_10
The MFR_SPECIFIC_10 command is used to configure input current sensing, and set the maximum output
current. These values are used for input current and output current telemetry.
The MFR_SPECIFIC_10 command must be accessed through Write Word/Read Word transactions.
MFR_SPECIFIC_10 is a paged register. In order to access MFR_SPECIFIC_10 command for channel A, PAGE
must be set to 00h. In order to access the MFR_SPECIFIC_10 register for channel B, PAGE must be set to 01h.
Note that input current calibration is shared across both channels, but the configuration makes use of both
PAGEs.
15
14
13
12
11
R
10
9
8
RW
RW
RW
RW
RW
RW
RW
IIN_MAX (PAGE 0, bits 15:8)
IIN_GAIN_CTRL (PAGE 1, bit 13)
IIN_OFS (PAGE 1, bits 12:8)
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
IOUT_MAX (PAGE 0, PAGE 1)
LEGEND: R/W = Read/Write; R = Read only
图 24. MFR_SPECIFIC_10
表 15. MFR_SPECIFIC_10 Register Field Descriptions
Bit
Field
Type
Reset
Description
Maximum IIN setting. LSB = 0.25 A. Valid values range from 0 A
to 63.75 A.
15:8
IIN_MAX (PAGE 0)
RW
NVM
Used to increase the effective IIN_RGAIN. See
MFR_SPECIFIC_12 for more information.
13
12:8
7:0
IIN_GAIN_CTRL (PAGE 1)
IIN_OFS (PAGE 1)
IOUT_MAX
RW
RW
RW
NVM
NVM
NVM
Input current sense offset calibration. See 表 16.
Sets the maximum output current for each channel (PAGE 0 for
channel A, PAGE 1 for channel B). LSB = 1 A.
58
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
表 16. Input Current Offset Calibration Settings
IIN_OFS (hex)
00h
IIN Offset (A)
0
01h
0.1
02h
0.2
03h
0.3
04h
0.4
05h
0.5
06h
0.6
07h
0.7
08h
0.8
09h
0.9
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
1.0
1.1
1.2
1.3
1.4
1.5
-1.6
-1.5
-1.4
-1.3
-1.2
-1.1
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
7.5.6.3 (DCh) MFR_SPECIFIC_12
The MFR_SPECIFIC_12 command is used to configure input current sensing.
The MFR_SPECIFIC_12 command must be accessed through Write Word/Read Word transactions.
MFR_SPECIFIC_12 is a paged register, but all relevant configuration bits are associated with PAGE 0. PAGE
should be set to 00h when accessing MFR_SPECIFIC_12.
15
14
13
R
12
11
10
RW
9
8
RW
RW
RW
RW
RW
RW
IIN_RGAIN
0
TI_INTERNAL
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
TI_INTERNAL
LEGEND: R/W = Read/Write; R = Read only
版权 © 2017–2019, Texas Instruments Incorporated
59
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
图 25. MFR_SPECIFIC_12
表 17. MFR_SPECIFIC_12 Register Field Descriptions
Bit
Field
Type
Reset
Description
Input shunt resistance value. Combined with IIN_RGAIN,
IIN_OFS, IIN_MAX to calibrate measured input current sensing.
Note that finer adjustments can be made using IIN_MAX.
15:14
IIN_RGAIN (PAGE 0 only)
RW
NVM
TI Internal bits. These bits are writeable, but should not be
modified from their factory default setting.
12:0
TI_INTERNAL
RW
NVM
表 18. AIIN, Input Current Sense Analog Gain(1)
IIN_GAIN_CTRL
( MFR_SPECIFIC_10)
IIN_RGAIN
( MFR_SPECIFIC_12)
Effective AIIN
0b
0b
0b
0b
1b
1b
1b
1b
00b
01b
10b
11b
00b
01b
10b
11b
0.15 mΩ
0.25 mΩ
0.3 mΩ
0.5 mΩ
1.2 mΩ
2.0 mΩ
2.4 mΩ
4.0 mΩ
(1) See Also 表 14
表 19. Maximum Temperature Settings
TMAX (binary)
Maximum Temperature (°C)
000b
001b
010b
011b
100b
101b
110b
111b
90
95
100
105
110
115
120
125
60
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
7.5.7 Output Current Sense and Calibration
The READ_IOUT command may be used to read the individual phase currents, and the total channel current.
7.5.7.1 Reading Individual Phase Currents
Using the PAGE and PHASE commands, the TPS53681 can be configured to return output current information
for each individual phase. The examples below demonstrate this process:
Example #1: Read back the output current of Channel A, First Phase
1. Select Channel A. Write PAGE to 00h
2. Select first phase. Write PHASE to 00h
3. Read READ_IOUT
Example #2: Read back the output current of Channel B, Second Phase
1. Select Channel B. Write PAGE to 01h
2. Select second phase. Write PHASE to 01h
3. Read READ_IOUT
7.5.7.1.1 Reading Total Current
When the PHASE command is set to 80h, the TPS53681 device is configured to return the total channel current
(sum of individual phase currents) in response to the READ_IOUT command.
Example: Read the Total Output Current of Channel A
1. Select Channel A. Write PAGE to 00h
2. Select total current measurement. Write PHASE to 80h
3. Read READ_IOUT
7.5.7.1.2 Calibrating Current Measurements
The IOUT_CAL_GAIN and IOUT_CAL_OFFSET commands are available to allow the user to fine-tune current
measurements. Setting the PHASE command to 80h also allows the total current measurement to be calibrated
in a similar manner. The TI power stage devices supply current information to the controller device, using the
CSPx and CSNx pins, with a scale of 5 mV/A. The IOUT_CAL_GAIN command may be used to fine-tune the
scaling inside the controller to account for any gain mismatch. Likewise, the IOUT_CAL_OFFSET command may
be used to apply an offset to the controller current measurements, to null offset errors.
Example: Calibrating Total Output Current Measurement
1. Select Channel A. Write PAGE to 00h
2. Select the total current. Write PHASE to 80h
3. First read back READ_IOUT under two known output currents:
1. For this example, apply a load of 60 A
2. Read back READ_IOUT, record the value. For this example, consider that READ_IOUT gives 59.0 A.
3. For this example, apply a load of 120 A
4. Read back READ_IOUT, record the value. For this example, consider that READ_IOUT gives 119.6 A
4. Calculate the gain error:
1. The current reading increased (119.6 A - 59.0 A) = 60.6 A for a 60 A current step
2. Hence, the current reading gain is (60.6 A / 60 A ) = 1.01.
3. Ideally, the current reading gain is 1.00, so the readings show a +1% gain error.
5. Apply IOUT_CAL_GAIN to correct the gain error:
1. The gain error is +1%, and the nominal current sense gain is 5 mΩ, so the current sense gain must be
lowered by 1%.
2. Hence, the IOUT_CAL_GAIN should be programmed to 5 mΩ × (1-1%) = 4.95 mΩ
3. Referring to 表 21 the closest acceptable value is 4.953125 mΩ, or D13Dh.
4. Write IOUT_CAL_GAIN to D13Dh.
版权 © 2017–2019, Texas Instruments Incorporated
61
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
6. Determine the offset error at a given point:
1. Apply a known load. In this example, 90 A.
2. Read back READ_IOUT. For this example, consider that READ_IOUT gives 89 A.
3. Hence, the offset error is (89 A - 90A) = -1A.
7. Apply IOUT_CAL_OFFSET to correct the gain error
1. The offset error is -1 A, so an offset of +1 A must be applied.
2. Refer to 表 24, the closest available value of IOUT_CAL_OFFSET is +1.0 A or E808h
3. Write IOUT_CAL_OFFSET to E808h.
8. Issue STORE_DEFAULT_ALL to commit the calibration values to NVM.
7.5.7.2 (38h) IOUT_CAL_GAIN
The IOUT_CAL_GAIN command is used to set the ratio of the voltage at the current sense pins to the sensed
current, in mΩ.
IOUT_CAL_GAIN is a linear format command. The IOUT_CAL_GAIN command must be accessed through Read
Word/Write Word transactions.
IOUT_CAL_GAIN is a paged register. In order to access IOUT_CAL_GAIN for channel A, PAGE must be set to
00h. In order to access the IOUT_CAL_GAIN register for channel B, PAGE must be set to 01h. For simultaneous
access of channels A and B, the PAGE command must be set to FFh. IOUT_CAL_GAIN is also a phased
register. Depending on the configuration of the design, for channel A, PHASE must be set to 00h to access
Phase 1, 01h to access Phase 2, etc... PHASE must be set to FFh to access all phases simultaneously. PHASE
may also be set to 80h to apply IOUT_CAL_GAIN to the total phase current (sum of all active phases for the
current channel) measurement, as described in Output Current Sense and Calibration.
15
R
14
R
13
R
12
R
11
R
10
9
8
RW
RW
RW
IOCG_EXP
IOCG_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
IOCG_MAN
LEGEND: R/W = Read/Write; R = Read only
图 26. IOUT_CAL_GAIN
表 20. IOUT_CAL_GAIN Register Field Descriptions
Bit
Field
Type
Reset
Description
15:11
IOCG_EXP
R
11010b
Linear two's complement exponent, –6. LSB = 0.015625 mΩ
Linear two's complement mantissa. See the table of acceptable
values below.
10:0
IOCG_MAN
RW
NVM
表 21. Acceptable Values of IOUT_CAL_GAIN
IOUT_CAL_GAIN (hex)
D131h
Current Sense Gain (mΩ)
4.765625
D132h
D133h
D134h
D135h
D136h
D137h
D138h
D139h
D13Ah
4.78125
4.796875
4.8125
4.828125
4.84375
4.859375
4.875
4.890625
4.90625
62
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
表 21. Acceptable Values of IOUT_CAL_GAIN (接下页)
IOUT_CAL_GAIN (hex)
D13Bh
D13Ch
D13Dh
D13Eh
D13Fh
Current Sense Gain (mΩ)
4.921875
4.9375
4.953125
4.96875
4.984375
5
D140h
D141h
5.015625
5.03125
5.046875
5.0625
D142h
D143h
D144h
D145h
5.078125
5.09375
5.109375
5.125
D146h
D147h
D148h
D149h
5.140625
5.15625
5.171875
5.1875
D14Ah
D14Bh
D14Ch
D14Dh
D14Eh
D14Fh
5.203125
5.21875
5.234375
5.25
D150h
Attempts to write any value other than those specified above results in invalid transactions. The device ignores
the invalid data, sets the appropriate flags in STATUS_CML and STATUS_WORD, and asserts the PMB_ALERT
signal to notify the system host of an invalid transaction.
7.5.7.3 (39h) IOUT_CAL_OFFSET
The IOUT_CAL_OFFSET command is used to compensate for offset errors in the READ_IOUT command, in
Amperes.
IOUT_CAL_OFFSET is a linear format command. The IOUT_CAL_OFFSET command must be accessed
through Read Word/Write Word transactions
IOUT_CAL_OFFSET is a paged register. In order to access IOUT_CAL_OFFSET for channel A, PAGE must be
set to 00h. In order to access the IOUT_CAL_OFFSET register for channel B, PAGE must be set to 01h. For
simultaneous access of channels A and B, the PAGE command must be set to FFh. IOUT_CAL_OFFSET is also
a phased register. Depending on the configuration of the design, for channel A, PHASE must be set to 00h to
access Phase 1, 01h to access Phase 2, etc... PHASE must be set to FFh to access all phases simultaneously.
PHASE may also be set to 80h to apply IOUT_CAL_OFFSET to the total phase current (sum of all active phases
for the current channel) measurement, as described in Output Current Sense and Calibration.
15
R
14
R
13
R
12
R
11
R
10
9
8
RW
RW
RW
IOCOS_EXP
IOCOS_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
IOCOS_MAN
LEGEND: R/W = Read/Write; R = Read only
版权 © 2017–2019, Texas Instruments Incorporated
63
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
图 27. IOUT_CAL_OFFSET
表 22. IOUT_CAL_OFFSET Register Field Descriptions
Bit
Field
Type
Reset
Description
15:11
IOCOS_EXP
R
11101b
Linear two's complement exponent, –3. LSB = 0.125 A
Linear two's complement mantissa. See the table of acceptable
values below. Note that there is a different set of acceptable
values for individual phases (e.g. PHASE = 00h - 05h, and FFh)
vs. the total current telemetry function (e.g. PHASE = 80h). See
Output Current Sense and Calibration for more information.
10:0
IOCOS_MAN
RW
NVM
表 23. Acceptable Values of IOUT_CAL_OFFSET (Individual Phases, PHASE ≠
80h)
IOUT_CAL_OFFSET (hex)
E800h
Current Sense Offset (A)
0.00
0.125
0.25
E801h
E802h
E803h
0.375
0.5
E804h
E805h
0.625
0.75
E806h
E807h
0.875
1.0
E808h
EFF9h
-0.875
-0.75
-0.625
-0.5
EFFAh
EFFBh
EFFCh
EFFDh
-0.375
-0.25
-0.125
EFFEh
EFFFh
表 24. Acceptable Values of IOUT_CAL_OFFSET (Total Current, PHASE = 80h)
IOUT_CAL_OFFSET (hex)
E800h
Current Sense Offset (A)
0.00
0.25
0.5
E802h
E804h
E806h
0.75
1.0
E808h
E80Ah
1.25
1.5
E80Ch
E80Eh
1.75
2.0
E810h
E812h
2.25
2.5
E814h
E816h
2.75
3.0
E818h
E81Ah
3.25
3.5
E81Ch
E81Eh
3.75
4.0
E820h
64
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
表 24. Acceptable Values of IOUT_CAL_OFFSET (Total Current, PHASE = 80h)
(接下页)
IOUT_CAL_OFFSET (hex)
EFE2h
Current Sense Offset (A)
-3.75
-3.5
EFE4h
EFE6h
-3.25
-3.0
EFE8h
EFEAh
-2.75
-2.5
EFECh
EFEEh
-2.25
-2.0
EFF0h
EFF2h
-1.75
-1.5
EFF4h
EFF6h
-1.25
-1.0
EFF8h
EFFAh
-0.75
-0.5
EFFCh
EFFEh
-0.25
Attempts to write any value other than those specified above results in invalid transactions. The device ignores
the invalid data, sets the appropriate flags in STATUS_CML and STATUS_WORD, and asserts the PMB_ALERT
signal to notify the system host of an invalid transaction.
版权 © 2017–2019, Texas Instruments Incorporated
65
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
7.5.8 Output Voltage Margin Testing
The TPS53681 provides several commands to enable voltage margin testing.
The upper two MARGIN bits in the OPERATION command can be used to toggle the active channel between
three states:
1. Margin None (MARGIN = 0000b). The output voltage target is equal to VOUT_COMMAND.
2. Margin Low (MARGIN = 01xxb). The output voltage target is equal to VOUT_MARGIN_LOW.
3. Margin High (MARGIN = 10xxb). The output voltage target is equal to VOUT_MARGIN_HIGH.
In order to use OPERATION, the active channel must be configured for to respect the OPERATION command,
via ON_OFF_CONFIG. Output voltage transitions will occur at the slew rate defined by
VOUT_TRANSITION_RATE.
The lower two MARGIN bits in the OPERATION command select overvoltage/undervoltage fault handling during
margin testing:
1. Ignore Faults (MARGIN = xx01b) . Overvoltage/Undervoltage faults will not trigger during margin tests.
2. Act on Faults (MARGIN = xx10b). Overvoltage/Undervoltage faults will trigger during margin tests.
Example: Output Voltage Margin Testing (Ignore Faults)
1. Write to the PAGE command to select the desired channel (E.g. PAGE = 00h for channel A).
2. Write VOUT_COMMAND to the desired VID code during Margin None operation.
3. Write VOUT_MARGIN_LOW to the desired VID code during Margin Low operation.
4. Write VOUT_MARGIN_HIGH to the desired VID code during Margin High operation.
5. Set the CMD bit in ON_OFF_CONFIG to 1b to ensure the device is configured to respect the OPERATION
command.
6. Margin None. Write OPERATION to 80h.
7. Margin Low. Write OPERATION to 94h.
8. Margin High. Write OPERATION to A4h.
7.5.8.1 (01h) OPERATION
The OPERATION command is used to turn the device output on or off in conjunction with the input from the
AVR_EN pin for channel A, and BEN pin for channel B, according to the configuration of the ON_OFF_CONFIG
command. It is also used to set the output voltage to the upper or lower MARGIN levels.
OPERATION is a paged register. In order to access OPERATION command for channel A, PAGE must be set to
00h. In order to access OPERATION register for channel B, PAGE must be set to 01h. For simultaneous access
of channels A and B, the PAGE command must be set to FFh.
The OPERATION command must be accessed through Read Byte/Write Byte transactions.
7
6
R
0
5
4
3
2
1
RW
0
0
RW
0
RW
ON
RW
RW
RW
RW
MARGIN
LEGEND: R/W = Read/Write; R = Read only
图 28. OPERATION
66
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
表 25. OPERATION Register Field Descriptions
Bit
Field
Type
Reset
Description
Enable/disable power conversion for the currently selected
channel(s) according to the PAGE command, when the
ON_OFF_CONFIG command is configured to require input from
the ON bit for output control. Note that there may be several
other requirements that must be satisfied before the currently
selected channel(s) can begin converting power (e.g. input
voltages above UVLO thresholds, AVR_EN/BEN pins high if
required by ON_OFF_CONFIG, etc...)
7
ON
RW
0b
0b: Disable power conversion
1b: Enable power conversion
Set the output voltage to either the value selected by the
VOUT_MARGIN_HIGH or MARGIN_LOW commands, for the
currently selected channel(s), according to the PAGE command.
0000b: Margin Off. Output voltage is set to the value of
VOUT_COMMAND
0101b: Margin Low (Ignore Fault). Output voltage is set to the
value of VOUT_MARGIN_LOW.
5:2
1:0
MARGIN
RW
RW
0000b
0110b: Margin Low (Act on Fault). Output voltage is set to the
value of VOUT_MARGIN_LOW.
1001b: Margin High (Ignore Fault). Output voltage is set to the
value of VOUT_MARGIN_HIGH
1010b: Margin High (Act on Fault). Output voltage is set to the
value of VOUT_MARGIN_HIGH.
0
00b
These bits are writeable but should always be set to 00b.
Note that the VOUT_MAX_WARN bit in STATUS_VOUT can be caused by a margin operation, if "Act on Fault"
is selected, and the VOUT_MARGIN_HIGH/VOUT_MARGIN_LOW value loaded by the margin operation
exceeds the value of VOUT_COMMAND.
7.5.8.2 (21h) VOUT_COMMAND
VOUT_COMMAND is used to set the output voltage of the active PAGE.
VOUT_COMMAND is a VID format command. VOUT_COMMAND command must be accessed through Read
Word/Write Word transactions.
VOUT_COMMAND is a paged register. In order to access VOUT_COMMAND for channel A, PAGE must be set
to 00h. In order to access the VOUT_COMMAND register for channel B, PAGE must be set to 01h. For
simultaneous access of channels A and B, the PAGE command must be set to FFh.
15
R
14
R
13
R
12
R
11
R
10
R
9
R
0
8
R
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_CMD_VID
LEGEND: R/W = Read/Write; R = Read only
图 29. VOUT_COMMAND
表 26. VOUT_COMMAND Register Field Descriptions
Bit
Field
Type
Reset
Description
Used to set the commanded VOUT. Cannot be set to a level
above the value set by VOUT_MAX.
7:0
VOUT_CMD_VID
RW
NVM
版权 © 2017–2019, Texas Instruments Incorporated
67
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
7.5.8.3 (26h) VOUT_MARGIN_LOW
The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed when
the OPERATION command is set to “Margin Low”.
VOUT_MARGIN_LOW is a VID format command. The VOUT_MARGIN_LOW command must be accessed
through Read Word/Write Word transactions.
VOUT_MARGIN_LOW is a paged register. In order to access VOUT_MARGIN_LOW for channel A, PAGE must
be set to 00h. In order to access the VOUT_MARGIN_LOW register for channel B, PAGE must be set to 01h.
For simultaneous access of channels A and B, the PAGE command must be set to FFh.
15
R
14
R
13
R
12
R
11
R
10
R
9
R
0
8
R
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_MARGL_VID
LEGEND: R/W = Read/Write; R = Read only
图 30. VOUT_MARGIN_LOW
表 27. VOUT_MARGIN_LOW Register Field Descriptions
Bit
Field
Type
Reset
Description
Used to set the output voltage to be loaded when the active
PAGE is set to Margin Low, in VID format.
7:0
VOUT_MARGL_VID
RW
00h
7.5.8.4 (25h) VOUT_MARGIN_HIGH
The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed when
the OPERATION command is set to “Margin High”.
VOUT_MARGIN_HIGH is a VID format command. The VOUT_MARGIN_HIGH command must be accessed
through Read Word/Write Word transactions.
VOUT_MARGIN_HIGH is a paged register. In order to access VOUT_MARGIN_HIGH for channel A, PAGE must
be set to 00h. In order to access the VOUT_MARGIN_HIGH register for channel B, PAGE must be set to 01h.
For simultaneous access of channels A and B, the PAGE command must be set to FFh.
15
R
14
R
13
R
12
R
11
R
10
R
9
R
0
8
R
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_MARGH_VID
LEGEND: R/W = Read/Write; R = Read only
图 31. VOUT_MARGIN_HIGH
表 28. VOUT_MARGIN_HIGH Register Field Descriptions
Bit
Field
Type
Reset
Description
Used to set the output voltage to be loaded when the active
PAGE is set to Margin High, in VID format.
7:0
VOUT_MARGH_VID
RW
00h
68
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
7.5.9 Loop Compensation
The TPS53681 provides several options for tuning the output voltage feedback and response to transients.
These may be configured by programming the MFR_SPECIFIC_07, VOUT_DROOP, and MFR_SPECIFIC_14.
Several such parameters may be configured through these commands:
•
DC Load Line - Selects the DC shift in output voltage corresponding to increased output current. The DC
load line affects both the final value the output voltage settles to, as well as the settling time. Use the
VOUT_DROOP command to select the DC load line.
•
•
Integration Time Constant - In order to maintain DC accuracy, the control loop includes an integration
stage. Use MFR_SPECIFIC_07 to select the integration time constant.
Integration Path Gain - The gain of the integration and AC paths may be selected independently. The AC
and DC gains both affect the small-signal bandwidth of the converter. Use MFR_SPECIFIC_07 to select the
integration path gain.
•
•
•
AC Load Line - Selects the AC response to output voltage error. The AC load line affects the settling and
response time following a load transient event. Use the MFR_SPECIFIC_07 command to select the AC load
line.
AC Path Gain - The gain of the integration and AC paths may be selected independently. The AC and DC
gains both affect the small-signal bandwidth of the converter. Use MFR_SPECIFIC_07 to select the AC path
gain.
Ramp Amplitude - Smaller ramp settings result in faster response, but may also lead to increased frequency
jitter. Likewise, large ramp settings result in lower frequency jitter, but may be slightly slower to respond to
changing conditions. The ramp setting also affects the small-signal bandwidth of the converter. Use
MFR_SPECIFIC_14 to select the ramp heigh setting.
7.5.9.1 (D7h) MFR_SPECIFIC_07
The MFR_SPECIFIC_07 command is used to configure the internal loop compensation for both channels. The
MFR_SPECIFIC_07 command must be accessed through Write Word/Read Word transactions.
MFR_SPECIFIC_07 is a paged register. In order to access MFR_SPECIFIC_07 command for channel A, PAGE
must be set to 00h. In order to access the MFR_SPECIFIC_07 register for channel B, PAGE must be set to 01h.
15
R
14
R
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
0
0
INT_GAIN
INT_TC
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
AC_GAIN
LEGEND: R/W = Read/Write; R = Read only
ACLL
图 32. MFR_SPECIFIC_07
表 29. MFR_SPECIFIC_07 Register Field Descriptions
Bit
Field
Type
Reset
Description
15:14
Not used
R
0
Not used and set to 0.
13:12
11:8
7:6
INT_GAIN
INT_TC
AC_GAIN
ACLL
RW
RW
RW
RW
NVM
NVM
NVM
NVM
Integration path gain. See 表 30.
Integration time constant. See 表 31.
AC path gain. See 表 32.
AC Load Line. See 表 33.
5:0
表 30. Integration path gain settings
INT_GAIN (binary)
Integration path gain (V/V)
2 × AC_GAIN
00b
01b
10b
1 × AC_GAIN
0.66 × AC_GAIN
版权 © 2017–2019, Texas Instruments Incorporated
69
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
表 30. Integration path gain settings (接下页)
INT_GAIN (binary)
Integration path gain (V/V)
11b
0.5 × AC_GAIN
表 31. Integration time constant settings
INT_TC (binary)
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
Time constant (µs)
5
10
15
20
25
30
35
40
1
2
3
4
5
6
7
8
表 32. AC path gain settings
AC_GAIN (binary)
AC path gain (V/V)
00b
01b
10b
11b
1
1.5
2
0.5
表 33. AC Load line settings
Bin
0
ACLL (hex)
AC Load line (mΩ)
0.0000
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
1
0.1250
2
0.2500
3
0.3125
4
0.3750
5
0.4375
6
0.5000
7
0.5625
8
0.6250
9
0.7500
10
11
12
13
14
15
16
0.7969
0.8125
0.8281
0.8438
0.8594
0.8750
0.8906
70
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
表 33. AC Load line settings (接下页)
Bin
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
ACLL (hex)
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
AC Load line (mΩ)
0.9063
0.9219
0.9375
0.9531
0.9688
0.9844
1.000
1.0156
1.0313
1.0469
1.0625
1.1250
1.2500
1.3750
1.5000
1.6250
1.7500
1.8750
1.9375
2.000
2.0625
2.1250
2.1875
2.2500
2.375
2.4218
2.4375
2.4531
2.4687
2.4843
2.5000
2.5156
2.5312
2.5468
2.5625
2.5781
2.5937
2.609
2.625
2.6406
2.6562
2.6718
2.6875
2.750
2.875
3.000
3.125
版权 © 2017–2019, Texas Instruments Incorporated
71
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
7.5.9.2 (28h) VOUT_DROOP
The VOUT_DROOP command sets the rate, in mV/A (mΩ) at which the output voltage decreases (or increases)
with increasing (or decreasing) output current for use with adaptive voltage positioning. This is also referred to as
the DC Load Line (DCLL).
VOUT_DROOP is a linear format command. The VOUT_DROOP command must be accessed through Read
Word/Write Word transactions.
VOUT_DROOP is a paged register. In order to access VOUT_DROOP for channel A, PAGE must be set to 00h.
In order to access the VOUT_DROOP register for channel B, PAGE must be set to 01h. For simultaneous
access of channels A and B, the PAGE command must be set to FFh.
15
R
14
R
13
12
R
11
R
10
9
RW
8
R
RW
RW
VDROOP_EXP
VDROOP_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VDROOP_MAN
LEGEND: R/W = Read/Write; R = Read only
图 33. VOUT_DROOP
表 34. VOUT_DROOP Register Field Descriptions
Bit
Field
Type
Reset
Description
Linear two's complement fixed exponent, –6. LSB = 0.015625
mΩ
15:11
VDROOP_EXP
R
11010b
Linear two's complement mantissa. See table of acceptable
values below, note that Channel A and Channel B support
different acceptable values of VOUT_DROOP.
10:0
VDROOP_MAN
RW
NVM
The table below summarizes the acceptable values of VOUT_DROOP for channel A and channel B. Attempts to
write any value other than those specified below will be treated as invalid data - invalid data will be ignored, the
appropriate flags in STATUS_CML and STATUS_WORD will be set, and the PMB_ALERT will be asserted to
notify the system host of an invalid transaction.
表 35. Acceptable VOUT_DROOP Values
VOUT_DROOP
(hex)
Supported by
Channel A
Supported by
Channel B
DC Load Line
Bin
(mΩ)
0
1
D000h
D008h
D010h
D014h
D018h
D01Ch
D020h
D024h
D028h
D030h
D033h
D034h
D035h
D036h
D037h
D038h
D039h
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
0
0.125
0.25
2
3
0.3125
0.375
0.4375
0.5
4
5
6
7
0.5625
0.625
0.7031
0.7969
0.8125
0.8281
0.8438
0.8594
0.875
0.8906
8
9
10
11
12
13
14
15
16
72
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
表 35. Acceptable VOUT_DROOP Values (接下页)
VOUT_DROOP
(hex)
Supported by
Channel A
Supported by
Channel B
DC Load Line
Bin
(mΩ)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
D03Ah
D03Bh
D03Ch
D03Dh
D03Eh
D03Fh
D040h
D041h
D042h
D043h
D044h
D048h
D050h
D058h
D060h
D068h
D070h
D078h
D07Ch
D080h
D084h
D088h
D08Ch
D090h
D098h
D09Bh
D09Ch
D09Dh
D09Eh
D09Fh
D0A0h
D0A1h
D0A2h
D0A3h
D0A4h
D0A5h
D0A6h
D0A7h
D0A8h
D0A9h
D0AAh
D0ABh
D0ACh
D0B0h
D0B8h
D0C0h
D0C8h
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
0.9063
0.9219
0.9375
0.9531
0.9688
0.9844
1
1.0156
1.0313
1.0469
1.0625
1.125
1.25
1.375
1.5
1.625
1.75
1.875
1.9375
2
2.0625
2.125
2.1875
2.25
2.328
2.4218
2.4375
2.4531
2.4687
2.4843
2.5
2.5156
2.5312
2.5468
2.5625
2.5781
2.5937
2.609
2.625
2.6406
2.6562
2.6718
2.6875
2.75
2.875
3
3.125
版权 © 2017–2019, Texas Instruments Incorporated
73
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
7.5.10 Converter Protection and Response
The TPS53681 supports a variety of power supply protection features. The table below summarizes these
protection features, and their related PMBus registers. See the following sections for more details.
Table 36. TPS53681 Protection and Response
Threshold
Command Name
Response
Command Name
Default Value
Default Value
Output Voltage
1.520 V (Ch A)
1.520 V (Ch B)
Shutdown,
do not restart
Over-Voltage Protection
VOUT_OV_FAULT_LIMIT
VOUT_MAX
VOUT_OV_FAULT_RESPONSE
Maximum Allowed Output
Voltage
1.520 V (Ch A)
1.520 V (Ch B)
Refer to Register Description
0.000 V (Ch A)
0.000 V (Ch B)
Shutdown,
do not restart
Under-Voltage Protection
VOUT_UV_FAULT_LIMIT
VOUT_MIN
VOUT_UV_FAULT_RESPONSE
Minimum Allowed Output
Voltage
0.000 V (Ch A)
0.000 V (Ch B)
Refer to Register Description
Output Current
IOUT_OC_FAULT_LIMIT
MFR_SPECIFIC_10
39 A (Ch A)
39 A (Ch B)
Shutdown,
do not restart
Over-Current Protection
IOUT_OC_FAULT_RESPONSE
N/A. Warning Only.
26 A (Ch A)
26 A (Ch B)
Over-Current Warning
IOUT_OC_WARN_LIMIT
Input Voltage
Turn-On Threshold
VIN_ON
6.25 V
N/A
Continue
Uninterrupted
Over-Voltage Protection
VIN_OV_FAULT_LIMIT
14.00 V
VIN_OV_FAULT_RESPONSE
Shutdown,
do not restart
Under-Voltage Protection
Input Current
VIN_UV_FAULT_LIMIT
5.50 V
VIN_UV_FAULT_RESPONSE
Shutdown,
do not restart
Over-Current Protection
IIN_OC_FAULT_LIMIT
IIN_OC_WARN_LIMIT
63.5 A
63.5 A
IIN_OC_FAULT_RESPONSE
N/A. Warning Only
Over-Current Warning
Temperature
Over-Temperature
Protection
135 °C (Ch A)
135 °C (Ch B)
Shutdown,
do not restart
OT_FAULT_LIMIT
OT_FAULT_RESPONSE
N/A. Warning Only.
105 °C (Ch A)
105 °C (Ch B)
Over-Temperature Warning OT_WARN_LIMIT
74
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
7.5.11 Output Overvoltage Protection and Response
The output overvoltage thresholds track the configured maximum output voltage, VOUT_MAX, with a fixed offset,
and may be read back in VID format via the read-only VOUT_OV_FAULT_LIMIT command. The converter
response to an overvoltage fault is configured by the read-only VOUT_OV_FAULT_RESPONSE command.
7.5.11.1 (40h) VOUT_OV_FAULT_LIMIT
The VOUT_OV_FAULT_LIMIT is used to read back the value of the output voltage measured at the sense or
output pins that causes an output overvoltage fault in VID format. VOUT_OV_FAULT_LIMIT is a VID format
command, and must be accessed through Read Word/Write Word transactions. VOUT_OV_FAULT_LIMIT is a
paged register. In order to access VOUT_OV_FAULT_LIMIT for channel A, PAGE must be set to 00h. In order to
access the VOUT_OV_FAULT_LIMIT register for channel B, PAGE must be set to 01h. For simultaneous access
of channels A and B, the PAGE command must be set to FFh.
15
R
14
R
13
R
12
R
11
R
10
R
9
R
0
8
R
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
VO_OVF_VID
LEGEND: R/W = Read/Write; R = Read only
图 34. VOUT_OV_FAULT_LIMIT
表 37. VOUT_OV_FAULT_LIMIT Register Field Descriptions
Bit
Field
Type
Reset
Description
Read-only overvoltage fault limit, in VID format.
See
below.
7:0
VO_OVF_VID
R
When the 5-mV DAC mode VID table is selected via MFR_SPECIFIC_13, the VOUT_OV_FAULT_LIMIT register
will be set to FFh. When the 10-mV DAC mode VID table is enabled, the VOUT_OV_FAULT_LIMIT is
determined according to the value of VOUT_MAX, with a fixed offset applied.
7.5.11.2 (41h) VOUT_OV_FAULT_RESPONSE
The VOUT_OV_FAULT_RESPONSE instructs the device on what action to take in response to an output
overvoltage fault. The VOUT_OV_FAULT_RESPONSE command must be accessed through Read Byte
transactions. The VOUT_OV_FAULT_RESPONSE command is shared between Channel A and Channel B. All
transactions to this command will affect both channels regardless of the PAGE command.
Upon triggering the over-voltage fault, the controller is latched off, and the following actions are taken:
•
•
•
•
Set the VOUT_OV_FAULT bit in the STATUS_BYTE
Set the VOUT bit in the STATUS_WORD
Set the VOUT_OV_FAULT bit in the STATUS_VOUT register
The device notifies the host (asserts PMB_ALERT, if the corresponding mask bit in SMBALERT_MASK is not
set)
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
VO_OV_RESP
LEGEND: R/W = Read/Write; R = Read only
图 35. VOUT_OV_FAULT_RESPONSE
版权 © 2017–2019, Texas Instruments Incorporated
75
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
表 38. VOUT_OV_FAULT_RESPONSE Register Field Descriptions
Bit
Field
Type
Reset
Description
80h: Latch-off and do not restart. To clear a shutdown event due
to a fault event, the user must toggle the AVR_EN/BEN pin
and/or the ON bit in OPERATION, per the settings in
ON_OFF_CONFIG, or power cycle the bias power to the V3P3
pin of the controller device.
7:0
VO_OV_RESP
R
80h
7.5.12 Maximum Allowed Output Voltage Setting
The VOUT_MAX command sets an upper limit on the output voltage that the unit may be commanded to,
regardless of an other commands or combinations. The intent of this command is to provide a safeguard against
a user accidentally setting the output voltage to a possibly destructive level.
7.5.12.1 (24h) VOUT_MAX
The VOUT_MAX command sets an upper limit on the output voltage that the unit may be commanded to,
regardless of an other commands or combinations. The intent of this command is to provide a safeguard against
a user accidentally setting the output voltage to a possibly destructive level. VOUT_MAX is a VID format
command, and must be accessed through Read Word/Write Word transactions. VOUT_MAX is a paged register.
In order to access VOUT_MAX for channel A, PAGE must be set to 00h. In order to access the
VOUT_COMMAND register for channel B, PAGE must be set to 01h. For simultaneous access of channels A
and B, the PAGE command must be set to FFh.
The device detects that an attempt has been made to program the output to a voltage greater than the value set
by the VOUT_MAX command. Attempts to program the output voltage greater than VOUT_MAX can include
VOUT_COMMAND attempts, and margin events where the VOUT_MARGIN_HIGH/VOUT_MARGIN_LOW
values exceed the value of VOUT_MAX. These events will be treated as warning conditions and not as fault
conditions. If an attempt is made to program the output voltage higher than the limit set by the VOUT_MAX
command,
the
device
will
respond
as
follows:
•
•
•
•
•
The commanded output voltage will be clamped to VOUT_MAX,
The OTHER bit will be set in the STATUS_BYTE,
The VOUT bit will be set in the STATUS_WORD,
The VOUT_MIN_MAX warning bit will be set in the STATUS_VOUT register, and
The device notifies the host (asserts PMB_ALERT, if the corresponding mask bit in SMBALERT_MASK is not
set).
This register should be programmed by the user depending upon the maximum output voltage the converter can
support.
15
R
14
R
13
R
12
R
11
R
10
R
9
R
0
8
R
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_MAX_VID
LEGEND: R/W = Read/Write; R = Read only
图 36. VOUT_MAX
表 39. VOUT_MAX Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
VOUT_MAX_VID
RW
NVM
Used to set the maximum VOUT of the device in VID format.
76
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
7.5.13 Output Undervoltage Protection and Response
The output undervoltage protection threshold is configured based on commanded output voltage,
VOUT_COMMAND, including the shift due to the DC load line, and a fixed offset. The undervoltage threshold
may be read back in VID format via the read-only VOUT_UV_FAULT_LIMIT command. The converter response
to an undervoltage fault is configured by the read-only VOUT_UV_FAULT_RESPONSE command.
7.5.13.1 (44h) VOUT_UV_FAULT_LIMIT
The VOUT_UV_FAULT_LIMIT is used to read back the value of the output voltage measured at the sense or
output pins that causes an output undervoltage fault in VID format. VOUT_UV_FAULT_LIMIT is a VID format
command, and must be accessed through Read Word transactions. VOUT_UV_FAULT_LIMIT is a paged
register. In order to access VOUT_UV_FAULT_LIMIT for channel A, PAGE must be set to 00h. In order to
access the VOUT_UV_FAULT_LIMIT register for channel B, PAGE must be set to 01h. For simultaneous access
of channels A and B, the PAGE command must be set to FFh.
15
R
14
R
13
R
12
R
11
R
10
R
9
R
0
8
R
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
VO_UVF_VID
LEGEND: R/W = Read/Write; R = Read only
图 37. VOUT_UV_FAULT_LIMIT
表 40. VOUT_UV_FAULT_LIMIT Register Field Descriptions
Bit
Field
Type
Reset
Description
Read-only undervoltage fault limit, in VID format.
See
below.
7:0
VO_UVF_VID
R
7.5.13.2 (45h) VOUT_UV_FAULT_RESPONSE
The VOUT_UV_FAULT_RESPONSE instructs the device on what action to take in response to an output
undervoltage fault.
Upon triggering the undervoltage fault, the following actions are taken:
•
•
•
•
Set the OTHER bit in the STATUS_BYTE
Set the VOUT bit in the STATUS_WORD
Set the VOUT_UV_FAULT bit in the STATUS_VOUT register
The device notifies the host (asserts PMB_ALERT, if the corresponding mask bit in SMBALERT_MASK is not
set)
The VOUT_UV_FAULT_RESPONSE command must be accessed through Read Byte/Write Byte transactions.
The VOUT_UV_FAULT_RESPONSE command is shared between Channel A and Channel B. All transactions to
this command will affect both channels regardless of the PAGE command.
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VO_UV_RESP
LEGEND: R/W = Read/Write; R = Read only
图 38. VOUT_UV_FAULT_RESPONSE
版权 © 2017–2019, Texas Instruments Incorporated
77
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
表 41. VOUT_UV_FAULT_RESPONSE Register Field Descriptions
Bit
Field
Type
Reset
Description
00h: Ignore. The controller will set the appropriate status bits,
and alert the host, but continue converting power.
BAh: Shutdown and restart. The controller will shutdown the
channel on which the fault occurred, and attempt to restart 20ms
later. This will occur continuously until the condition causing the
fault has disappeared, or the controller has been disabled.
7:0
VO_UV_RESP
RW
NVM
80h: Latch-off and do not restart. To clear a shutdown event due
to a fault event, the user must toggle the AVR_EN/BEN pin
and/or the ON bit in OPERATION, per the settings in
ON_OFF_CONFIG, or power cycle the bias power to the V3P3
pin of the controller device.
7.5.14 Minimum Allowed Output Voltage Setting
The VOUT_MIN command sets a lower bound on the output voltage to which the unit can be commanded,
regardless of any other commands or combinations. The intent of this command is to provide a safeguard
against a user accidentally setting the output voltage to a possibly destructive level rather than to be the primary
output under voltage protection.
7.5.14.1 (2Bh) VOUT_MIN
The VOUT_ MIN command sets a lower bound on the output voltage to which the unit can be commanded,
regardless of any other commands or combinations. The intent of this command is to provide a safeguard
against a user accidentally setting the output voltage to a possibly destructive level rather than to be the primary
output under voltage protection. VOUT_MIN is a VID format command, and must be accessed through Read
Word/Write Word transactions. VOUT_MIN is a paged register. In order to access VOUT_MIN for channel A,
PAGE must be set to 00h. In order to access the VOUT_MIN register for channel B, PAGE must be set to 01h.
For simultaneous access of channels A and B, the PAGE command must be set to FFh.
If an attempt is made to program the output voltage lower than the limit set by this command, the device will
respond as follows:
•
•
•
•
•
The commanded output voltage will be clamped to VOUT_MIN
The OTHER bit will be set in the STATUS_BYTE
The VOUT bit will be set in the STATUS_WORD
The VOUT_MIN_MAX Warning bit will be set in the STATUS_VOUT register
The device notifies the host (asserts PMB_ALERT, if the corresponding mask bit in SMBALERT_MASK is not
set).
15
R
14
R
13
R
12
R
11
R
10
R
9
R
0
8
R
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VOUT_MIN_VID
LEGEND: R/W = Read/Write; R = Read only
图 39. VOUT_MIN
表 42. VOUT_MIN Register Field Descriptions
Bit
Field
Type
Reset
Description
Used to set a lower bound for output voltage programming for
the active PAGE, is set to in VID format.
7:0
VOUT_MIN_VID
RW
NVM
78
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
7.5.15 Output Overcurrent Protection and Response
Overcurrent thresholds are configured using the IOUT_OC_FAULT_LIMIT. When the overcurrent fault threshold
is reached, the converter will respond according to the settings in IOUT_OC_FAULT_RESPONSE. The
IOUT_OC_WARN_LIMIT may also be used to configure an information-only overcurrent warning, which triggers
prior to an overcurrent fault. Note, that the MFR_SPECIFIC_00 command, not listed below, also contains
settings for per-phase overcurrent limits. Refer to the device Technical Reference Manual for more information.
7.5.15.1 (46h) IOUT_OC_FAULT_LIMIT
The IOUT_OC_FAULT_LIMIT command sets the value of the total output current, in amperes, that causes the
over-current detector to indicate an over-current fault condition. The command has two data bytes and the data
format is Linear as shown in the table below. The units are amperes. IOUT_OC_FAULT_LIMIT is a linear format
command, and must be accessed through Read Word/Write Word transactions. IOUT_OC_FAULT_LIMIT is a
paged register. In order to access IOUT_OC_FAULT_LIMIT command for channel A, PAGE must be set to 00h.
In order to access IOUT_OC_FAULT_LIMIT register for channel B, PAGE must be set to 01h. For simultaneous
access of channels A and B, the PAGE command must be set to FFh.
15
R
14
R
13
R
12
R
11
R
10
9
8
RW
RW
RW
IOOCF_EXP
IOOCF_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
IOOCF_MAN
LEGEND: R/W = Read/Write; R = Read only
图 40. IOUT_OC_FAULT_LIMIT
表 43. IOUT_OC_FAULT_LIMIT Register Field Descriptions
Bit
Field
Type
Reset
Description
15:11
IOOCF_EXP
R
00000b
Linear two's complement exponent, 0. LSB = 1.0 A
Linear two's complement mantissa
See
below.
10:0
IOOCF_MAN
RW
At power-on, or after a RESTORE_DEFAULT_ALL operation, the IOUT_OC_FAULT_LIMIT command will be
loaded with the value of IOUT_MAX × 1.50. The IOUT_MAX bits for each channel are stored in
MFR_SPECIFIC_10 (PAGE 0 for channel A, PAGE 1 for channel B). IOUT_OC_FAULT_LIMIT may be changed
during operation, but returns to this value on reset.
7.5.15.2 (4Ah) IOUT_OC_WARN_LIMIT
The IOUT_OC_WARN_LIMIT command sets the value of the output current, in amperes, that causes the over-
current detector to indicate an over-current warning condition. IOUT_OC_WARN_LIMIT is a linear format
command, and must be accessed through Read Word/Write Word transactions. IOUT_OC_WARN_LIMIT is a
paged register. In order to access IOUT_OC_WARN_LIMIT command for channel A, PAGE must be set to 00h.
In order to access IOUT_OC_WARN_LIMIT register for channel B, PAGE must be set to 01h. For simultaneous
access of channels A and B, the PAGE command must be set to FFh.
注
IOUT_OC_WARN_LIMIT maximum default value is 255A. In case, Application maximum
load current is greater than 255A, IOUT_OC_WARN_LIMIT needs to change as max load
current value each time after power-on or RESTORE_DEFAULT_ALL operation.
Upon triggering the overcurrent warning, the following actions are taken:
•
•
•
•
Set the OTHER bit in the STATUS_BYTE
Set the IOUT bit in the STATUS_WORD
Set the IOUT Over current Warning bit in the STATUS_IOUT register
The device notifies the host (asserts PMB_ALERT, if the corresponding mask bit in SMBALERT_MASK is not
版权 © 2017–2019, Texas Instruments Incorporated
79
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
set)
15
R
14
R
13
R
12
R
11
R
10
9
8
RW
RW
RW
IOOCW_EXP
IOOCW_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
IOOCW_MAN
LEGEND: R/W = Read/Write; R = Read only
图 41. IOUT_OC_WARN_LIMIT
表 44. IOUT_OC_WARN_LIMIT Register Field Descriptions
Bit
Field
Type
Reset
Description
15:11
IOOCW_EXP
R
00000b
Linear two's complement exponent, 0. LSB = 1.0 A
Linear two's complement mantissa.
See
below.
10:0
IOOCW_MAN
RW
At power-on, or after a RESTORE_DEFAULT_ALL operation, the IOUT_OC_WARN_LIMIT command will be
loaded with the value of IOUT_MAX. The IOUT_MAX bits for each channel are stored in MFR_SPECIFIC_10
(PAGE 0 for channel A, PAGE 1 for channel B). IOUT_OC_WARN_LIMIT may be changed during operation, but
will return to this value on reset.
7.5.15.3 (47h) IOUT_OC_FAULT_RESPONSE
The IOUT_OC_FAULT_RESPONSE instructs the device on what action to take in response to an output over-
current fault. The IOUT_OC_FAULT_RESPONSE command must be accessed through Read Byte/Write Byte
transactions. The IOUT_OC_FAULT_RESPONSE command is shared between Channel A and Channel B. All
transactions to this command will affect both channels regardless of the PAGE command.
Upon triggering the over-current fault, the controller is latched off, and the following actions are taken:
•
•
•
•
Set the IOUT_OC_FAULT bit in the STATUS_BYTE
Set the IOUT bit in the STATUS_WORD
Set the IOUT_OC_FAULT bit in the STATUS_IOUT register
The device notifies the host (asserts PMB_ALERT, if the corresponding mask bit in SMBALERT_MASK is not
set)
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
IO_OC_RESP
LEGEND: R/W = Read/Write; R = Read only
图 42. IOUT_OC_FAULT_RESPONSE
表 45. IOUT_OC_FAULT_RESPONSE Register Field Descriptions
Bit
Field
Type
Reset
Description
C0h: Latch-off and do not restart. To clear a shutdown event
due to a fault event, the user must toggle the AVR_EN/BEN pin
and/or the ON bit in OPERATION, per the settings in
ON_OFF_CONFIG, or power cycle the bias power to the V3P3
pin of the controller device.
7:0
IO_OC_RESP
RW
NVM
FAh: Shutdown and restart. The controller will shutdown the
channel on which the fault occurred, and attempt to restart 20ms
later. This will occur continuously until the condition causing the
fault has disappeared, or the controller has been disabled.
80
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
7.5.16 Input Under-Voltage Lockout (UVLO)
The TPS53681 may not start converting power, until the power stage input voltage reaches the level specified by
VIN_ON.
7.5.16.1 (35h) VIN_ON
The VIN_ON command sets the value of the input voltage, in Volts, at which the unit should start power
conversion. This command has two data bytes encoded in linear data format, and must be accessed through
Read Word/Write Word transactions. The VIN_ON command is shared between Channel A and Channel B. All
transactions to this command will affect both channels regardless of the PAGE command. The supported range
for VIN_ON is from 4.0 V volts to 11.25 Volts.
15
R
14
R
13
R
12
R
11
R
10
9
8
RW
RW
RW
VINON_EXP
VINON_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VINON_MAN
LEGEND: R/W = Read/Write; R = Read only
图 43. VIN_ON
表 46. VIN_ON Register Field Descriptions
Bit
Field
Type
Reset
Description
Linear two's complement exponent, –2. LSB = 0.25 V
15:11
VINON_EXP
R
11110b
Linear two's complement mantissa. See the table of acceptable
values below.
10:0
VINON_MAN
RW
NVM
表 47. Acceptable Values of VIN_ON
VIN_ON (hex)
Turn-On Voltage (V)
F010h
F015h
F019h
F01Dh
F021h
F025h
F029h
F02Dh
4.0
5.25
6.25
7.25
8.25
9.25
10.25
11.25
7.5.17 Input Over-Voltage Protection and Response
The TPS53681 provides protection from input transients via the VIN_OV_FAULT_LIMIT and
VIN_OV_FAULT_RESPONSE commands.
7.5.17.1 (55h) VIN_OV_FAULT_LIMIT
The VIN_OV_FAULT_LIMIT command sets the value of the input voltage that causes an input overvoltage fault.
VIN_OV_FAULT_LIMIT is a linear format command, and must be accessed through Read Word/Write Word
transactions. The VIN_OV_FAULT_LIMIT command is shared between Channel A and Channel B. All
transactions to this command will affect both channels regardless of the PAGE command.
版权 © 2017–2019, Texas Instruments Incorporated
81
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
15
R
14
R
13
R
12
R
11
R
10
9
RW
8
RW
RW
VIN_OVF_EXP
VIN_OVF_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VIN_OVF_MAN
LEGEND: R/W = Read/Write; R = Read only
图 44. VIN_OV_FAULT_LIMIT
表 48. VIN_OV_FAULT_LIMIT Register Field Descriptions
Bit
Field
Type
Reset
Description
15:11
VIN_OVF_EXP
R
00000b
Linear two's complement exponent, 0. LSB = 1 V
Linear two's complement mantissa. Valid values of the mantissa
range from 0d to 31d.
10:0
VIN_OVF_MAN
RW
NVM
7.5.17.2 (56h) VIN_OV_FAULT_RESPONSE
The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an input
overvoltage fault. The VIN_OV_FAULT_RESPONSE command must be accessed through Read Byte
transactions. The VIN_OV_FAULT_RESPONSE command is shared between Channel A and Channel B. All
transactions to this command will affect both channels regardless of the PAGE command.
In response to the VIN_OV_LIMIT being exceeded, the device will:
•
•
•
•
Set the OTHER bit in the STATUS_BYTE
Set the INPUT bit in the upper byte of the STATUS_WORD
Sets the VIN_OV_FAULT bit in the STATUS_INPUT register
Notify the host (assert the PMB_ALERT signal, if the corresponding mask bit in SMBALERT_MASK is not
set)
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
VI_OVF_RESP
LEGEND: R/W = Read/Write; R = Read only
图 45. VIN_OV_FAULT_RESPONSE
表 49. VIN_OV_FAULT_RESPONSE Register Field Descriptions
Bit
Field
Type
Reset
Description
00h: Ignore. The controller will set the appropriate status bits,
and alert the host, but continue converting power.
7:0
VI_OVF_RESP
R
00h
7.5.18 Input Undervoltage Protection and Response
The TPS53681 provides protection from input transients via the VIN_UV_FAULT_LIMIT and
VIN_UV_FAULT_RESPONSE commands.
7.5.18.1 (59h) VIN_UV_FAULT_LIMIT
The VIN_UV_FAULT_LIMIT command sets the value of the input voltage that causes an Input Under voltage
Fault. This fault is masked until the input exceeds the value set by the VIN_ON command for the first time, and
the unit has been enabled. VIN_UV_FAULT_LIMIT is a linear format command, and must be accessed through
Read Word/Write Word transactions. The VIN_UV_FAULT_LIMIT command is shared between Channel A and
Channel B. All transactions to this command will affect both channels regardless of the PAGE command.
82
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
15
14
13
RW
12
11
10
9
RW
8
RW
RW
RW
RW
RW
RW
VIN_UVF_EXP
VIN_UVF_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
VIN_UVF_MAN
LEGEND: R/W = Read/Write; R = Read only
图 46. VIN_UV_FAULT_LIMIT
表 50. VIN_UV_FAULT_LIMIT Register Field Descriptions
Bit
Field
Type
Reset
Description
Linear two's complement exponent. See the table of acceptable
values below.
15:11
VIN_UVF_EXP
RW
NVM
Linear two's complement mantissa. See the table of acceptable
values below.
10:0
VIN_UVF_MAN
RW
NVM
表 51. Acceptable Values of VIN_UV_FAULT_LIMIT
VIN_UV_FAULT_LIMIT (hex)
VIN UVF Limit (V)
F011h
F80Bh
F80Dh
F80Fh
F811h
F813h
F815h
F817h
4.25
5.5
6.5
7.5
8.5
9.5
10.5
11.5
7.5.18.2 (5Ah) VIN_UV_FAULT_RESPONSE
The VIN_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an input
overvoltage fault. The VIN_UV_FAULT_RESPONSE command must be accessed through Read Byte
transactions. The VIN_UV_FAULT_RESPONSE command is shared between Channel A and Channel B. All
transactions to this command will affect both channels regardless of the PAGE command.
In response to the VIN_UV_LIMIT being exceeded, the device will:
•
•
•
•
Set the OTHER bit in the STATUS_BYTE
Set the INPUT bit in the upper byte of the STATUS_WORD
Set the VIN_UV_FAULT bit in the STATUS_INPUT register
The device notifies the host (asserts PMB_ALERT, if the corresponding mask bit in SMBALERT_MASK is not
set)
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
VI_UVF_RESP
LEGEND: R/W = Read/Write; R = Read only
图 47. VIN_UV_FAULT_RESPONSE
表 52. VIN_UV_FAULT_RESPONSE Register Field Descriptions
Bit
Field
Type
Reset
Description
C0h: Shutdown and restart when the fault condition is no longer
present.
7:0
VI_UVF_RESP
R
C0h
版权 © 2017–2019, Texas Instruments Incorporated
83
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
7.5.19 Input Overcurrent Protection and Response
Input overcurrent protection is configured via the IIN_OC_FAULT_LIMIT, IIN_OC_WARN_LIMIT and
IIN_OC_FAULT_RESPONSE commands.
7.5.19.1 (5Bh) IIN_OC_FAULT_LIMIT
The IIN_OC_FAULT_LIMIT command sets the value of the input current, in amperes, that causes the input over
current fault condition. IIN_OC_FAULT_LIMIT is a linear format command, and must be accessed through Read
Word/Write Word transactions. The IIN_OC_FAULT_LIMIT command is shared between Channel A and Channel
B. All transactions to this command will affect both channels regardless of the PAGE command.
15
R
14
R
13
R
12
R
11
R
10
9
8
RW
RW
RW
IIN_OCF_EXP
IIN_OCF_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
IIN_OCF_MAN
LEGEND: R/W = Read/Write; R = Read only
图 48. IIN_OC_FAULT_LIMIT
表 53. IIN_OC_FAULT_LIMIT Register Field Descriptions
Bit
Field
Type
Reset
Description
15:11
IIN_OCF_EXP
R
11111b
Linear two's complement format exponent, –1. LSB = 0.5 A.
See
below.
Linear two's complement format mantissa. Acceptable values
range from 0d (0 A) to 127d (63.5 A).
10:0
IIN_OCF_MAN
RW
During operation, the IIN_OC_FAULT_LIMIT may be changed to any valid value, as specified above. The
IIN_OC_FAULT_LIMIT command has only limited NVM backup. The table below summarizes the values that
IIN_OC_FAULT_LIMIT may be restored to following a reset, or RESTORE_DEFAULT_ALL operation.
表 54. IIN_OC_FAULT_LIMIT reset values
IIN_OC_FAULT_LIMIT during
NVM store operation
IIN_OC_FAULT_LIMIT following
Reset/Restore Operation
Hex Value
F810h
F820h
8 A
8 A
16 A
24 A
32 A
40 A
48 A
56 A
63.5 A
63.5 A
16 A
F830h
24 A
F840h
32 A
40 A
F850h
F860h
48 A
F870h
56 A
F87Fh
63.5 A
Any other valid data
Any other valid data
7.5.19.2 (5Dh) IIN_OC_WARN_LIMIT
The IIN_OC_WARN_LIMIT command sets the value of the input current, in amperes, that causes the input
overcurrent warning condition. The IIN_OC_WARN_LIMIT command must be accessed through Read
Word/Write Word transactions. The IIN_OC_WARN_LIMIT command is shared between Channel A and Channel
B. All transactions to this command will affect both channels regardless of the PAGE command.
Upon triggering the over-current warning, the following actions are taken:
•
•
•
•
Set the OTHER bit in the STATUS_BYTE
Set the INPUT bit in the STATUS_WORD
Set the IIN Over-current Warning bit in the STATUS_INPUT register
The device notifies the host (asserts PMB_ALERT, if the corresponding mask bit in SMBALERT_MASK is not
set)
84
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
15
R
14
R
13
R
12
R
11
R
10
R
9
8
R
R
IIN_OCW_EXP
IIN_OCW_MAN
7
6
5
4
3
2
1
0
R
RW
RW
RW
RW
RW
RW
RW
IIN_OCW_MAN
LEGEND: R/W = Read/Write; R = Read only
图 49. IIN_OC_WARN_LIMIT
表 55. IIN_OC_FAULT_LIMIT Register Field Descriptions
Bit
Field
Type
Reset
Description
15:11
IIN_OCW_EXP
R
11111b
Linear two's complement format exponent, –1. LSB = 0.5 A.
See
below.
Linear two's complement format mantissa. Acceptable values
range from 0d (0 A) to 127d (63.5 A).
10:0
IIN_OCW_MAN
RW
During operation, the IIN_OC_FAULT_LIMIT may be changed to any valid value, as specified above. The
IIN_OC_FAULT_LIMIT command has only limited NVM backup. The table below summarizes the values that
IIN_OC_FAULT_LIMIT may be restored to following a reset, or RESTORE_DEFAULT_ALL operation.
表 56. IIN_OC_WARN_LIMIT reset values
IIN_OC_WARN_LIMIT during
NVM store operation
IIN_OC_WARN_LIMIT following
Reset/Restore Operation
Hex Value
F810h
F820h
8 A
8 A
16 A
24 A
32 A
40 A
48 A
56 A
63.5 A
63.5 A
16 A
F830h
24 A
F840h
32 A
40 A
F850h
F860h
48 A
F870h
56 A
F87Fh
63.5 A
Any other valid data
Any other valid data
7.5.19.3 (5Ch) IIN_OC_FAULT_RESPONSE
The IIN_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an input
over-current fault. IIN_OC_FAULT_RESPONSE command must be accessed through Read Byte transactions.
The IIN_OC_FAULT_RESPONSE command is shared between Channel A and Channel B. All transactions to
this command will affect both channels regardless of the PAGE command.
Upon triggering the input over-current fault, the controller is latched off, and the following actions are taken:
•
•
•
•
Set the OTHER bit in the STATUS_BYTE
Set the INPUT bit in the STATUS_WORD
Set the IIN_OC_FAULT bit in the STATUS_INPUT register
The device notifies the host (asserts PMB_ALERT and VR_FAULT, if the corresponding mask bit in
SMBALERT_MASK is not set)
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
IIN_OC_RESP
LEGEND: R/W = Read/Write; R = Read only
版权 © 2017–2019, Texas Instruments Incorporated
85
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
图 50. IIN_OC_FAULT_RESPONSE
表 57. IIN_OC_FAULT_LIMIT Register Field Descriptions
Bit
Field
Type
Reset
Description
C0h: Latch-off and do not restart. To clear a shutdown event
due to a fault event, the user must toggle the AVR_EN/BEN pin
and/or the ON bit in OPERATION, per the settings in
ON_OFF_CONFIG, or power cycle the bias power to the V3P3
pin of the controller device.
7:0
IIN_OC_RESP
R
C0h
7.5.20 Over-Temperature Protection and Response
Overtemperature protection is configured via
the
OT_FAULT_LIMIT,
OT_WARN_LIMIT
and
OT_FAULT_RESPONSE commands.
7.5.20.1 (4Fh) OT_FAULT_LIMIT
The OT_FAULT_LIMIT command sets the value of the temperature limit, in degrees Celsius, that causes an
overtemperature fault condition when the sensed temperature from the external sensor exceeds this limit. The
default value is selected inMFR_SPECIFIC_13, using the OTF_DFLT bit. Refer to the device Technical
Reference Manual for more information. OT_FAULT_LIMIT is a linear format command, and must be accessed
through Read Word/Write Word transactions. OT_FAULT_LIMIT is a paged register. In order to access
OT_FAULT_LIMIT command for channel A, PAGE must be set to 00h. In order to access OT_FAULT_LIMIT
register for channel B, PAGE must be set to 01h. For simultaneous access of channels A and B, the PAGE
command must be set to FFh.
15
R
14
R
13
R
12
R
11
R
10
9
8
RW
RW
RW
OTF_EXP
OTF_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
OTF_MAN
LEGEND: R/W = Read/Write; R = Read only
图 51. OT_FAULT_LIMIT
表 58. OT_FAULT_LIMIT Register Field Descriptions
Bit
Field
Type
Reset
Description
Linear two's complement exponent, 0. LSB = 1 ºC
Linear two's complement mantissa.
OT_FAULT_LIMIT is set by the OTF_DFLT bit in
MFR_SPECIFIC_13.
15:11
OTF_EXP
R
00000b
The
default
10:0
OTF_MAN
RW
NVM
7.5.20.2 (51h) OT_WARN_LIMIT
The OT_WARN_LIMIT command sets the temperature, in degrees Celsius, of the unit at which it should indicate
an Over-temperature Warning event. OT_WARN_LIMIT is a linear format command, and must be accessed
through Read Word/Write Word transactions. OT_WARN_LIMIT is a paged register. In order to access
OT_WARN_LIMIT command for channel A, PAGE must be set to 00h. In order to access OT_WARN_LIMIT
register for channel B, PAGE must be set to 01h. For simultaneous access of channels A and B, the PAGE
command must be set to FFh.
In response to the OT_WARN_LIMIT being exceeded, the device will:
•
•
•
Set the TEMPERATURE bit in the STATUS_BYTE
Set the Over-temperature Warning bit in the STATUS_TEMPERATURE register
Notify the host (asserts PMB_ALERT, if the corresponding mask bit in SMBALERT_MASK is not set)
86
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
15
R
14
R
13
R
12
R
11
R
10
9
8
RW
RW
RW
OTW_EXP
OTW_MAN
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
OTW_MAN
LEGEND: R/W = Read/Write; R = Read only
图 52. OT_WARN_LIMIT
表 59. OT_WARN_LIMIT Register Field Descriptions
Bit
Field
Type
Reset
Description
15:11
OTF_EXP
R
00000b
Linear two's complement exponent, 0. LSB = 1 ºC
Linear two's complement mantissa. Default = 105 ºC
10:0
OTF_MAN
RW
105d
7.5.20.3 (50h) OT_FAULT_RESPONSE
The OT_FAULT_RESPONSE instructs the device on what action to take in response to an output over-
temperature fault. The OT_FAULT_RESPONSE command must be accessed through Read Byte/Write Byte
transactions. The OT_FAULT_RESPONSE command is shared between Channel A and Channel B. All
transactions to this command will affect both channels regardless of the PAGE command.
Upon triggering the over-temperature fault, the controller is latched off, and the following actions are taken:
•
•
•
Set the TEMPERATURE bit in the STATUS_BYTE
Set the OT_FAULT bit in the STATUS_TEMPERATURE register
The device notifies the host (asserts PMB_ALERT, if the corresponding mask bit in SMBALERT_MASK is not
set).
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
OTF_RESP
LEGEND: R/W = Read/Write; R = Read only
图 53. OT_FAULT_RESPONSE
表 60. OT_FAULT_RESPONSE Register Field Descriptions
Bit
Field
Type
Reset
Description
80h: Latch-off and do not restart. To clear a shutdown event due
to a fault event, the user must toggle the AVR_EN/BEN pin
and/or the ON bit in OPERATION, per the settings in
ON_OFF_CONFIG, or power cycle the bias power to the V3P3
pin of the controller device.
7:0
OTF_RESP
RW
NVM
C0h: Shutdown and restart when the fault condition is no longer
present.
版权 © 2017–2019, Texas Instruments Incorporated
87
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
7.5.21 Dynamic Phase Shedding (DPS)
The dynamic phase shedding (DPS) feature allows the TPS53681 to dynamically select the number of
operational phases for each channel, based on the total output current. This increases the total converter
efficiency by reducing unnecessary switching losses when the output current is low enough to be supported by a
fewer number of phases, than are available in hardware. The MFR_SPECIFIC_14 and MFR_SPECIFIC_15
commands may be used to configure dynamic phase shedding behavior and thresholds.
The DPS_EN bit in MFR_SPECIFIC_14 may be used to enable or disable dynamic phase shedding. Un-setting
(writing to 0b) this bit forces each channel to use the maximum number of available phases, regardless of the
output current.
The phase add/drop thresholds, at which phases are added or dropped are configured based on the peak
efficiency point per phase. For a given switching frequency/duty cycle, the efficiency of an individual power stage
has a "peak" point, at which switching losses become less significant and conduction losses begin to dominate.
For a multiphase converter, the optimum efficiency is achieved when all of the power stages operate as close as
possible to their peak efficiency point. For example, consider a 4-phase design, with power stages that have a
peak efficiency point of 12 A per phase. When the total output current is 25 A, if all four phases were active, each
phase would be supplying 6.25 A, and hence would be operating far away from their peak efficiency point. With
only two phases active, however, each phase supplies 12.5A, meaning that each power stage is operating close
to its peak efficiency point, therefore the total converter efficiency is higher overall.
In order to maintain regulation during severe load transient events, phases may be added immediately whenever
the total peak current reaches phase addition thresholds. To prevent chattering, phases are dropped when the
total average current falls below phase drop thresholds, after a delay of 85 µs typically. Phases are always
added/dropped, in numerical order. For example, phase 3 is added after phase 2, and dropped after phase 4.
The DPS_COURSE_TH bits in MFR_SPECIFIC_15 select the peak efficiency point per phase. Refer to the
power stage datasheet to determine the peak efficiency point per phase.
Phase adding thresholds are configured based on the peak efficiency point per phase. Each phase transition has
a configurable threshold of 6 A to 12 A above the peak efficiency point. For example, the threshold at which the
converter transitions from 2 phases to 3 phases is determined by the DPS_2TO3_FINE_ADD bits in
MFR_SPECIFIC_15. When 8 A is selected, the total peak current which causes the third phase to be added is 2
× IEFF(PEAK) + 8 A. See the register descriptions below for more detailed information.
Likewise, phase drop thresholds are configured based on the peak efficiency point per phase. Each phase
transition has a configurable threshold of 2A below to 4 A above the peak efficiency point. For example, the
threshold at which the converter transitions from
3 phases to 2 phases is determined by the
DPS_3TO2_FINE_DROP bits in MFR_SPECIFIC_14. When 0 A is selected, the total average current which
causes the third phase to be dropped is 2 × IEFF(PEAK). See the register descriptions below for more detailed
information.
88
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
7.5.21.1 (DEh) MFR_SPECIFIC_14
The MFR_SPECIFIC_14 command is used to configure dynamic phase shedding, and compensation ramp
amplitude, and dynamic ramp amplitude during USR, and different power states. The MFR_SPECIFIC_14
command must be accessed through Write Word/Read Word transactions.
MFR_SPECIFIC_14 is a paged register. In order to access MFR_SPECIFIC_14 command for channel A, PAGE
must be set to 00h. In order to access the MFR_SPECIFIC_14 register for channel B, PAGE must be set to 01h.
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
DPS_6TO5_FINE_DROP
(PAGE 0 only)
DPS_5TO4_FINE_DROP
(PAGE 0 only)
DPS_4TO3_FINE_DROP
(PAGE 0 only)
DPS_3TO2_FINE_DROP
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
DYN_RAMP_2 DYN_RAMP_1
PH PH
DPS_EN
DYN_RAMP_USR
RAMP
LEGEND: R/W = Read/Write; R = Read only
图 54. MFR_SPECIFIC_14
表 61. MFR_SPECIFIC_14 Register Field Descriptions
Bit
Field
Type
Reset
Description
Dynamic phase drop threshold, fine adjustment, 6 phases to 5
phases. Set as an offset from peak efficiency point per phase in
Amperes. Phases drop when average phase current reaches the
stated threshold. IEFF(PEAK) refers to the value selected by
DPS_COURSE_TH in MFR_SPECIFIC_15.
DPS_6TO5_FINE_DROP
(PAGE 0 only)
15:14
RW
NVM
00b: Threshold = 5 × IEFF(PEAK) – 2 A
01b: Threshold = 5 × IEFF(PEAK)
10b: Threshold = 5 × IEFF(PEAK) + 2 A
11b: Threshold = 5 × IEFF(PEAK) + 4 A
Dynamic phase drop threshold, fine adjustment, 5 phases to 4
phases. Set as an offset from peak efficiency point per phase in
Amperes. Phases drop when average phase current reaches the
stated threshold. IEFF(PEAK) refers to the value selected by
DPS_COURSE_TH in MFR_SPECIFIC_15.
DPS_5TO4_FINE_DROP
(PAGE 0 only)
13:12
11:10
9:8
RW
RW
RW
NVM
NVM
NVM
00b: Threshold = 4 × IEFF(PEAK) – 2 A
01b: Threshold = 4 × IEFF(PEAK)
10b: Threshold = 4 × IEFF(PEAK) + 2 A
11b: Threshold = 4 × IEFF(PEAK) + 4 A
Dynamic phase drop threshold, fine adjustment, 4 phases to 3
phases. Set as an offset from peak efficiency point per phase in
Amperes. Phases drop when average phase current reaches the
stated threshold. IEFF(PEAK) refers to the value selected by
DPS_COURSE_TH in MFR_SPECIFIC_15.
DPS_4TO3_FINE_DROP
(PAGE 0 only)
00b: Threshold = 3 × IEFF(PEAK) – 2 A
01b: Threshold = 3 × IEFF(PEAK)
10b: Threshold = 3 × IEFF(PEAK) + 2 A
11b: Threshold = 3 × IEFF(PEAK) + 4 A
Dynamic phase drop threshold, fine adjustment, 3 phases to 2
phases. Set as an offset from peak efficiency point per phase in
Amperes. Phases drop when average phase current reaches the
stated threshold. IEFF(PEAK) refers to the value selected by
DPS_COURSE_TH in MFR_SPECIFIC_15.
DPS_3TO2_FINE_DROP
00b: Threshold = 2 × IEFF(PEAK) – 2 A
01b: Threshold = 2 × IEFF(PEAK)
10b: Threshold = 2 × IEFF(PEAK) + 2 A
11b: Threshold = 2 × IEFF(PEAK) + 4 A
版权 © 2017–2019, Texas Instruments Incorporated
89
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
表 61. MFR_SPECIFIC_14 Register Field Descriptions (接下页)
Bit
Field
Type
Reset
Description
Enable or Disable Dynamic Phase Shedding
0b: Disable dynamic phase shedding
1b: Enable dynamic phase shedding
7
DPS_EN
RW
NVM
Dynamic ramp amplitude setting during USR operation. Only
applies to USR Level 1.
00b: Equal to the settings in the RAMP bits
6:5
DYN_RAMP_USR
DYN_RAMP_2PH
RW
RW
NVM
NVM
01b: 40 mV
10b: 80 mV
11b: 120 mV
Dynamic ramp amplitude setting during 2 phase operation.
0b: Equal to the settings in the RAMP bits
1b: 120 mV
4
Dynamic ramp amplitude setting during 1 phase operation.
0b: Equal to the settings in the RAMP bits
1b: 80 mV
3
DYN_RAMP_1PH
RAMP
RW
RW
NVM
NVM
2:0
Ramp amplitude settings. See 表 62.
表 62. Ramp Amplitude Settings
RAMP (binary)
Ramp Amplitude Setting (mV)
000b
001b
010b
011b
100b
101b
110b
111b
40
80
120
160
200
240
280
320
7.5.21.2 (DFh) MFR_SPECIFIC_15
The MFR_SPECIFIC_15 command is used to configure dynamic phase shedding. The MFR_SPECIFIC_15
command must be accessed through Write Word/Read Word transactions.
MFR_SPECIFIC_15 is a paged register. In order to access MFR_SPECIFIC_15 command for channel A, PAGE
must be set to 00h. In order to access the MFR_SPECIFIC_15 register for channel B, PAGE must be set to 01h.
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
DPS_3TO4_FI
NE_ADD
(PAGE 0 only)
DPS_5TO6_FINE_ADD
(PAGE 0 only)
DPS_4TO5_FINE_ADD
(PAGE 0 only)
DPS_DCM
DPS_2TO1_FINE_DROP
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
DPS_3TO4_FI
NE_ADD
DPS_2TO3_FINE_ADD
DPS_1TO2_FINE_ADD
2TO1_PH_EN
DPS_COURSE_TH
(PAGE 0 only)
LEGEND: R/W = Read/Write; R = Read only
图 55. MFR_SPECIFIC_15
90
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
表 63. MFR_SPECIFIC_15 Register Field Descriptions
Bit
Field
Type
Reset
Description
Enable DCM mode during 1 phase operation, when higher order
phases are dropped due to dynamic phase shedding.
15
DPS_DCM
RW
NVM
0b: Disable DCM operation during 1 phase operation
1b: Enable DCM operation during 1 phase operation
Dynamic phase drop threshold, fine adjustment, 2 phases to
1phase. Set as an offset from peak efficiency point per phase in
Amperes. Phases drop when average phase current reaches the
stated threshold. IEFF(PEAK) refers to the value selected by
DPS_COURSE_TH below.
14:13
12:11
10:9
8:7
DPS_2TO1_FINE_DROP
RW
RW
RW
RW
RW
NVM
NVM
NVM
NVM
NVM
00b: Threshold = 1× IEFF(PEAK) – 2 A
01b: Threshold = 1 × IEFF(PEAK)
10b: Threshold = 1 × IEFF(PEAK) + 2 A
11b: Threshold = 1 × IEFF(PEAK) + 4 A
Dynamic phase add threshold, fine adjustment, 5 phases to 6
phases. Set as an offset from peak efficiency point per phase in
Amperes. Phases add when peak phase current reaches the
stated threshold. IEFF(PEAK) refers to the value selected by
DPS_COURSE_TH below.
DPS_5TO6_FINE_ADD
(PAGE 0 only)
00b: Threshold = 5 × IEFF(PEAK) + 6A
01b: Threshold = 5 × IEFF(PEAK) + 8 A
10b: Threshold = 5 × IEFF(PEAK) + 10 A
11b: Threshold = 5 × IEFF(PEAK) + 12 A
Dynamic phase add threshold, fine adjustment, 4 phases to 5
phases. Set as an offset from peak efficiency point per phase in
Amperes. Phases add when peak phase current reaches the
stated threshold. IEFF(PEAK) refers to the value selected by
DPS_COURSE_TH below
DPS_4TO5_FINE_ADD
(PAGE 0 only)
00b: Threshold = 4 × IEFF(PEAK) + 6A
01b: Threshold = 4 × IEFF(PEAK) + 8 A
10b: Threshold = 4 × IEFF(PEAK) + 10 A
11b: Threshold = 4 × IEFF(PEAK) + 12 A
Dynamic phase add threshold, fine adjustment, 3 phases to 4
phases. Set as an offset from peak efficiency point per phase in
Amperes. Phases add when peak phase current reaches the
stated threshold. IEFF(PEAK) refers to the value selected by
DPS_COURSE_TH below
DPS_3TO4_FINE_ADD
(PAGE 0 only)
00b: Threshold = 3 × IEFF(PEAK) + 6A
01b: Threshold = 3 × IEFF(PEAK) + 8 A
10b: Threshold = 3 × IEFF(PEAK) + 10 A
11b: Threshold = 3 × IEFF(PEAK) + 12 A
Dynamic phase add threshold, fine adjustment, 2 phases to 3
phases. Set as an offset from peak efficiency point per phase in
Amperes. Phases add when peak phase current reaches the
stated threshold. IEFF(PEAK) refers to the value selected by
DPS_COURSE_TH below
6:5
DPS_2TO3_FINE_ADD
00b: Threshold = 2 × IEFF(PEAK) + 6A
01b: Threshold = 2 × IEFF(PEAK) + 8 A
10b: Threshold = 2 × IEFF(PEAK) + 10 A
11b: Threshold = 2 × IEFF(PEAK) + 12 A
版权 © 2017–2019, Texas Instruments Incorporated
91
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
表 63. MFR_SPECIFIC_15 Register Field Descriptions (接下页)
Bit
Field
Type
Reset
Description
Dynamic phase add threshold, fine adjustment, 1 phase to 2
phases. Set as an offset from peak efficiency point per phase in
Amperes. Phases add when peak phase current reaches the
stated threshold. IEFF(PEAK) refers to the value selected by
DPS_COURSE_TH below
5:4
DPS_1TO2_FINE_ADD
RW
NVM
00b: Threshold = 1 × IEFF(PEAK) + 6A
01b: Threshold = 1 × IEFF(PEAK) + 8 A
10b: Threshold = 1 × IEFF(PEAK) + 10 A
11b: Threshold = 1 × IEFF(PEAK) + 12 A
Enable phase dropping from 2 phases to 1 phase operation.
0b: Disable phase shedding to 1 phase
3
2TO1_PH_EN
RW
RW
NVM
NVM
1b: Enable phase shedding to 1 phase
Sets the peak efficiency point per phase. This is used to
determine phase add/drop thresholds.
00b: IEFF(PEAK) = 12 A
01b: IEFF(PEAK) = 14 A
10b: IEFF(PEAK) = 16 A
11b: IEFF(PEAK) = 18 A
2:0
DPS_COURSE_TH
92
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
7.5.22 NVM Programming
The USER_DATA_00 - USER_DATA_12 commands are provided to streamline NVM programming. These 6-
byte block commands are mapped internally to all of the user-configurable parameters the TPS53681 supports.
The MFR_SERIAL command also provides a checksum, to streamline verification of desired programming
values.
The generalized procedure for programming the TPS53681 is summarized below.
Configure User-Programmable Parameters
1. First, configure all of the user-accessible parameters via the standard PMBus, and Manufacturer Specific
commands. TI provides the Fusion Digital Power Designer graphical interface software to streamline this
step. The user can also refer to the Technical Reference Manual for a full set of register maps for these
commands.
2. Once the device is configured as desired, issue the STORE_DEFAULT_ALL command to commit these
values to NVM, and update the checksum value. Wait approximately 100 ms after issuing
STORE_DEFAULT_ALL before communicating with the device again.
3. Write PAGE to 00h
4. Read-back and Record the value of IC_DEVICE_ID and IC_DEVICE_REV commands
5. Read-back and Record the value of the USER_DATA_00 through USER_DATA_12 commands
6. Read-back and Record the value of the MFR_SERIAL command
7. Read-back and Record the value of VOUT_MAX
8. Write PAGE to 01h
9. Read-back and Record the value of VOUT_MAX
Program and Verify NVM (repeat for each device)
1. Power the device by supplying +3.3V to the V3P3 pin. Power conversion should be disabled for NVM
programming.
2. Read-back and verify that IC_DEVICE_ID and IC_DEVICE_REV values match those recorded previously.
This ensures that user-parameters being programmed correspond to the same device/revision as previously
configured.
3. Write PAGE to 00h.
4. Write the USER_DATA_00 through USER_DATA_12 commands, with the values recorded previously.
5. Write VOUT_MAX (Page 0) with the value recorded previously.
6. Write PAGE to 01h
7. Write VOUT_MAX (Page 1) with the value recorded previously.
8. Issue STORE_DEFAULT_ALL. Wait appx 100 ms after issuing STORE_DEFAULT_ALL before
communicating with the device again.
9. Read-back the MFR_SERIAL command, and compare the value to that recorded previously. If the new
MFR_SERIAL matches the value recorded previously, NVM programming was successful.
版权 © 2017–2019, Texas Instruments Incorporated
93
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
7.5.23 NVM Security
The MFR_SPECIFIC_42 command can be optionally used to set a password for NVM programming. To prevent
a hacker from simply sending the password command with all possible passwords, the TPS53681 goes into a
special extra-secure state when an incorrect password is received. In this state, all passwords are rejected, even
the valid one. The device must be power cycled to clear this state so that another password attempt may be
made. When NVM security is enabled, the TPS53681 will not accept writes to any command other than PAGE
and PHASE, which are necessary for reading certain parameters.
Enabling NVM Security
1. Set the NVM password. Write MFR_SPECIFIC_42 to a value other than FFFFh.
2. Issue STORE_DEFAULT_ALL
3. Wait 100ms for the NVM store to complete
4. Power cycle V3P3. NVM Security will be enabled at the next power-up.
Disabling NVM Security
To disable NVM security, use the following procedure:
1. Write the password to MFR_SPECIFIC_42 to disable NVM security. Once the correct password has been
given, NVM security will be disabled, and the device will once again accept write transactions to configuration
registers.
NVM security will be re-enabled at the next power-on, unless MFR_SPECIFIC_42 is set to FFFFh (NVM Security
Disabled), and an NVM store operation (issue STORE_DEFAULT_ALL and wait 100 ms) is performed.
Determining Whether NVM Security is Active
Reads to the MFR_SPECIFIC_42 command returns one of three values:
•
•
•
0000h = NVM Security is Disabled
0001h = NVM Security is Enabled
0002h = MFR_SPECIFIC_42 is locked due to incorrect password entry
7.5.23.1 (FAh) MFR_SPECIFIC_42
MFR_SPECIFIC_42 is used for NVM Security. The MFR_SPECIFIC_42 command must be accessed through
Read Word/Write Word transactions.
MFR_SPECIFIC_42 is a shared register. Write transactions to this register will apply to both channels, and read
transactions to this register returns the same data regardless of the current PAGE.
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
NVM_SECURITY_KEY
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
NVM_SECURITY_KEY
LEGEND: R/W = Read/Write; R = Read only
图 56. MFR_SPECIFIC_42
表 64. MFR_SPECIFIC_42 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
NVM_SECURITY_KEY
RW
NVM
16 bit code for NVM security key.
94
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
7.5.24 Black Box Recording
The TPS53681 provides a "black box" feature to aid in system-level debugging. According to the PMBus
specification, status bits are latched whenever the condition causing them occurs, regardless of whether or not
other status bits are already set. This, however, makes it difficult for the system designer to understand which
fault condition occurred first, in the case that one fault condition causes others to trigger. The
MFR_SPECIFIC_08 command provides a "snapshot" of the first faults to occur chronologically, for each channel,
which may be stored to NVM, for future debugging. Only the most catastrophic fault conditions are logged, such
as the over-voltage fault, over-current fault, and power stage failure. The black box command may also be reset,
or cleared by writing 00h to the register, and storing to NVM if the NVM value must also be cleared.
Resetting the Black Box Record
Resetting the record allows the user to determine which faults occur first, after the register is cleared. To clear
the record, write 00h to MFR_SPECIFIC_08, and issue STORE_DEFAULT_ALL.
Triggering Black Box Recording
Black box recording is always active, whether or not the TPS53681 is converting power. Note however many of
the critical faults summarized in MFR_SPECIFIC_08 are only possible to trigger during power conversion.
Whenever any of the following catastrophic faults occur, the MFR_SPECIFIC_08 register will be updated
according to the register description below, but only if the black box record has been cleared since the last
catastrophic faults occurred. Faults logged include:
•
•
•
•
•
•
Overvoltage Fault (Device was Converting Power)
Overvoltage Fault (Device was not Converting Power)
Input Overcurrent Fault
Output Overcurrent Fault
Power Stage Fault
Input Over-Power Fault
Retrieving the Black Box Record
Reading the MFR_SPECIFIC_08 returns the current value of the Black Box record. If the register reads 00h, no
catastrophic faults have occurred since the record was last cleared. If any value other than 00h is stored in the
register, then de-code the value according to the register description below. In order to read-back the black box
record following a power-down, the STORE_DEFAULT_ALL command must be issued, to store the contents of
the black box record to NVM.
7.5.24.1 (D8h) MFR_SPECIFIC_08
The MFR_SPECIFIC_08 command is used to identify catastrophic faults which occur first, and store this
information to NVM. The MFR_SPECIFIC_08 command must be accessed through Write Byte/Read Byte
transactions. MFR_SPECIFIC_08 is a shared register. Transactions to this register do not require specific PAGE
settings. However, note that channels A and B have independent bit fields within the command.
7
R
0
6
R
0
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
CF_CHB
CF_CHA
LEGEND: R/W = Read/Write; R = Read only
图 57. MFR_SPECIFIC_08
表 65. MFR_SPECIFIC_08 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:6
Not used
R
0
Not used and set to 0.
5:3
2:0
CF_CHB
CF_CHA
RW
RW
NVM
NVM
Catastrophic fault record for channel B.
Catastrophic fault record for channel A.
版权 © 2017–2019, Texas Instruments Incorporated
95
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
Whenever a catastrophic fault occurs, the first event detected will trigger the MFR_SPECIFIC_08 command to
update according to the tables below. This recording happens independently for channel A and channel B. If the
PMBus host issues a STORE_DEFAULT_ALL, this information will be committed to NVM, and may be retrieved
at a later time. In order to clear the record for either channel, the PMBus host must write the corresponding bits
(CF_CHA for channel A, CF_CHB for channel B) to 000b, and issue STORE_DEFAULT_ALL.
Attempts to write any non-zero value to this command will be treated as invalid data - data will be ignored, the
appropriate flags in STATUS_CML, and STATUS_WORD, will be set, and the PMB_ALERT pin will be asserted
to notify the host of the invalid transaction.
表 66. Catastrophic Fault Recording Interpretation
CF_CHA / CF_CHB (binary)
Interpretation
No fault occurred
000b
001b
010b
011b
100b
101b
110b
111b
OVF occurred, power conversion was disabled
OVF occurred, power conversion was enabled
IIN Overcurrent fault occurred
IOUT Overcurrent fault occurred
Overtemperature fault occurred
Power stage fault occurred
Input overpower warning occurred
7.5.25 Board Identification and Inventory Tracking
The TPS53681 provides several bytes of arbitrarily programmable NVM-backed memory to allow for inventory
management and board identification. By default, these values reflect information about the date/revision of the
TPS53681 device being used itself. However, they may be re-programmed by the user, at the board level during
manufacturing. This provides a convenient and easy to use method of tracking boards, revisions and
manufacturing dates. The following commands are provided for this purpose:
•
•
•
•
MFR_ID - 16 bits of NVM for end-users to track the PCB/power supply supplier name
MFR_MODEL - 16 bits of NVM for tracking the manufacturer model number
MFR_REVISION - 16 bits of NVM for tracking PCB/power supply revision code
MFR_DATE - 16 bits of NVM for tracking PCB manufacturing date code
7.5.25.1 (9Ah) MFR_MODEL
The MFR_MODEL command is used to either set or read the manufacturer’s model number.
The MFR_MODEL command must be accessed through Block Write/Block Read transactions.
The MFR_MODEL command is shared between Channel A and Channel B. All transactions to this command will
affect both channels regardless of the PAGE command.
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
MFR_MODEL
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
MFR_MODEL
LEGEND: R/W = Read/Write; R = Read only
图 58. MFR_MODEL
表 67. MFR_MODEL Register Field Descriptions
Bit
Field
Type
Reset
Description
Arbitrary 16 bits with NVM backup for Model number
identification
15:0
MFR_MODEL
RW
NVM
96
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
7.5.25.2 (9Bh) MFR_REVISION
The MFR_REVISION command is used to either set or read the manufacturer’s revision number
The MFR_REVISION command must be accessed through Block Write/Block Read transactions.
The MFR_REVISION command is shared between Channel A and Channel B. All transactions to this command
will affect both channels regardless of the PAGE command.
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
MFR_REV
MFR_REV
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
LEGEND: R/W = Read/Write; R = Read only
图 59. MFR_REVISION
表 68. MFR_REVISION Register Field Descriptions
Bit
Field
Type
Reset
Description
Arbitrary 16 bits with NVM backup for revision number
identification
15:0
MFR_REV
RW
NVM
7.5.25.3 (9Dh) MFR_DATE
The MFR_DATE command is used to either set or read the manufacturing date.
The MFR_DATE command must be accessed through Block Write/Block Read transactions.
The MFR_DATE command is shared between Channel A and Channel B. All transactions to this command will
affect both channels regardless of the PAGE command.
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
MFR_DATE
MFR_DATE
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
LEGEND: R/W = Read/Write; R = Read only
图 60. MFR_DATE
表 69. MFR_DATE Register Field Descriptions
Bit
Field
Type
Reset
Description
Arbitrary 16 bits with NVM backup for manufacture date
identification
15:0
MFR_DATE
RW
NVM
版权 © 2017–2019, Texas Instruments Incorporated
97
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
7.5.26 Status Reporting
The TPS53681 provides several registers containing status information. The flags in these registers are latched
whenever their corresponding condition occurs, and are not cleared until either the CLEAR_FAULTS command is
issued, or the host writes a value of 1b to that bit location. Register maps for the all of the supported status
registers are shown in the following sections.
7.5.26.1 (78h) STATUS_BYTE
The STATUS_BYTE command returns one byte of information with a summary of the most critical faults, such as
over-voltage, overcurrent, over-temperature, etc.
The STATUS_BYTE command must be accessed through Read Byte transactions. STATUS_BYTE is a paged
register. In order to access STATUS_BYTE command for channel A, PAGE must be set to 00h. In order to
access STATUS_BYTE register for channel B, PAGE must be set to 01h. If PAGE is set FFh, the device return
value will reflect the status of Channel A.
7
0
6
R
5
R
4
R
3
R
2
R
1
R
0
R
BUSY
OFF
VOUT_OV
IOUT_OC
VIN_UV
TEMP
CML
OTHER
图 61. STATUS_BYTE
表 70. STATUS_BYTE Register Field Descriptions
Bit
Field
BUSY
OFF
Type
R
Reset
Description
7
6
0
Not supported and always set to 0.
R
Current
Status
This bit is asserted if the unit is not providing power to the
output, regardless of the reason, including simply not being
enabled.
0: Raw status indicating the IC is providing power to VOUT.
1: Raw status indicating the IC is not providing power to VOUT.
5
4
3
2
1
VOUT_OV
IOUT_OC
VIN_UV
TEMP
R
R
R
R
R
Current
Status
Output Over-Voltage Fault Condition
0: Latched flag indicating no VOUT OV fault has occurred.
1: Latched flag indicating a VOUT OV fault occurred
Current
Status
Output Over-Current Fault Condition
0: Latched flag indicating no IOUT OC fault has occurred.
1: Latched flag indicating an IOUT OC fault has occurred.
Current
Status
Input Under-Voltage Fault Condition
0: Latched flag indicating VIN is above the UVLO threshold.
1: Latched flag indicating VIN is below the UVLO threshold.
Current
Status
Over-Temperature Fault/Warning
0: Latched flag indicating no OT fault or warning has occurred.
1: Latched flag indicating an OT fault or warning has occurred.
CML
Current
Status
Communications, Memory or Logic Fault
0: Latched flag indicating no communication, memory, or logic
fault has occurred.
1: Latched flag indicating a communication, memory, or logic
fault has occurred.
0
OTHER
R
Current
Status
Other Fault (None of the Above)
This bit is used to flag faults not covered with the other bit faults.
In this case, UVF or OCW faults are examples of other faults not
covered by the bits [7:1] in this register.
0: No fault has occurred
1: A fault or warning not listed in bits [7:1] has occurred.
Per the description in the PMBus 1.3 specification, part II, TPS53681 does support clearing of status bits by
writing to STATUS registers. However, the bits in the STATUS_BYTE are summary bits only and reflect the
status of corresponding bits in STATUS_VOUT, STATUS_IOUT, etc... To clear these bits individually, the user
must clear them by writing to the corresponding STATUS_X register. For example: the output overcurrent fault
sets the IOUT_OC bit in STATUS_BYTE, and the IOUT_OC_FLT bit in STATUS_IOUT. Writing a 1 to the
IOUT_OC_FLT bit in STATUS_IOUT clears the fault in both STATUS_BYTE and STATUS_IOUT. Writes to
STATUS_BYTE itself will be treated as invalid transactions.
98
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
7.5.26.2 (79h) STATUS_WORD
The STATUS_WORD command returns two bytes of information with a summary of critical faults, such as over-
voltage, overcurrent, over-temperature, etc..
The STATUS_WORD command must be accessed through Read Word transactions. STATUS_WORD is a
paged register. In order to access STATUS_WORD command for channel A, PAGE must be set to 00h. In order
to access STATUS_WORD register for channel B, PAGE must be set to 01h. If PAGE is set FFh, the device
return value will reflect the status of Channel A.
15
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
VOUT
IOUT
INPUT
MFR
PGOOD
FANS
OTHER
UNKNOWN
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
R
BUSY
OFF
VOUT_OV
IOUT_OC
VIN_UV
TEMP
CML
OTHER
图 62. STATUS_WORD
表 71. STATUS_WORD Register Field Descriptions
Bit
Field
Type
Reset
Description
15
VOUT
R
Current
Status
Output Voltage Fault/Warning. Refer to STATUS_VOUT for
more information.
0: Latched flag indicating no VOUT fault or warning has
occurred.
1: Latched flag indicating a VOUT fault or warning has occurred.
14
13
IOUT
R
R
Current
Status
Output Current Fault/Warning. Refer to STATUS_IOUT for more
information.
0: Latched flag indicating no IOUT fault or warning has occurred.
1: Latched flag indicating an IOUT fault or warning has occurred.
INPUT
Current
Status
Input Voltage/Current Fault/Warning. Refer to STATUS_INPUT
for more information.
0: Latched flag indicating no VIN or IIN fault or warning has
occurred.
1: Latched flag indicating a VIN or IIN fault or warning has
occurred.
12
11
MFR
R
R
Current
Status
MFR_SPECIFIC Fault. Refer to STATUS_MFR for more
information.
0: Latched flag indicating no MFR_SPECIFIC fault has occurred.
1: Latched flag indicating a MFR_SPECIFIC fault has occurred.
PGOOD
Current
Status
Power Good Status. Note: Per the PMBus specification, the
PGOOD bit is not latched, always reflecting the current status of
the AVR_RDY/BVR_RDY pin.
0: Raw status indicating AVR_RDY/BVR_RDY pin is at logic
high.
1: Raw status indicating AVR_RDY/BVR_RDY pin is at logic
low.
10
9
FANS
R
R
R
R
R
0
0
0
0
Not supported and always set to 0.
Not supported and always set to 0.
Not supported and always set to 0.
Not supported and always set to 0.
OTHER
8
UNKNOWN
BUSY
7
6
OFF
Current
Status
This bit is asserted if the unit is not providing power to the
output, regardless of the reason, including simply not being
enabled.
0: Raw status indicating the IC is providing power to VOUT.
1: Raw status indicating the IC is not providing power to VOUT.
5
4
VOUT_OV
IOUT_OC
R
R
Current
Status
Output Over-Voltage Fault Condition
0: Latched flag indicating no VOUT OV fault has occurred.
1: Latched flag indicating a VOUT OV fault occurred
Current
Status
Output Over-Current Fault Condition
0: Latched flag indicating no IOUT OC fault has occurred.
1: Latched flag indicating an IOUT OC fault has occurred.
版权 © 2017–2019, Texas Instruments Incorporated
99
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
表 71. STATUS_WORD Register Field Descriptions (接下页)
Bit
Field
Type
Reset
Description
3
VIN_UV
R
Current
Status
Input Under-Voltage Fault Condition
0: Latched flag indicating VIN is above the UVLO threshold.
1: Latched flag indicating VIN is below the UVLO threshold.
2
1
TEMP
CML
R
R
Current
Status
Over-Temperature Fault/Warning
0: Latched flag indicating no OT fault or warning has occurred.
1: Latched flag indicating an OT fault or warning has occurred.
Current
Status
Communications, Memory or Logic Fault
0: Latched flag indicating no communication, memory, or logic
fault has occurred.
1: Latched flag indicating a communication, memory, or logic
fault has occurred.
0
OTHER
R
Current
Status
Other Fault (None of the Above)
This bit is used to flag faults not covered with the other bit faults.
In this case, UVF or OCW faults are examples of other faults not
covered by the bits [7:1] in this register.
0: No fault has occurred
1: A fault or warning not listed in bits [7:1] has occurred.
Per the description in the PMBus 1.3 specification, part II, TPS53681 does support clearing of status bits by
writing to STATUS registers. However, the bits in the STATUS_WORD are summary bits only and reflect the
status of corresponding bits in STATUS_VOUT, STATUS_IOUT, etc... To clear these bits individually, the user
must clear them by writing to the corresponding STATUS_X register. For example: the output overcurrent fault
sets the IOUT_OC bit in STATUS_WORD, and the IOUT_OC_FLT bit in STATUS_IOUT. Writing a 1 to the
IOUT_OC_FLT bit in STATUS_IOUT clears the fault in both STATUS_WORD and STATUS_IOUT. Writes to
STATUS_WORD will be treated as invalid transactions.
7.5.26.3 (7Ah) STATUS_VOUT
The STATUS_VOUT command returns one byte of information relating to the status of the converter's output
voltage related faults.
The STATUS_VOUT command must be accessed through Read Byte/Write Byte transactions. STATUS_VOUT
is a paged register. In order to access STATUS_VOUT command for channel A, PAGE must be set to 00h. In
order to access STATUS_VOUT register for channel B, PAGE must be set to 01h. If PAGE is set FFh, the
device return value will reflect the status of Channel A.
7
6
5
4
3
2
0
1
0
RW
0
0
RW
RW
0
0
VOUT_OVF
VOUT_OVW
VOUT_UVW
VOUT_UVF
VOUT_MIN_M
AX
TON_MAX
TOFF_MAX
VOUT_TRACK
图 63. STATUS_VOUT
表 72. STATUS_VOUT Register Field Descriptions
Bit
Field
VOUT_OVF
Type
Reset
Description
7
RW
Current
Status
Output Over-Voltage Fault
0: Latched flag indicating no VOUT OV fault has occurred.
1: Latched flag indicating a VOUT OV fault has occurred.
6
5
4
VOUT_OVW
VOUT_UVW
VOUT_UVF
R
0
0
Not supported and always set to 0.
Not supported and always set to 0.
R
RW
Current
Status
Output Under-Voltage Fault
0: Latched flag indicating no VOUT UV fault has occurred.
1: Latched flag indicating a VOUT UV fault has occurred.
100
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
表 72. STATUS_VOUT Register Field Descriptions (接下页)
Bit
Field
Type
Reset
Description
3
VOUT_MIN_MAX
RW
Current
Status
Output Voltage Max/Min Exceeded Warning
0: Latched flag indicating no VOUT_MAX/VOUT_MIN warning
has occurred.
1: Latched flag indicating that an attempt has been made to set
the output voltage to a value higher than allowed by the
VOUT_MAX/VOUT_MIN command.
2
1
0
TON_MAX
R
R
R
0
0
0
Not supported and always set to 0.
Not supported and always set to 0.
Not supported and always set to 0.
TOFF_MAX
VOUT_TRACK
Per the description in the PMBus 1.3 specification, part II, TPS53681 does support clearing of status bits by
writing to STATUS registers. Writing a 1 to any supported bit in this register will attempt to clear it as a fault
condition.
7.5.26.4 (7Bh) STATUS_IOUT
The STATUS_IOUT command returns one byte of information relating to the status of the converter's output
current related faults.
The STATUS_IOUT command must be accessed through Read Byte/Write Byte transactions. STATUS_IOUT is
a paged register. In order to access STATUS_IOUT command for channel A, PAGE must be set to 00h. In order
to access STATUS_IOUT register for channel B, PAGE must be set to 01h. If PAGE is set FFh, the device return
value will reflect the status of Channel A.
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
0
0
IOUT_OCF
IOUT_OCUVF
IOUT_OCW
IOUT_UCF
CUR_SHAREF
POW_LIMIT
POUT_OPF
POUT_OPW
图 64. STATUS_IOUT
表 73. STATUS_IOUT Register Field Descriptions
Bit
Field
IOUT_OCF
Type
Reset
Description
7
RW
Current
Status
Output Over-Current Fault
0: Latched flag indicating no IOUT OC fault has occurred.
1: Latched flag indicating a IOUT OC fault has occurred .
6
5
IOUT_OCUVF
IOUT_OCW
R
0
Not supported and always set to 0.
RW
Current
Status
0: Latched flag indicating no IOUT OC warning has occurred
1: Latched flag indicating a IOUT OC warning has occurred
4
3
IOUT_UCF
R
0
Not supported and always set to 0.
CUR_SHAREF
RW
Current
Status
0: Latched flag indicating no current sharing fault has occurred
1: Latched flag indicating a current sharing fault has occurred
2
1
0
POW_LIMIT
POUT_OPF
POUT_OPW
R
R
R
0
0
0
Not supported and always set to 0.
Not supported and always set to 0.
Not supported and always set to 0.
Per the description in the PMBus 1.3 specification, part II, TPS53681 does support clearing of status bits by
writing to STATUS registers. Writing a 1 to any supported bit in this register will attempt to clear it as a fault
condition.
7.5.26.5 (7Ch) STATUS_INPUT
The STATUS_INPUT command returns one byte of information relating to the status of the converter's input
voltage and current related faults.
The STATUS_INPUT command must be accessed through Read Byte/Write Byte transactions. The
STATUS_INPUT command is shared between Channel A and Channel B. All transactions to this command will
affect both channels regardless of the PAGE command.
版权 © 2017–2019, Texas Instruments Incorporated
101
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
7
6
0
5
0
4
3
2
1
0
RW
RW
RW
RW
RW
RW
VIN_OVF
VIN_OVW
VIN_UVW
VIN_UVF
LOW_VIN
IIN_OCF
IIN_OCW
PIN_OPW
图 65. STATUS_INPUT Register
表 74. STATUS_INPUT Register Field Descriptions
Bit
Field
Type
Reset
Description
7
VIN_OVF
R
Current
Status
Input Over-Voltage Fault
0: Latched flag indicating no VIN OV fault has occurred.
1: Latched flag indicating a VIN OV fault has occurred.
6
5
4
VIN_OVW
VIN_UVW
VIN_UVF
R
R
R
0
0
Not supported and always set to 0.
Not supported and always set to 0.
Current
Status
Input Under-Voltage Fault
0: Latched flag indicating no VIN UV fault has occurred.
1: Latched flag indicating a VIN UV fault has occurred.
3
2
1
0
LOW_VIN
IIN_OCF
IIN_OCW
PIN_OPW
R
R
R
R
Current
Status
Unit Off for insufficient input voltage
0: Latched flag indicating no LOW_VIN fault has occurred.
1: Latched flag indicating a LOW_VIN fault has occurred
Current
Status
Input Over-Current Fault
0: Latched flag indicating no IIN OC fault has occurred.
1: Latched flag indicating a IIN OC fault has occurred.
Current
Status
Input Over-Current Warning
0: Latched flag indicating no IIN OC warning has occurred.
1: Latched flag indicating a IIN OC warning has occurred.
Current
Status
Input Over-Power Warning
0: Latched flag indicating no input over-power warning has
occurred.
1: Latched flag indicating a input over-power warning has
occurred.
Per the description in the PMBus 1.3 specification, part II, TPS53681 does support clearing of status bits by
writing to STATUS registers. Writing a 1 to any supported bit in this register will attempt to clear it as a fault
condition.
7.5.26.6 (7Dh) STATUS_TEMPERATURE
The STATUS_TEMPERATURE command returns one byte of information relating to the status of the converter's
temperature related faults.
The STATUS_TEMPERATURE command must be accessed through Read Byte/Write Byte transactions.
STATUS_TEMPERATURE is a paged register. In order to access STATUS_TEMPERATURE command for
channel A, PAGE must be set to 00h. In order to access STATUS_TEMPERATURE register for channel B,
PAGE must be set to 01h. If PAGE is set FFh, the device return value will reflect the status of Channel A.
7
6
5
0
4
0
3
0
2
0
1
0
0
0
RW
OTF
RW
OTW
UTW
UTF
Reserved
图 66. STATUS_TEMPERATURE Register
表 75. STATUS_TEMPERATURE Register Field Descriptions
Bit
Field
Type
Reset
Description
7
OTF
RW
Current
Status
Over-Temperature Fault
0: (Default) A temperature fault has not occurred.
1: A temperature fault has occurred.
6
OTW
RW
Current
Status
Over-Temperature Warning
0: (Default) A temperature warning has not occurred.
1: A temperature warning has occurred.
102
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
表 75. STATUS_TEMPERATURE Register Field Descriptions (接下页)
Bit
5
Field
Type
R
Reset
0
Description
UTW
Not supported and always set to 0.
Not supported and always set to 0.
Always set to 0.
4
UTF
R
0
3-0
Reserved
R
0000
Per the description in the PMBus 1.3 specification, part II, TPS53681 does support clearing of status bits by
writing to STATUS registers. Writing a 1 to any supported bit in this register will attempt to clear it as a fault
condition.
7.5.26.7 (7Eh) STATUS_CML
The STATUS_CML command returns one byte with contents regarding communication, logic, or memory
conditions.
The STATUS_CML command must be accessed through Read Byte/Write Byte transactions. The STATUS_CML
command is shared between Channel A and Channel B. All transactions to this command will affect both
channels regardless of the PAGE command.
7
6
5
4
3
2
0
1
0
RW
RW
RW
RW
MEM
0
RW
0
IV_CMD
IV_DATA
PEC_FAIL
PRO_FAULT
Reserved
COM_FAIL
CML_OTHER
图 67. STATUS_CML Register
表 76. STATUS_CML Register Field Descriptions
Bit
Field
Type
Reset
Description
7
IV_CMD
RW
Current
Status
Invalid or Unsupported Command Received
0: Latched flag indicating no invalid or unsupported command
has been received.
1: Latched flag indicating an invalid or unsupported command
has been received.
6
5
IV_DATA
RW
RW
Current
Status
Invalid or Unsupported Data Received
0: Latched flag indicating no invalid or unsupported data has
been received.
1: Latched flag indicating an invalid or unsupported data has
been received.
PEC_FAIL
Current
Status
Packet Error Check Failed
0: Latched flag indicating no packet error check has failed
1: Latched flag indicating a packet error check has failed
4
3
Reserved
MEM
R
0
Always set to 0.
RW
Current
Status
Memory/NVM Error
0: Latched flag indicating no memory error has occurred
1: Latched flag indicating a memory error has occurred
2
1
Reserved
R
0
Always set to 0.
COM_FAIL
RW
Current
Status
Other Communication Faults
0: Latched flag indicating no communication fault other than the
ones listed in this table has occurred.
1: Latched flag indicating a communication fault other than the
ones listed in this table has occurred.
0
CML_OTHER
R
0
Not supported and always set to 0.
Per the description in the PMBus 1.3 specification, part II, TPS53681 does support clearing of status bits by
writing to STATUS registers. Writing a 1 to any bit in this register will attempt to clear it as a fault condition.
7.5.26.8 (80h) STATUS_MFR_SPECIFIC
The STATUS_MFR_SPECIFIC command returns one byte containing manufacturer-defined faults or warnings.
版权 © 2017–2019, Texas Instruments Incorporated
103
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
The STATUS_MFR_SPECIFIC command must be accessed through Read Byte/Write Byte transactions.
STATUS_MFR_SPECIFIC is a paged register. In order to access STATUS_MFR_SPECIFIC command for
channel A, PAGE must be set to 00h. In order to access STATUS_MFR_SPECIFIC register for channel B, PAGE
must be set to 01h. If PAGE is set FFh, the device return value will reflect the status of Channel A.
图 68. STATUS_MFR_SPECIFIC Register
7
6
5
4
3
2
0
1
0
0
RW
RW
RW
RW
RW
RW
FLT_PS
VSNS_OPEN MAX_PH_WAR
N
TSNS_LOW
RST_VID
(Page 0)
Reserved
PHFLT
表 77. STATUS_MFR_SPECIFIC Register Field Descriptions
Bit
Field
Type
Reset
Description
7
MFR_FAULT_PS
RW
Current
Status
Power Stage Fault
0b: Latched flag indicating no fault from TI power stage has
occurred.
1b: Latched flag indicating a fault from TI power stage has
occurred.
6
5
VSNS_OPEN
RW
RW
Current
Status
VSNS pin open
0b: Latched flag indicating VSNS pin was not open at power-up.
1b: Latched flag indicating VSNS pin was open at power-up.
MAX_PH_WARN
Current
Status
Maximum Phase Warning
If the selected operational phase number is larger than the
maximum available phase number specified by the hardware,
then MAX_PH_WARN is set, and the operational phase number
is changed to the maximum available phase number.
0b: Latched flag indicating no maximum phase warning has
occurred.
1b: Latched flag indicating a maximum phase warning has
occurred.
4
3
TSNS_LOW
RW
RW
Current
Status
0b: Latched flag indicating that TSEN < 150 mV before soft-
start.
1b: Latched flag indicating that TSEN ≥ 150 mV before soft-start.
RST_VID (Page 0)
Current
Status
RST_VID (Page 0 only)
0b: A VID reset operation has NOT occurred
1b: A VID reset operation has occurred
Always set to 0.
2:1
0
Reserved
PHFLT
R
00b
RW
Current
Status
Phase current share fault. The PHFLT bit is set if any phase has
current imbalance warnings occurring repetitively for 7 detection
cycles (~500 µs continuously). Phases with current imbalance
warnings may be read back via MFR_SPECIFIC_03.
0b: No repetitive current share fault has occurred
1b: Repetitive current share fault has occurred
Per the description in the PMBus 1.3 specification, part II, TPS53681 does support clearing of status bits by
writing to STATUS registers. Writing a 1 to any supported bit in this register will attempt to clear it as a fault
condition.
104
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
8 Applications, Implementation, and Layout
NOTE
Information in the following Applications section is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI's customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS53681 device has a very simple design procedure. All programmable parameters can be configured by
PMBus and stored in NVM as the new default values to minimize external component count. This design
describes a typical 6-phase, 0.9-V, 300-A application and 2-phase 0.8-V, 90-A application.
8.2 Typical Application
8.2.1 6-phase, 0.9-V, 300-A Application and 2-phase 0.8-V, 90-A Application
Copyright © 2017–2019, Texas Instruments Incorporated
105
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
8.2.1.1 Schematic
C2
C1
C3
1 mF
1 mF
1 mF
VREF_P
R17 475 kΩ
R2
0 Ω
R16
154 kΩ
3.3-V VIN
R12
0ꢀ
C4
1 mF
R1
0 Ω
38
37
36
35
34
33
32
31
40
39
VREF_P
C5
1 mF
R15 0 Ω
30
29
28
VOUT_B
BVSP
BCSP2
ACSP6/BCSP3
BPWM1
BPWM2
BPWM1
1
2
3
4
5
6
7
8
9
BCSP2
BPWM2
APWM6/BPWM3
APWM5
ACSP6/BCSP3
APWM6/BPWM3
ACSP5 27
ACSP5
ACSP4
APWM5
APWM4
APWM3
APWM2
APWM1
SMB_DIO
26
25
24
23
22
21
ACSP4
APWM4
TPS53681
U1
ACSP3
ACSP2
ACSP3
ACSP2
ACSP1
AVSN
APWM3
APWM2
ACSP1
APWM1
R6 0 Ω
PMB_DIO
R5 0 Ω
AVSP
VOUT_A
R18
SMB_CLK
11
PMB_CLK
10
3.3-V VIN
12 13 14
15
16
17
18
19
20
R27
R20
10 kΩ
R19
R21
10 kΩ
R28
C9
10 kΩ
10 kΩ 10 kΩ
10 kΩ
BVR_EN
0.1 mF
C7
1 nF
C6
1 nF
Figure 69. 6-Phase + 2-Phase Application
106
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
VREF_P
1
2
3
REFIN
IOUT
TAO/FLT 12
ATAO
C20
DNP
VREF_P
1
2
3
REFIN
IOUT
TAO/FLT 12
ATAO
ACSP2
R21
R24 0ꢀ
C10
DNP
ACSP1
R16
5-V VIN
LSET
EN/FCCM 11
PWM 10
R19 0ꢀ
R22
2.2 Ω
110 kΩ
5-V VIN
LSET
EN/FCCM 11
PWM 10
APWM2
R17
2.2 Ω
110 kΩ
4
VDD
5-V VIN
APWM1
BOOT
CSD95490Q5MC
9
C21
2.2 µF
C22
2.2 µF
4
VDD
5-V VIN
U3
R25
0 Ω
C25
0.1 mF
BOOT
CSD95490Q5MC
9
C11
2.2 µF
C12
2.2 µF
U2
12-V VIN
R20
0 Ω
C15
0.1 mF
VOS
SW
BOOTR
VIN
8
7
12-V VIN
5
6
VOS
SW
BOOTR
VIN
8
7
VOUTA
L1
5
6
VOUTA
C26
C27
C28
C29
L1
150 nH
4.7 nF 22 mF 22 mF
22 mF
C23
0.1 mF
PC8
PC7
PC6
C16
C17
C18
C19
PC5 0.18 mΩ
470 mF
R23
DNP
150 nH
470 mF 470 mF 470 mF
4.7 nF 22 mF 22 mF
22 mF
C13
PC4
PC3
PC2
PC1 0.18 mΩ
470 mF
R18
DNP
0.1 mF
470 mF 470 mF 470 mF
C24
DNP
C14
DNP
VREF_P
1
2
3
REFIN
IOUT
TAO/FLT 12
ATAO
C40
DNP
VREF_P
1
2
3
REFIN
IOUT
TAO/FLT 12
ATAO
ACSP4
R31
R34 0ꢀ
C30
DNP
ACSP3
5-V VIN
LSET
EN/FCCM 11
PWM 10
R26
R29 0ꢀ
R32
2.2 Ω
110 kΩ
5-V VIN
LSET
EN/FCCM 11
PWM 10
APWM4
R27
2.2 Ω
110 kΩ
4
VDD
5-V VIN
APWM3
BOOT
CSD95490Q5MC
9
C41
2.2 µF
C42
2.2 µF
4
VDD
5-V VIN
U5
R35
0 Ω
C45
0.1 mF
BOOT
CSD95490Q5MC
9
C31
2.2 µF
C32
2.2 µF
U4
12-V VIN
R30
0 Ω
C35
0.1 mF
VOS
SW
BOOTR
VIN
8
7
12-V VIN
5
6
VOS
SW
BOOTR
VIN
8
7
VOUTA
L1
5
6
VOUTA
C46
C47
C48
C49
L1
150 nH
4.7 nF 22 mF 22 mF
22 mF
C13
0.1 mF
PC16 PC15 PC14
470 mF 470 mF 470 mF
C36
C37
C38
C39
PC13 0.18 mΩ
470 mF
R33
DNP
150 nH
4.7 nF 22 mF 22 mF
22 mF
C13
PC12 PC11 PC10
PC9 0.18 mΩ
470 mF
R28
DNP
0.1 mF
470 mF 470 mF 470 mF
C44
DNP
C34
DNP
VREF_P
1
2
3
REFIN
IOUT
TAO/FLT 12
ATAO
C60
DNP
VREF_P
1
2
3
REFIN
IOUT
TAO/FLT 12
ATAO
ACSP6
R41
R44 0ꢀ
C50
DNP
ACSP5
5-V VIN
LSET
EN/FCCM 11
PWM 10
R36
R39 0ꢀ
R42
2.2 Ω
110 kΩ
5-V VIN
LSET
EN/FCCM 11
PWM 10
APWM6
R37
2.2 Ω
110 kΩ
4
VDD
5-V VIN
APWM5
BOOT
CSD95490Q5MC
9
C61
2.2 µF
C62
2.2 µF
4
VDD
5-V VIN
U7
R45
0 Ω
C65
0.1 mF
BOOT
CSD95490Q5MC
9
C51
2.2 µF
C52
2.2 µF
U6
12-V VIN
R40
0 Ω
C55
0.1 mF
VOS
SW
BOOTR
VIN
8
7
12-V VIN
5
6
VOS
SW
BOOTR
VIN
8
7
VOUTA
L1
5
6
VOUTA
C66
C67
C68
C69
L1
150 nH
4.7 nF 22 mF 22 mF
22 mF
C13
0.1 mF
PC24 PC23 PC22
470 mF 470 mF 470 mF
C56
C57
C58
C59
PC21 0.18 mΩ
470 mF
R43
DNP
150 nH
4.7 nF 22 mF 22 mF
22 mF
C13
PC20 PC19 PC18
PC17 0.18 mΩ
470 mF
R38
DNP
0.1 mF
470 mF 470 mF 470 mF
C64
DNP
C54
DNP
VREF_P
1
2
3
REFIN
TAO/FLT 12
BTAO
VREF_P
1
2
3
REFIN
IOUT
TAO/FLT 12
BTAO
C80
DNP
C70
DNP
BCSP2
IOUT
LSET
BCSP1
R46
R51
R54 0ꢀ
R49 0ꢀ
5-V VIN
EN/FCCM 11
PWM 10
5-V VIN
LSET
EN/FCCM 11
PWM 10
R52
2.2 Ω
110 kΩ
R47
2.2 Ω
110 kΩ
BPWM2
BPWM1
4
VDD
5-V VIN
4
VDD
5-V VIN
BOOT
CSD95490Q5MC
9
C81
2.2 µF
C82
2.2 µF
BOOT
CSD95490Q5MC
9
U9
C71
2.2 µF
C72
2.2 µF
U8
R55
C85
R50
0 Ω
C75
0.1 mF
12-V VIN
0 Ω
0.1 mF
12-V VIN
VOS
SW
BOOTR
VIN
8
7
VOS
SW
BOOTR
VIN
8
7
5
6
5
6
VOUTB
L1
VOUTB
L1
150 nH
C86
C87
C88
C89
C76
C77
C78
C79
150 nH
4.7 nF 22 mF 22 mF
22 mF
C13
0.1 mF
4.7 nF 22 mF 22 mF
22 mF
PC32 PC31 PC30
470 mF 470 mF 470 mF
PC29 0.18 mΩ
470 mF
C13
0.1 mF
PC28 PC27 PC26
470 mF 470 mF 470 mF
R53
DNP
PC25 0.18 mΩ
470 mF
R48
DNP
C84
DNP
C74
DNP
Figure 70. Power Stage
Copyright © 2017–2019, Texas Instruments Incorporated
107
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
IIN_CSN
IIN_CSP
L2
55 nH
0.2 mΩ
R48
0.5 mΩ
12 V
VIN
P12V
C43
22 µF
C40
22 µF
C41
22 µF
PC2
470 µF
PC3
470 µF
C44
22 µF
Figure 71. 12-V Input Filter
VOUTA
C60
DNP
C61
DNP
C62
DNP
C63
DNP
C64
DNP
C65
DNP
C66
DNP
C67
DNP
C68
DNP
C69
DNP
C70
DNP
C71
10 mF
C72
10 mF
C73
10 mF
C74
10 mF
C75
10 mF
C76
10 mF
Figure 72. VOUTA Filter for a 6-Phase Application
VOUTB
C77
C78
C79
C80
10 mF
10 mF
DNP
DNP
VOUTB
C81
C82
C83
DNP
DNP
DNP
Figure 73. VOUTB Filter for a 2-Phase Application
8.2.1.2 Design Requirements
Table 78. Target Application Specifications
VOUTA
VOUTB
Number of phases
6
2
Input voltage range
Output voltage
IOUT
10.8 V – 13.2 V
0.9 V
300 A
150 A
0 mΩ
0.8 V
90 A
45 A
0 mΩ
IDYN(max)
Load-line
Fast slew rate (min)
Boot voltage, VBOOT
Maximum temperature, TMAX
PMBus Address
10 mV/μs
0.9 V
0.8 V
90°C
1100000 (C0h)
500 kHz
Switching frequeny (fSW
)
108
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
8.2.1.3 Detailed Design Procedure
The following steps illustrate how to configure and fine-tune via PMBus and stored in NVM as the new default
setting.
8.2.1.3.1 Choose Inductor
Smaller inductance values yield better transient performance, but also have a higher ripple and lower efficiency.
Higher inductance values have the opposite characteristics. It is common practice to limit the ripple current to
between 30% and 45% of the maximum per-phase current. In this design example, 30% of the maximum per-
phase current is used.
IOUT
; F VOUT
300 A
IPFP
=
× 30% =
× 0.3 = 15 A
13.2 V F 0.9 V 0.9 V
(4)
V
VOUT
1
1
:
IN max
L N
×
×
=
×
×
= 0.112 µH
IPFP
V
fSW
15 A
13.2 V 500 kHz
:
;
IN max
(5)
A standard inductor value of 150 nH with 0.18 mΩ DCR is chosen. With the same design procedure, the inductor
value for the Rail B (VOUTB) of 150 nH is chosen.
8.2.1.3.2 Select the Per-Phase Valley Current Limit
Equation 6 shows the calculation of the per-phase, valley current limit based on the maximum processor current,
the operating phase number and the per-phase current ripple IP-P
.
IOUT
n
IPFP
2
300 A
6
15 A
2
IOCL = lk ×
p F l
p = 150% ×
F l
p = 67.5A
where
•
•
•
•
k is the maximum operating margin
IOUT is the maximum processor current
IP-P is the ripple current
n is the number of phases
(6)
The factor k of 150% is used to avoid reaching current limits during transients. For this design, a 70-A valley
current limit is selected in PMBus GUI.
ISAT = IOCL + IPFP = 70 A + 15 A = 85A
(7)
Equation 7 indicates that the maximum saturation current for the inductor needs to be higher than 85 A. Using
the same design procedure, the valley current limit for Channel B is selected to be 80 A.
8.2.1.3.3 Set the Maximum Temperature Level (TMAX
)
For this design, TMAX is selected as 90°C. The temperature is sensed by the ATSEN and BTSEN pins through its
connection to the xTAO pins of each phase of the CSD95490Q5MC. The controller reports the highest
temperature sensed by power stages of Rail A and Rail B.
8.2.1.3.4 Set USR Thresholds to Improve Load Transient Performance
There are two levels of undershoot reduction protection (USR) (USR1/USR2) selection. USR1 enables up to 3 or
4 phases and USR2 enables up to the maximum number of phases. The initial setting of the USR threshold is to
start with USR1 and USR2 as OFF, and then to meet the load insertion transient requirement by lowering the
threshold to enable pulse-overlap during the load transients.
For this design, VOUTA USR1 is selected as 240 mV and USR2 is selected as 300 mV. VOUTB USR1 and
USR2 are selected as OFF.
8.2.1.4 Inductor DCR and Shunt Current Sensing Design for Input Power
This section describes designing the thermal compensation network. The NTC thermistor is used to compensate
thermal variations in the resistance of the inductor winding. The winding is usually copper. And as such has a
resistance coefficient of 3900 PPM/°C. Alternatively, the NTC thermistor characteristic is very non-linear and
requires two or three resistors to linearize them over the range of interest. Figure 74 shows a typical DCR circuit.
Copyright © 2017–2019, Texas Instruments Incorporated
109
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
RDCR
L
To load
VIN
RNTC RSERIES
RSEQU
RPAR
CSENSE
IIN_CSP
IIN_CSN
Figure 74. Typical DCR Current Sensing Circuit
Equation 8 calculates the voltage across the CSENSE capacitor when it exactly equals the voltage across RDCR
.
.
CSENSE × REQ
=
RDCR
where
•
REQ is the series/parallel combination of RSEQU, RNTC, RSERIES and RPAR
(8)
(9)
RP_N × RSEQU
REQ
=
RP_N + RSEQU
RPAR × (RNTC + RSERIES
RPAR + RNTC +RSERIES
)
RP_N
=
(10)
Ensure that CSENSE is a capacitor type which is stable over temperature, use X7R or better dielectric (C0G
preferred). Because calculating these values by hand can be time-consuming, TI offers a spreadsheet using the
Excel Solver function available to provide calculation assistance. Contact your local TI representative to get a
copy of the spreadsheet.
This example uses a simple design process to enable input shunt sensing, so no DCR network is needed. Insert
a 0.5-mΩ shunt resistor in series between the input inductor and the input bulk capacitors.
8.2.1.4.1 Compensation Design
Figure 75 shows the compensation block diagram of the DCAP+ architecture.
VRAMP
1/KACLL
+
+
VFB
+
+
+
+
+
tINT
1/KDCLL
RSENSE
KDIV
KINT
KAC
ꢀ
ꢀ
VDAC
ISUM_U
IL
Figure 75. DCAP+ Compensation Block Diagram
•
•
•
•
•
RSENSE: typical 5 mΩ which is gain from power stage
KDCLL: DC load line which is adjustable from 0 mΩ to 3.125 mΩ
KACLL: AC load line which is adjustable from 0.5 mΩ to 3.125 mΩ
KDIV: not be adjustable. Changing DCLL, this parameter changes automatically
τINT: Integrator time constant which is adjustable from 01 µs to 08 µs (scale = 1 µs) and from 10 µs to 40 µs
(scale = 5 µs)
•
•
KINT: Integrator time gain which can be adjustable from 0.5×, 0.66×, 1×, 2×
KAC: AC gain which is adjustable from 0.5×, 1×, 1.5×, 2×
For this design, Table 79 lists the default values that are preset into the PMBus GUI.
110
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
Table 79. PMBus GUI Default Values
VOUTA
VOUTB
AC_gain
AC_LL
2×
0.5 mΩ
INT_Time
INTGAIN
01 µs
10 µs
2×
8.2.1.4.2 Set PMBus Addresses
To communicate with other system controllers with the PMBus interfaces, use the values of R16 and R17
resistors to set the PMBus address.
R17
475 kΩ
VREF_P
ADDR
R16
154 kΩ
Figure 76. PMBus Address Setting
Contact your local Texas Instruments representative for a copy of PMBus address setting design tool
spreadsheet.
Copyright © 2017–2019, Texas Instruments Incorporated
111
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
8.2.1.5 Application Performance Plots
For this design, choose 500 kHz for the switching frequency. The frequency is an approximate frequency and is
expected to vary based on load and input voltage.
VVIN = 12 V
IOUTA = 10 A
VVOUT_A = 0.9 V
VVIN = 12 V
IOUTA = 10 A
VVOUT_A = 0.9 V
Figure 77. VOUT_A Enable Start-up
Figure 78. VOUT_A Enable Shut-down
VVIN = 12 V
IOUTB = 10 A
VVOUT_B = 0.8 V
VVIN = 12 V
IOUTB = 10 A
VVOUT_B = 0.8 V
Figure 79. VOUT_B Enable Start-up
Figure 80. VOUT_B Enable Shut-down
112
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
VVIN = 12 V
IOUTA = 30 A
VVOUT_A = 0.9 V
VVIN = 12 V
VVOUT_B = 0.8 V
IOUT_B = 30 A
Figure 81. Output Voltage (VOUTA) Ripple
Figure 82. Output Voltage (VOUTB) Ripple
VVIN = 12 V
VVOUT_A = 0.9 V
VVIN = 12 V
IOUT_A = 10 A
VVOUT_A = 0.9 V
IOUT_A = 10 A
Figure 83. VOUTA PWM Interleaving (Phases 1-4)
Figure 84. VOUTA PWM Interleaving (Phases 4-6)
VVIN = 12 V
VVOUT_B = 0.8 V
VVIN = 12 V
VVOUT_A = 0.9 V
IOUT_B = 10 A
IOUT_A = 10 A
Figure 86. VOUTB PWM Jitter
Figure 85. VOUTA PWM Jitter
Copyright © 2017–2019, Texas Instruments Incorporated
113
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
VVIN = 12 V
VVOUT_A = 0.9 V
VVIN = 12 V
VVOUT_B = 0.8 V
IOUT_A from 150 A to 300 A
Slew rate = 100 A/µs
IOUT_B from 1 A to 41 A
Slew rate = 100 A/µs
Figure 87. VOUTA Transient Response
Figure 88. VOUTB Transient Response
VVIN = 12 V
IVOUT_A = 30 A
VVIN = 12 V
IVOUT_A = 30 A
VOUT_A VID step from 0.8 V to 1.2 V
VOUT_A VID step from 1.2 V to 0.8 V
Figure 89. VOUTA VID-up Change
Figure 90. VOUTA VID-down Change
VVIN = 12 V
IVOUT_B = 30 A
VVIN = 1.2 V
IVOUT_B = 30 A
VOUT_B VID step from 0.8 V to 1.2 V
VOUT_B VID step from 1.2 V to 0.8 V
Figure 91. VOUTB VID-up Change
Figure 92. VOUTB VID-down Change
114
Copyright © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
VVIN = 12 V
VOUT_A change from 0.9 V to 1.2 V
VOUT_B change from 0.8 V to 1.2 V
Figure 93. RESET Function
60
50
40
30
20
10
0
300
250
60
50
300
250
200
150
100
50
200
150
100
50
40
30
20
10
0
0
0
-10
-20
-50
-100
-150
-200
-10
-20
-30
-40
-50
-100
-150
-200
Gain
Phase
Gain
Phase
-30
-40
103
104
105
106
103
104
105
106
Frequency (Hz)
Frequency (Hz)
D00182
D00182
VVIN = 12 V
VVOUT_A = 900 mV
VVIN = 12 V
VVOUT_B = 800 mV
IOUT_A = 100 A
IOUT_B = 30 A
Figure 94. Bode Plot
Figure 95. Bode Plot
版权 © 2017–2019, Texas Instruments Incorporated
115
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
9 Power Supply Recommendations
The TPS53681 device operates from 3.3-V supply at the V3P3 pin (pin 39) and the 12-V supply from the
VIN_CSNIN pin (pin 38). TI recommends the following power-up and power-down sequence in order for the
controller to monitor the complete power-up and power-down procedure, fault protection and fault recording. The
device provides pre-start up overvoltage protection when the controller and the power stage are enabled before
the 12-V input is applied.
3.3V
5V
PS_EN
12V
VR_EN
图 96. StartUp Waveforms
The recommended power-up sequence is:
1. 3.3 V
2. 5 V
3. PS_EN
4. 12 V
5. VR_EN
The recommended power-down sequence is:
1. VR_EN
2. 12 V
3. PS_EN
4. 5 V
5. 3.3 V
116
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
10 Layout
10.1 Layout Guidelines
Contact your local TI representative to get a copy of the schematic and PCB layout guide.
10.1.1 Device Guidelines
The TPS53681 device makes it easy to separate noisy driver interface lines from sensitive interface lines.
Because the power stage is external to the device, all gate-drive and switch-node traces must be local to the
inductor and power stages.
The device does not require special care in the layout of power chain components, because independent isolated
current feedback is provided. Route the phases as symmetrically as possible. Current feedback from each phase
must be free of noise and have equal amounts of effective current sense resistance.
MOST IMPORTANT LAYOUT SUGGESTION
Separate noisy driver interface lines from sensitive analog and PMBus interface
lines.
10.1.2 Power Stage Guidelines
•
•
•
•
•
•
Use the recommended land pattern including the via pattern for the power stage footprint.
The input voltage bypass capacitors require a minimum of two vias per pad (for both VIN and GND).
Place additional GND vias along the sides of the device as space allows.
For multi-phase systems, ensure that the GND pour connects all phases.
The VOS pin feedback point begins at the inner edge of the inductor output voltage pad.
Place the VDD and PVDD bypass capacitors directly next to pins on the top layer of the board.
版权 © 2017–2019, Texas Instruments Incorporated
117
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
10.2 Layout Examples
图 97. Controller Layout Example
118
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
Layout Examples (接下页)
ACSP6
ACSP3
ACSP5
ACSP2
ACSP4
ACSP1
BCSP1
VREF_P
VREF_P
VREF_P
VREF_P
VREF_P
VREF_P
VREF_P
图 98. Power Stage Current Sense Differential Pairs Layout Example
版权 © 2017–2019, Texas Instruments Incorporated
119
TPS53681
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
www.ti.com.cn
11 器件和文档支持
11.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.3 商标
NexFET, AutoBalance, PowerPad, PMBus, D-CAP+, E2E are trademarks of Texas Instruments.
Broadcom is a registered trademark of Broadcom Limited .
Cavium is a registered trademark of Cavium, Inc..
Intel is a registered trademark of Intel Corporation.
PMBus is a trademark of SMIF, Inc..
Xilinx is a registered trademark of Xilinx Inc..
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
120
版权 © 2017–2019, Texas Instruments Incorporated
TPS53681
www.ti.com.cn
ZHCSGE0B –JUNE 2017–REVISED JANUARY 2019
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2017–2019, Texas Instruments Incorporated
121
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS53681RSBR
TPS53681RSBT
ACTIVE
WQFN
WQFN
RSB
40
40
3000 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
TPS
53681
ACTIVE
RSB
NIPDAUAG
TPS
53681
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS53681RSBR
TPS53681RSBT
WQFN
WQFN
RSB
RSB
40
40
3000
250
330.0
330.0
12.4
12.4
5.25
5.25
5.25
5.25
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS53681RSBR
TPS53681RSBT
WQFN
WQFN
RSB
RSB
40
40
3000
250
338.0
338.0
355.0
355.0
50.0
50.0
Pack Materials-Page 2
PACKAGE OUTLINE
RSB0040E
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
7
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
5.1
4.9
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.6
(0.2) TYP
EXPOSED
11
20
THERMAL PAD
36X 0.4
10
21
2X
41
SYMM
3.6
3.15 0.1
1
30
0.25
0.15
40X
40
31
PIN 1 ID
(OPTIONAL)
0.1
C A B
SYMM
0.5
0.3
0.05
40X
4219096/A 11/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RSB0040E
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.15)
SYMM
40
31
40X (0.6)
40X (0.2)
1
30
36X (0.4)
41
SYMM
(4.8)
(1.325)
(
0.2) TYP
VIA
10
21
(R0.05)
TYP
11
20
(1.325)
(4.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219096/A 11/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RSB0040E
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.785)
4X ( 1.37)
40
31
40X (0.6)
1
30
40X (0.2)
36X (0.4)
SYMM
(0.785)
(4.8)
41
(R0.05) TYP
10
21
METAL
TYP
20
11
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 41
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219096/A 11/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
TPS53688
Dual-channel, 8-phase step-down, digital multiphase D-CAP+™ controller with VR13.HC SVID and PMBus
TI
TPS53688RSBR
Dual-channel, 8-phase step-down, digital multiphase D-CAP+™ controller with VR13.HC SVID and PMBus | RSB | 40 | -40 to 125
TI
TPS53688RSBT
Dual-channel, 8-phase step-down, digital multiphase D-CAP+™ controller with VR13.HC SVID and PMBus | RSB | 40 | -40 to 125
TI
©2020 ICPDF网 联系我们和版权申明