TPS541620RPBR [TI]
具有高级电流模式的 4.5V 至 15V 双路 6A 同步 SWIFT™ 降压转换器 | RPB | 25 | -40 to 150;
| 型号： | TPS541620RPBR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有高级电流模式的 4.5V 至 15V 双路 6A 同步 SWIFT™ 降压转换器 | RPB | 25 | -40 to 150 转换器 |
| 文件： | 总55页 (文件大小：4287K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS541620
ZHCSNC8A –FEBRUARY 2021 –REVISED MARCH 2021
具有内部补偿的TPS541620 4.5V 至15V、双路6A/单路12A、同步降压SWIFT™
转换器
1 特性
2 应用
• 具有无损电流感应功能的集成型24mΩ 和10mΩ
MOSFET
• 无线和有线通信基础设施设备
• 以太网交换机和路由器
• ASIC、SoC、FPGA、DSP I/O 电压轨
• 工业测试和测量设备
• 固定频率、内部补偿高级电流模式(ACM) 控制
• 输出电流高达6A 的双路输出
• 具有高达12A 的双相单路输出
• 面向单相或双相的相位交错运行
• 使用SYNC 和CLKO 同步到外部时钟
• 0.5V 至5.5V 输出电压范围
3 说明
TPS541620 是一款高度集成的非隔离式双路直流/直流
转换器，具有较高的工作频率，采用 3mm × 5mm 封
装。该器件可配置为两个单独的 6A 轨道，也可合并驱
动一个 12A 电流负载。该器件实现了具有可选斜坡幅
度配置的固定频率高级电流模式控制 (ACM)，可优化
环路带宽。两个模式选择引脚（MODE1 和 2）用于选
择开关频率、配置、时钟相位延迟和内部补偿。
• 每个开关频率有四种可选的PWM 斜坡选项，可优
化控制环路性能
• 软启动时间可由外部电容在单输出多相配置中配
置；对于双输出配置，固定为1ms
• 采用多相操作的真正差分遥感
• 独立的使能和电源正常指示功能
• 四个可选择的开关频率选项：500kHz、1MHz、
1.5MHz 和2.0MHz
• 支持安全预偏置启动
• 具有迟滞的过热保护
• -40°C 至150°C 的工作结温范围
• 3mm × 5mm 25 引脚VQFN-HR 封装，间距为
0.5mm
器件信息
封装(1)
封装尺寸（标称值）
器件型号
TPS541620
VQFN-HR (25)
3mm × 5mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
VIN
EN2/ISHARE
PGOOD2/CLKO
SYNC
PVIN
BP5
BOOT1
BOOT2
EN1
VOUT1
VOUT2
SW1
SW2
LO1
LO2
TPS541620
PGOOD1
CO1
CO2
FB1
FB2/VSHARE
SS
MODE2
10kW
GOSNS
PGND
MODE1
AGND
RMD1
RMD2
简化原理图（双路输出）
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSAZ4
TPS541620
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ZHCSNC8A –FEBRUARY 2021 –REVISED MARCH 2021
Table of Contents
8 Application and Implementation..................................19
8.1 Application Information............................................. 19
8.2 Typical Application - Dual Independent Outputs.......19
9 Power Supply Recommendations................................43
10 Layout...........................................................................43
10.1 Layout Guidelines................................................... 43
10.2 Layout Example...................................................... 44
11 Device and Documentation Support..........................48
11.1 Device Support........................................................48
11.2 接收文档更新通知................................................... 48
11.3 支持资源..................................................................48
11.4 Trademarks............................................................. 48
11.5 静电放电警告...........................................................48
11.6 术语表..................................................................... 48
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................6
6.5 Electrical Characteristics ............................................6
6.6 Typical Characteristics................................................9
7 Detailed Description......................................................11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram.........................................12
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................18
Information.................................................................... 48
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (February 2021) to Revision A (March 2021)
Page
• 将器件状态从“预告信息”更改为“量产数据”................................................................................................ 1
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5 Pin Configuration and Functions
5
6
4
3
2
1
24
PGND
SYNC
7
8
9
23 PGND
22 PGOOD1
21 PGOOD2/CLKO
25
PGND
MODE1
MODE2 10
20 EN1
11
12
13
14
15
16
17
18
19
图5-1. 25-Pin VQFN-HR RPB Package (Top View)
表5-1. Pin Functions
PIN
I/O/B/P(2)
DESCRIPTION
NAME
NO.
Bootstrap pin for the internal flying high-side driver. Connect a typical 100-nF capacitor from
this pin to SW2.
BOOT2
1
I
SW2
2
B
G
B
Channel 2 power stage switch node. Connect this pin to the channel 2 output inductor.
Power stage ground return
PGND
SW1
3, 7, 23, 25
4
Channel 1 power stage switch node. Connect this pin to the channel 1 output inductor.
Bootstrap pin for the internal flying high-side driver. Connect a typical 100-nF capacitor from
this pin to SW1.
BOOT1
PVIN1
SYNC
5
6
8
I
I
I
Power conversion input. Bypass with capacitor from PVIN1 (pin 6) to PGND (pin 7).
Synchronizes to external clock. Tie to BP5 for internal switching frequency. Connect it to an
external clock for frequency synchronization.
Pin strap set pin. Connect a resistor from this pin to GND to set supply configurations, dual
independent outputs, primary/secondary, and clock delays.
MODE1
9
I
Pin strap set pin. Select from four preselected switching frequencies, each with four settings
of compensation.
MODE2
NC1
10
11
I
No internal connection
—
External soft start for multi-phase configuration only. Place a capacitor from SS to AGND to
set output rise time. Float for dual-output configurations. Dual-output mode uses an internal
soft start of 1 ms.
SS
12
13
O
I
Feedback input. Connect to the output voltage of channel 1 with a resistor divider for dual-
output mode. For multi-phase configuration, FB1 is used for positive input of the remote
sense amplifier.
FB1
Connect to ground of the output capacitor as remote sense ground in multi-phase operation.
In dual-output mode, simply ground this pin to PGND.
GOSNS
AGND
BP5
14
15
16
I
G
Analog ground. Connect to PGND at one single point away from noisy circuitry.
LDO output. Connect a 2.2-µF to 4.7-µF capacitor to PGND. BP5 must not be connected to
an external load.
I/O
Feedback input. Connect to the output voltage of channel 2 with a resistor divider for dual-
output mode.
FB2/VSHARE
17
18
I/O
I/O
EN2/
Enable high to power on. This pin can also be used to externally adjust EN UVLO by
connecting a resistor divider between PVIN and AGND.
ISHARE(1)
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表5-1. Pin Functions (continued)
PIN
I/O/B/P(2)
DESCRIPTION
NAME
NO.
NC2
19
No internal connection
—
Enable high to power on. This pin can also be used to externally adjust EN UVLO by
connecting a resistor divider between PVIN and AGND.
EN1
20
21
I
PGOOD2/
CLKO
O
Open-drain power-good indicator for channel 2 output
PGOOD1
PVIN2
22
24
O
I
Open-drain power-good indicator for channel 1 output
Power conversion input. Bypass with a capacitor from PVIN2 (pin 24) to PGND (pin 23).
(1) Pin 18 only uses one operating mode for its lifetime.
(2) I = Input, O = Output, B = Bidirectional, P = Supply, G = Ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–3
MAX
16
18
16
18
6
UNIT
V
Input Voltage
Input Voltage
PVIN
PVIN to SW1, PVIN to SW2 (10 ns)
V
Output Voltage SW1, SW2
V
Output Voltage SW1, SW2 transients (10 ns)
Output Voltage BP5
V
V
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
–65
Input Voltage
Input Voltage
Input Voltage
6
V
BOOT1 –SW1, BOOT2 –SW2
FB1, FB2/ISHARE
6
V
PGOOD1, PGOOD2/CLKO
6
V
Output Voltage EN1, EN2/VSHARE
6
V
Input Voltage
MODE1, MODE2, SS, SYNC
6
V
TJ
Junction temperature
Storage temperature
150
150
°C
°C
Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, allpins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specificationJESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ± WWW V and/or ± XXX V may actually have higher
performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ± YYY V and/or ± ZZZ V may actually have higher
performance.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
MAX
UNIT
Input
Voltage
PVIN
4.5
15
V
Output
Voltage
PVIN Transient (10ns)
BP5
15
5.5
5.5
5.5
5.5
5.5
V
V
V
V
V
V
–0.1
–0.1
–0.1
–0.1
–0.1
–0.1
Output
Voltage
Input
Voltage
BOOT1 - SW1, BOOT2 - SW2
FB1, FB2/ISHARE
PGOOD1, PGOOD2/CLKO
EN1, EN2/VSHARE
Input
Voltage
Output
Voltage
Input
Voltage
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over operating junction temperature range (unless otherwise noted)
MIN
MAX
UNIT
Input
MODE1, MODE2, SS, SYNC
Voltage
5.5
V
–0.1
TJ
Junction temperature
Storage temperature
-40
-55
150
150
°C
°C
Tstg
6.4 Thermal Information
TPS541620
THERMAL METRIC(1)
RPB (VQFN-HR)
UNIT
25 PINS
37.5
0.6
RθJA
ΨJT
Junction-to-ambient thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
°C/W
°C/W
°C/W
9.4
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating junction temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
MOSFET RDS(ON)
RDS(on)HS
High-side FET on resistance
Low-side FET on resistance
VBST - VSW = 5 V, TJ = 25°C
BP5 = 5 V, TJ = 25°C
24
10
mΩ
RDS(on)LS
mΩ
Power stage driver dead-time from
Low-side off to high-side on(1)
tDEAD(LtoH)
5
ns
PVIN ≥12 V, TJ = 25°C, ILoad = 3 A
PVIN ≥12 V, TJ = 25°C, ILoad = 3 A
Power stage driver dead-time from
High-side off to low-side on(1)
tDEAD(HtoL)
RSW_disch
5
ns
SW discharge FET
32
Ω
INPUT SUPPLY and CURRENT
VPVIN1, VPVIN2 Power stage voltage
IVINSTBY
4.5
15
V
PVIN bias current
TJ = 25°C, EN = 5 V, non-switching
TJ = 25°C, EN1 = EN2 = 0 V
4
mA
µA
IVINSTBY
PVIN standby current
270
UNDERVOLTAGE LOCKOUT
VPVIN_UVLO
VPVIN_UVLO_HYS
VBP5
PVIN UVLO rising threshold
VIN slew rate 1 V/1 ms
3.5
4.8
3.7
200
5
3.9
5.2
V
mV
V
PVIN UVLO hysteresis
BP5 regulation voltage
BP5 UVLO rising voltage
BP5 UVLO falling voltage
BP5 UVLO hysteresis
LDO dropout voltage
IOUT = 70 mA, PVIN ≥6 V
VBP5_UVLO_RI
VBP5_UVLO_FA
VBP5_UVLO_HYS
VDROPOUT
3
V
2.7
300
V
mV
mV
PVIN = 4.5 V, ILOAD = 70 mA
550
1%
INTERNAL REFERENCE VOLTAGE
Feedback Voltage Feedback voltage
TJ = 25°C
500
mV
Feedback
Feedback accuracy(1)
accuracy
TJ = –40°C to 125°C
–1%
REMOTE SENSE AMPLIFIER
fUGBW
A0
Unity gain bandwidth(1)
Open loop gain(1)
Slew rate(1)
12
MHz
dB
75
SR
4.7
V/µs
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over operating junction temperature range (unless otherwise noted)
PARAMETER
Input range(1)
TEST CONDITIONS
MIN
–0.2
–1.5
TYP
MAX UNIT
VICM
0.6
1.5
V
VOFFSET
Input offset voltage(1)
mV
EN1 AND EN2 LOGIC THRESHOLD
VEN_TO_SW
VEN_ON_TH
VEN_OFF_TH
VENHYS
Enable to start switching
PVIN > 4.5 V, toggle EN
0.3
1.2
1.1
100
1.4
ms
V
EN rising threshold
EN falling threshold
EN hysteresis
1.3
1
V
mV
µA
IEN_pullup
EN pullup current, EN floating
PVIN = 12 V
INTERNAL BOOTSTRAP SWITCH
VF
BOOTSTRAP voltage drop
BOOT UVLO
Iboot = 10 mA
200
mV
V
VBOOT_UVLO
2.3
SWITCHING FREQUENCY
FSW1
PVIN = 12 V, VOUT = 1.2 V
PVIN = 12 V, VOUT = 1.2 V
PVIN = 12 V, VOUT = 1.2 V
PVIN = 12 V, VOUT = 1.2 V
450
900
500
1000
1500
2000
550
1100
1650
2200
kHz
kHz
kHz
kHz
FSW2
FSW
FSW3
1350
1800
FSW4
SW1, SW2 minimum controllable on-
time
ton_min
toff_min
SYNCHRONIZATION
40
50
ns
ns
SW1, SW2 minimum controllable off
time
150
200
VIH(SYNC)
VIL(SYNC)
DSYNC
High-level input
2
V
V
Low-level input
Input duty cycle
0.6
20%
–20%
2.2
80%
Sync to SW variation, % from sync to
SW(1)
FSYNC to SW
+20%
0.4
VCLKOHigh
VCLKOLow
tPSW(CLKO)
CLKO high-level output
CLKO low-level output
Pulsewidth output
V
V
Io = 20 μA, Cload = 20 pF
Io = 20 μA, Cload = 20 pF
Cload = 20 pF
80
ns
PRIMARY PHASE SHIFT
tSW12SW2
Phase delay from SW1 to SW2
180
216
°
Phase primary SYNC IN to SW1 delay
in 2-phase
tSYNC2SW1(P)
ns
SECONDARY
PHASE SHIFT
tSYNC2SW1(S)
tSYNC2SW1(S)
Phase delay from SYNC IN to SW1
Phase delay from SYNC IN to SW2
90
°
°
270
HIGH SIDE CURRENT DETECTION
High-side current limit, peak inductor
current
LOW SIDE CURRENT DETECTION
IHSOC
12 VIN, 1 VOUT, 1 MHz
8.0
9.5
11.5
A
Low-side current limit, valley inductor
current
ILSOC
12 VIN, 1 VOUT, 1 MHz
12 VIN, 1 VOUT, 1 MHz
6.2
6.8
9.0
A
A
Low-side negative current limit, valley
inductor current
ILSNOC
-4.2
-3.5
-2.8
Low Side Zero
Cross
Low-side zero cross
250
16
mA
tENTER_HICCUP
OCP hiccup entry time
cycles
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over operating junction temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
tHICDLY
Hiccup delay time
Tss = 1 ms
7
ms
OV / UV PROTECTION
VOVP
Overvoltage threshold
120%
10
tOVPDLY
VUVP
OVP response time(1)
Undervoltage threshold
UVP response time(1)
µs
80%
16
tUVPDLY
cycles
THERMAL SHUTDOWN
TSDN
Built-in thermal shutdown threshold(1)
165
20
°C
°C
Built-in thermal shutdown
hysteresis(1)
TSDN_HYS
INTERNAL SOFT START
Soft-start time (from switching to
tSS_single-output
Without CSS
Fixed
1
1
ms
ms
PGOOD high)
Soft-start time (from switching to
PGOOD high)
tSS_dual-output
EXTERNAL SOFT START
IC_tSS CSS charge current
RSS Soft-start discharge FET
CURRENT SHARE ACCURACY
Output current sharing accuracy,
2
µA
Tss <= 50 ms, Css < 0.3 μF
600
Ω
defined as the ratio of the current
difference between channels to total
current(sensing error only)(1)
ISHARE(acc)
15%
1
Load ≥0.5 × 6 A
Output current sharing accuracy,
defined as the ratio of the current
difference between channels to total
current(sensing error only)(1)
ISHARE(acc)
Load < 0.5 × 6 A
A
VISHARE_L
VISHARE_L
Fault voltage falling
Fault voltage rising
200
300
mV
mV
POWER GOOD COMPARATOR
VPG(thresh)
VPG(thresh)
VPG(thresh)
VPG(thresh)
IPGD_lkg
Power good threshold (%VFB
)
)
)
)
FB falling, PG high to low
FB rising, PG low to high
FB rising, PG high to low
FB falling, PG low to high
V(PGOOD1) = V(PGOOD2) = 5.5 V
87%
90%
90%
93%
93%
96%
Power good threshold (%VFB
Power good threshold (%VFB
Power good threshold (%VFB
107%
104%
110%
107%
113%
110%
PGOOD1, PGOOD2 leakage current
Delay for PGOOD low to high
Delay for PGOOD high to low
PGOOD output low voltage
1
µA
µs
µs
V
tPGDLY
50
10
tPGDLY
VPGDLOW
VMINVIN_OUTPUT
VIN = 4 V, VOUT = 0 V, IPGOOD = 6 mA
0.4
1.5
Minimum PVIN for asserted output
V
VPGOOD ≤0.4V
(1) Specified by design. Not production tested.
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6.6 Typical Characteristics
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
5VIN
5VIN
9VIN
9VIN
12VIN
16VIN
12VIN
16VIN
0
2
4
6
8
10
12
0
2
4
6
8
10
12
Output Current (A)
Output Current (A)
图6-1. Efficiency vs Output Current, VOUT = 1.0 V, 图6-2. Efficiency vs Output Current, VOUT = 1.8 V,
FSW = 1 MHz FSW = 1 MHz
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
5VIN
9VIN
9VIN
12VIN
16VIN
12VIN
12VIN
0
2
4
6
8
10
12
0
2
4
6
8
10
12
Output Current (A)
Output Current (A)
图6-3. Efficiency vs Output Current, VOUT = 3.3 V, 图6-4. Efficiency vs Output Current, VOUT = 5 5 V,
FSW = 1 MHz FSW = 1 MHz
4.5
1.015
1.014
1.013
1.012
1.011
1.01
5VIN
9VIN
4
12VIN
16VIN
3.5
3
2.5
2
1.009
1.008
1.007
1.006
1.005
1.5
1
1Vout
1.8Vout
3.3Vout
5.5Vout
0.5
0
2
4
6
8
10
12
0
2
4
6
8
10
12
Output Current (A)
Output Current (A)
图6-5. Power Dissipation vs Output Current, VIN
=
图6-6. Output Voltage Regulation vs Output
12 V, FSW = 1 MHz
Current, VOUT = 1.0 V, FSW = 1 MHz
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3.33
1120
1080
1040
1000
960
5VIN
9VIN
3.327
12VIN
16VIN
3.324
3.321
3.318
3.315
3.312
3.309
3.306
3.303
3.3
1Vout
920
1.8Vout
3.3Vout
5.5Vout
880
0
1
2
3
4
5
6
7
8
9
10
11
12
0
2
4
6
8
10
12
Output Current (A)
Output Current (A)
图6-7. Output Voltage Regulation vs Output
图6-8. Switching Frequency vs Output Current, VIN
Current, VOUT = 3.3 V, FSW = 1 MHz
= 12 V, FSW = 1 MHz
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7 Detailed Description
7.1 Overview
The TPS541620 regulator is an easy-to-use, dual-output, synchronous step-down DC-DC converter that
operates 4.5-V to 15-V supply voltage. The device is capable of delivering up to 6-A DC load current per output
with exceptional efficiency and thermal performance in a very small solution size. The device is highly
configurable where two outputs can be combined to deliver up to 12 A. When the TPS541620 operates in multi-
phase mode, phase interleaving enables the following:
• Input and output current and voltage ripple reduction
• Reduced RMS current power dissipation
• Better transient performance
• Use of a small inductor to save board space and cost
The TPS541620 uses a fixed-frequency, internally compensated advanced current mode control, which reduces
design time and requires fewer external components. The switching frequency, internal compensation, and
phase operation can be configured using pin strapping. MODE1 (pin 9) configures the phase operation. 表 7-3
shows the resistor values that are required to configure the phase operation and phase offset. The switching
frequency can be selected from preset values through pin-strapping on MODE2 (pin 10). Four switching
frequency options are available:
• 500 kHz
• 1.0 MHz
• 1.5 MHz
• 2.0 MHz
Each switching frequency has four options of ramp amplitude to optimize the loop bandwidth performance. The
TPS541620 is also capable of synchronization to an external clock. The wide switching frequency option allows
the device to meet a wide range of design requirements. It can be optimized to a small solution size with higher
frequency or to high efficiency with lower switching frequency. Applications with switching frequency of 1.5 MHz
and above can show a minor non-monotonic behavior at the beginning of start-up.
The TPS541620 also features the following:
• Open-drain power-good (PGOOD) flag
• Precision enable
• Internal or adjustable soft start time
• Start-up into pre-bias voltage
It provides a flexible and easy-to-use solution for a wide range of applications. Protection features include the
following:
• Thermal shutdown
• BP5 undervoltage lockout
• Cycle-by-cycle current limiting
• Short-circuit hiccup protection
The device pinout is optimized for simple, optimum PCB layout for EMI and thermal performance. The
TPS541620 is available in a 3-mm × 5-mm lead-less package.
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7.2 Functional Block Diagram
EN1 PGOOD1
Regulator
PVIN
BOOT1
Ext SS
SS
AGND
REFDAC
PWM
And
Deadtime
Control
+
FB1
Control
SW1
œ
GOSNS
Remote Sense
Amp
SYNC
PGND
MODE1
MODE2
Mode
Decode
Oscillator
OC
Protection
And
Current
Balance
OV/UV
Protection
TSD,
180o
Supervisory
PGND
PWM
And
Deadtime
Control
SW2
Control
FB2/VSHARE
Mux
BOOT2
PVIN
Ibalance
Mux
PGOOD2/
CLKO
EN2/
SHARE
7.3 Feature Description
7.3.1 Fixed-Frequency, Internally Compensated Advanced-Current-Mode Control
The TPS541620 synchronous buck converter employs a new control architecture. It supports stable static and
transient operation without complex external compensation design. This architecture employs ramp emulation
which enables very small duty cycles. The internally generated ramp is a function of emulating inductor current
information, enabling the use of low-ESR output capacitors such as multi-layered ceramic capacitors (MLCC).
Loop response can be optimized by tuning the amplitude of the internal ramp for different application
requirements with various inductor and output capacitor combinations through the MODE2 (pin 10). The
TPS541620 is easy to use and allows low external component count for high power density. Fixed-frequency
modulation also provides ease-of-filter design to overcome EMI noise.
7.3.2 Enable and UVLO
The precision enable feature of the TPS541620 allows the voltage on the EN1/EN2 pin (VEN) to control the
ON/OFF functionality of the device. The EN pin has a 1.4-μA typical internal pullup current source. Floating the
EN pin allows the device to start up when a valid input voltage is applied. The TPS541620 switching action and
output regulation are enabled when VEN is greater than 1.2 V (typical). While the device is switching, if the EN
voltage falls below 1.1 V (typical), the device stops switching.
It is recommended to enable the device at a voltage greater than the minimum input voltage. Control the turn-on
and turn-off using a resistor divider on the EN1 (EN2) pin, between VIN and AGND (see 图 7-1). Set the divider
to a voltage greater than the minimum input voltage as shown in 图 7-2. Select a top enable resistor of 100 kΩ
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and use 方程式 1 for RENB selection. It is recommended to use divider resistors with 1% tolerance or better and
with a temperature coefficient of 100 ppm or lower.
The minimum input voltage of the TPS541620 is 4.5 V, however, the minimum input voltage increases at higher
output voltages. 图7-2 plots the minimum required input voltage for each of the allowable switching frequencies
across the output voltage range. It is recommended to control the turn-on and turn-off of the device at an input
voltage greater than the minimum shown in 图7-2 using a resistor divider on the EN1 (EN2) pin, between VIN
and AGND (see 图7-1).
RENT ì 1.1
RENB
=
V -1.1
IN
(1)
VIN
VIN
100kO
EN1 (EN2)
AGND
RENB
图7-1. Enable ON/OFF Control
10
9.5
9
500 kHz
1000 kHz
1500 kHz
2000 kHz
8.5
8
7.5
7
6.5
6
5.5
5
4.5
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Output Voltage (V)
图7-2. Minimum Input Voltage
7.3.3 Internal LDO
The TPS541620 integrates an internal LDO, generating 5 V for control circuitry and MOSFET drivers. The (BP5)
LDO output is monitored and generates a power okay signal, enabling internal circuits when the voltage is 3 V or
greater. The signal disables internal circuits when the BP5 voltage is 2.7 V or lower. The BP5 pin must have a
minimum 1-µF bypass capacitor placed as close as possible to the pin and properly grounded. BP5 is not
designed to power external circuitry. The UVLO on BP5 voltage turns off the device when BP5 voltage is below
the threshold. It prevents the TPS541620 from operating until the BP5 voltage is enough for the internal circuitry.
Hysteresis on UVLO prevents the part from turning off during power up if VIN droops due to momentary input
current demands.
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7.3.4 Pre-biased Output Start-up
The device prevents current from being discharged from the output during start-up when a pre-biased output
condition exists. If the output is pre-biased, no SW pulses occur until the internal soft-start voltage rises above
the error amplifier input voltage (FB pins). As soon as the soft-start voltage exceeds the error amplifier input, SW
pulses start, the low-side zero-cross signal is used to shut down the low-side FET for the first eight cycles. This
prevents inductor current from reversing and discharging the output voltage. Once the eight cycles are
completed, the BOOT to SW cap is charged enough during the off-time periods to turn on the high-side FET
completely.
7.3.5 Current Sharing
In instances when a load current higher than 6 A is required by an application, the TPS541620 can be
configured to share current. Additionally, the advantage of multi-phase setup is that the output voltage ripple and
the input ripple current is reduced by the number of phases in parallel. Pin strapping on the MODE1 pin
configures the various modes that current sharing can be enabled as shown in 表 7-3. For applications requiring
up to 12 A of load current, the two outputs of the TPS541620 can be connected to enable current sharing
between two outputs of a single TPS541620.
7.3.6 Frequency Selection and Minimum On-Time and Off-Time
Switching frequency for the TPS541620 can be configured through the MODE2 pin on the device. The options
available to you are the following:
• 500 kHz
• 1 MHz
• 1.5 MHz
• 2.0 MHz
Selecting the appropriate resistor from 表 7-1 sets one of the four options, as well as the ramp capacitor value
for compensation.
The device has a minimum on-time of 40 ns (typ.) and a minimum off-time of 150 ns (typ.). Pay attention in
applications with minimum duty cycle at high input voltage and maximum duty cycle at low input voltage. The
minimum on-time and minimum off-time constrain the output voltage regulation in steady state operation. The
device pulse skips if the input voltage, output voltage, and switching frequency require an on-time that is smaller
than the minimum controllable on-time of 40 ns. Similarly, the device will operate in dropout when the input
voltage, output voltage, and switching frequency require a lower off-time than the controllable off-time of 150 ns.
The user must always stay away from operating beyond Ton_min and Toff_min conditions.
7.3.7 Ramp Compensation Selection
Internal ramp voltage is generated from an internal current source charging a capacitor. The current source
charges the capacitor with a slope of (VIN-VOUT)/L and discharges with a slope of (VOUT/L) to emulate the
inductor ripple current. This ramp is then fed back for control loop regulation and optimization according to
required output power stage, duty ratio, and switching frequency. Internal ramp amplitude is set by selecting the
appropriate ramp capacitor value. There are four ramp capacitor values available to the user:
• 1.5 pF
• 2.5 pF
• 4 pF
• 6 pF
These can be selected through the MODE pins. For the best performance, TI recommendeds using 1.5 pF for
output voltage less or equal to 4 V. For output voltage higher than 4 V, use 2.5 pF. In some cases, a feedforward
capacitor in parallel with a top-side feedback resistor is recommended to boost phase margin. Refer to TI
application note SLVA289 for details. It is a good practice to have a placeholder for the feedforward capacitor on
the board and only populate it when needed.
Connecting the pin-strapping resistor from MODE2 to ground selects the ramp capacitor value along with other
functions. The MODE2 pin is also used to set the desired switching frequency. Every switching frequency opnion
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(FSW) has four ramp capacitor values to allow you to tune the transient performance. 表 7-1 shows the pin-
strapping resistor options for switching frequency and internal ramp capacitor. For dual-output mode operation,
which includes an application with two one-phase outputs, MODE1 provides the selection of the internal ramp
capacitor for VOUT2 as shown in 表7-3. VOUT1 ramp is set by MODE2 as shown in 表7-1.
表7-1. MODE2 Pin-Strap Configuration
RAMP CAPACITOR VALUE FOR VOUT1
FREQUENCY (kHz)
RESISTOR FROM MODE2 TO AGND (kΩ)
(pF)
1.5
2.5
4
10.7
12.1
13.7
15.4
17.4
19.6
22.1
24.9
28.7
33.2
38.3
45.3
53.6
64.9
78.7
100
500
6
1.5
2.5
4
1000
1500
2000
6
1.5
2.5
4
6
1.5
2.5
4
6
7.3.8 Soft Start
The soft-start feature is used to prevent inrush current impacting the TPS541620 and its supply when power is
first applied. Soft start is achieved by slowly ramping up the target regulation voltage when the device is first
enabled or powered up. For dual-output applications, the external soft start is disabled and the outputs turn on
with an internally-set soft start time of 1 ms. In this situation, leave the SS pin floating. The external soft start is
enabled when the device is configured in multi-phase operation. Multi-phase applications that deliver high load
current can have a large amount of capacitance at the output. The soft-start time for such applications can be
extended by connecting an external capacitor CSS from the SS pin to AGND to make sure there is no sudden
current surge. Extended soft-start time further reduces the supply current required to charge up output
capacitors and supply any output loading. An internal current source (ICt_SS = 2 μA) charges CSS and generates
a ramp from 0 V to VFB to control the ramp-up rate of the output voltage. The soft-start capacitor CSS is
discharged through an internal FET of 600-Ω resistance when VOUT is shut down by fault protection or EN low.
The total time required to discharge the soft-start capacitor completely is 500 µs. When a large value of CSS is
connected and EN is toggled low only for a short period of time, CSS may not be fully discharged. The next soft-
start ramp follows the internal soft-start ramp before reaching the leftover voltage on CSS and then follows the
ramp programmed by CSS
.
7.3.9 Remote Sense Function
The device supports differential remote sense function for accurate output regulation. In multi-phase
configuration, FB1 and GOSNS pins are used for remote sensing purpose. If feedback resistors are required for
output voltage programming, the FB1 pin must be connected to the mid-point of the resistor divider. Additionally,
the GOSNS pin must always be connected to the load return. If feedback resistors are not required, the FB1 pin
must be connected to the positive sensing point of the load. Additionally, the GOSNS pin must always be
connected to the load return. The FB1 and GOSNS pins are extremely high-impedance input terminals of the
true differential remote sense amplifier. The feedback resistor divider must use resistor values much less than
100 kΩto reduce susceptibility to noise. A simple rule of thumb is to use a 10-kΩlower divider resistor and then
size the upper resistor to achieve the desired ratio.
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7.3.10 Adjustable Output Voltage
The voltage regulation loop in the TPS541620 regulates the FB pin voltage to be equal to the internal reference
voltage. The output voltage of the TPS541620 is set by a resistor divider to program the ratio from VOUT to VFB.
The resistor divider is connected from the output to ground with the mid-point connecting to the FB pin (VFB = 0.5
V).
The internal voltage reference and feedback loop produce precise voltage regulation over temperature. TI
recommends using divider resistors with 1% tolerance or better, and with a temperature coefficient of 100 ppm or
lower for increased DC accuracy over temperature. Typically, RFBT (top feedback resistor) equal to 10 kΩ to 100
kΩ is recommended. Larger RFBT and RFBB (bottom feedback resistor) values reduce the quiescent current
going through the divider, which helps maintain high efficiency at very light load. However, larger divider values
also make the feedback path more susceptible to noise. RFBB can be calculated by 方程式2.
≈
∆
«
’
÷
◊
VOUT - VFB
VFB
RFBT = RFBB
ì
(2)
7.3.11 Power Good
The power good pins (PGOOD1, PGOOD2) are open-drain outputs that must be connected to a pullup resistor
of 10 kΩ to a source less than 5.5 V (for example, BP5) to indicate the output voltage is within the PGOOD
window. The PGOOD detection is activated after soft start is completed. When the output voltage falls within a
window of ±10% of the target, there is a 50-μs delay after soft start is finished and PGOOD goes high. If the
output voltage falls outside of ±10% of target voltage during operation, PGOOD is pulled low after a 10-µs delay.
The PGOOD feature is active while the voltage at PVIN pin is either equal to or greater than 1.5 V.
7.3.12 Overcurrent Protection
The device detects low-side (LS) current during off-time and high-side (HS) current during on-time. The device
responds to an overcurrent fault when soft start is done.
Low-side Overcurrent Protection:
The device monitors valley current during HS off-time. If the inductor current is above the valley current limit
threshold, the next HS pulse is skipped, the LS FET remains on, and an internal counter increments. This
counter counts as long as inductor current is higher than valley at the clock edge. If the current goes below
valley at the clock edge, the counter is reset.
If the counter is able to count to 16 cycles without reset, then it is identified as a current limit fault and the device
hiccups. The device enters hiccup for seven cycles of internal soft start and then attempts a normal soft start.
High-side Overcurrent Limit:
The device implements a high-side overcurrent limit-to-limit peak current and prevents the inductor from
saturation when a short circuit happens. When the device hits peak current limit, the HS FET turns off and the
LS FET turns on. Once the inductor current clears the valley limit, the HS FET turns on at the next clock edge.
Negative Overcurrent Protection:
When the inductor current goes below the negative overcurrent threshold, the low-side FET turns off. It turns on
again at the next clock pulse.
7.3.13 Overvoltage and Undervoltage Protection
The device includes both output overvoltage protection and output undervoltage protection capability. The device
compares the FB voltage to internal preset voltages. If the FB voltage with respect to GOSNS voltage rises
above the output overvoltage protection threshold after a 10-μs delay, the device terminates normal switching
and enters continuous hiccup process. The device waits for 7 × Tss and tries to restart. Overvoltage protection is
enabled both during and after soft start is completed.
If the FB pin voltage with respect to GOSNS falls below the undervoltage protection threshold, the device enters
hiccup after 7 × Tss of wait time. Undervoltage protection is enabled after soft start is completed.
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7.3.14 Overtemperature Protection
An internal temperature sensor protects the devices from thermal runaway. The internal thermal shutdown
threshold, TSD, is fixed at 165°C typical with 20°C hysteresis. When the devices sense a temperature above TSD
,
power conversion stops until the sensed junction temperature falls by the thermal shutdown hysteresis amount.
Then, the device starts up again.
7.3.15 Frequency Synchronization
The TPS541620 device can synchronize to an external clock, which must fall in the ±20% range of the internal
frequency setting. For a standalone device, the external clock must be applied to the SYNC pin. A sudden
change in synchronization clock frequency causes an associated control loop response. This change results in
an overshoot or undershoot on the output voltage. When external sync is lost, the IC switches to its internal
preset switching frequency.
When the device is synchronized to an external clock signal, if the external clock signal is missing, the device
switches back to 75% of the preset free running frequency for approximately eight cycles. After that, the device
runs at its free running frequency.
The following occurs in dual-phase configuration with external clock:
• Both the outputs of the device are tied together.
• Switching frequency is set by the clock received at the SYNC pin of the device.
• Clock phase shift is set by MODE1 pin of the device. See Current Sharing for more details.
• GOSNS functions as the GND remote sense input.
VIN
PVIN
BP5
BOOT1
L1a
TPS541620
SYNC
VOUT
SW1
FB1
EN1
CO
PG2/CLKO
GOSNS
BOOT2
MODE1
MODE2
10 kΩ
RMODE1
SW2
L1b
CO
RMODE2
图7-3. Dual-phase Configuration with External Clock
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7.4 Device Functional Modes
7.4.1 Operation Mode
The TPS541620 is a highly-configurable device. It can be configured through pin strapping on the MODE1 and
MODE2 pins. 表 7-1, 表 7-2, and 表 7-3 show what aspects of the device can be configured by the respective
mode pins.
表7-2. MODE1 and MODE2 Pin Functions
PIN
FUNCTION 1
FUNCTION 2
Compensation tuning on VOUT2 in dual-
output conditions
MODE1
Phase setting for single and multi phase operation
Frequency and compensation tuning on output in multi-
phase operation or VOUT1 in dual-output operation
MODE2
表7-3. MODE1 Pin-Strap Configuration
PHASE
POSITION
FOR
PHASE
POSITION
FOR
RAMP
CAPACITOR
FOR VOUT2
(pF)
RESISTOR FROM
MODE1 TO AGND
OPERATION MODE
NOTES
(kΩ)
CHANNEL 1 CHANNEL 2
Sets phase positions for the two outputs
of the device.
10.7
In two-phase configuration
0°
180°
15.4
17.4
19.6
22.1
24.9
28.7
33.2
38.3
1.5
2.5
4
Sets phase position for both channels in
dual-output independent single phase
operation to 0° and 180°. Sets ramp
capacitor value for VOUT2.
Dual-output independent
single phase
0°
180°
6
1.5
2.5
4
Sets phase position for both channels in
dual output independent single phase
operation to 90° and 270°. Sets ramp
capacitor value for VOUT2.
Dual-output independent
single phase
270° from
Sync
90° from Sync
6
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPS541620 is a synchronous buck regulator designed for 4.5-V to 15-V input and two 6-A loads. This
procedure illustrates the design of a high-frequency switching regulator using ceramic output capacitors.
8.2 Typical Application - Dual Independent Outputs
L1
VOUT1
560nH
PVIN
J7
TPS541620RPBR
Cout1
Cout1
Cout1
1
2
100uF
100uF
100uF
U1
CBOOT1
CIN
47uF
CIN
22uF
CIN
100nF
CIN
0.1uF
1
2
6
5
BOOT1
SW1
PVIN
PVIN
BOOT1
SW1
24
0.1uF
100k
4
Cff1
J1
BP5
PGND
PGOOD1
FB1
16
22
13
1
BP5
PGOOD1
FB1
BP5
L2
open
Rfbt1
Rpg1
Rfbb1
Rinj1
PGND
CBP5
2.2µF
CBP5
EN2
0.1uF
CIN
47uF
CIN
22uF
CIN
100nF
CIN
0.1uF
18
20
CBOOT2
10.0k
10.0k
49.9
EN2/ISHARE
EN1
BOOT2
BOOT2
EN1
AGND
VOUT2
0.1uF
SW2
2
SW2
PVIN
1.2µH
BP5
Rpg2
PGND
PGOOD2/CLKO
J8
21
PGOOD2/CLKO
FB2/VSHARE
GOSNS
Cout2
100uF
Cout2
100uF
SYNC
MODE1
8
9
1
2
100k
SYNC
MODE1
MODE2
SS
Ren1t
open
Ren2t
open
17 FB2/ISHARE
14
EN1
EN2
MODE2 10
3
PGND
PGND
PGND
PGND
RM1M2
Ren1b
open
Ren2b
open
SS
12
7
23
Rinj2
49.9
PGND
10.0k
Rmode2
17.4k
Rmode1
PGND
11
19
25
NC
NC
Rfbb2
Rfbt2
15.4k
15
10.0k
56.2k
AGND
AGND
AGND
Cff2
TPS541620RPBR
NT2
AGND
AGND
100pF
PGND
AGND
Net-Tie
NT1
Net-Tie
AGND
PGND
图8-1. 12-V Input, 1.0-V and 3.3-V Dual Output Regulator Application Schematic
8.2.1 Design Requirements
For this design example, use the parameters shown in 表8-1.
表8-1. Design Parameters
PARAMETER
EXAMPLE VALUE
Input voltage range (VIN)
7 to 15 V, 12 V nominal
Output voltage (VOUT1
)
1.0 V
6 A
Output current rating (IOUT1
)
Steady state output ripple voltage
Output current load step
Transient response
10 mV
3 A
± 50 mV (± 5%)
3.3 V
Output voltage (VOUT2
)
Output current rating (IOUT2
)
6 A
Steady state output ripple voltage
Output current load step
Transient response
33 mV
3 A
± 165 mV (± 5%)
1000 kHz
Internal
Switching frequency (fSW
Soft start time
)
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表8-1. Design Parameters (continued)
PARAMETER
EXAMPLE VALUE
Operating temperature
25°C
8.2.2 Detailed Design Procedure
8.2.2.1 Switching Frequency
The first step is to decide on a switching frequency. The TPS541620 can operate at four different frequencies
from 500 kHz to 2.0 MHz. fSW is set by the resistor value from the MODE2 pin to ground. Typically, the highest
switching frequency possible is desired because it produces the smallest solution size or lower switching
frequency for a more efficient converter. The minimum controllable on-time and maximum off-time affect the
input voltage range and switching frequency.
The maximum switching frequency for a given application can be limited by the minimum on-time of the regulator
and the maximum fSW can be estimated with 方程式 3. Using the minimum 50-ns on-time, 15-V maximum input
voltage, and the lower voltage of the dual-output 1 V for this application, the maximum switching frequency is
1333 kHz. The minimum regulating input voltage is limited by the maximum off-time, switching frequency, and
output voltage. Using the maximum off-time of 150 ns, 7-V minimum input voltage, and the higher voltage of the
dual-output 3.3 V for this application with 方程式 4, the maximum switching frequency from 3.3 V and maximum
off-time is 3524 kHz.
The selected switching frequency must also consider the tolerance of the switching frequency. A switching
frequency of 1000 kHz is selected for a good balance of solution size and efficiency. To set the frequency to
1000 kHz, the selected MODE2 resistor is 17.4 kΩ per 表 7-1. To set for dual-output configuration, select a
MODE1 resistor is 15.4 kΩper 表7-3.
Voutmin
1 V
fsw =
fsw =
=
= 1333 kHz
tonì Vinmax 50 nsì15 V
(3)
Voutmax
3.3 V
1-
7 V
1-
Vinmin
toff
=
= 3524 kHz
150 ns
(4)
图 8-2 shows the maximum recommended input voltage versus output voltage for each frequency. 图 8-2 uses
the maximum minimum on-time of 50 ns and includes 10% tolerance on the switching frequency.
17
16
15
14
13
12
11
10
9
8
500 kHz
1000 kHz
1500 kHz
2000 kHz
7
6
5
4
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5
Output Voltage (V)
图8-2. Maximum Input Voltage Versus Output Voltage
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8.2.2.2 Output Inductor Selection
To calculate the effective value of the output inductor, use 方程式 5. K is a ratio that represents the amount of
inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output
capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor since
the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current.
Choosing small inductor ripple currents (through a large inductor) can degrade the transient response
performance. The inductor ripple, K, is normally 0.1 to 0.4 for the majority of applications, giving a peak-to-peak
ripple current range of 0.6 A to 2.4 A. The target Iripple must be 0.3 A or larger.
For this design example, K = 0.3 is used and the inductor values Lo1 and Lo2 are calculated to be 0.506 µH and
1.329 µH, respectively. An inductor with an inductance of 0.56 μH is selected for VOUT1 and 1.2 μH for VOUT2. It
is important that the RMS (Root Mean Square) current and saturation current ratings of the inductor not be
exceeded. The RMS and peak inductor current can be found in 方程式7 and 方程式8, respectively. For VOUT1 in
this design, the RMS inductor current is 6.019 A and the peak inductor current is 6.833 A. The chosen inductor is
a Coilcraft XAL6030-561. For VOUT2 in this design, the RMS inductor current is 6.032 A and the peak inductor
current is 7.073 A. The chosen inductor for VOUT2 is a Coilcraft XAL6030-122. XAL6030-561 has a saturation
current rating of 29 A, an RMS current rating of 17 A, and a typical DC series resistance of 3.01 mΩ. The
XAL6030-122 has a saturation current rating of 22 A, an RMS current rating of 13 A, and a typical DC series
resistance of 6.8 mΩ.
The peak current through the inductor is the inductor ripple current plus the DC output current. During power up,
faults, or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated in 方程式 8. In transient conditions, the inductor current can increase up to the switch current
limit of the device. For this reason, the most conservative approach is to specify the current ratings of the
inductor based on the switch current limit rather than the steady-state peak inductor current.
Vin - Vout
K ìIout
12 V -1 V
(
)
(
)
Vout
1 V
≈
’
≈
∆
’
Lo1=
Lo2 =
=
= 0.506 mH
∆
«
÷
◊
÷
◊
Vinì fsw
0.3ì 6 A 12 V ì1000 kHz
«
Vin - Vout
K ìIout
12 V - 3.3V
(
)
(
)
Vout
3.3 V
12 V ì1000 kHz
≈
’
≈
’
=
= 1.329 mH
∆
÷
∆
«
÷
Vinì fsw
0.3ì 6 A
«
◊
◊
(5)
vertical spacer
Vinmax- Vout1
15 V -1 V
(
)
(
)
Vout1
1 V
≈
’
≈
∆
’
Iripple1=
=
= 1.667 A
∆
÷
◊
÷
◊
Lo_eff ìN
Vinmax- Vout2
Lo_eff ìN
Vinmaxì fsw
0.56 mHì1 15 V ì1000 kHz
«
«
15 V - 3.3 V
(
)
(
)
Vout2
3.3 V
15 V ì1000 kHz
≈
’
≈
’
Iripple2 =
=
= 2.145 A
∆
÷
∆
«
÷
Vinmaxì fsw
1.2 mHì1
«
◊
◊
(6)
vertical spacer
2
2
2
2
1.667 A
(
12
I
IRIPPLE1
)
6
1
≈
’
≈
’
OUT1
IL1 RMS
=
+
=
+
= 6.019 A
)
= 6.032 A
∆
«
÷
◊
∆
«
÷
◊
(
)
N
12
2
2
2
2
2.145 A
12
I
IRIPPLE2
(
+
6
∆
1
≈
’
≈
’
OUT2
IL2 RMS
=
+
=
∆
÷
÷
◊
(
)
N
12
«
«
◊
(7)
vertical spacer
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IOUT1 IRIPPLE1
+
1.667 A
2
IL1 PEAK
=
= 6 A +
= 6.833 A
= 7.073 A
(
)
N
2
IOUT2 IRIPPLE2
+
2.145 A
IL2 PEAK
=
= 6 A +
(
)
N
2
2
(8)
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8.2.2.3 Output Capacitor
The two primary considerations for selecting the value of the output capacitor are how the regulator responds to
a large change in load current and the output voltage ripple. The third consideration is to ensure converter
stability, which is typically met from the first two considerations. The output capacitance needs to be selected
based on the most stringent of these criteria.
The desired response to a large change in the load current is the first criteria and is typically the most stringent.
A regulator does not respond immediately to a large, fast increase or decrease in load current. The output
capacitor supplies or absorbs charge until the regulator responds to the load step. The control loop needs to
sense the change in the output voltage then adjust the peak switch current in response to the change in load.
The minimum output capacitance is selected based on an estimate of the loop bandwidth. Typically, the loop
bandwidth is near fSW/10. 方程式 9 estimates the minimum output capacitance necessary, where ISTEP is the
change in output current and VTRANS is the allowable change in the output voltage.
For this example, the transient load response is specified as a 5% change in VOUT1 for a load step of 3 A.
Therefore, ISTEP1 is 3 A and VTRANS1 is 50 mV. Using this target gives a minimum output capacitance of 95.5
μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For
ceramic capacitors, the effect of the ESR can be small enough to be ignored. Aluminum electrolytic and tantalum
capacitors have higher ESR that must be considered for load step response. Similarly, ISTEP2 is 3 A and VTRANS2
is 165 mV, which gives a minimum output capacitance of 28.9 μF.
ISTEP1
1
3 A
1
COUT1_LOOP
>
ì
=
ì
= 95.5 µF
fsw
1000 kHz
VTRANS1
50 mV
2pì
2pì
10
10
1
ISTEP2
1
3 A
COUT2_LOOP
>
ì
=
ì
= 28.9 µF
fsw
10
1000 kHz
10
VTRANS2
165 mV
2pì
2pì
(9)
In addition to the loop bandwidth, it is possible for the inductor current slew rate to limit how quickly the regulator
responds to the load step. For low duty cycle applications, the time it takes for the inductor current to ramp down
after a load step down can be the limiting factor. 方程式 10 estimates the minimum output capacitance
necessary to limit the output voltage undershoot after a load step up. 方程式 11 estimates the minimum output
capacitance necessary to limit the change in the output voltage overshoot after a load step down. Using the
selected 0.56-μH inductance gives a minimum capacitance of 4.6 μF for VOUT1 to meet the undershoot
requirement due to a load step-up. Using the selected 0.56-µH inductance gives a minimum capacitance of 50.4
µF for VOUT1 to meet the overshoot requirement due to a load step down. Using the selected 1.2-μH inductance
for VOUT2 gives a minimum output capacitance of 3.8 μF and 9.9 μF to meet the undershoot and overshoot
requirements, respectively.
2
2
0.56 µHì 3 A
Lo1ìISTEP
(
)
COUT1_UNDERSHOOT
>
>
= 4.6 µF
2ì VTRANS ì Vin - V
2ì50 mV ì 12 V - 1 V
(
)
(
)
OUT1
2
2
1.2 µHì 3 A
Lo2ìISTEP
(
)
COUT2_UNDERSHOOT
>
>
= 3.8 µF
2ì VTRANS ì Vin - V
2ì165 mV ì 12 V - 3.3 V
OUT2
(10)
2
2
0.56 µHì 3 A
Lo1ìISTEP
(
)
COUT1_OVERSHOOT
>
=
= 50.4 µF
)
= 9.9 µF
2ì VTRANS ì VOUT1
2ì50 mV ì1 V
2
2
1.2 µHì 3 A
Lo2ìISTEP
(
COUT2_OVERSHOOT
>
=
2ì VTRANS ì VOUT2 2ì165 mV ì3.3 V
(11)
方程式 12 calculates the minimum output capacitance needed to meet the output voltage ripple specification,
where fsw is the switching frequency, VRIPPLE1 is the maximum allowable steady-state output voltage ripple, and
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IRIPPLE1 is the inductor ripple current. In this case, the target maximum steady-state output voltage ripple is 10
mV for VOUT1. Under this requirement, 方程式 12 yields 20.8 µF. Similarly, VRIPPLE2 is the maximum allowable
VOUT2 steady-state output voltage ripple, and IRIPPLE2 is the inductor ripple current for VOUT2. For 33-mV steady-
state output voltage ripple, 方程式12 yields 8.13 µF for VOUT2
.
IRIPPLE1
8ì VRIPPLE1 ì fSW 8ì10 mV ì1000 kHz
IRIPPLE2
8ì VRIPPLE2 ì fSW 8ì33 mV ì1000 kHz
1.667 A
COUT1_RIPPLE
>
=
= 20.8 µF
= 8.13 µF
2.145 A
COUT2_RIPPLE
>
=
(12)
Lastly, if an application does not have a stringent load transient response or output ripple requirement, a
minimum amount of capacitance is still required to ensure the control loop is stable with the lowest gain ramp
setting on the MODE pin. 方程式13 estimates the minimum capacitance needed for loop stability. 方程式13 sets
the minimum amount of capacitance by keeping the LC frequency at a maximum of 1/30th the switching
frequency. 方程式13 gives a minimum capacitance of 40.7 µF and 19 µF for VOUT1 and VOUT2, respectively.
2
2
15
1
15
1
≈
’
≈
’
COUT1_STABILITY
>
ì
=
ì
= 40.7 µF
= 19 µF
∆
«
÷
◊
∆
«
÷
◊
pì fsw
Lo1
pì1000 kHz
0.56 µH
2
2
15
1
15
1
≈
’
≈
’
COUT2_STABILITY
>
ì
=
ì
∆
÷
∆
÷
◊
pì fsw
Lo2
pì1000 kHz
«
1.2 µH
«
◊
(13)
方程式 14 calculates the maximum combined ESR the output capacitors can have to meet the output voltage
ripple specification and shows that the ESR must be less than 6 mΩfor VOUT1. This application uses all ceramic
capacitors so the effects of ESR on the ripple and transient were ignored. If the user is using non-ceramic
capacitors as a starting point, the ESR must be below the values calculated in 方程式 14 and 方程式 15 to meet
both the ripple and transient response requirements. For more accurate calculations or if you are using mixed
output capacitors, the impedance of the output capacitors must be used to determine if the ripple and transient
requirements can be met. Similary, 方程式 14 calculates the maximum combined ESR the output capacitors can
have to meet the output voltage ripple specification. This shows the ESR must be less than 15.4 mΩ for VOUT2
.
In this case, ceramic capacitors are used and the combined ESR of the ceramic capacitors in parallel is much
less than is needed to meet the ripple.
VRIPPLE1
10 mV
RESR1_RIPPLE
<
=
= 6.00 mW
= 15.4 mW
IRIPPLE1 1.667 A
VRIPPLE2
33 mV
RESR2_RIPPLE
<
=
IRIPPLE2
2.145 A
(14)
vertical spacer
RESR1_ TRANS
RESR2_ TRANS
VTRANS
50 mV
3 A
<
=
= 16.7 mW
ISTEP
VTRANS
ISTEP
165 mV
3 A
<
=
= 55 mW
(15)
Capacitors also have limits to the amount of ripple current they can handle without producing excess heat and
failing. An output capacitor that can support the inductor ripple current must be specified. The capacitor data
sheet specifies the RMS value of the maximum ripple current. 方程式16 can be used to calculate the RMS ripple
current the output capacitor needs to support.
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Ico1rms =
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Vinmax- Vout1
15 V -1 V
(
)
(
)
Vout1
1 V
≈
’
≈
’
=
= 0.481 A
∆
«
÷
◊
∆
«
÷
Vinmaxì fsw
15 V ì1000 kHz
12 ìLo1
Vinmax- Vout2
12 ìLo2
12 ì0.56 mH
◊
15 V - 3.3 V
(
)
(
)
Vout2
3.3 V
≈
’
≈
’
Ico2rms =
=
= 0.619 A
÷
∆
÷
∆
Vinmaxì fsw
15 V ì1000 kHz
◊
12 ì1.2 mH
«
◊
«
(16)
For this application, 方程式 16 yields 0.481 A and 0.619 A, for VOUT1 and VOUT2, respectively. Ceramic
capacitors typically have a ripple current rating much higher than this. Select X5R and X7R ceramic dielectrics or
equivalent for power regulator capacitors since they have a high capacitance-to-volume ratio and are fairly stable
over temperature. The output capacitor must also be selected with the DC bias and AC voltage derating taken
into account. The derated capacitance value of a ceramic capacitor due to DC voltage bias and AC RMS voltage
is usually found on the capacitor manufacturer's website. For a VOUT1 application example, three 100-μF, 6.3-V,
X7S, 0805 ceramic capacitors, each with 2 mΩ of ESR, are used. With the three parallel capacitors, the
estimated effective output capacitance after derating using the capacitor manufacturer’s website is 240 μF.
This is well above the calculated minimum capacitance so this design is expected to meet the transient response
requirement with added margin. 图 8-13 shows the transient response and the output voltage stays within ±4%,
below the ±5% target of ±50 mV for VOUT1. For the VOUT2 application example, two 100-μF, 6.3-V, X7S, 0805
ceramic capacitorsm each with 2 mΩof ESRm are used. With the two parallel capacitors the estimated effective
output capacitance after derating using the capacitor manufacturer’s website is 80 μF. 图 8-14 shows the
transient response and the output voltage stays within ±3%, below the ±5% target of ±165 mV for VOUT2
.
8.2.2.4 Input Capacitor
It is required to have input decoupling ceramic capacitors type X5R, X7R, or similar from both the PVIN1 and
PVIN2 pins to PGND to bypass the power-stage and be placed as close as possible. A total of at least 10 µF of
capacitance is required. Some applications can require a bulk capacitance. At least 1 µF of bypass capacitance
is recommended near both VIN pins to minimize the input voltage ripple. A 0.1-µF to 1-µF capacitor must be
placed by both PVIN1 and PVIN2 pins 8 and 12 to provide high frequency bypass to reduce the high frequency
overshoot and undershoot on the following pins:
• PVIN1
• SW1
• PVIN2
• SW2
The voltage rating of the input capacitor must be greater than the maximum input voltage. In addition to this,
more bulk capacitance can be needed on the input depending on the application to minimize variations on the
input voltage during transient conditions. The input capacitance required to meet a specific input ripple target
can be calculated with 方程式 17. A recommended target input voltage ripple is 5% the minimum input voltage,
which is 350 mV in this example. The calculated input capacitance is 2.1 µF and 4.3 µF. Use the larger of the
two values and distribute evenly between PVIN1 and PVIN2. Since the values are less than 10 μF, 2 × 10 μF
are used. This example meets these two requirements with 4 × 10-µF ceramic capacitors and 2 × 100-µF bulk
capacitance. The capacitor must also have a ripple current rating greater than the maximum RMS input current.
The RMS input current can be calculated using 方程式18 and 方程式19.
For this example design, a ceramic capacitor with at least a 16-V voltage rating is required to support the
maximum input voltage. Two 10-µF, 0805, X7S, 25-V and two 0.1-μF, 0402, X7R 50-V capacitors in parallel
have been selected to be placed on both sides of the IC near both PVIN pins to PGND pins. Based on the
capacitor manufacturer's website, the total ceramic input capacitance derates to 5.4 µF at the nominal input
voltage of 12 V. A 100-µF bulk capacitance is also used to bypass long leads when connected a lab bench top
power supply.
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using 方程式 37. The maximum input ripple occurs when operating nearest to 50% duty cycle. Using
the nominal design example values of IOUT1 = 6 A, fSW = 1000 kHz, VOUT1 the input voltage ripple with the 12-V
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nominal input is 350 mV, and the RMS input ripple current with the 7-V minimum input is 2.106 A. Similarly, for
VOUT2, the input RMS current is 3.01 A.
For applications requiring bulk capacitance on the input, such as ones with low input voltage and high current,
the selection process in the How To Select Input Capacitors For A Buck Converter technical brief is
recommended.
≈
’
VOUT1
1 V
7 V
≈
«
’
◊
VOUT1 ìIOUT1 ì 1-
∆
÷
÷
1 V ì 6 A ì 1-
∆
∆
÷
V
min
(
)
IN
«
◊
CIN1
>
=
= 2.1 ꢀF
= 4.3 ꢀF
Nì fSW ì V min ì V
1ì1000 kHzì7 V ì350 mV
(
)
IN
IN_RIPPLE
≈
’
VOUT2
3.3 V
≈
«
’
◊
VOUT2 ìIOUT2 ì 1-
∆
÷
÷
3.3 V ì 6 A ì 1-
∆
∆
÷
V
min
(
)
7 V
IN
«
◊
CIN2
>
=
Nì fSW ì V min ì V
1ì1000 kHzì7 V ì350 mV
IN
IN_RIPPLE
(17)
vertical spacer
2
≈
∆
∆
∆
’
Iripple1
≈
’
÷
÷
÷
2
∆
«
÷
◊
V
min - V
OUT1
(
)
(
)
ì
VOUT1
I
OUT1
≈
’
N
IN
ICIN1 RMS
=
ì
+
=
∆
«
÷
◊
(
)
)
V
min
V
min
N
12
(
)
(
)
IN
IN
∆
∆
«
÷
÷
◊
2
≈
∆
∆
∆
’
1.531
1
≈
«
’
÷
÷
÷
2
∆
÷
◊
7 V -1 V
(
)
1 V
7 V
6 A
1
≈
’
ICIN1 RMS
=
ì
ì
+
= 2.11 A
∆
÷
◊
(
7 V
12
«
∆
∆
«
÷
÷
◊
(18)
2
≈
∆
’
÷
÷
÷
Iripple2
≈
’
2
∆
«
÷
◊
V
min - V
OUT2
(
)
(
IN
∆
)
VOUT2
I
OUT2
≈
’
N
ICIN2 RMS
=
ì
ì
+
+
=
∆
«
÷
◊
(
)
)
∆
V
min
V
min
N
12
(
)
(
)
IN
IN
∆
∆
«
÷
÷
◊
2
≈
’
÷
÷
÷
1.454
1
≈
’
∆
∆
∆
2
∆
«
÷
7 V - 3.3 V
(
)
3.3 V
7 V
6 A
1
≈
’
◊
ICIN2 RMS
=
ì
ì
= 3.01 A
∆
«
÷
◊
(
7 V
12
∆
∆
«
÷
÷
◊
(19)
8.2.2.5 Output Voltage Resistors Selection
The output voltage is set with a resistor divider created by RFB_T1 and RFB_B1 from the output node to the FB1
pin. It is recommended to use 1% tolerance or better resistors. For this example design, 10.0 kΩ is selected for
RFB_B1. Using 方程式 20, RFB_T1 is calculated as 10.0 kΩ for VOUT1 = 1 V. For this example design, 10.0 kΩ is
selected for RFB_B2. Using 方程式20, RFB_T2 is calculated as 56.0 kΩfor VOUT2 = 3.3 V.
≈
∆
«
’
÷
◊
VOUT1 - VFB
VFB
1 V - 0.5 V
0.5 V
≈
’
Rfb_ t1 = Rfb_b1
ì
= 10 kW ì
= 10 kW
∆
«
÷
◊
≈
’
÷
◊
VOUT2 - VFB
VFB
3.3 V - 0.5 V
0.5 V
≈
’
Rfb_ t2 = Rfb_b2
ì
= 10 kW ì
= 56 kW
∆
∆
«
÷
◊
«
(20)
where
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• VFB = 0.5 V
8.2.2.6 Adjustable Undervoltage Lockout
The undervoltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and RENB. The
UVLO has a threshold for power up when the input voltage is rising. UVLO has another threshold for power
down or brownouts when the input voltage is falling. For this example design, the supply is set to turn on and
start switching once the input voltage increases above 6 V (UVLO start or enable). After the regulator starts
switching, it continues to do so until the input voltage falls below 5.5 V (UVLO stop or disable). In this example,
these start and stop voltages set by the EN resistor divider are selected to have more hysteresis than the
internally fixed VIN UVLO. 方程式 21 can be used to calculate the values for the upper resistor. For these
equations to work, VSTART must be 1.1 × VSTOP due to the voltage hysteresis of the EN pin. To set the start
voltage, first select the bottom resistor (REN_B). The recommended value is between 1 kΩ and 100 kΩ. This
example uses a 10-kΩresistor.
For the voltages specified, the standard resistor value used for RENT is 39.2 kΩ and for RENB is 10 kΩ.
REN_B ì VSTART
10 kWì6 V
1.2 V
REN_T
=
-REN_B
=
-10 kW = 39.9 kW
VENH
(21)
8.2.2.7 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the BOOT1 and SW1 and BOOT2 and SW2 pins for
proper operation. The capacitor must be rated for 10 V or greater to minimize DC bias derating.
8.2.2.8 BP5 Capacitor Selection
A minimum of 2.2-µF (4.7 µF preferred) ceramic capacitor must be connected between the BP5 pin and PGND
for proper operation. The capacitor must be rated for at least 10 V to minimize DC bias derating.
8.2.2.9 PGOOD Pullup Resistor
A 1-kΩto 100-kΩresistor can be used to pull up the power good signal when FB conditions are met. The pullup
voltage source must be less than the 6-V absolute maximum of the PGOOD pin.
8.2.2.10 Current Limit
The current limit is fixed.
8.2.2.11 Soft-Start Time Selection
When using the TPS541620 in the dual-output configuration, the soft-start time is internally fixed at 1 ms as
described in 节7.3.8.
8.2.2.12 MODE1 and MODE2 Pins
To configure the TPS541620 for dual-output mode and a 1.5-pF ramp capacitor on VOUT2, the MODE1 resistor
is chosen to be 15.4 kΩ as described in 表 7-3. To set the switching frequency to 1 MHz and a 1.5-pF ramp
capacitor for VOUT1, the MODE2 resistor is chosen to be 17.4 kΩas described in 表7-1.
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8.2.3 Application Curves
90
85
80
75
70
65
100
95
90
85
80
75
70
65
60
VIN = 12 V
60
55
50
VIN = 12 V
VOUT2 = 3.3 V
fsw = 1000 kHz
Lo2 = 1.2 uH
VOUT1 = 1 V
fsw = 1000 kHz
Lo1 = 560 nH
0
0.5
1
1.5
2
2.5
Output Current (A)
3
3.5
4
4.5
5
5.5
6
0
0.5
1
1.5
2
2.5
Output Current (A)
3
3.5
4
4.5
5
5.5
6
图8-3. VOUT1 Efficiency
图8-4. VOUT2 Efficiency
1.005
1.00375
1.0025
1.00125
1
3.35
3.3475
3.345
3.3425
3.34
3.3375
3.335
3.3325
3.33
3.3275
3.325
3.3225
3.32
3.3175
3.315
3.3125
3.31
0.99875
0.9975
0.99625
0.995
VIN = 12 V
VIN = 12 V
Lo1 = 560 nH
Lo2 = 1200 nH
fsw = 1000 kHz
Iout2 = 6 A
Lo1 = 560 nH
Lo2 = 1200 nH
fsw = 1000 kHz
Iout1 = 6 A
0
0.5
1
1.5
2
2.5
3
3.5
4
Iout1 - Output Current (A)
4.5
5
5.5
6
0
0.5
1
1.5
2
2.5
3
3.5
4
Iout2 - Output Current (A)
4.5
5
5.5
6
图8-5. VOUT1 Load Regulation
图8-6. VOUT2 Load Regulation
1.005
1.00375
1.0025
1.00125
1
3.35
3.3475
3.345
3.3425
3.34
3.3375
3.335
3.3325
3.33
VIN = 12 V
3.3275
3.325
3.3225
3.32
3.3175
3.315
3.3125
3.31
Lo1 = 560 nH
Lo2 = 1200 nH
fsw = 1000 kHz
Iout1 = 6 A
0.99875
0.9975
0.99625
0.995
VIN = 12 V
Lo1 = 560 nH
Lo2 = 1200 nH
fsw = 1000 kHz
Iout2 = 6 A
0
0.5
1
1.5
2
2.5
3
3.5
4
Iout2 - Output Current (A)
4.5
5
5.5
6
0
0.5
1
1.5
2
2.5
3
3.5
4
Iout1 - Output Current (A)
4.5
5
5.5
6
图8-7. VOUT1 Cross Regulation
图8-8. VOUT2 Cross Regulation
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1.005
3.34
3.339
3.338
3.337
3.336
3.335
3.334
3.333
3.332
3.331
3.33
Iout1 = 6 A
Iout2 = 6 A
1.004
1.003
1.002
1.001
560 nH
1000 kHz
1200 nH
1000 kHz
1
5
6
7
8
9
Input Voltaget (V)
10
11
12
13
14
15
5
6
7
8
9
Input Voltaget (V)
10
11
12
13
14
15
图8-9. Line Regulation VOUT1
图8-10. Line Regulation VOUT2
80
70
60
50
40
30
20
10
0
400
350
300
250
200
150
100
50
80
70
60
50
40
30
20
10
0
280
240
200
160
120
80
Gain
Phase
Gain
Phase
40
0
0
-40
-80
-120
-160
-200
-10
-20
-50
-10
-20
-30
-40
VIN = 12 V, Vout2 = 3.3 V,
Iout2 = 6 A, 1.2uH, 2x100uF, 1000 kHz
-100
-150
-200
VIN = 12 V, Vout1 = 1.0 V,
Iout1 = 6 A, 560nH, 3x100uF, 1000 kHz
-30
-40
1000 2000 5000 10000
100000
1000000
1000 2000 5000 10000
100000
1000000
Frequency (Hz)
Frequency (Hz)
图8-11. VOUT1 Bode Plot
图8-12. VOUT2 Bode Plot
图8-14. VOUT2 Load Transient
图8-13. VOUT1 Load Transient
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图8-15. Power Up with EN 1
图8-16. Power Up with EN 2
图8-18. Power Down with EN 2
图8-17. Power Down with EN 1
图8-19. Power Up with EN 1 with Pre Bias
图8-20. Power Up with EN 2 with Pre Bias
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图8-22. Power Down with EN 2 with Pre Bias
图8-21. Power Down with EN 1 with Pre Bias
图8-23. Power Up with VIN VOUT1
图8-24. Power Down with VIN VOUT1
图8-25. Power Up with VIN VOUT2
图8-26. Power Down with VIN VOUT2
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图8-28. VOUT1 Output Ripple –6-A Load
图8-27. Sync In to SW1 and SW2 Delay
图8-30. Input Ripple PVIN1 –6-A Load
图8-29. VOUT2 Output Ripple –6-A Load
图8-31. Input Ripple PVIN2 –6-A Load
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8.2.4 Typical Application - 2-Phase Operation
PVIN
TPS541620RPBR
VOUT1
U1
L1
560nH
CBOOT1
CIN
47uF
CIN
22uF
CIN
100nF
CIN
0.1uF
BOOT1
SW1
1
2
6
24
5
PVIN
BOOT1
SW1
PVIN
BP5
0.1uF
J7
4
Cout
100uF
Cout
100uF
1
2
J1
BP5
Cout
Cout
100uF
Cout
100uF
Cout
100uF
PGOOD1
FB1
16
22
13
1
PGOOD1
FB1
BP5
100uF
Rpg1
100k
PGND
CBP5
2.2µF
CBP5
CIN
47uF
CIN
22uF
CIN
100nF
CIN
0.1uF
18
20
CBOOT2
EN2/ISHARE
EN1
0.1uF
BOOT2
SW2
BOOT2
L2
EN1
Cff
0.1uF
2
SW2
560nH
PGND
open
PGND
21
17
14
PGOOD2/CLKO
FB2/ISHARE
PGOOD2/CLKO
FB2/VSHARE
GOSNS
PVIN
SYNC
MODE1
MODE2
8
9
SYNC
MODE1
MODE2
SS
Rfbb
Rfbt
Rinj
49.9
10.0k
10.0k
Rent
open
EN1
10
AGND
3
PGND
PGND
PGND
PGND
RM1M2
10.0k
10.7k
SS 12
7
Rmode1
Rmode2
17.4k
23
25
Renb
11
PGND
NC
NC
open
Css
0.01µF
19
15
AGND
TPS541620RPBR
NT2
AGND
AGND
PGND
AGND
Net-Tie
NT1
Net-Tie
PGND
AGND
图8-32. 12-V Input, 1.0-V Output 2-Phase Converter Application Schematic
8.2.4.1 Design Requirements
For this design example, use the parameters shown in 表8-2.
表8-2. Design Parameters
PARAMETER
EXAMPLE VALUE
7 to 15 V, 12 V nominal
1.0 V
Input voltage range (VIN)
Output voltage (VOUT
Output current rating (IOUT
Switching frequency (fSW
)
)
12 A
)
1000 kHz/phase
10 mV
Steady state output ripple voltage
Output current load step
Transient response
6 A
± 50 mV (± 5%)
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8.2.4.2 Detailed Design Procedure
8.2.4.2.1 Switching Frequency
The first step is to decide on a switching frequency. The TPS541620 can operate at four different frequencies
from 500 kHz to 2.0 MHz. fSW is set by the resistor value from the MODE2 pin to ground. Typically the highest
switching frequency possible is desired because it produces the smallest solution size, or a lower switching
frequency is selected for a more efficient converter. The minimum controllable on-time and maximum off-time
affect the input voltage range and switching frequency.
The maximum switching frequency for a given application can be limited by the minimum on-time of the regulator
and the maximum fSW can be estimated with 方程式22. Using the maximum minimum on-time of 50 ns and 15-V
maximum input voltage for this application, the maximum switching frequency is 1333 kHz. The minimum
regulating input voltage is limited by the maximum off-time, switching frequency, and output voltage. Using the
maximum 150-ns off-time, 7-V minimum input voltage, 1.0-V output voltage for this application, and 方程式 23,
the maximum switching frequency from 1.0 V and maximum off-time is 5714 kHz.
The selected switching frequency must also consider the tolerance of the switching frequency. A switching
frequency of 1000 kHz is selected for a good balance of solution size and efficiency. To set the frequency to
1000 kHz, the selected MODE2 resistor is 17.4 kΩper 表7-1.
Voutmin
1 V
fsw =
=
= 1333 kHz
tonì Vinmax 50 nsì15 V
(22)
Voutmax
1.0 V
7 V
1-
1-
Vinmin
toff
fsw =
=
= 5714 kHz
150 ns
(23)
图 8-33 shows the maximum recommended input voltage versus output voltage for each FSEL frequency. 图
8-33 uses the maximum minimum on-time of 50 ns and includes 10% tolerance on the switching frequency.
17
16
15
14
13
12
11
10
9
8
500 kHz
1000 kHz
1500 kHz
2000 kHz
7
6
5
4
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5
Output Voltage (V)
图8-33. Maximum Input Voltage Versus Output Voltage
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8.2.4.2.2 Output Inductor Selection
To calculate the effective value of the output inductor, use 方程式 24. K is a ratio that represents the amount of
inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output
capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor
because the output capacitor must have a ripple current rating equal to or greater than the inductor ripple
current. Choosing small inductor ripple currents (through a large inductor) can degrade the transient response
performance. The inductor ripple, K, is normally from 0.1 to 0.4 for the majority of applications giving a peak-to-
peak ripple current range of 0.6 A to 2.4 A. The target Iripple must be 0.3 A or larger.
For this design example, KIND = 0.3 is used and the inductor value Lo_eff is calculated to be 0.255 µH. The per
phase value is calculated to 0.51 μH. An inductor with an inductance of 0.56 µH is selected. The inductor ripple
current is calculated as 1.674 A using 方程式 25. It is important that the RMS (Root Mean Square) current and
saturation current ratings of the inductor not be exceeded. The RMS and peak inductor current can be found
from 方程式 26 and 方程式 27, respectively. For this design, the RMS inductor current is 6.019 A and the peak
inductor current is 6.837 A. The chosen inductor is a Coilcraft XAL6030-561, which has a saturation current
rating of 29 A, an RMS current rating of 17 A, and a typical DC series resistance of 3.01 mΩ.
The peak current through the inductor is the inductor ripple current plus the DC output current. During power up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated in 方程式 27. In transient conditions, the inductor current can increase up to the switch current
limit of the device. For this reason, the most conservative approach is to specify the current ratings of the
inductor based on the switch current limit rather than the steady-state peak inductor current.
Vin - Vout
K ìIout
12 V -1 V
(
)
(
)
Vout
1 V
≈
’
≈
∆
’
Lo_eff =
=
= 0.255 mH
∆
÷
÷
◊
Vinì fsw
0.3ì12 A 12 V ì1000 kHz
«
◊
«
Lo = NìLo_eff = 0.255 mH ì2 = 0.509 mH
(
)
whereN = 1,2or4
(24)
(25)
vertical spacer
Vinmax- Vout
Lo_eff ìN
15 V -1 V
(
)
(
)
Vout
1 V
≈
’
≈
∆
’
Iripple =
=
= 1.667 A
∆
«
÷
◊
÷
Vinmaxì fsw
0.280 mHì2 15 V ì1000 kHz
«
◊
vertical spacer
2
2
2
2
1.667 A
I
IRIPPLE
(
)
12 A
2
≈
’
≈
’
OUT
IL RMS
=
+
=
+
÷
= 6.019 A
∆
«
÷
◊
∆
«
(
)
N
12
12
◊
(26)
(27)
vertical spacer
IOUT IRIPPLE
12 A 1.667 A
+
IL PEAK
=
+
=
= 6.833 A
(
)
N
2
2
2
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8.2.4.2.3 Output Capacitor
The two primary considerations for selecting the value of the output capacitor are how the regulator responds to
a large change in load current and the output voltage ripple. The third consideration is to ensure converter
stability, which is typically met from the first two considerations. The output capacitance needs to be selected
based on the more stringent of these criteria.
The desired response to a large change in the load current is the first criteria and is typically the most stringent.
A regulator does not respond immediately to a large, fast increase or decrease in load current. The output
capacitor supplies or absorbs charge until the regulator responds to the load step. The control loop needs to
sense the change in the output voltage, then adjust the peak switch current in response to the change in load.
The minimum output capacitance is selected based on an estimate of the loop bandwidth. Typically, the loop
bandwidth is near fSW/10. 方程式 28 estimates the minimum output capacitance necessary, where ISTEP is the
change in output current and VTRANS is the allowable change in the output voltage.
For this example, the transient load response is specified as a 5% change in VOUT for a load step of 6 A.
Therefore, ITRANS is 6 A and VTRANS is 50 mV. Using this target gives a minimum capacitance of 191 μF. This
value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic
capacitors, the effect of the ESR can be small enough to be ignored. Aluminum electrolytic and tantalum
capacitors have higher ESR that must be considered for load step response.
ISTEP
1
6 A
1
COUT _LOOP
>
ì
=
ì
= 191 µF
fsw
1000 kHz
10
VTRANS
50 mV
2pì
2pì
10
(28)
In addition to the loop bandwidth, it is possible for the inductor current slew rate to limit how quickly the regulator
responds to the load step. For low duty cycle applications, the time it takes for the inductor current to ramp down
after a load step down can be the limiting factor. 方程式 29 estimates the minimum output capacitance
necessary to limit the undershoot of the output voltage after a load step-up. Using the 0.56-µH inductance
selected gives a minimum capacitance of 9.2 µF to meet to undershoot requirement. 方程式 30 estimates the
minimum output capacitance necessary to limit the overshoot of the output voltage after a load step down. Using
the 0.56-μH inductance selected gives a minimum capacitance of 100.8 μF to meet the overshoot requirement.
2
Lo_eff ìISTEP
COUT _UNDERSHOOT
>
>
2ì VTRANS ì VIN - VOUT
(
)
0.56 µH
2
2
ì 6 A
(
)
COUT _UNDERSHOOT
= 9.2 µF
2ì50 mV ì 12 V -1 V
(29)
(30)
0.56 µH
2
2ì50 mV ì1V
2
ì 6 A
2
(
)
Lo_eff ìISTEP
COUT _OVERSHOOT
>
=
= 100.8 µF
2ì VTRANS ì VOUT
方程式 31 calculates the minimum output capacitance needed to meet the output voltage ripple specification,
where fsw is the switching frequency, VRIPPLE is the maximum allowable steady-state output voltage ripple, N is
the number of phases, and IRIPPLE is the inductor ripple current calculated from 方程式25. In this case, the target
maximum steady-state output voltage ripple is 10 mV. Under this requirement, 方程式31 yields 10.4 µF.
IRIPPLE
8ì VRIPPLE ìNì fSW 8ì10 mV ì2ì1000 kHz
1.667 A
COUT _RIPPLE
>
=
= 10.4 µF
(31)
Lastly, if an application does not have a stringent load transient response or output ripple requirement, a
minimum amount of capacitance is still required to ensure the control loop is stable with the lowest gain ramp
setting on the MODE pin. 方程式 32 estimates the minimum capacitance needed for loop stability. This equation
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sets the minimum amount of capacitance by keeping the LC frequency at a maximum of 1/30th the switching
frequency. 方程式32 gives a minimum capacitance of 81.4 µF.
2
2
15
1
Lo
15
1
≈
’
≈
’
COUT _STABILITY
>
ì
=
ì
= 81.4 µF
∆
«
÷
◊
∆
«
÷
◊
0.56
pì fsw
pì1000 kHz
µH
(32)
方程式 33 calculates the maximum combined ESR the output capacitors can have to meet the output voltage
ripple specification, showing the ESR should be less than 6 mΩ. This application uses all ceramic capacitors, so
the effects of ESR on the ripple and transient were ignored. If you are using non-ceramic capacitors, as a
starting point, the ESR should be below the values calculated in 方程式 33 and 方程式 34, respectively, to meet
the ripple and transient requirements. For more accurate calculations or if using mixed output capacitors, the
impedance of the output capacitors must be used to determine if the ripple and transient requirements can be
met.
VRIPPLE
10 mV
RESR _RIPPLE
<
=
= 6.00 mW
IRIPPLE
1.667 A
(33)
(34)
vertical spacer
VTRANS
50 mV
RESR _ TRANS
<
=
= 8.3 mW
ISTEP
6 A
vertical spacer
Vinmax- Vout
12 ìLo
15 V -1 V
(
)
(
)
Vout
1 V
≈
’
≈
’
Icorms =
=
= 0.481 A
∆
«
÷
◊
∆
«
÷
◊
Vinmaxì fsw
15 V ì1000 kHz
12 ì0.56 mH
(35)
In this case, ceramic capacitors are used and the combined ESR of the ceramic capacitors in parallel is much
less than is needed to meet the ripple. Capacitors also have limits to the amount of ripple current they can
handle without producing excess heat and failing. An output capacitor that can support the inductor ripple current
must be specified. The capacitor data sheet specifies the RMS value of the maximum ripple current. 方程式 35
can be used to calculate the RMS ripple current the output capacitor needs to support. For this application, 方程
式 35 yields 0.481 A, and ceramic capacitors typically have a ripple current rating much higher than this. Select
X5R and X7R ceramic dielectrics or equivalent for power regulator capacitors because they have a high
capacitance-to-volume ratio and are fairly stable over temperature. The output capacitor must also be selected
with the DC bias and AC voltage derating taken into account. The derated capacitance value of a ceramic
capacitor due to DC voltage bias and AC RMS voltage is usually found on the capacitor manufacturer's website.
For this application example, six 100-μF, 6.3-V, X7S, 0805 ceramic capacitors, each with 2 mΩ of ESR, are
used. With the six parallel capacitors, the estimated effective output capacitance after derating using the
capacitor manufacturer’s website is 240 μF. This is well above the calculated minimum capacitance, so this
design is expected to meet the transient response requirement with added margin. 图 8-38 shows the transient
response. The output voltage stays within ±3%, below the ±5% target.
8.2.4.2.4 Input Capacitor
It is required to have input decoupling ceramic capacitors type X5R, X7R, or similar from both the PVIN1 and
PVIN2 pins to PGND to bypass the power-stage and placed as close as possible to the IC. A total of at least 10
µF of capacitance is required and some applications can require a bulk capacitance. At least 1 µF of bypass
capacitance is recommended near both VIN pins to minimize the input voltage ripple. A 0.1-µF to 1-µF capacitor
must be placed by both PVIN1 and PVIN2 pins 8 and 12 to provide high frequency bypass to reduce the high
frequency overshoot and undershoot on the following pins:
• PVIN1
• SW1
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• PVIN2
• SW2
The voltage rating of the input capacitor must be greater than the maximum input voltage. In addition to this,
more bulk capacitance can be needed on the input depending on the application to minimize variations on the
input voltage during transient conditions. A recommended target input voltage ripple is 5% of the minimum input
voltage, which is 350 mV in this example. The calculated input capacitance is 2.1 µF. Use the larger of the two
values and distribute evenly between PVIN1 and PVIN2. Since the values are less than 10 μF, 2 × 10 μF are
used. This example meets these two requirements with 4 × 10-µF ceramic capacitors and 2 × 100-µF bulk
capacitance. The capacitor must also have a ripple current rating greater than the maximum RMS input current.
The RMS input current can be calculated using 方程式36.
For this example design, a ceramic capacitor with at least a 16-V voltage rating is required to support the
maximum input voltage. Two 10-µF, 0805, X7S, 25-V and two 0.1-μF, 0402, X7R 50-V capacitors in parallel
have been selected to be placed on both sides of the IC near both PVIN pins to PGND pins. Based on the
capacitor manufacturer's website, the total ceramic input capacitance derates to 5.4 µF at the nominal input
voltage of 12 V. 100-µF bulk capacitance is also used to bypass long leads when connected a lab bench top
power supply.
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using 方程式 37. The maximum input ripple occurs when operating closest to 50% duty cycle. Using
the nominal design example values of Ioutmax = 12 A, fSW = 1000 kHz, and VOUT = 1 V, the input voltage ripple
with the 12-V nominal input is 350 mV and the RMS input ripple current with the 7-V minimum input is 2.106 A.
For applications requiring bulk capacitance on the input, such as ones with low input voltage and high current,
the selection process in the How To Select Input Capacitors For A Buck Converter technical brief is
recommended.
≈
’
VOUT
min
1 V
7 V
≈
«
’
◊
VOUT ìIOUT ì 1-
∆
÷
÷
1 V ì12 A ì 1-
∆
∆
÷
V
(
)
IN
«
◊
CIN
>
=
= 2.1 ꢀF
Nì fSW ì V min ì V
2ì1000 kHzì7 V ì350 mV
IN
IN_RIPPLE
(36)
vertical spacer
2
2
≈
’
÷
V
min - V
OUT
(
)
min
Iripple
12
(
)
ì
VOUT
min
I
(
)
≈
’
IN
OUT
∆
ICIN RMS
=
=
ì
+
=
∆
«
÷
◊
(
)
)
V
∆
V
N
÷
(
)
(
)
IN
IN
«
◊
2
2
≈
∆
’
÷
7 V -1 V
1.687
(
)
(
)
1 V
7 V
12
2
≈
’
ICIN RMS
ì
ì
+
= 2.106 A
∆
÷
◊
(
∆
7 V
12
÷
«
«
◊
(37)
8.2.4.2.5 Output Voltage Resistors Selection
The output voltage is set with a resistor divider created by RFB_T and RFB_B from the output node to the FB pin. It
is recommended to use 1% tolerance or better resistors. For this example design, 10.0 kΩis selected for RFB_B
.
Using 方程式38, RFB_T is calculated as 10.0 kΩfor a 1-V output. This is a standard 1% resistor.
≈
∆
«
’
÷
◊
VOUT - VFB
VFB
1 V - 0.5 V
0.5 V
≈
’
Rfb_ t = Rfb_b
ì
= 10 kWì
= 10 kW
∆
«
÷
◊
(38)
where
• VFB = 0.5 V
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8.2.4.2.6 Adjustable Undervoltage Lockout
The undervoltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and RENB. The
UVLO has a threshold for power up when the input voltage is rising. UVLO has another threshold for power
down or brownouts when the input voltage is falling. For the example design, the supply is set to turn on and
start switching once the input voltage increases above 6 V (UVLO start or enable). After the regulator starts
switching, it continues to do so until the input voltage falls below 5.5 V (UVLO stop or disable). In this example,
these start and stop voltages set by the EN resistor divider are selected to have more hysteresis than the
internally fixed VIN UVLO. 方程式 39 can be used to calculate the value for the upper resistor. For these
equations to work, VSTART must be 1.1 × VSTOP due to the voltage hysteresis of the EN pin. To set the start
voltage, first select the bottom resistor (REN_B). The recommended value is between 1 kΩ and 100 kΩ. This
example uses a 10-kΩresistor.
For the voltages specified, the standard resistor value used for RENT is 39.2 kΩ and for RENB is 10 kΩ.
REN_B ì VSTART
10 kWì6 V
1.2 V
REN_T
=
-REN_B
=
-10 kW = 39.9 kW
VENH
(39)
8.2.4.2.7 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the BOOT1 and SW1 and BOOT2 and SW2 pins for
proper operation. The capacitor must be rated for 10 V or greater to minimize DC bias derating.
8.2.4.2.8 BP5 Capacitor Selection
A 2.2-µF (4.7 µF preferred) ceramic capacitor must be connected between the BP5 pin and PGND for proper
operation. The capacitor must be rated for at least 10-V to minimize DC bias derating.
8.2.4.2.9 PGOOD Pullup Resistor
A 1-kΩto 100-kΩresistor can be used to pull up the power good signal when FB conditions are met. The pullup
voltage source must be less than the 6-V absolute maximum of the PGOOD pin.
8.2.4.2.10 Current Limit
The current limit is fixed.
8.2.4.2.11 Soft-Start Time Selection
The SS pin is used to program different soft-start times in multi-phase mode. In dual-output mode, an internally
fixed soft start is used.
This is useful if a load has specific timing requirements for the output voltage of the regulator. A longer soft-start
time is also useful if the output capacitance is very large and would require large amounts of current to quickly
charge the output capacitors to the output voltage level. The large currents necessary to charge the capacitor
can reach the current limit or cause the input voltage rail to sag due excessive current draw from the input power
supply. Limiting the output voltage slew rate solves both of these problems. The example design has the soft-
start time set to 2.5 ms.
8.2.4.2.12 MODE1 Pin
The MODE1 resistor is set to 10.7 kΩto select multiphase mode as described by 表7-3.
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8.2.4.3 Application Curves
90
85
80
75
70
65
1.0032
1.0024
1.0016
1.0008
1
0.9992
0.9984
0.9976
0.9968
VIN = 12 V
VOUT = 1 V
fsw = 1000 kHz
Lo1,Lo2 = 560 nH
VIN = 12 V
VOUT = 1 V
fsw = 1000 kHz
Lo1,Lo2 = 560 nH
60
55
50
0
1
2
3
4
5
6
7
Output Current (A)
8
9
10 11 12
0
1
2
3
4
5
6
7
Output Current (A)
8
9
10 11 12
图8-35. Load Regulation
图8-34. Efficiency
80
70
60
50
40
30
20
10
0
280
1.005
1.004
1.003
1.002
1.001
1
Gain
Phase
240
200
160
120
80
40
0
0.999
0.998
0.997
0.996
0.995
-40
-80
-120
-160
-200
VIN = 12 V
VOUT = 1 V
fsw = 1000 kHz
Lo1,Lo2 = 560 nH
Co = 6 x 100uF
-10
-20
-30
-40
Iout = 12 A
fsw = 1000 kHz
Lo1,Lo2 = 560 nH
1000 2000 5000 10000
100000
Frequency (Hz)
1000000
5
6
7
8
9
10
11
Input Voltaget (V)
12
13
14
15
图8-37. Bode Plot
图8-36. Line Regulation
图8-39. Power Up with EN
图8-38. Load Transient
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图8-40. Power Down with EN
图8-41. Power Up with VIN
图8-43. Power Down with EN –Prebias
图8-42. Power Up with EN –Prebias
图8-44. Power Down with VIN
图8-45. Output Ripple –No Load
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图8-46. Output Ripple –12-A Load
图8-47. Input Ripple PVIN1 –12-A Load
图8-48. Input Ripple PVIN2 - 12-A Load
图8-49. Sync In to SW1, SW2 and CLKO Delay
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9 Power Supply Recommendations
The TPS541620 is designed to operate from an input voltage supply range between 4.5 V and 15 V. This supply
voltage must be well regulated. Proper bypassing of the input supply is critical for proper electrical performance,
as is the PCB layout and the grounding scheme. A minimum of one 22-μF (after derating) ceramic capacitor,
type X5R or better, must be placed between VIN and PGND on each side of the device.
10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. See 图 10-1 for a PCB layout example. Key guidelines
to follow for the layout are:
• VIN, PGND, and SW traces must be as wide as possible to reduce trace impedance and improve heat
dissipation.
• Place a 10-nF to 100-nF capacitor from each VIN to PGND pin and place them as close as possible to
the device (It is recommended the edge of input bypass capacitor pads to be no more than 8 mils
away from the VIN pin). Place the remaining ceramic input capacitance next to these high frequency bypass
capacitors.
• Use multiple vias near the PGND pins and use the layer directly below the device to connect them together.
This helps to minimize noise and can help heat dissipation.
• Use vias near both VIN pins and provide a low impedance connection between them through an internal
layer.
• Place the inductor as close as possible to the device to minimize the length of the SW node routing.
• Place the BOOT-SW capacitor as close as possible to the BOOT and SW pins. If a boot resistor is needed,
the value of the resistor should be no more than 10 Ω.
• Place the BP5 capacitor as close as possible to the BP5 and PGND pins.
• Place the bottom resistor in the FB divider as close as possible to the FB and AGND pins of the IC. Also keep
the upper feedback resistor and the feedforward capacitor, if used, near the IC. Connect the FB divider to the
output voltage at the desired point of regulation.
• Return the MODE1 and MODE2 resistors to a quiet AGND island.
• Use multiple vias in the AGND island to connect it back to internal PGND layers. Place the vias near the BP5
cap but away from the bottom FB resistor.
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10.2 Layout Example
图10-1. Example PCB Layout for Dual-output Configuration
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图10-2. Example PCB Layout for Dual-phase Configuration
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10.2.1 Thermal Performance
图10-3. Thermal Image at 25°C Ambient - 2-phase Operation, fsw = 1 MHz, VIN = 12 V, VOUT = 1 V, IOUT = 12
A, Inductor = 560 nH (3.3 mΩtypical)
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图10-4. Thermal Image at 25°C Ambient - Dual Output Operation, fsw = 1 MHz, VIN = 12 V, VOUT1 = 1 V,
IOUT1 = 6 A, L1 = 560 nH (3.3 mΩMax), VOUT2 = 3.3 V, IOUT2 = 6 A, L2 = 1.2 μH (7.5 mΩMax)
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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30-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS541620RPBR
ACTIVE
VQFN-HR
RPB
25
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
T541B1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Nov-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS541620RPBR
VQFN-
HR
RPB
25
3000
330.0
17.6
3.25
5.25
1.13
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Nov-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN-HR RPB 25
SPQ
Length (mm) Width (mm) Height (mm)
336.0 336.0 48.0
TPS541620RPBR
3000
Pack Materials-Page 2
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLAT-NO LEAD
RPB0025A
A
3.1
2.9
B
PIN 1 INDEX AREA
5.1
4.9
C
1 MAX
SEATING PLANE
0.05
0.00
0.08
C
2.5
1.100±0.1
2X 0.8±0.1
2X 0.375±0.05
PKG
15X 0.4±0.1
(0.1) TYP
2X 0.625±0.1
7
10
23X 0.25±0.05
6
5
11
12
0.1
C A B
2X 1.913
0.05
C
2X 1.3
2X 0.738
0.6±0.05
0.1
C A B
PKG
0.05
C
4
25
2.8±0.1
2X
47°
2X 0.375±0.05
1
0.1
C A B
18
0.05
C
18X 0.5
2X 0.8±0.1
24
19
0.3
0.2
4X (0.375) REF
4X (0.125) REF
2X 0.425±0.05
2X 0.573±0.1
2X 0.35±0.05
4224091/A 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLAT-NO LEAD
RPB0025A
(2.825)
2X (0.55)
2X (0.773)
(0.25)
19
24
2X (1)
18X (0.5)
47°
18
2X (0.425)
2X (0.375)
1
PKG
25
(2.8)
(0.6)
(4) (4.8)
2X (0.738)
2X (1.3)
5
6
12
11
2X (1.84)
2X (1.913)
23X (0.25)
2X (0.825)
10
7
PKG
(2.5)
15X (0.6)
2X (0.575)
2X (1)
(1.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.05 MAX
ALL AROUND
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAIL
4224091/A 04/2018
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) .
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLAT-NO LEAD
RPB0025A
(2.825)
2X (0.55)
0.68
2X (0.773)
(0.25)
19
24
2X (1)
18X (0.5)
18
47°
2X (0.4)
1
3X (0.8)
2X (0.375)
PKG
2X (0.6)
(4)
(4.8)
25
2X (1)
2X (0.738)
EXPOSED METAL
2X (1.3)
5
6
12
11
2X (1.84)
2X (1.9)
23X (0.25)
2X (0.825)
10
7
PKG
(2.5)
15X (0.6)
2X (0.575)
2X (0.55)
2X (1)
SOLDER PASTE EXAMPLE
BASED ON 0.100 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA
UNDER PACKAGE
PAD 3, 6, 24 & 25: 87%
SCALE: 15X
4224091/A 04/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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