TPS54262MPWPTEP [TI]
具有低 Iq、电压监控和复位功能且采用增强型塑料封装的 2A、60V 降压直流/直流转换器 | PWP | 20 | -55 to 125;
| 型号： | TPS54262MPWPTEP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有低 Iq、电压监控和复位功能且采用增强型塑料封装的 2A、60V 降压直流/直流转换器 | PWP | 20 | -55 to 125 监控 开关 光电二极管 输出元件 转换器 |
| 文件： | 总49页 (文件大小：2343K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS54262-EP
ZHCSFU3 –DECEMBER 2016
TPS54262-EP Iq 较低并配有电压监测器的
2A、60V 降压 DC-DC 转换器
1 特性
2 应用范围
1
•
•
•
异步开关模式稳压器
•
•
汽车远程信息处理和紧急呼叫
汽车信息娱乐系统和仪表板
适用于汽车电子 应用
3.6V 至 48V 运行范围，可耐受高达 60V 的瞬态电
压
–
–
–
音响主机
导航
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2A 最大负载电流
显示屏
50µA 静态电流（典型值）
200kHz 至 2.2MHz 开关频率
0.8V ± 1.5% 电压基准
3 说明
TPS54262-EP 器件是一款 60V、2A 降压开关模式电
源，支持低功耗模式并配有集成N 沟道金属氧化物半
导体 (NMOS) 开关 FET 的可编程电压监控器。集成输
入电压线路前馈拓扑结构改进了电压模式降压稳压器的
线路瞬态稳压性能。稳压器具有逐周期电流限值。此
外，该器件还 具备 在轻载条件下以低功耗模式运行的
特性，可将电源电流降至 50µA（典型值）。通过将
EN 引脚下拉为低电平，电源关断电流可降至 1µA（典
型值）。
耐高压的使能输入
启用周期上的软启动
内部电源开关上的转换率控制
低功耗模式，适用于轻载条件
可通过编程设定的上电复位延迟
误差放大器外部补偿
针对快速负瞬态变化的复位功能滤波时间
可编程过压、欠压输出监测计
热感应和关断
开漏复位信号指示标称输出降至通过外部电阻分压器网
络设置的复位阈值以下。输出电压启动斜坡由软启动电
容控制。内部欠压关断在输入电源电压斜降至 2.6V 时
激活。 该器件具有 短路保护电路，能够在过载条件下
为器件提供保护，此外还具备热关断保护功能。
开关电流限制保护
场效应晶体管 (FET) 的短路和过流保护
结温范围：-55°C 至 150°C
20 引脚散热薄型小外形尺寸 (HTSSOP)
PowerPAD™的 8 引脚小外形尺寸 (SO) 封装
器件信息(1)
•
支持国防、航天和医疗 应用：
器件型号
封装
封装尺寸（标称值）
–
–
–
–
–
–
–
可控基线
TPS54262-EP
HTSSOP (20)
6.50mm x 4.40mm
一个组装/测试场所
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
一个制造场所
在扩展温度范围（-55°C 至 125°C）内可用
延长的产品生命周期
延长产品的变更通知
产品可追溯性
简化电路原理图
转换器典型效率
D1
TPS54262
VReg
VIN
VIN
EN
VBATT
90
R12
C1
R11
R10
RESET
L
RST
VIN = 14 V
80
70
60
50
40
30
20
10
0
BOOT
C3
D2
VReg
C4
PH
LPM
C7
R9
SYNC
VIN = 7 V
R4
R5
R7
C6
Rslew
VSENSE
SS
C8
C5
VReg = 5 V
fsw = 500 kHz
L = 22 µH
R6
R8
C2
COMP
RT/CLK
R1
R2
R3
RST_TH
C = 100 µF
Rslew = 30 kW
TA = 25°C
Cdly
GND
OV_TH
0.05
0.5
1
ILoad - Load Current - A
1.5
2
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSDP3
TPS54262-EP
ZHCSFU3 –DECEMBER 2016
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 19
Application and Implementation ........................ 25
8.1 Application Information............................................ 25
8.2 Typical Application ................................................. 25
Power Supply Recommendations...................... 37
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 DC Electrical Characteristics .................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................. 10
10 Layout................................................................... 38
10.1 Layout Guidelines ................................................. 38
10.2 Layout Example .................................................... 38
10.3 Power Dissipation and Temperature
Considerations ......................................................... 39
11 器件和文档支持 ..................................................... 41
11.1 接收文档更新通知 ................................................. 41
11.2 社区资源................................................................ 41
11.3 商标....................................................................... 41
11.4 静电放电警告......................................................... 41
11.5 Glossary................................................................ 41
12 机械、封装和可订购信息....................................... 42
7
4 修订历史记录
日期
修订版本
注释
2016 年 12 月
*
最初发布。
2
Copyright © 2016, Texas Instruments Incorporated
TPS54262-EP
www.ti.com.cn
ZHCSFU3 –DECEMBER 2016
5 Pin Configuration and Functions
PWP Package
20-Pin HTSSOP
Top View
1
20
19
18
17
16
15
14
13
12
11
NC
NC
BOOT
VIN
VIN
2
3
SYNC
LPM
EN
4
PH
VReg
5
6
RT
Rslew
COMP
7
VSENSE
RST_TH
OV_TH
8
RST
Cdly
9
10
GND
SS
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NC
NO.
1
NC
NC
Connect to ground.
Connect to ground.
NC
2
External synchronization clock input to override the internal oscillator clock. An internal
pulldown resistor of 62 kΩ (typical) is connected to ground. Connect this pin to GND if not
used.
SYNC
3
I
Low-power mode control using digital input signal. An internal pulldown resistor of 62 kΩ
(typical) is connected to ground.
LPM
EN
4
5
I
I
Enable pin, internally pulled up. Must be externally pulled up or down to enable or disable
the device.
RT
6
7
O
O
External resistor to ground to program the internal oscillator frequency.
External resistor to ground to control the slew rate of internal switching FET.
Rslew
Active low, open-drain reset output connected to external bias voltage through a resistor,
asserted high after the device starts regulating.
RST
Cdly
GND
SS
8
O
O
O
O
I
9
External capacitor to ground to program power on reset delay.
Ground pin, must be electrically connected to the exposed pad on the PCB for proper
thermal performance.
10
11
12
External capacitor to ground to program soft-start time.
Sense input for overvoltage detection on regulated output, an external resistor network is
connected between VReg and ground to program the overvoltage threshold.
OV_TH
Sense input for undervoltage detection on regulated output, an external resistor network is
connected between VReg and ground to program the reset and undervoltage threshold.
RST_TH
13
I
VSENSE
COMP
VReg
PH
14
15
16
17
18
19
20
I
O
I
Inverting node of error amplifier for voltage mode control.
Error amplifier output to connect external compensation components.
Internal low-side FET to load output during start-up or limit overshoot.
Source of the internal switching FET.
O
I
VIN
Unregulated input voltage. Pin 18 and pin 19 must be connected externally.
Unregulated input voltage. Pin 18 and pin 19 must be connected externally.
External bootstrap capacitor to PH to drive the gate of the internal switching FET.
VIN
I
BOOT
O
Copyright © 2016, Texas Instruments Incorporated
3
TPS54262-EP
ZHCSFU3 –DECEMBER 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.85
–0.5
–2
MAX
UNIT
EN
60
60
VIN
VReg
20
LPM
5.5
5.5
5.5
5.5
5.5
65
Input voltage
OV_TH
V
RST_TH
SYNC
VSENSE
BOOT
DC voltage
60
DC voltage, TJ = –55°C
DC voltage, TJ = 125°C
30-ns transient pulse
200-ns transient pulse
PH
Output voltage
–1
V
RT
–0.3
–0.3
–0.3
–0.3
–0.3
–55
5.5
5.5
8
RST
Cdly
SS
COMP
8
7
Operating virtual junction temperature, TJ
Storage temperature, Tstg
150
165
°C
°C
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD) Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.6
NOM
MAX
48
UNIT
V
VI
Unregulated buck supply input voltage (VIN, EN)
In continuous conduction mode (CCM)
0.9
18
V
VReg
Regulated output voltage
Power up in low-power mode (LPM) or
discontinuous conduction mode (DCM)
0.9
5.5
V
Bootstrap capacitor (BOOT)
Switched outputs (PH)
3.6
3.6
0
56
48
V
V
Logic levels (RST, VSENSE, OV_TH, RST_TH, Rslew, SYNC, RT)
Logic levels (SS, Cdly, COMP)
5.25
6.5
V
0
V
TA
Operating ambient temperature
–55
125
°C
4
Copyright © 2016, Texas Instruments Incorporated
TPS54262-EP
www.ti.com.cn
ZHCSFU3 –DECEMBER 2016
6.4 Thermal Information
TPS54262-EP
THERMAL METRIC(1)
PWP (HTSSOP)
UNIT
20 PINS
37.1
20.8
8.7
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
8.7
RθJC(bot)
1.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 DC Electrical Characteristics
VIN = 7 V to 48 V, EN = VIN, TJ = –55°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TEST(1)
MIN
TYP
MAX UNIT
INPUT POWER SUPPLY
Normal mode: after initial start-up
3.6
48
Falling threshold
(LPM disabled)
8
8.5
31
VIN
Supply voltage on VIN
Info
V
Rising threshold
(LPM activated)
Low-power mode
High voltage threshold
(LPM disabled)
29
34
Quiescent current,
normal mode
Open loop test – maximum duty cycle
VIN = 7 V to 48 V
Iq-Normal
Iq-LPM
ISD
PT
PT
PT
5
10
mA
µA
µA
TA = 25°C
50
70
75
75
75
ILoad < 1 mA,
VIN = 12 V
–55 < TJ < 150°C
TA = 25°C
Quiescent current, low-
power mode
ILoad < 1 mA,
VIN = 24 V
–55 < TJ < 150°C
EN = 0 V,
device is off
Shutdown current
TA = 25°C, VIN = 12 V
1
4
TRANSITION TIMES (LOW POWER – NORMAL MODES)
Transition delay, normal
mode to low-power mode
td1
td2
VIN = 12 V, VReg = 5 V, ILoad = 1 A to 1 mA
VIN = 12 V, VReg = 5 V ILoad = 1 mA to 1 A
CT
CT
100
5
µs
µs
Transition delay, low-power
mode to normal mode
SWITCH MODE SUPPLY; VReg
VReg
Regulator output
VSENSE = 0.8 Vref
Info
CT
PT
0.9
18
V
V
VSENSE
RDS(ON)
Feedback voltage
VReg = 0.9 V to 18 V (open loop)
Measured across VIN and PH, ILoad = 500 mA
0.788
0.8 0.812
Internal switch resistance
500 mΩ
Switch current limit, cycle by
cycle
ICL
VIN = 12 V
Info
2.5
3.2
4.1
A
tON-Min
tOFF-Min
fsw
Duty cycle pulse width
Bench CHAR only
Info
Info
PT
50
100
0.2
100
200
150
250
ns
ns
Bench CHAR only
Switching frequency
Set using external resistor on RT pin
2.2 MHz
Internal oscillator frequency
tolerance
PT
fsw
–10%
10%
ISink
ILimit
Start-up condition
Prevent overshoot
OV_TH = 0 V, VReg = 10 V
Info
Info
1
mA
mA
0 V < OV_TH < 0.8 V, VReg = 10 V
80
(1) PT: Production tested
CT: Characterization tested only, not production tested
Info: User information only, not production tested
Copyright © 2016, Texas Instruments Incorporated
5
TPS54262-EP
ZHCSFU3 –DECEMBER 2016
www.ti.com.cn
DC Electrical Characteristics (continued)
VIN = 7 V to 48 V, EN = VIN, TJ = –55°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TEST(1)
MIN
TYP MAX UNIT
ENABLE (EN)
VIL
VIH
Low input threshold voltage
High input threshold voltage
PT
PT
0.7
V
V
1.7
EN = 60 V
EN = 12 V
100
8
135
15
Leakage current into EN
terminal
Ilkg
PT
µA
RESET DELAY (Cdly)
External capacitor charge
current
IO
EN = high
PT
PT
1.4
1.7
2
2
3
µA
V
VThreshold
Switching threshold voltage
Output voltage in regulation
LOW-POWER MODE (LPM)
VIL
VIH
Low input threshold voltage
VIN = 12 V
PT
PT
0.7
95
V
V
High input threshold voltage VIN = 12 V
Leakage current into LPM
terminal
Ilkg
LPM = 5 V
PT
65
µA
RESET OUTPUT (RST)
trdly
POR delay timer
Based on Cdly capacitor
Check RST output
PT
PT
PT
3.2
0.768
10
7
0.832
35
ms/nF
V
Reset threshold voltage for
VReg
VReg_RST
tnRSTdly
Filter time
Delay before RST is asserted low
20
50
µs
SOFT START (SS)
ISS
Soft-start source current
PT
40
60
0.7
95
µA
SYNCHRONIZATION (SYNC)
VIL
VIH
Ilkg
Low input threshold voltage
PT
PT
PT
V
V
High input threshold voltage
Leakage current
1.7
SYNC = 5 V
65
µA
VIN = 12 V, VReg = 5 V,
180 kHz < fsw < fext < 2 × fsw < 2.2 MHz
External input clock
frequency
SYNC (fext
SYNCtrans
SYNCtrans
)
CT
Info
Info
180
2200 kHz
External clock to internal
clock
No external clock, VIN = 12 V, VReg = 5 V
32
µs
µs
Internal clock to external
clock
External clock = 1 MHz, VIN = 12 V,
VReg = 5 V
2.5
SYNCCLK
SYNCCLK
Rslew
Minimum duty cycle
Maximum duty cycle
CT
CT
30%
70%
IRslew
Rslew = 50 kΩ
Rslew = 10 kΩ
CT
CT
20
µA
µA
IRslew
100
OVERVOLTAGE SUPERVISORS (OV_TH)
Threshold voltage for VReg
during overvoltage
Internal switch is turned off
0.768
0.832
V
VReg_OV
PT
VReg = 5 V
Internal pulldown on VReg, OV_TH = 1 V
70(2)
mA
THERMAL SHUTDOWN
Thermal shutdown junction
temperature
TSD
CT
CT
175
30
°C
°C
THYS
Hysteresis
(2) This is the current flowing into the VReg pin when voltage at OV_TH pin is 1 V.
6
Copyright © 2016, Texas Instruments Incorporated
TPS54262-EP
www.ti.com.cn
ZHCSFU3 –DECEMBER 2016
6.6 Typical Characteristics
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
Rslew = 14 kW
Rslew = 30 kW
VIN = 7 V
VIN = 14 V
-10
-0.5
0
0.5
1
1.5
2
-0.5
0
0.5
1
1.5
2
Load Current (A)
VReg = 5 V
C = 100 µF
Load Current (A)
fsw = 500 kHz
Rslew = 30 kΩ
D003
D004
VIN = 14 V
L = 22 µH
fsw = 500 kHz
TA = 25°C
VReg = 5 V
C = 100 µF
L = 22 µH
TA = 25°C
Figure 1. Efficiency vs Load Current for Different Rslew
Resistors
Figure 2. Efficiency vs Load Current for Different Vin
65
63
61
59
57
55
53
51
49
9
8
7
6
5
4
3
2
VS = 12 V
VS = 24 V
VS = 12 V
VS = 24 V
1
47
45
0
-55
0
55
110
150
-55
0
55
110
150
Temperature (èC)
Temperature (èC)
D005
D007
EN not connected to VIN
EN not connected to VIN
Figure 3. LPM, Quiescent Current Variation With
Temperature
Figure 4. Shutdown Current Variation With Temperature
6
5
4
3
2
8
7.5
7
6.5
6
ILOAD = 1 A
ILOAD = 500 mA
ILOAD = 0 A
1
0
5.5
Power Up (Start Up)
Power Down (Tracking)
5
2
3
4
5
6
7
8
0
50
100
150 200
Input Voltage (V)
Load Current (mA)
D006
D002
VReg = 5 V
TA = 25°C
Figure 5. Output Voltage vs Input Voltage for Different
Load Currents (1)
Figure 6. Input Voltage vs Load Current During Power Up
(1)
and Power Down
(1) Figure 5 shows the dropout operation during low input conditions.
Figure 6 shows the following plots:
(a) Power Up (Start Up): Input voltage required to achieve the 5-V regulation during power up over the range of load currents
(b) Power Down (Tracking): Input voltage at which the output voltage drops approximately by 0.7 V from the programmed 5-V regulated
voltage
Copyright © 2016, Texas Instruments Incorporated
7
TPS54262-EP
ZHCSFU3 –DECEMBER 2016
www.ti.com.cn
Typical Characteristics (continued)
802.5
1015
1010
1005
1000
995
801.5
800.5
799.5
798.5
797.5
796.5
990
985
980
975
970
-55
0
55
110
150
-55
0
55
110
150
Temperature (èC)
Temperature (èC)
D008
D009
VIN = 12 V
EN = high
VIN = 12 V
EN = high
Figure 7. Internal Reference Voltage
Figure 8. Voltage Drop ON Rslew for Current Reference
(Slew Rate / Rslew)
5.5
5.4
5.3
5.2
5.1
5
4.9
4.8
-55
0
55
110
150
Temperature (èC)
D001
VIN = 12 V
EN = high
Figure 9. Current Consumption With Temperature
8
Copyright © 2016, Texas Instruments Incorporated
TPS54262-EP
www.ti.com.cn
ZHCSFU3 –DECEMBER 2016
7 Detailed Description
7.1 Overview
The TPS54262-EP device is a 60-V, 2-A DC-DC step down (buck) converter using voltage-control mode
scheme. The device features a supervisory function for power-on-reset during system power on. Once the output
voltage has exceeded the threshold set by RST_TH pin, a delay of 1 ms/nF (based on capacitor value on Cdly
terminal) is invoked before the RST line is released high. Conversely on power down, once the output voltage
falls below the same set threshold, the RST line is pulled low only after a deglitch filter of approximately 20 µs
(typical) expires. This is implemented to prevent reset from being triggered due to fast transient line noise on the
regulated output supply.
An overvoltage monitor function is used to limit regulated output voltage to the threshold set by OV_TH pin. Both
the RST_TH and OV_TH monitoring voltages are set to be a prescale of the output voltage, and thresholds
based on the internal bias voltages of the voltage comparators (0.8-V typical).
Detection of undervoltage on the regulated output is based on the RST_TH setting and will invoke RST line to be
asserted low. Detection of overvoltage on the output is based on the OV_TH setting and will not invoke the RST
line to be asserted low. However, the internal switch is commanded to turn OFF.
In systems where power consumption is critical, low-power mode (LPM) is implemented to reduce the non-
switching quiescent current during light-load conditions. After the device has been operating in discontinuous
conduction mode (DCM) for at least 100 µs (typical), depending upon the load current, it may enter in pulse skip
mode (PSM). The operation of when the device enters DCM is dependent on the selection of the external
components.
If thermal shutdown is invoked due to excessive power dissipation, the internal switch is disabled and the
regulated output voltage starts to decrease. Depending on the load current, the regulated output voltage could
decay and the RST_TH threshold may assert the RST output low.
7.2 Functional Block Diagram
BOOT
20
Rslew
Bandgap
Ref
LPM
VIN
0.8 V ref
0.2 V ref
4
7
R7
D1
Internal
Supply
Internal
Voltage
Rail
19
16
VIN
18
VBATT
R11
VReg
C1
C3
Gate Drive with
Over-Current Limit
for Internal Switch
5
L
R10
EN
RT
PH
VReg
17
Selectable
Oscillator
Thermal
Sensor
6
D2
C4
C7
R9
R8
ref
Error
Amp
-
R4
R5
VSENSE
SS
SYNC
Cdly
3
9
14
11
+
C5
C8
0.8 V ref
C6
C2
Vreg
15
COMP
R6
+
-
0.82 V ref
R12
+
-
R1
R2
0.8 V ref
RST_ TH
8
13
RST
C10
Voltage
Comp
OV_ TH
Reset with
Delay Timer
-
12
GND
+
R3
10
0.8 V ref
C9
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7.3 Feature Description
The TPS54262-EP device is a DC-DC converter using a voltage-control mode scheme with an input voltage
feed-forward technique. The device can be programmed for a range of output voltages with a wide input voltage
range. The following sections provide details regarding setting up the device, detailed functionality, and the
modes of operation.
7.3.1 Unregulated Input Voltage
The input voltage is supplied through VIN pins (pin 18 and 19) which must be externally protected against
voltage levels greater than 60 V and reverse input polarity. An external diode is connected to protect these pins
from reverse input polarity. The input current drawn from this pin is pulsed, with fast rise and fall times.
Therefore, this input line requires a filter capacitor to minimize noise. Additionally, for EMI considerations, an
input filter inductor may also be required.
NOTE
For design considerations, VIN/VReg ratios should always be set such that the minimum
required duty cycle pulse (tON-Min) is greater than 150 ns. The minimum off time (tOFF-Min) is
250 ns for all conditions.
7.3.2 Regulated Output Voltage
The regulated output voltage (VReg) is fed back to the device through VReg pin (pin 16). Typically, an output
capacitor of value within range of 10 µF to 400 µF is connected at this pin. TI also recommends using a filter
capacitor with low ESR characteristics to minimize ripple in regulated output voltage. The VReg pin is also
internally connected to a load of approximately 100 Ω, which is turned ON in the following conditions:
•
During start-up condition, when the device is powered up with no-load, or whenever EN is toggled, the
internal load connected to VReg pin is turned ON to charge the bootstrap capacitor to provide gate drive
voltage to the switching transistor.
•
During normal operating conditions, when the regulated output voltage (VReg) exceeds the overvoltage
threshold (VReg_OV, preset by external resistors R1, R2, and R3), the internal load is turned ON, and this
pin is pulled down to bring the regulated output voltage down.
•
•
When VIN is less than typical VIN falling threshold level while LPM is disabled. From device specifications,
VIN typical falling threshold (LPM disabled) = 8 V (see DC Electrical Characteristics).
When RST is low.
7.3.3 Regulation and Feedback Voltage
The regulated output voltage (VReg) can be programmed by connecting external resistor network at VSENSE pin
(pin 14). The output voltage is selectable from 0.9 V to 18 V according to the following relationship:
where
•
•
R4, R5 = feedback resistors (see Functional Block Diagram)
Vref = 0.8 V (typical)
(1)
The overall tolerance of the regulated output voltage is given by Equation 2.
R4
tolVReg = tolVref
+
´(tolR4 + tolR5 )
R4 + R5
where
•
•
tolVref = tolerance of internal reference voltage (tolVref = ± 1.5%)
tolR4,tolR5 = tolerance of feedback resistors R4, R5
(2)
For a tighter tolerance on VReg, lower-value feedback resistors can be selected. However, for proper operation in
low-power mode (see Figure 17), TI recommends keeping R4 + R5 around 250 kΩ (typical).
The output tracking depends upon the loading conditions and is explained in Table 1 and is shown in Figure 6.
10
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Feature Description (continued)
Table 1. Load Conditions
LOAD CONDITION
OUTPUT TRACKING
Nominal load in CCM
VReg tracks VIN approximately as: VReg = 95% (VIN – ILoad × 0.5)
To enable the tracking feature, following conditions should be met:
1) fSW < 600 kHz
No load/light load in LPM
2) VReg < 8 V, typical (related to VIN falling threshold when LPM is disabled)
7.3.4 Enable and Shutdown
The EN pin (pin 5) provides electrical ON/OFF control of the regulator. Once the EN pin voltage exceeds the
upper threshold voltage (VIH), the regulator starts operating and the internal soft start begins to ramp. If the EN
pin voltage is pulled below the lower threshold voltage (VIL), the regulator stops switching and the internal soft
start resets. Connecting this pin to ground or to any voltage less than VIL disables the regulator and causes the
device to shut down. This pin must have an external pullup or pulldown to change the state of the device.
7.3.5 Soft Start
An external soft-start capacitor is connected to SS pin (pin 11) to set the minimum time to reach the desired
regulated output voltage (VReg) during power-up cycle. This prevents the output voltage from overshooting when
the device is powered up. This is also useful when the load requires a controlled voltage slew rate, and also
helps to limit the current drawn from the input voltage supply line.
For proper operation, the following conditions must be satisfied during power up and after a short circuit event:
•
•
VIN – VReg > 2.5 V
Load current < 1 A, until RST goes high
The power-up current limit (30% of the typical current limit value) is released after the feedback voltage (at
VSENSE pin) is high enough such that RST is asserted high. The recommended value of soft-start capacitor is
100 nF (typical) for start-up load current of 1 A (maximum).
7.3.6 Oscillator Frequency
The oscillator frequency can be set by connecting an external resistor (R8 in Functional Block Diagram) to RT
pin (pin 6). Figure 10 shows the relation between the resistor value (RT) and switching frequency (fsw). The
switching frequency can be set in the range 200 kHz to 2200 kHz. In addition, the switching frequency can be
imposed externally by a clock signal (fext) at the SYNC pin.
7.3.6.1 Selecting the Switching Frequency
A power supply switching at a higher switching frequency allows use of lower value inductor and smaller output
capacitor compared to a power supply that switches at a lower frequency. Typically, the user will want to choose
the highest switching frequency possible because this will produce the smallest solution size. The switching
frequency that can be selected is limited by the following factors:
•
•
•
•
The input voltage
The minimum target regulated voltage
Minimum on-time of the internal switching transistor
Frequency shift limitation
Selecting lower switching frequency results in using an inductor and capacitor of a larger value, where as
selecting higher switching frequency results in higher switching and gate drive power losses. Therefore, a
tradeoff must be made between physical size of the power supply and the power dissipation at the system/
application level.
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The minimum and maximum duty cycles can be expressed in terms of input and output voltage as shown in
Equation 3.
where
•
•
•
•
•
•
DMin = minimum duty cycle
DMax = maximum duty cycle
VINMin = minimum input voltage
VINMax = maximum input voltage
VReg-Min = minimum regulated output voltage
VReg-Max = maximum regulated output voltage
(3)
(4)
Maximum switching frequency can be calculated using Equation 4.
where
•
•
fsw-Max = maximum switching frequency
tON-Min = minimum on-time of the NMOS switching transistor
Knowing the switching frequency, the value of resistor to be connected at RT pin can be calculated using the
graph shown in Figure 10. Consider the oscillator tolerance (±10%) while selecting the external RT resistor. For
example if fsw = 2.2 MHz is required, select the RT resistor which corresponds to fsw = 2 MHz in Figure 10 to
allow +10% oscillator tolerance.
600
VIN = 8 V
VIN = 14 V
VIN = 24 V
500
400
300
200
100
0
VIN = 40 V
0
200
400
600
800
1000
1200
1400
1600
1800
2000
2200
Switching Frequency (kHz)
D010
Figure 10. Switching Frequency vs Resistor Value
12
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7.3.6.2 Synchronization With External Clock
An external clock signal can be supplied to the device through SYNC pin (pin 3) to synchronize the internal
oscillator frequency with an external clock frequency. The synchronization input overrides the internal fixed
oscillator signal. The synchronization signal must be valid for approximately two clock cycles before the transition
is made for synchronization with the external frequency input. If the external clock input does not transition low or
high for 32 µs (typical), the system defaults to the internal clock set by the resistor connected to the RT pin. The
SYNC input can have a frequency according to Equation 5.
180 kHz < fsw < fext < 2 × fsw < 2.2 MHz
where
•
•
fsw = oscillator frequency determined by resistor connected to the RT pin
fext = frequency of the external clock fed through SYNC pin
(5)
For example, if the resistor connected at RT pin is selected such that the switching frequency (fsw) is 500 kHz,
then the external clock can have a frequency (fext) from 500 kHz to 1000 kHz. But, if the resistor connected at RT
pin is selected such that the switching frequency (fsw) is 1500 kHz, then the external clock can have a frequency
(fext) from 1500 kHz to 2200 kHz only.
If the external clock goes off for less than 32 µs, the NMOS switching FET is turned off and the output voltage
starts decreasing. Depending upon the load conditions, the output voltage may hit the undervoltage threshold
and reset threshold before the external clock appears. The NMOS switching FET stays OFF until the external
clock appears again. If the output voltage hits the reset threshold, the RST pin is asserted low after a deglitch
time of 20 µs (typical).
If the external clock goes off for more than 32 µs, the NMOS switching FET is turned off and the output voltage
starts decreasing. Under this condition the default internal oscillator clock set by RT pin overrides the external
after 32 µs and the NMOS switching FET resumes switching. When the external clock appears again (such that
180 kHz < fsw < fext < 2 × fsw < 2.2 MHz), the NMOS switching FET starts switching at the frequency determined
by the external clock.
7.3.7 Slew Rate Control
The slew rate of the NMOS switching FET can be set by using an external resistor (R7 in Functional Block
Diagram). The range of rise times and fall times for different values of slew resistor are shown in Figure 11 and
Figure 12.
350
300
250
200
150
100
50
35
30
25
20
15
10
5
40 V
14 V
8 V
24 V
24 V
14 V
8 V
40 V
0
0
10
20
30
40
50
60
70
10
20
30
40
50
60
70
Rslew - Slew Resistor - kW
Rslew - Slew Resistor - kW
Figure 12. FET Fall Time
Figure 11. FET Rise Time
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7.3.8 Reset
The RST pin (pin 8) is an open-drain output pin used to indicate external digital devices and loads if the device
has powered up to a programmed regulated output voltage properly. This pin is asserted low until the regulated
output voltage (VReg) exceeds the programed reset threshold (VREG_RST, see Equation 8) and the reset delay
timer (set by Cdly pin) has expired. Additionally, whenever the EN pin is low or open, RST is immediately
asserted low regardless of the output voltage. There is a reset filter timer to prevent reset being invoked due to
short negative transients on the output line. If thermal shutdown occurs due to excessive thermal conditions, this
pin is asserted low when the switching FET is commanded OFF and the output falls below the reset threshold.
VIN
Css
VReg_RST
VReg
Cdly
t
delay
RST
Figure 13. Power-On Condition and Reset Line
14
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VIN
Css
VReg_RST
VReg
Cdly
RST
20 ms
(Typ-Deglitch Time)
Figure 14. Power-Down Condition and Reset Line
7.3.9 Reset Delay
The delay time to assert the RST pin high after the supply has exceeded the programmed VReg_RST voltage
(see Equation 8 to calculate VReg_RST) can be set by external capacitor (C2 in Functional Block Diagram)
connected to the Cdly pin (pin 9). The delay may be programmed in the range of 2.2 ms to 200 ms using a
capacitor in the range of 2.2 nF to 200 nF. The delay time is calculated using Equation 6:
where
•
C = capacitor on Cdly pin
(6)
7.3.10 Reset Threshold and Undervoltage Threshold
The undervoltage threshold (VReg_UV) level for proper regulation in low-power mode and the reset threshold
level (VReg_RST) to initiate a reset output signal can be programmed by connecting an external resistor string to
the RST_TH pin (pin 13). The resistor combination of R1, R2, and R3 is used to program the threshold for
detection of undervoltage. Voltage bias on R2 + R3 sets the reset threshold.
Undervoltage threshold for transient and low-power mode operation is given by the Equation 7. The
recommended range for VReg_UV is 73% to 95% of VReg
.
(7)
(8)
Reset threshold is given by Equation 8. The recommended range for VReg_RST is 70% to 92% of VReg
.
7.3.11 Overvoltage Supervisor
The overvoltage monitoring of the regulated output voltage, VReg can be achieved by connecting an external
resistor string to the OV_TH pin (pin 12). The resistor combination of R1, R2, and R3 is used to program the
threshold for detection of overvoltage. The bias voltage of R3 sets the overvoltage threshold and the accuracy of
regulated output voltage in hysteretic mode during transient events.
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(9)
Recommended range for VReg_OV is 106% to 110% of VReg
.
7.3.12 Noise Filter on RST_TH and OV_TH Terminals
External capacitors may be required to filter the noise added to RST_TH and OV_TH terminals. The noise is
more pronounced with fast falling edges on the PH pin. Therefore, selecting a smaller Rslew resistor (R7 in
Functional Block Diagram) for a higher slew rate will require more external capacitance to filter the noise.
The RC time constant depends on external components (R2, R3, C9 and C10 in Functional Block Diagram)
connected to RST_TH and OV_TH pins. For proper noise filtering, improved loop transient response and better
short circuit protection, Equation 10 must be satisfied.
(R2 + R3) × (C9 + C10) < 2 µs
(10)
To meet this requirement, TI recommends to use lower values of external capacitors and resistors. The value of
the time constant is also affected by the PCB capacitance and the application setup. Therefore, in some cases
the external capacitors (C9, C10) on RST_TH and OV_TH terminals may not be required. Users can place a
footprint on the application PCB and only populate it if necessary. Also, the external resistors (R1, R2, R3) must
be sized appropriately to minimize any significant effect of board leakage.
For most cases, TI recommends keeping the external capacitors (either from board capacitance or by connecting
external capacitors) between 10 pF to 100 pF; therefore, to meet time constant requirement in Equation 10, the
total external resistance (R1 + R2 + R3) should be less than 200 kΩ.
7.3.13 Boot Capacitor
An external boot strap capacitor (C3 in Functional Block Diagram) is connected to pin 20 (BOOT) to provide the
gate drive voltage for the internal NMOS switching FET. TI recommends X7R or X5R grade dielectrics because
of their stable values over temperature. The capacitor value may need to be adjusted higher for high VReg and/or
low frequencies applications (for example, 100 nF for 500 kHz/5 V and 220 nF for 500 kHz/8 V).
7.3.14 Short Circuit Protection
The TPS54262-EP features an output short circuit protection. Short circuit conditions are detected by monitoring
the RST_TH pin, and when the voltage on this node drops below 0.2 V, the switching frequency is decreased
and current limit is folded back to protect the device. The switching frequency is folded back to approximately
25 kHz and the current limit is reduced to 30% of the typical current limit value.
7.3.15 Overcurrent Protection
The device features overcurrent protection to protect it from load currents greater than 2 A. Overcurrent
protection is implemented by sensing the current through the NMOS switching FET. The sensed current is
compared to a current reference level representing the overcurrent threshold limit (ICL). If the sensed current
exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The system will ignore the
overcurrent indicator for the leading edge blanking time at the beginning of each cycle to avoid any turnon noise
glitches.
Once overcurrent indicator is set true, overcurrent protection is triggered. The NMOS switching FET is turned off
for the rest of the cycle after a propagation delay. The overcurrent protection scheme is called cycle-by-cycle
current limiting. If the sensed current continues to increase during cycle-by-cycle current limiting, the temperature
of the part will start rising, the TSD will kick in and shutdown switching until the part cools down.
7.3.16 Internal Undervoltage Lockout (UVLO)
This device is enabled on power up once the internal bandgap and bias currents are stable; this happens
typically at VIN = 3.4 V (minimum). On power down, the internal circuitry is disabled at VIN = 2.6 V (maximum).
16
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7.3.17 Thermal Shutdown (TSD)
The TPS54262-EP protects itself from overheating with an internal thermal shutdown (TSD) circuit. If the junction
temperature exceeds the thermal shutdown trip point, the NMOS switching FET is turned off. The device is
automatically restarted under the control of soft-start circuit when the junction temperature drops below the
thermal shutdown hysteretic trip point. During low-power mode operation, the thermal shutdown sensing circuitry
is disabled for reduced current consumption. If VReg drops below VReg_UV, thermal shutdown monitoring is
activated.
7.3.18 Loop Control Frequency Compensation – Type 3
Type 3 compensation has been used in the feedback loop to improve the stability of the convertor and regulation
in the output in response to the changes in input voltage or load conditions. This becomes important because the
ceramic capacitors used to filter the output have a low Equivalent Series Resistance (ESR). Type 3
compensation is implemented by connecting external resistors and capacitors to the COMP pin (output of the
error amplifier, pin 15) of the device as shown in Figure 15.
Figure 15. Type 3 Compensation
The crossover frequency should be less than 1/5th to 1/10th of the switching frequency, and should be greater
than five times the double pole frequency of the LC filter.
fc < fsw × (0.1 to 0.2)
where
•
fsw = switching frequency
(11)
The modulator break frequencies as a function of the output LC filter are derived from Equation 12 and
Equation 13. The LC output filter gives a double pole that has a –180° phase shift.
1
fLC
=
2pÖLC
where
•
•
L = output inductor
C = output capacitor (C4 in functional block diagram)
(12)
The ESR of the output capacitor C gives a ZERO that has a 90° phase shift.
1
fESR
=
2pC × ESR
where
•
ESR = Equivalent series resistance of a capacitor at a specified frequency
(13)
17
The regulated output voltage, VReg is given by Equation 14.
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R4
R5
VReg = Vref
1 +
(14)
(15)
VReg
For VIN = 8 V to 50 V, the VIN/Vramp modulator gain is approximately 10 and has a tolerance of about 20%.
VIN
Vramp
Gain = Amod
=
= 10
(16)
(17)
Therefore,
Also, Vramp is fixed for the following range of VIN. Vramp = 1 V for VIN < 8 V, and Vramp = 5 V for VIN > 48 V.
The frequencies for poles and zeros are given by following equations.
(C5 + C8)
fp1 =
2p ´ R6 ´ (C5 ´ C8)
(18)
(19)
(20)
(21)
1
fp2 =
2π × R9 × C7
1
fz1 =
2π × R6 × C5
Guidelines for selecting compensation components selection are provided in the Application and Implementation
section of this document.
7.3.18.1 Bode Plot of Converter Gain
Open Loop Error
Amp Gain
f
f
Z1 Z2
f
f
P1 P2
20 log R6(R4+R9)/(R4*R9)
20 log (R6/R4)
20 log (10)
Modulator Gain
Compensation
Gain
Closed Loop Gain
f
f
f
C
LC
ESR
f - Frequency - Hz
Figure 16. Bode Plot of Converter Gain Plot
18
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7.4 Device Functional Modes
TPS54262-EP operates in the following modes based on the output loading conditions, input voltage, and LPM
pin configuration. These operating conditions and modes of operations are shown in Figure 17.
Heavy Loading
LPM Pin = Don’t care
Active Mode CCM
Light Loading
LPM Pin = High
Active Mode DCM
PSM + DCM
Very Light Loading
LPM Pin = High
Light/ Very Light Loading
LPM Pin = Low
LPM
V when
tOFF<tOFF-Min
V when
tON<tON-Min
~8.5 V
~32 V
VIN
Figure 17. Modes of Operation
7.4.1 Active Mode Continuous Conduction Mode (CCM)
In this mode of operation the switcher operates in continuous conduction mode, and the inductor current is
always non-zero if the total load current (internal and external) is greater than IL_DISCONT shown in Equation 22.
(1-D)×V
=
Reg
I =I
L_DISCONT L_LPM
2×f ×L
sw
where
•
•
•
•
D = duty cycle
L = output inductor
VReg = output voltage
fsw = switching frequency
(22)
For VIN < 8.5 V, the device enables an internal approximately 100-Ω load. This, combined with the external load,
can cause the device to enter into CCM even under light external loading conditions (see Device Functional
Modes). This mode of operation is shown in Figure 18 is also called the Normal mode of operation.
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Device Functional Modes (continued)
VIN = 14 V
ILoad = 55 mA
fsw = 500 kHz
VIN = 14 V
ILoad = 1 A
fsw = 500 kHz
LPM pin = disable
LPM pin = don't care
Figure 19. Active Mode DCM
Figure 18. Active Mode CCM
7.4.2 Active Mode Discontinuous Conduction Mode (DCM)
In this mode of operation the switcher operates in discontinuous conduction mode, and the inductor current
becomes zero if the total load current (internal and external) is less than IL_DISCONT shown in Equation 23.
(1-D)×V
=
Reg
I =I
L_DISCONT L_LPM
2×f ×L
sw
(23)
The device enters in this mode of operation when LPM pin is set high (disabled) and output loading is less than
IL_DISCONT. This mode of operation is shown in Figure 19.
7.4.3 Pulse Skip Mode (PSM)
In this mode of operation the switcher operates in discontinuous conduction mode, and the inductor current
becomes zero. The device enters in this mode of operation in the following conditions:
•
At low input voltages when VReg starts losing regulation and the OFF time (tOFF) of the switching FET tends to
be close to or slightly less than the minimum OFF time (tOFF-Min). If OFF time is much smaller than tOFF-Min
,
there is a risk that the part stops switching and regulation is lost until power is re-cycled with OFF time
greater than tOFF-Min. This mode of operation is shown in Figure 21. Comparing Figure 20 and Figure 21, pulse
skipping occurs in Figure 21 but not in Figure 20 under similar output loading conditions.
V
æ
ç
ç
è
ö
1
Reg
÷
VIN-I ´R
Load DS(ON)
<~V
Reg
1-
´
>t
OFF-Min
and
÷
VIN
f
sw
ø
(24)
20
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Device Functional Modes (continued)
VIN = 5.5 V
ILoad = 50 mA
fsw = 500 kHz
VIN = 6.2 V
ILoad = 50 mA
fsw = 500 kHz
LPM pin = don't care
LPM pin = don't care
Figure 21. PSM at Low VIN
Figure 20. Active Mode CCM
•
•
Likewise, at higher input voltages when the ON time (tON) of the switching FET becomes close to or slightly
less than the minimum ON time (tON-Min) and the VReg start losing regulation, the device enters in PSM. If ON
time is much smaller than tON-Min, there is a risk that the part stops switching and regulation is lost until power
is recycled with ON time greater than tON-Min
.
At nominal input voltages during very light output loading. This mode of operation is shown in Figure 22.
Comparing Figure 19 and Figure 22, in both cases the device is operating in discontinuous conduction mode;
however, pulse skipping happens in Figure 22 because of very light output loading for similar input voltage.
LPM pin must be set high (disabled) for this to happen.
VIN = 14 V
ILoad = 50 µA
fsw = 500 kHz
LPM pin = disable
Figure 22. PSM at Nominal VIN
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Device Functional Modes (continued)
7.4.4 Low-Power Mode (LPM)
In this mode of operation the device briefly operates in discontinuous conduction mode and then turns off until
VReg < VReg_UV threshold and this cycle is repeated. The LPM pin must be enabled to enable LPM mode of
operation. When total load is less than IL_DISCONT, the device operates in LPM for VIN approximately 8.5 V to
approximately 32 V. This mode of operation is shown in Figure 23 and Figure 24 (zoomed out).
VIN = 14 V
ILoad = 50 mA
fsw = 500 kHz
VIN = 14 V
ILoad = 50 mA
fsw = 500 kHz
LPM pin = enable
LPM pin = enable
Figure 24. Low-Power Mode (Zoom In)
Figure 23. Low-Power Mode
Any transition from low-power mode to active mode CCM occurs within 5 µs (typical). In low-power mode, the
converter operates as a hysteretic controller with the threshold limits set by VReg_UV (see Equation 7,
Functional Block Diagram and Figure 25), for the lower limit and approximately VReg for the upper limit. To
ensure tight regulation in the low-power mode, R2 and R3 values are set accordingly (see discussion on Noise
Filter on RST_TH and OV_TH Terminals). The device operates in both automatic (LPM pin is connected to
ground) and digitally controlled (status of LPM pin is controlled by an external device, for example by a
microcontroller) low-power mode. The digital low-power mode can over-ride the automatic low-power mode
function by applying the appropriate signal on the LPM terminal. The part goes into active mode CCM for at least
100 µs, whenever RST_TH or VReg_UV is tripped.
Table 2. LPM Pin Status
LPM PIN STATUS
MODES OF OPERATION
Device is forced in normal mode.
At light loads, the device operates in DCM with a switching frequency determined by the
external resistor connected to RT pin.
High
At very light loads, the device operates in PSM with a reduced switching frequency (see
Figure 17).
Device automatically changes between normal mode and low-power mode depending on the
load current.
Low or open
22
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Table 3. Modes of Operation
MODES OF OPERATION
DESCRIPTION
All circuits including overvoltage threshold circuit (OV_TH) are enabled.
At heavy loads, the device operates in continuous conduction mode irrespective of the status
of LPM pin.
OR
Normal mode (active mode)
At light loads, the device operates in discontinuous conduction mode (DCM) only if LPM pin
is externally set high.
OV_TH circuit is disabled.
The device is in DCM, and LPM pin should be forced low.
Low-power mode
When the device is operating in low-power mode, and if the output is shorted to ground, a reset is asserted. The
thermal shutdown and current limiting circuitry is activated to protect the device. The LPM pin is active low and is
internally pulled down; therefore, the low-power mode is automatically enabled unless this pin is driven high
externally (for example, by a microcontroller) and the device is in continuous conduction mode. However, the
low-power mode operation is initiated only when the device enters discontinuous mode of operation at light
loads, and the LPM pin is low (or connected to ground).
7.4.5 Hysteretic Mode
The device enters in this mode of operation when the main loop fails to respond during line and load transients
and regulate within specified tolerances. The device exits this mode of operation when the main control loop
responds, after the error amplifier stabilizes, and controls the output voltage within tighter tolerance.
The power up conditions in different modes of operations are explained in Table 4.
Table 4. Power-Up Conditions
MODE OF OPERATION
CCM
POWER-UP CONDITIONS
VIN > 3.6 V (minimum)
LPM/DCM
VReg < 5.5 V and (VIN – VReg) > 2.5 V (applicable only for fsw > 600 kHz)
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7.4.6 Output Tolerances in Different Modes of Operation
Figure 25. Output Tolerances Diagram
Table 5. Mode of Operation Descriptions
MODE OF OPERATION
Hysteretic mode
VReg LOWER LIMIT
VReg UPPER LIMIT
VReg_OV
COMMENTS
VReg_UV
VReg_UV
Minimum to maximum ripple on output
Minimum to maximum ripple on output
Minimum to maximum ripple on output
Low-power mode
VReg + tolVReg
VReg + tolVReg
Active mode (Normal)
VReg – tolVReg
Table 6. Supervisor Thresholds Descriptions
SUPERVISOR
THRESHOLDS
VReg TYPICAL
VALUE
TOLERANCE
COMMENTS
R1 + R2
VReg_OV
Overvoltage threshold setting
± (tolVref + (
± (tolVref + (
)´(tolR1 + tolR2 + tolR3
)´(tolR1 + tolR2 + tolR3
)
R1 + R2 + R3
R1
VReg_RST
Reset threshold setting
)
R1 + R2 + R3
24
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54262-EP step-down DC-DC converter features an integrated NMOS switching FET and voltage
supervisor circuit. It is designed to provide up to a 2-A output current from an input voltage source of 3.6 V to 48
V, and it can withstand transient voltages up to 60 V on its input pin. The device's input voltage line feed forward
topology improves line transient regulation of the voltage mode buck regulator. The device also features low-
power mode operation under light-load conditions, which reduces the supply current to 50 μA (typical). It can
work for wide switching frequency range (200 kHz to 2.2 MHz), which allows regulator design to be optimized for
efficiency or solution size.
8.2 Typical Application
This section explains considerations for the external components selection. Figure 26 shows the interconnection
between external components and the device for a typical DC-DC step-down application.
The following examples demonstrate the design of a high frequency switching regulator using ceramic output
capacitors. A few parameters must be known to start the design process. These parameters are typically
determined at the system level.
D1
VIN
C11
C1
+
VBATT
C3
1
2
20
19
18
17
16
15
14
13
12
11
GND
GND
GND
GND
NC
BOOT
VIN
GND
NC
VReg
VIN
3
L1
SYNC
LPM
EN
VIN
R11
R10
4
PH
D2
R9
C7
5
VReg
VREG
COMP
VSENSE
RST_TH
OV_TH
SS
GND
C12
C4
+
R8
C5
6
GND
GND
RT
VOUT
R4
R7
7
RSLEW
RST
CDLY
AGND
C8
R6
R12
C2
8
VReg
VReg
GND
GND
R1
9
GND
10
GND
C6
R5
R2
R3
C10
GND
GND
GND
GND
C9
GND
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 26. Typical Application Schematic
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Typical Application (continued)
8.2.1 Design Requirements
The input voltage is supplied through VIN pins (pin 18 and 19), which must be externally protected against
voltage levels greater than 60 V and reverse input polarity. An external diode is connected to protect these pins
from reverse input polarity. The input current drawn from this pin is pulsed, with fast rise and fall times.
Therefore, this input line requires a filter capacitor to minimize noise. Additionally, for EMI considerations, an
input filter inductor may also be required.
For design considerations, VIN/VReg ratios must always be set such that the minimum required duty cycle pulse
(tON-Min) is greater than 150 ns. The minimum off time (tOFF-Min) is 250 ns for all conditions. The Detailed Design
Procedure section provides the necessary equations and guidelines for selecting external components for this
regulator.
8.2.2 Detailed Design Procedure
8.2.2.1 Component Selection
8.2.2.1.1 Input Capacitors (C1, C11)
Input filter capacitor (C11) is used to filter out high frequency noise in the input line. Typical values of C11 are 0.1
µF to 0.01 µF. For higher frequency noise, low capacitor values are recommended.
To minimize the ripple voltage, input ceramic de-coupling capacitor (C1) of type X5R or X7R should be used.
The DC voltage rating for the input decoupling capacitor must be greater than the maximum input voltage. This
capacitor must have an input ripple current rating higher than the maximum input ripple current of the converter
for the application; and is determined by Equation 25.
VReg(VINMin - VReg
)
IRMS = ILoad
2
VINMin
(25)
The input capacitors for power regulators are chosen to have a reasonable capacitance-to-volume ratio and fairly
stable over temperature. The value of the input capacitance also determines the input ripple voltage of the
regulator, shown by Equation 26.
0.25´ILoad-Max
DVIN =
C1´ fSW
(26)
Input ceramic filter capacitors should be located in close proximity to the VIN terminal. Surface mount capacitors
are recommended to minimize lead length and reduce noise coupling.
8.2.2.1.2 Output Capacitor (C4, C12)
The selection of the output capacitor will determine several parameters in the operation of the converter (for
example, voltage drop on the output capacitor and the output ripple). The capacitor value also determines the
modulator pole and the roll-off frequency due to the LC output filter double pole. This is expressed in
Equation 12.
The minimum capacitance needed to maintain desired output voltage during high to low load transition and
prevent over shoot is given by Equation 27.
2
L × (ILoad-Max2 – ILoad-Min
)
C4 =
2
VReg-Max2 – VReg-Min
where
•
•
•
•
•
L = output inductor
ILoad-Max = maximum load current
ILoad-Min = minimum load current
VReg-Max = maximum tolerance of regulated output voltage
VReg-Min = minimum tolerance of regulated output voltage
(27)
26
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Typical Application (continued)
During a load step from no load to full load or changes in the input voltage, the output capacitor must hold up the
output voltage above a certain level for a specified time and not issue a reset, until the main regulator control
loop responds to the change. The minimum output capacitance required to allow sufficient drop on the output
voltage without issuing a reset is determined by Equation 28.
2´ DILoad
C4 >
fSW ´ DVReg
where
•
ΔVReg = transient response during load stepping
(28)
The minimum capacitance needed for output voltage ripple specification is given by Equation 29.
(29)
Additional capacitance deratings for temperature, aging, and DC bias must be factored in, and so a value of
100 µF with ESR calculated using Equation 30 of less than 100 mΩ should be used on the output stage.
Maximum ESR of the output capacitor is based on output ripple voltage specification in Equation 30. The output
ripple voltage is a product of the output capacitor ESR and ripple current.
VReg-Ripple
<
RESR
IRipple
(30)
Output capacitor root mean square (RMS) ripple current is given by Equation 31. This is to prevent excess
heating or failure due to high ripple currents. This parameter is sometimes specified by the manufacturers.
VReg (VINMax – VReg
)
ILoad-RMS
=
Ö12 × VINMax × fsw × L1
(31)
Filter capacitor (C12) of value 0.1 µF (typical) is used to filter out the noise in the output line.
8.2.2.1.3 Soft-Start Capacitor (C6)
The soft-start capacitor determines the minimum time to reach the desired output voltage during a power-up
cycle. This is useful when a load requires a controlled voltage slew rate, and helps to limit the current draw from
the input voltage supply line. TI recommends a 100-nF capacitor for start-up loads of 1 A (maximum).
8.2.2.1.4 Bootstrap Capacitor (C3)
A 0.1-µF ceramic capacitor must be connected between the PH and BOOT terminals for the converter to operate
and regulate to the desired output voltage. TI recommends using a capacitor with X5R or better grade dielectric
material, and the voltage rating on this capacitor of at least 25 V to allow for derating.
8.2.2.1.5 Power-On Reset Delay (PORdly) Capacitor (C2)
The value of this capacitor can be calculated using Equation 6.
8.2.2.1.6 Output Inductor (L1)
Use a low EMI inductor with a ferrite type shielded core. Other types of inductors may be used; however, they
must have low EMI characteristics and should be placed away from the low-power traces and components in the
circuit.
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Typical Application (continued)
To calculate the minimum value of the inductor, the ripple current should be first calculated using Equation 32.
IRipple = KIND × ILoad
where
•
•
•
ILoad = maximum output load current
IRipple = allowable peak to peak inductor ripple current, typically 20% of maximum ILoad
KIND = coefficient that represents the amount of inductor ripple current relative to the maximum output current.
(32)
The inductor ripple current is filtered by the output capacitor; therefore, KIND is typically in the range of 0.2 to 0.3,
depending on the ESR and the ripple current rating of the output capacitor (C4).
The minimum value of output inductor can be calculated using Equation 33.
(VINMax – VReg) × VReg
LMin
=
fsw × IRipple × VINMax
where
•
•
•
VINMax = maximum input voltage
VReg = regulated output voltage
fsw = switching frequency
(33)
The RMS and peak currents flowing in the inductor are given by Equation 34 and Equation 35.
2
IRipple
2
IL,RMS
=
ILoad
+
12
(34)
(35)
IRipple
IL,pk = ILoad
+
2
8.2.2.1.7 Flyback Schottky Diode (D2)
The TPS54262-EP requires an external Schottky diode connected between the PH and power ground
termination. The absolute voltage at PH pin should not go beyond the values in Absolute Maximum Ratings. The
Schottky diode conducts the output current during the off state of the internal power switch. This Schottky diode
must have a reverse breakdown voltage higher than the maximum input voltage of the application. A Schottky
diode is selected for its lower forward voltage. The Schottky diode is selected based on the appropriate power
rating, which factors in the DC conduction losses and the AC losses due to the high switching frequencies; this is
determined by Equation 36.
2
(VINMax – VReg) × ILoad × Vfd
VINMax
(VIN – Vfd) × fsw × CJ
2
Pdiode
=
+
where
•
•
•
Pdiode = power rating
Vfd = forward conducting voltage of Schottky diode
CJ = junction capacitance of the Schottky diode
(36)
Recommended part numbers are PDS 360 and SBR8U60P5.
8.2.2.1.8 Resistor to Set Slew Rate (R7)
The slew rate setting is asymmetrical; that is, for a selected value of R7, the rise time and fall time are different.
R7 can be approximately determined from Figure 11 and Figure 12. The minimum recommended value is 10 kΩ.
8.2.2.1.9 Resistor to Select Switching Frequency (R8)
See Selecting the Switching Frequency, Figure 10 and Equation 4.
28
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Typical Application (continued)
8.2.2.1.10 Resistors to Select Output Voltage (R4, R5)
To minimize the effect of leakage current on the VSENSE terminal, the current flowing through the feedback
network should be greater than 5 mA to maintain output accuracy. Higher resistor values help improve the
converter efficiency at low-output currents, but may introduce noise immunity problems. See Equation 1. TI
recommends fixing R4 to a standard value (for example, 187 kΩ) and calculate R5.
8.2.2.1.11 Resistors to Set Undervoltage, Overvoltage, and Reset Thresholds (R1, R2, R3)
8.2.2.1.11.1 Overvoltage Resistor Selection
Using Equation 9, the value of R3 can be determined to set the overvoltage threshold at up to 106% to 110% of
VReg. The sum of R1, R2, and R3 resistor network to ground should be approximately 100 kΩ .
8.2.2.1.11.2 Reset Threshold Resistor Selection
Using Equation 8 the value of R2 + R3 can be calculated, and knowing R3 from the OV_TH setting, R2 can be
determined. Suggested value of reset threshold is 92% of VReg
.
8.2.2.1.11.3 Undervoltage Threshold for Low-Power Mode and Load Transient Operation
This threshold is set above the reset threshold to ensure the regulator operates within the specified tolerances
during output load transient of low load to high load and during discontinuous conduction mode. The typical
voltage threshold can be determined using Equation 7. Suggested value of undervoltage threshold is 95% of
VReg
.
8.2.2.1.12 Low-Power Mode (LPM) Threshold
An approximation of the output load current at which the converter is operating in discontinuous mode can be
obtained from Equation 23 with ± 30% hysteresis. The values used in Equation 3 for minimum and maximum
input voltage will affect the duty cycle and the overall discontinuous mode load current. These are the nominal
values, and other factors are not taken into consideration like external component variations with temperature
and aging.
8.2.2.1.13 Enable Pin Pull-Up Resistor (R11) and Voltage Divider Resistor (R10)
An external pull-up resistor, R11= 30.1 kΩ, is recommended to enable the device for operation and R10 can be
left open.
Based on the application needs, if the device needs to be turned on at certain input voltage using EN pin
threshold, R10 can be used as a voltage divider resistor along with pull-up resistor (R11=30.1 kΩ) and R10 can
be calculated accordingly.
8.2.2.1.14 Pull-Up Resistor (R12) at RST Pin
A standard pull-up resistor, R12 = 2 K Ω can be used at this pin
8.2.2.1.15 Type 3 Compensation Components (R5, R6, R9, C5, C7, C8)
First, make the ZEROs close to double pole frequency, using Equation 12, Equation 13, and Equation 11.
fz1 = (50% to 70%) fLC
fz2 = fLC
Second, make the POLEs above the crossover frequency, using Equation 18 and Equation 19.
fp1 = fESR
fp2 = ½fsw
8.2.2.1.15.1 Resistors
From Equation 1, knowing VReg and R4 (fix to a standard value), R5 can be calculated as shown in Equation 37:
(37)
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Typical Application (continued)
Using Equation 11 and Equation 15, R6 can be calculated as shown in Equation 38:
(38)
(39)
R9 can be calculated as shown in Equation 39:
8.2.2.1.15.2 Capacitors
Using Equation 20, C5 can be calculated as shown in Equation 40:
(40)
(41)
(42)
C7 can be calculated as shown in Equation 41:
C8 can be calculated as shown in Equation 42:
8.2.2.1.16 Noise Filter on RST_TH and OV_TH Terminals (C9, C10)
These capacitors may be required in some applications to filter the noise on RST_TH and OV_TH pins. Typical
capacitor values for RST_TH and OV_TH pins are from 10 pF to 100 pF for total resistance on RST_TH/OV_TH
divider of less than 200 kΩ. See Noise Filter on RST_TH and OV_TH Terminals.
8.2.2.2 Design Example 1
For this example, we will start with the following known and target parameters:
Table 7. Design Parameters – Example 1(1)
PARAMETER TYPE
PARAMETER NAME
PARAMETER VALUE
Minimum = 8 V, Maximum = 28
V, Typical = 14 V
Known
Input voltage, VIN
Output voltage, VReg
Maximum output current, ILoad-Max
5 V ± 2%
1.8 A
Ripple/ transient occurring in input voltage, ΔVIN
Reset threshold, VReg_RST
1% of VIN (minimum)
92% of VReg
106% of VReg
95% of VReg
5% of VReg
Target
Overvoltage threshold, VReg_OV
Undervoltage threshold, VReg_UV
Transient response 0.25 A to 2-A load step, ΔVReg
Power-on Reset delay, PORdly
2.2 ms
(1) For the circuit diagram, see Figure 26.
8.2.2.2.1 Calculate the Switching Frequency (fsw
)
To reduce the size of output inductor and capacitor, higher switching frequency can be selected. It is important to
understand that higher switching frequency results in higher switching losses, causing the device to heat up. This
may result in degraded thermal performance. To prevent this, proper PCB layout guidelines must be followed
(see Layout Guidelines).
30
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Based upon the discussion in section Selecting the Switching Frequency, calculate the maximum and minimum
duty cycle.
Knowing VReg and tolerance on VReg, the VReg-Max and VReg-Min are calculated to be:
VReg-Max = 102% of VReg = 5.1 V and VReg-Min = 98% of VReg = 4.9 V.
Using Equation 3, the minimum duty cycle is calculated to be, DMin = 17.5%
Knowing: tON-Min = 150 ns from the device specifications, and using Equation 4, maximum switching frequency is
calculated to be, fsw-Max = 1166 kHz
Because the oscillator can also vary by ±10%, the switching frequency can be further reduced by 10% to add
margin. Also, to improve efficiency and reduce power losses due to switching, the switching frequency can be
further reduced by about 550 kHz. Therefore, fsw = 500 kHz.
From Figure 10, R8 can be approximately determined to be, R8 = 205 kΩ.
8.2.2.2.2 Calculate the Ripple Current (IRipple
)
Using Equation 32, for KIND = 0.2 (typical), inductor ripple current is calculated to be: IRipple = 0.36 A.
The ripple current is chosen such that the converter enters discontinuous mode (DCM) at 20% of maximum load.
The 20% is a typical value, it could go higher to a maximum of up to 40%.
8.2.2.2.3 Calculate the Inductor Value (L1)
Using Equation 33, the inductor value is calculated to be, LMin = 22.8 µH. A closest standard inductor value can
be used.
8.2.2.2.4 Calculate the Output Capacitor and ESR (C4)
8.2.2.2.4.1 Calculate Capacitance
To calculate the capacitance of the output capacitor, first determine the minimum load current. Typically, in
standby mode the load current is 100 µA; however, this really depends on the application. With this value of
minimum load current and using Equation 27, Equation 28, and Equation 29, C4 is calculated to be, C4 > 34 µF .
To allow wider operating conditions and improved performance in low-power mode, TI recommends using a 100-
µF capacitor. A higher value of the output capacitor allows improved transient response during load stepping.
8.2.2.2.4.2 Calculate ESR
Using Equation 30, ESR is calculated to be, RESR < 555 mΩ.
Capacitors with lowest ESR values should be selected. To meet both the requirements, capacitance and low
ESR, several low ESR capacitors may be connected in parallel. In this example, we will select a capacitor with
ESR value as 30 mΩ.
Filter capacitor (C12) of value 0.1 µF can be added to filter out the noise in the output line.
8.2.2.2.5 Calculate the Feedback Resistors (R4, R5)
To keep the quiescent current low and avoid instability problems, TI recommends selecting R4 and R5 such that,
R4 + R5 is approximately 250 kΩ.
Using Equation 1 and using a fixed standard value of R4 = 187 kΩ, R5 is calculated to be, R5 = 35.7 kΩ .
8.2.2.2.6 Calculate Type 3 Compensation Components
8.2.2.2.6.1 Resistances (R6, R9)
Using Equation 16, for VINTyp = 14 V, VRamp is calculated to be, VRamp = 1.4 V.
Using Equation 12, fLC is calculated to be, fLC = 3.33 kHz.
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Using VRamp, fLC from above, assuming fc as 1/10th of fsw and Equation 38, R6 is calculated to be,
R6 = 280.65 kΩ.
Using Equation 39, R9 is calculated to be, R9 = 2.53 kΩ.
8.2.2.2.6.2 Capacitors (C5, C8, C7)
Using Equation 40, C5 is calculated to be, C5 = 340.45 pF.
Using Equation 13, fESR is calculated to be, fESR = 53.06 kHz.
Using Equation 42, C8 is calculated to be, C8 = 11.04 pF.
Using Equation 41, C7 is calculated to be, C7 = 250.07 pF.
8.2.2.2.7 Calculate Soft-Start Capacitor (C6)
The recommended value of soft-start capacitor is 100 nF (typical).
8.2.2.2.8 Calculate Bootstrap Capacitor (C3)
The recommended value of bootstrap capacitor is 0.1 µF (typical).
8.2.2.2.9 Calculate Power-On Reset Delay Capacitor (C2)
To achieve 2.2-ms delay, the reset delay capacitor can be calculated using Equation 6 to be C2 = 2.2 nF.
8.2.2.2.10 Calculate Input Capacitor (C1, C11)
Typical values for C11 are 0.1 µF and 0.01 µF.
Input capacitor (C1) should be rated more than the maximum input voltage (VINMax). The input capacitor should
be big enough to maintain supply in case of transients in the input line. Using Equation 26, C1 is calculated to
be, C1 = 1.2 µF. For improved transient response, TI recommends a higher value of C1 such as 220 µF.
8.2.2.2.11 Calculate Resistors to Control Slew Rate (R7)
The value of slew rate resistor (R7) can be approximately determined from Figure 11 and Figure 12 at different
typical input voltages. The minimum recommended value is 10 kΩ. To achieve rise time, tr = 20 ns and fall time,
tf = 35 ns, the slew rate resistor is approximately of value 30 kΩ.
8.2.2.2.12 Resistors to Select Undervoltage, Overvoltage and Reset Threshold Values (R1, R2, R3)
The sum of these three resistors should be approximately equal to 100 kΩ. In this example,
•
•
•
VReg_OV = 106% of VReg = 5.3 V
VReg_RST = 92% of VReg = 4.6 V
VReg_UV = 95% of VReg = 4.75 V
Using Equation 9, R3 = 15 kΩ.
Using Equation 8, R2 = 2.29 kΩ.
Using Equation 7, R1 = 82.6 kΩ
8.2.2.2.13 Diode D1 and D2 Selection
Diode D1 is used to protect the IC from the reverse input polarity connection. The diode should be rated at
maximum load current. Only Schottky diode should be connected at the PH pin. The recommended part numbers
are PDS360 and SBR8U60P5.
8.2.2.2.14 Noise Filter on RST_TH and OV_TH Terminals (C9 and C10)
Typical capacitor values for RST_TH and OV_TH pins are from 10 pF to 100 pF for total resistance on RST_TH/
OV_TH divider of less than 200 kΩ.
32
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8.2.2.2.15 Power Budget and Temperature Estimation
Using Equation 43, conduction losses for typical input voltage are calculated to be, PCON = 0.289 W.
Assuming slew resistance R7 = 30 kΩ, from Figure 11 and Figure 12, rise time, tr = 20 ns and fall time, tf = 35
ns. Using Equation 44, switching losses for typical input voltage are calculated to be, PSW = 0.693 W.
Using Equation 45, gate drive losses are calculated to be, PGate = 3 mW.
Using Equation 46, power supply losses are calculated to be, PIC = 1.8 mW.
Using Equation 47, the total power dissipated by the device is calculated to be, PTotal = 987 mW.
Using Equation 49, and knowing the thermal resistance of package = 35°C/W, the rise in junction temperature
due to power dissipation is calculated to be, ∆T = 34.5°C.
Using Equation 50, for a given maximum junction temperature 150°C, the maximum ambient temperature at
which the device can be operated is calculated to be, TA-Max = 115°C (approximately).
8.2.2.3 Design Example 2
For this example, start with the following known and target parameters:
Table 8. Design Parameters – Example 2(1)
PARAMETER TYPE
PARAMETER NAME
PARAMETER VALUE
Minimum = 8 V, Maximum = 28
V, Typical = 14 V
Known
Input voltage, VIN
Output voltage, VReg
Maximum output current, ILoad-Max
3.3 V ± 2%
2 A
Ripple/ transient occurring in input voltage, ΔVIN
Reset threshold, VReg_RST
1% of VIN (minimum)
92% of VReg
106% of VReg
95% of VReg
5% of VReg
Target
Overvoltage threshold, VReg_OV
Undervoltage threshold, VReg_UV
Transient response 0.25-A to 2-A load step, ΔVReg
Power on Reset delay, PORdly
2.2 ms
(1) For the circuit diagram, see Figure 26.
8.2.2.3.1 Calculate the Switching Frequency (fsw
)
To reduce the size of output inductor and capacitor, higher switching frequency can be selected. It is important to
understand that higher switching frequency results in higher switching losses, causing the device to heat up. This
may result in degraded thermal performance. To prevent this, proper PCB layout guidelines must be followed
(see Layout Guidelines).
Based upon the discussion in section Selecting the Switching Frequency, calculate the maximum and minimum
duty cycle.
Knowing VReg and tolerance on VReg, the VReg-Max and VReg-Min are calculated to be:
VReg-Max = 102% of VReg = 3.366 V and VReg-Min = 98% of VReg = 3.234 V.
Using Equation 3, the minimum duty cycle is calculated to be, DMin = 11.55%
Knowing tON-Min = 150 ns from the device specifications, and using Equation 4, maximum switching frequency is
calculated to be, fsw-Max = 770 kHz.
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Because the oscillator can also vary by ±10%, the switching frequency can be further reduced by 10% to add
margin. Also, to improve efficiency and reduce power losses due to switching, the switching frequency can be
further reduced by about 100 kHz. Therefore fsw = 593 kHz.
From Figure 10, R8 can be approximately determined to be, R8 = 170 kΩ.
8.2.2.3.2 Calculate the Ripple Current (IRipple
)
Using Equation 32, for KIND = 0.2 (typical), inductor ripple current is calculated to be: IRipple = 0.4 A.
The ripple current is chosen such that the converter enters discontinuous mode (DCM) at 20% of maximum load.
The 20% is a typical value, although it could go higher to a maximum of up to 40%.
8.2.2.3.3 Calculate the Inductor Value (L1)
Using Equation 33, the inductor value is calculated to be, LMin = 12.3 µH. A closest standard inductor value can
be used.
8.2.2.3.4 Calculate the Output Capacitor and ESR (C4, C12)
8.2.2.3.4.1 Calculate Capacitance
To calculate the capacitance of the output capacitor, minimum load current must be first determined. Typically, in
standby mode the load current is 100 µA; however, this really depends on the application. With this value of
minimum load current and using Equation 27, Equation 28, and Equation 29, C4 is calculated to be, C4 > 56 µF .
To allow wider operating conditions and improved performance in low-power mode, TI recommends using a 100-
µF capacitor. An output capacitor with a higher value allows improved transient response during load stepping.
8.2.2.3.4.2 Calculate ESR
Using Equation 30, ESR is calculated to be, RESR < 330 mΩ.
Capacitors with lowest ESR values should be selected. To meet both the requirements, capacitance and low
ESR, several low ESR capacitors may be connected in parallel. In this example, we will select a capacitor with
ESR value as 30 mΩ.
Filter capacitor (C12) of value 0.1 µF can be added to filter out the noise in the output line.
8.2.2.3.5 Calculate the Feedback Resistors (R4, R5)
To keep the quiescent current low and avoid instability problems, TI recommends selecting R4 and R5 such that,
R4 + R5 is approximately 250 kΩ.
Using Equation 1 and using a fixed standard value of R4 = 187 kΩ, R5 is calculated to be, R5 = 59.8 kΩ .
8.2.2.3.6 Calculate Type 3 Compensation Components
8.2.2.3.6.1 Resistances (R6, R9)
Using Equation 16, for VINTyp = 14 V, VRamp is calculated to be, VRamp = 1.4 V.
Using Equation 12, fLC is calculated to be, fLC = 4.54 kHz.
Using VRamp, fLC from above, assuming fc as 1/10th of fsw and Equation 38, R6 is calculated to be, R6 = 244 kΩ.
Using Equation 39, R9 is calculated to be, R9 = 2.9 kΩ.
8.2.2.3.6.2 Capacitors (C5, C8, C7)
Using Equation 40, C5 is calculated to be, C5 = 287.04 pF.
Using Equation 13, fESR is calculated to be, fESR = 53.06 kHz.
34
Copyright © 2016, Texas Instruments Incorporated
TPS54262-EP
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ZHCSFU3 –DECEMBER 2016
Using Equation 42, C8 is calculated to be, C8 = 12.84 pF.
Using Equation 41, C7 is calculated to be, C7 = 184.4 pF.
8.2.2.3.7 Calculate Soft-Start Capacitor (C6)
The recommended value of soft-start capacitor is 100 nF (typical).
8.2.2.3.8 Calculate Bootstrap Capacitor (C3)
The recommended value of bootstrap capacitor is 0.1 µF (typical).
8.2.2.3.9 Calculate Power-On Reset Delay Capacitor (C2)
To achieve 2.2-ms delay, the reset delay capacitor can be calculated using Equation 6 to be C2 = 2.2 nF.
8.2.2.3.10 Calculate Input Capacitor (C1, C11)
Typical values for C11 are 0.1 µF and 0.01 µF.
Input capacitor (C1) should be rated more than the maximum input voltage (VINMax). The input capacitor should
be big enough to maintain supply in case of transients in the input line. Using Equation 26, C1 is calculated to
be, C1 = 10.53 µF. For improved transient response, TI recommends a higher value of C1 such as 220 µF.
8.2.2.3.11 Calculate Resistors to Control Slew Rate (R7)
The value of slew rate resistor (R7) can be approximately determined from Figure 11 and Figure 12 at different
typical input voltages. The minimum recommended value is 10 kΩ. To achieve rise time, tr = 20 ns and fall time,
tf = 35 ns, the slew rate resistor is approximately of value 30 kΩ.
8.2.2.3.12 Resistors to Select Undervoltage, Overvoltage and Reset Threshold Values (R1, R2, R3)
The sum of these three resistors should be approximately equal to 100 kΩ. In this example,
VReg_OV = 106% of VReg = 3.498 V
VReg_RST = 92% of VReg = 3.036 V
VReg_UV = 95% of VReg = 3.135 V
Using Equation 9, R3 = 22.87 kΩ.
Using Equation 8, R2 = 3.48 kΩ.
Using Equation 7, R1 = 73.65 kΩ
8.2.2.3.13 Diode D1 and D2 Selection
Diode D1 is used to protect the IC from the reverse input polarity connection. The diode should be rated at
maximum load current. Only Schottky diode should be connected at the PH pin. The recommended part numbers
are PDS360 and SBR8U60P5.
8.2.2.3.14 Noise Filter on RST_TH and OV_TH Terminals (C9 and C10)
Typical capacitor values for RST_TH and OV_TH pins are from 10 pF to 100 pF for total resistance on RST_TH/
OV_TH divider of less than 200 kΩ.
8.2.2.3.15 Power Budget and Temperature Estimation
Using Equation 43, conduction losses for typical input voltage are calculated to be, PCON = 0.235 W.
Assuming slew resistance R7 = 30 kΩ, from Figure 17 and Figure 18, rise time, tr = 20 ns and fall time, tf = 35
ns. Using Equation 19, switching losses for typical input voltage are calculated to be, PSW = 0.913 W.
Using Equation 44, gate drive losses are calculated to be, PGate = 3.5 mW.
Using Equation 46, power supply losses are calculated to be, PIC = 1.8 mW.
Copyright © 2016, Texas Instruments Incorporated
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TPS54262-EP
ZHCSFU3 –DECEMBER 2016
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Using Equation 47, the total power dissipated by the device is calculated to be, PTotal = 1.15 W.
Using Equation 49, and knowing the thermal resistance of package = 35°C/W, the rise in junction temperature
due to power dissipation is calculated to be, ∆T = 40.4°C.
Using Equation 50, for a given maximum junction temperature 150°C, the maximum ambient temperature at
which the device can be operated is calculated to be, TA-Max approximately 105°C.
8.2.3 Application Curves
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
Rslew = 14 kW
Rslew = 30 kW
VIN = 7 V
VIN = 14 V
-10
-0.5
0
0.5
1
1.5
2
-0.5
0
0.5
1
1.5
2
Load Current (A)
Load Current (A)
D003
D004
Figure 27. Efficiency vs Load Current for Different Rslew
Resistors
Figure 28. Efficiency vs Load Current for Different VIN
36
Copyright © 2016, Texas Instruments Incorporated
TPS54262-EP
www.ti.com.cn
ZHCSFU3 –DECEMBER 2016
9 Power Supply Recommendations
The design of the TPS54262-EP devices is for operation using an input supply range from 3.6 V to 48 V. Both
the VIN input pins must be shorted together at the board level. One high frequency filter capacitor in the range
from 0.1 uF to 0.01 uF is recommended at VIN pin. Additionally, to minimize the ripple voltage, use a ceramic
bulk capacitor of type X5R or X7R at the VIN pin. See Equation 25 and Equation 26 for calculating the value of
this bulk capacitor. If there is a possibility for a reverse-voltage condition to occur, place a series Schottky diode
in the power routing.
Copyright © 2016, Texas Instruments Incorporated
37
TPS54262-EP
ZHCSFU3 –DECEMBER 2016
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
A proper layout is critical for the operation of a switched-mode power supply, even more at high switching
frequencies. Therefore, the PCB layout of the TPS54262-EP device demands careful attention to ensure
operation and to get the performance specified. A poor layout can lead to issues like poor regulation (line and
load), stability and accuracy weaknesses, increased EMI radiation, and noise sensitivity. See Figure 29 for
recommended layout example for TPS54262-EP device.
•
•
•
It is critical to provide a low-inductance, low-impedance ground path and hence use wide and short traces for
the main current paths.
The input capacitor, catch diode, output capacitor, and inductor should be placed as close as possible to the
IC pins and use thick traces (low impedance path) to connect them.
Route the feedback trace so that there is minimum interaction with any noise sources associated with the
switching components. Recommended practice is to place the inductor away from the feedback trace to
prevent EMI noise.
•
•
Place compensation network components away from switching components and route their connections away
from noisy area.
In a two-sided PCB, TI recommends having ground planes on both sides of the PCB to help reduce noise and
ground-loop errors. Connect the ground connection for the input and output capacitors and IC ground to this
ground plane.
•
•
•
In a multilayer PCB, the ground plane separates the power plane (where high switching currents and
components are placed) from the signal plane (where the feedback trace and components are) for improved
performance.
Also, arrange the components such that the switching-current loops curl in the same direction. Place the high-
current components such that during conduction the current path is in the same direction. Doing so prevents
magnetic field reversal caused by the traces between the two half cycles, helping to reduce radiated EMI.
Add multiple thermal via's on the device thermal pad for better thermal performance.
10.2 Layout Example
Output
Capacitor
Topside Supply Area
Input Capacitor
Ground
Plane
Output
Inductor
Catch Diode
NC
NC
BOOT
VIN
VIN
SYNC
LPM
EN
PH
VReg
Compensation Network
Supervisor Network
RT
COMP
VSENSE
RST_TH
OV_TH
SS
Rslew
RST
Resistor
Divider
Cdly
GND
Signal via to
Ground Plane
Topside Ground Area
Thermal Via
Signal Via
Figure 29. PCB Layout Example
38
Copyright © 2016, Texas Instruments Incorporated
TPS54262-EP
www.ti.com.cn
ZHCSFU3 –DECEMBER 2016
10.3 Power Dissipation and Temperature Considerations
The power dissipation losses are applicable for continuous conduction mode operation (CCM). The total power
dissipated by the device is the sum of the following power losses.
Conduction losses, PCON
VReg
PCON = IL2oad ´RDS(ON)
´
VIN
(43)
Switching losses, PSW
1
PSW
=
VIN´ILoad´(tr + tf )´ fSW
2
(44)
(45)
(46)
Gate drive losses, PGate
PGate = Vdrive × Qg × fsw
Power supply losses, PIC
PIC = VIN × Iq-Normal
Therefore, the total power dissipated by the device is given by Equation 47.
PTotal = PCON + PSW + PGate + PIC
where
•
•
•
•
•
•
•
•
VIN = unregulated input voltage
ILoad = output load current
tr = FET switching rise time (tr= 40 ns (maximum))
tf = FET switching fall time
fsw = switching frequency
Vdrive = FET gate drive voltage (Vdrive = 6 V (typical), Vdrive = 8 V (maximum))
Qg = 1×10–9
C
Iq-Normal = quiescent current in normal mode (Active Mode CCM)
(47)
For device under operation at a given ambient temperature (TA), the junction temperature (TJ) can be calculated
using Equation 48.
TJ = TA + (Rth × PTotal
)
(48)
Therefore, the rise in junction temperature due to power dissipation is shown in Equation 49.
ΔT = TJ – TA = (Rth × PTotal
)
(49)
For a given maximum junction temperature (TJ-Max), the maximum ambient temperature (TA-Max) in which the
device can operate is calculated using Equation 50.
TA-Max = TJ-Max – (Rth × PTotal
)
where
•
•
•
•
•
TJ = junction temperature in °C
TA = ambient temperature in °C
Rth = thermal resistance of package in W/°C
TJ-Max = maximum junction temperature in °C
TA-Max = maximum ambient temperature in °C
(50)
There are several other factors that also affect the overall efficiency and power losses. Examples of such factors
are AC and DC losses in the inductor, voltage drop across the copper traces on PCB, power losses in the
flyback catch diode and so forth. The previous discussion does not include such factors.
Copyright © 2016, Texas Instruments Incorporated
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TPS54262-EP
ZHCSFU3 –DECEMBER 2016
www.ti.com.cn
Power Dissipation and Temperature Considerations (continued)
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
-55
-40
-20
0
20
40
60
80
100
120
140 150
Temperture (°C)
Figure 30. Power Dissipation vs Ambient Temperature
NOTE
The output current rating for the regulator may must be derated for ambient temperatures
above 85°C. The derated value will depend on calculated worst-case power dissipation
and the thermal management implementation in the application.
40
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TPS54262-EP
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ZHCSFU3 –DECEMBER 2016
11 器件和文档支持
11.1 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
42
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Copyright © 2017 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS54262MPWPREP
TPS54262MPWPTEP
V62/16626-01XE
ACTIVE
ACTIVE
ACTIVE
HTSSOP
HTSSOP
HTSSOP
PWP
PWP
PWP
20
20
20
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-55 to 125
-55 to 125
-55 to 125
54262M1
250
250
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
54262M1
54262M1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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