TPS54262QPWPRQ1 [TI]
2-A 60-V STEP-DOWN DC/DC CONVERTER WITH LOW QUIESCENT CURRENT; 2 -A 60 -V降压型DC / DC具有低静态电流转换器
| 型号： | TPS54262QPWPRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2-A 60-V STEP-DOWN DC/DC CONVERTER WITH LOW QUIESCENT CURRENT |
| 文件： | 总44页 (文件大小：2608K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS54262-Q1
www.ti.com
SLVS996C –SEPTEMBER 2009–REVISED JUNE 2010
2-A 60-V STEP-DOWN DC/DC CONVERTER WITH LOW QUIESCENT CURRENT
Check for Samples: TPS54262-Q1
1
FEATURES
•
Asynchronous Switch Mode Regulator
•
Programmable Overvoltage, Undervoltage
Output Monitor
•
3.6 V to 48 V Operating Range, Withstands
Transients up to 60 V
•
•
•
Thermal Sensing and Shutdown
Switch Current Limit Protection
•
•
•
•
•
•
•
•
•
•
•
2 A Maximum Load Current
50 µA Typical Quiescent Current
Short Circuit and Overcurrent Protection of
FET
200 kHz to 2.2 MHz Switching Frequency
0.8 V ± 1.5% Voltage Reference
•
•
Junction Temperature Range: –40°C to 150°C
20-Pin HTSSOP PowerPAD™ Package
High Voltage Tolerant Enable Input
Soft Start on Enable Cycle
APPLICATIONS
Slew Rate Control on Internal Power Switch
Low-Power Mode for Light Load Conditions
Programmable Delay for Power-On Reset
External Compensation for Error Amplifier
•
•
•
•
•
Qualified for Automotive Applications
Automotive Telematics
Navigation Systems
In-Dash Instrumentation
Reset Function Filter Time for Fast Negative
Transients
Battery Powered Applications
DESCRIPTION
The TPS54262 is a step-down switch-mode power supply with a voltage supervisor and an integrated NMOS
switching FET. Integrated input voltage line feed forward topology improves line transient regulation of the
voltage mode buck regulator. The regulator has a cycle-by-cycle current limit. The device also features
low-power mode operation under light load conditions which reduces the supply current to 50 µA (typical). By
pulling the EN pin low, the supply shutdown current is reduced to 1 µA (typical).
An open drain reset signal indicates when the nominal output drops below the reset threshold set by an external
resistor divider network. The output voltage start up ramp is controlled by a soft start capacitor. There is an
internal undervoltage shut down which is activated when the input supply ramps down to 2.6 V. The device is
protected during an overload condition on output by frequency foldback operation, and also has a thermal
shutdown protection.
TYPICAL APPLICATION
TYPICAL CONVERTER EFFICIENCY
D1
TPS54262
VReg
VIN
VIN
EN
VBATT
R12
C1
R11
R10
RESET
RST
BOOT
L
C3
D2
VReg
C4
PH
LPM
C7
SYNC
R4
R5
R7
C6
R9
Rslew
VSENSE
SS
C8
C5
R6
R8
C2
COMP
RT/CLK
R1
R2
R3
RST_TH
Cdly
GND
OV_TH
Figure 1.
Figure 2.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
TPS54262-Q1
SLVS996C –SEPTEMBER 2009–REVISED JUNE 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
TJ
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
–40°C to 150°C
TSSOP – PWP Reel of 2000
TPS54262QPWPRQ1
54262Q1
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS(1)
VALUE
-0.3 to 60
-0.3 to 60
-0.3 to 20
-0.3 to 5.5
-0.3 to 5.5
-0.3 to 5.5
-0.3 to 5.5
-0.3 to 5.5
-0.3 to 65
-0.3 to 60
-2 for 30ns
-1 for 200ns
-0.85 at TJ= -40°C
-0.5 at TJ= 125°C
-0.3 to 5.5
-0.3 to 5.5
-0.3 to 8
UNIT
Input voltage
EN
V
VIN
VReg
LPM
OV_TH
RST_TH
SYNC
VSENSE
BOOT
PH
Output voltage
V
RT
RST
Cdly
SS
-0.3 to 8
COMP
-0.3 to 7
Temperature
Operating virtual junction temperature range, TJ
Storage temperature range, TS
-40 to 150
-55 to 165
2
°C
kV
Electrostatic discharge (HBM)(2)
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages
are with respect to ground.
(2) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
2
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SLVS996C –SEPTEMBER 2009–REVISED JUNE 2010
RECOMMENDED OPERATING CONDITIONS
MIN
3.6
MAX UNIT
VI
Unregulated buck supply input voltage (VIN, EN)
In continuous conduction mode (CCM)
48
18
V
V
0.9
VReg
Regulated output voltage
Power up in low-power mode (LPM) or discontinuous conduction
mode (DCM)
0.9
5.5
V
Bootstrap capacitor (BOOT)
Switched outputs (PH)
3.6
3.6
0
56
48
V
V
V
V
Logic levels (RST, VSENSE, OV_TH, RST_TH, Rslew, SYNC, RT)
5.25
6.5
Logic levels (SS, Cdly, COMP)
0
qJA
qJC
TJ
Thermal resistance, junction to ambient(1)
Thermal resistance, junction to case(2)
Operating junction temperature(3)
35 °C/W
10 °C/W
–40
150
°C
(1) This assumes a JEDEC JESD 51-5 standard board with thermal vias with High K profile – See PowerPAD section and application note
from Texas Instruments (SLMA002) for more information.
(2) This assumes junction to exposed thermal pad.
(3) This assumes TA = TJ – power dissipation × qJA
.
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MAX UNIT
DC ELECTRICAL CHARACTERISTICS
VIN = 7 V to 48 V, EN = VIN, TJ = –40°C to 150°C (unless otherwise noted)
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
INPUT POWER SUPPLY
Normal mode: after initial start up
3.6
48
V
V
Falling threshold
(LPM disabled)
8
8.5
31
Info
PT
VIN
Supply voltage on VIN
Rising threshold
(LPM activated)
Low-power mode
V
V
High voltage threshold
(LPM disabled)
29
34
10
Quiescent current,
normal mode
Open loop test – maximum duty cycle
VIN = 7 V to 48 V
Iq-Normal
5
mA
TA = 25°C
50
70
75
75
75
4
µA
µA
µA
µA
µA
ILoad < 1 mA, VIN = 12 V
–40 < TJ < 150°C
Quiescent current,
low-power mode
PT
PT
Iq-LPM
TA = 25°C
ILoad < 1 mA, VIN = 24 V
EN = 0 V, device is off
–40 < TJ < 150°C
TA = 25°C, VIN = 12 V
ISD
Shutdown current
1
TRANSITION TIMES (LOW POWER – NORMAL MODES)
Transition delay, normal
mode to low-power mode
CT
CT
td1
td2
VIN = 12 V, VReg = 5 V, ILoad = 1 A to 1 mA
100
5
µs
µs
Transition delay, low-power
mode to normal mode
VIN = 12 V, VReg = 5 V ILoad = 1 mA to 1 A
SWITCH MODE SUPPLY; VReg
Info
CT
PT
VReg
Regulator output
VSENSE = 0.8 Vref
0.9
18
V
V
VSENSE
RDS(ON)
Feedback voltage
VReg = 0.9 V to 18 V (open loop)
Measured across VIN and PH, ILoad = 500 mA
0.788
0.8 0.812
Internal switch resistance
500 mΩ
Switch current limit, cycle by
cycle
Info
ICL
VIN = 12 V
2.5
3.2
4.1
A
Info
Info
PT
tON-Min
tOFF-Min
fsw
Duty cycle pulse width
Bench CHAR only
50
100
0.2
100
200
150
250
ns
Bench CHAR only
Switching frequency
Set using external resistor on RT pin
2.2 MHz
PT
Internal oscillator frequency
tolerance
fsw
–10
10
%
Info
Info
ISink
ILimit
Start-up condition
Prevent overshoot
OV_TH = 0 V, VReg = 10 V
1
mA
mA
0 V < OV_TH < 0.8 V, VReg = 10 V
80
PT: Production tested
CT: Characterization tested only, not production tested
Info: User information only, not production tested
4
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SLVS996C –SEPTEMBER 2009–REVISED JUNE 2010
DC ELECTRICAL CHARACTERISTICS
VIN = 7 V to 48 V, EN = VIN, TJ = –40°C to 150°C (unless otherwise noted)
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ENABLE (EN)
PT
PT
VIL
VIH
Low input threshold voltage
High input threshold voltage
0.7
V
V
1.7
EN = 60 V
EN = 12 V
100
8
135
15
µA
µA
PT
Ilkg
Leakage current into EN terminal
RESET DELAY (Cdly)
PT
PT
IO
External capacitor charge current
Switching threshold voltage
EN = high
1.4
1.7
2
2
2.6
µA
V
VThreshold
Output voltage in regulation
LOW-POWER MODE (LPM)
PT
PT
PT
VIL
VIH
Ilkg
Low input threshold voltage
High input threshold voltage
Leakage current into LPM terminal
VIN = 12 V
VIN = 12 V
LPM = 5 V
0.7
95
V
V
65
µA
RESET OUTPUT (RST)
PT
PT
PT
trdly
POR delay timer
Based on Cdly capacitor
Check RST output
3.6
0.768
10
7
0.832
35
ms/nF
V
VReg_RST
tnRSTdly
Reset threshold voltage for VReg
Filter time
Delay before RST is asserted low
20
50
µs
SOFT START (SS)
PT ISS
Soft-start source current
40
60
0.7
95
µA
SYNCHRONIZATION (SYNC)
PT
PT
PT
VIL
VIH
Ilkg
Low input threshold voltage
High input threshold voltage
Leakage current
V
V
1.7
SYNC = 5 V
65
µA
VIN = 12 V, VReg = 5 V,
180 kHz < fsw < fext < 2 × fsw < 2.2 MHz
CT
SYNC (fext
SYNCtrans
SYNCtrans
)
External input clock frequency
External clock to internal clock
Internal clock to external clock
180
2200 kHz
Info
Info
No external clock, VIN = 12 V, VReg = 5 V
32
µs
µs
%
External clock = 1 MHz, VIN = 12 V,
VReg = 5 V
2.5
CT
SYNCCLK
SYNCCLK
Minimum duty cycle
Maximum duty cycle
30
CT
70
%
Rslew
CT
IRslew
IRslew
Rslew = 50 kΩ
Rslew = 10 kΩ
20
µA
µA
CT
100
OVERVOLTAGE SUPERVISORS (OV_TH)
Threshold voltage for VReg during
Internal switch is turned off
0.768
0.832
V
overvoltage
PT
VReg_OV
VReg = 5 V
Internal pulldown on VReg, OV_TH = 1 V
70(1)
mA
THERMAL SHUTDOWN
Thermal shutdown junction
temperature
CT
CT
TSD
175
30
°C
°C
THYS
Hysteresis
PT: Production tested
CT: Characterization tested only, not production tested
(1) This is the current flowing into the VReg pin when voltage at OV_TH pin is 1 V.
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DEVICE INFORMATION
PWP PACKAGE
(TOP VIEW)
1
20
19
18
17
16
15
14
13
12
11
NC
NC
BOOT
VIN
VIN
2
3
SYNC
LPM
EN
4
PH
VReg
5
6
RT
Rslew
COMP
7
VSENSE
RST_TH
OV_TH
8
RST
Cdly
9
10
GND
SS
Figure 3.
TERMINAL FUNCTIONS
NAME
NO.
1
I/O
NC
NC
DESCRIPTION
NC
NC
Connect to ground.
Connect to ground.
2
External synchronization clock input to override the internal oscillator clock. An internal pull down
resistor of 62kΩ (typical) is connected to ground.
SYNC
LPM
3
4
I
I
Low-power mode control using digital input signal. An internal pull down resistor of 62kΩ (typical) is
connected to ground.
EN
5
6
7
I
Enable pin, internally pulled up. Must be externally pulled up or down to enable/ disable the device.
External resistor to ground to program the internal oscillator frequency.
RT
O
O
Rslew
External resistor to ground to control the slew rate of internal switching FET.
Active low, open drain reset output connected to external bias voltage through a resistor, asserted high
after the device starts regulating.
RST
Cdly
GND
SS
8
O
O
O
O
I
9
External capacitor to ground to program power on reset delay.
Ground pin, must be electrically connected to the exposed pad on the PCB for proper thermal
performance.
10
11
12
External capacitor to ground to program soft start time.
Sense input for overvoltage detection on regulated output, an external resistor network is connected
between VReg and ground to program the overvoltage threshold.
OV_TH
Sense input for undervoltage detection on regulated output, an external resistor network is connected
between VReg and ground to program the reset and undervoltage threshold.
RST_TH
13
I
VSENSE
COMP
VReg
PH
14
15
16
17
18
19
20
I
O
I
Inverting node of error amplifier for voltage mode control.
Error amplifier output to connect external compensation components.
Internal low-side FET to load output during startup or limit overshoot.
Source of the internal switching FET.
O
I
VIN
Unregulated input voltage. Pin 18 and pin 19 must be connected externally.
Unregulated input voltage. Pin 18 and pin 19 must be connected externally.
External bootstrap capacitor to PH to drive the gate of the internal switching FET.
VIN
I
BOOT
O
6
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SLVS996C –SEPTEMBER 2009–REVISED JUNE 2010
FUNCTIONAL BLOCK DIAGRAM
BOOT
20
Rslew
7
Bandgap
ref
LPM
VIN
0.8 V ref
0.2 V ref
4
R7
D1
Internal
supply
Internal
Voltage
Rail
19
VIN
18
VBATT
16
R11
VReg
C3
C1
Gate Drive with
Over-Current Limit
for Internal Switch
5
L
R10
EN
RT
PH
VReg
17
Selectable
Oscillator
Thermal
Sensor
6
D2
C4
C7
R9
R8
ref
Error
amp
-
R4
R5
VSENSE
SS
SYNC
Cdly
3
9
14
11
+
C5
C8
0.8 V ref
C6
C2
Vreg
15
COMP
R6
+
-
0.82 V ref
R12
+
-
R1
R2
0.8 V ref
RST_ TH
8
13
RST
C10
Voltage
comp
OV_ TH
Reset with
Delay Timer
-
12
GND
+
R3
10
0.8 V ref
C9
Figure 4.
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TYPICAL CHARACTERISTICS
Efficiency Data of Power Supply
FET SWITCHING
FAST SLEW RATE ON SWITCHING FET
Figure 5.
Figure 6.
LPM, QUIESCENT CURRENT VARIATION
WITH TEMPERATURE
SHUTDOWN CURRENT VARIATION
WITH TEMPERATURE
Figure 7.
Figure 8.
8
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TYPICAL CHARACTERISTICS (continued)
Output Voltage Drop Out
VReg DROP OUT
OUTPUT VOLTAGE TRACKING
Figure 9.
Figure 10.
NOTE
•
•
Power up (Start up): This curve shows the input voltage required to achieve the 5 V regulation
during power up over the range of load currents (see Figure 10).
Power down (Tracking): This curve shows the input voltage at which the output voltage drops
approximately by 0.7 V from the programmed 5 V regulated voltage (see Figure 10) or for low
input voltages (tracking function) over the range of load currents (see Figure 9).
•
In Figure 5 and Figure 6, L and C are output inductor and capacitor respectively.
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TYPICAL CHARACTERISTICS (continued)
VOLTAGE DROP ON Rslew FOR CURRENT REFERENCE;
(SLEW RATE / Rslew)
INTERNAL REFERENCE VOLTAGE
Figure 11.
Figure 12.
CURRENT CONSUMPTION WITH TEMPERATURE
Figure 13.
10
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OVERVIEW
The TPS54262 is a 60 V, 2 A DC/DC step down (buck) converter using voltage-control mode scheme. The
device features supervisory function for power-on-reset during system power on. Once the output voltage has
exceeded the threshold set by RST_TH pin, a delay of 1 ms/nF (based on capacitor value on Cdly terminal) is
invoked before the RST line is released high. Conversely on power down, once the output voltage falls below the
same set threshold, the RST line is pulled low only after a de-glitch filter of approximately 20 µs (typical) expires.
This is implemented to prevent reset from being triggered due to fast transient line noise on the regulated output
supply.
An overvoltage monitor function, is used to limit regulated output voltage to the threshold set by OV_TH pin. Both
the RST_TH and OV_TH monitoring voltages are set to be a pre-scale of the output voltage, and thresholds
based on the internal bias voltages of the voltage comparators (0.8 V typical).
Detection of undervoltage on the regulated output is based on the RST_TH setting and will invoke RST line to be
asserted low. Detection of overvoltage on the output is based on the OV_TH setting and will not invoke the RST
line to be asserted low. However, the internal switch is commanded to turn OFF.
In systems where power consumption is critical, low-power mode (LPM) is implemented to reduce the
non-switching quiescent current during light load conditions. After the device has been operating in discontinuous
conduction mode (DCM) for at least 100 µs (typ), depending upon the load current, it may enter in pulse skip
mode (PSM). The operation of when the device enters DCM is dependent on the selection of the external
components.
If thermal shutdown is invoked due to excessive power dissipation, the internal switch is disabled and the
regulated output voltage starts to decrease. Depending on the load current, the regulated output voltage could
decay and the RST_TH threshold may assert the RST output low.
DETAILED DESCRIPTION
The TPS54262 is a DC/DC converter using a voltage-control mode scheme with an input voltage feed-forward
technique. The device can be programmed for a range of output voltages with a wide input voltage range. Below
are details with regard to setting up the device, detailed functionality and the modes of operation.
Unregulated Input Voltage
The input voltage is supplied through VIN pins (pin 18 and 19) which must be externally protected against
voltage levels greater than 60 V and reverse input polarity. An external diode is connected to protect these pins
from reverse input polarity. The input current drawn from this pin is pulsed, with fast rise and fall times.
Therefore, this input line requires a filter capacitor to minimize noise. Additionally, for EMI considerations, an
input filter inductor may also be required.
NOTE
For design considerations, VIN/VReg ratios should always be set such that the minimum
required duty cycle pulse (tON-Min) is greater than 150 ns. The minimum off time (tOFF-Min) is
250 ns for all conditions.
Regulated Output Voltage
The regulated output voltage (VReg) is fed back to the device through VReg pin (pin 16). Typically, an output
capacitor of value within range of 10 µF to 400 µF is connected at this pin. It is also recommended to use a filter
capacitor with low ESR characteristics to minimize ripple in regulated output voltage. The VReg pin is also
internally connected to a load of ~100 Ω, which is turned ON in the following conditions:
•
During startup condition, when the device is powered up with no-load, or whenever EN is toggled, the internal
load connected to VReg pin is turned ON to charge the bootstrap capacitor to provide gate drive voltage to
the switching transistor.
•
During normal operating conditions, when the regulated output voltage (VReg) exceeds the overvoltage
threshold (VReg_OV, preset by external resistors R1, R2, and R3), the internal load is turned ON, and this
pin is pulled down to bring the regulated output voltage down.
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•
•
When VIN is less than typical VIN falling threshold level while LPM is disabled. From device specifications,
VIN typical falling threshold (LPM disabled) = 8 V (see DC Electrical Characteristics).
When RST is low.
Regulation/Feedback Voltage
The regulated output voltage (VReg) can be programmed by connecting external resistor network at VSENSE pin
(pin 14). The output voltage is selectable between 0.9 V to 18 V according to the following relationship:
(1)
Where,
R4, R5 = feedback resistors (see Figure 4)
Vref = 0.8 V (typical)
The overall tolerance of the regulated output voltage is given by Equation 2.
(2)
Where,
tolVref = tolerance of internal reference voltage (tolVref = ± 1.5%)
tolR4,tolR5 = tolerance of feedback resistors R4, R5
For a tighter tolerance on VReg, lower-value feedback resistors can be selected. However, for proper
operation in low-power mode (see Modes of Operation), it is recommended to keep R4 + R5 around 250 kΩ
(typical).
The output tracking depends upon the loading conditions and is explained in Table 1 and is shown in Figure 10.
Table 1. Load Conditions
LOAD CONDITION
Nominal load in CCM
OUTPUT TRACKING
VReg tracks VIN approximately as: VReg = 95% (VIN – ILoad × 0.5)
To enable the tracking feature, following conditions should be met:
1) fSW < 600 kHz
No load/light load in LPM
2) VReg < 8 V, typical (related to VIN falling threshold when LPM is disabled)
Modes of Operation
TPS54262 operates in the following modes based on the output loading conditions, input voltage and LPM pin
configuration. These operating conditions and modes of operations are shown in Figure 14.
Heavy Loading
LPM Pin = Don’t care
Active Mode CCM
Light Loading
LPM Pin = High
Active Mode DCM
PSM + DCM
Very Light Loading
LPM Pin = High
Light/ Very Light Loading
LPM Pin = Low
LPM
V when
tOFF<tOFF-Min
V when
tON<tON-Min
~8.5 V
~32 V
VIN
Figure 14. Modes of Operation
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1) Active Mode Continuous Conduction Mode (CCM)
In this mode of operation the switcher operates in continuous conduction mode, and the inductor current is
always non-zero if the total load current (internal and external) is greater than IL_DISCONT shown in Equation 3.
(1-D)×V
=
Reg
I =I
L_DISCONT L_LPM
2×f ×L
sw
(3)
Where,
D = duty cycle
L = output inductor
VReg = output voltage
fsw = switching frequency
For VIN < 8.5 V, the device enables an internal ~100 Ω load. This, combined with the external load, can cause
the device to enter into CCM even under light external loading conditions (see Figure 14). This mode of
operation is shown in Figure 15 is also called the Normal mode of operation.
Figure 15. Active Mode CCM
Figure 16. Active Mode DCM
2) Active Mode Discontinuous Conduction Mode (DCM)
In this mode of operation the switcher operates in discontinuous conduction mode, and the inductor current
becomes zero if the total load current (internal and external) is less than IL_DISCONT shown in Equation 4.
(1-D)×V
=
Reg
I =I
L_DISCONT L_LPM
2×f ×L
sw
(4)
The device enters in this mode of operation when LPM pin is set high (i.e disabled) and output loading is less
than IL_DISCONT. This mode of operation is shown in Figure 16.
3) Pulse Skip Mode (PSM)
In this mode of operation the switcher operates in discontinuous conduction mode, and the inductor current
becomes zero. The device enters in this mode of operation in the following conditions:
•
At low input voltages when VReg starts losing regulation and the OFF time (tOFF) of the switching FET tends to
be close to or slightly less than the minimum OFF time (tOFF-Min). If OFF time is much smaller than tOFF-Min
,
there is a risk that the part stops switching and regulation is lost until power is re-cycled with OFF time
greater than tOFF-Min. This mode of operation is shown in Figure 18. Comparing Figure 17 and Figure 18,
pulse skipping occurs in Figure 18 but not in Figure 17 under similar output loading conditions.
V
æ
ç
ç
è
ö
1
Reg
÷
VIN-I ´R
Load DS(ON)
<~V
Reg
1-
´
>t
OFF-Min
and
÷
VIN
f
sw
ø
(5)
13
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Figure 17. Active Mode CCM
Figure 18. PSM at Low VIN
•
•
Likewise, at higher input voltages when the ON time (tON) of the switching FET becomes close to or slightly
less than the minimum ON time (tON-Min) and the VReg start losing regulation, the device enters in PSM. If ON
time is much smaller than tON-Min, there is a risk that the part stops switching and regulation is lost until power
is re-cycled with ON time greater than tON-Min
.
At nominal input voltages during very light output loading. This mode of operation is shown in Figure 19.
Comparing Figure 16 and Figure 19, in both cases the device is operating in discontinuous conduction mode;
however, pulse skipping happens in Figure 19 because of very light output loading for similar input voltage.
LPM pin must be set high (i.e., disabled) for this to happen.
Figure 19. PSM at Nominal VIN
4) Low Power Mode (LPM)
In this mode of operation the device briefly operates in discontinuous conduction mode and then turns off until
VReg < VReg_UV threshold and this cycle is repeated. The LPM pin must be enabled to enable LPM mode of
operation. When total load is less than IL_DISCONT, the device operates in LPM for VIN ~8.5 V to ~32 V. This
mode of operation is shown in Figure 20 and Figure 21 (zoomed out).
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Figure 20. Low Power Mode
Figure 21. Low Power Mode (Zoom In)
Any transition from low-power mode to active mode CCM occurs within 5 µs (typical). In low-power mode, the
converter operates as a hysteretic controller with the threshold limits set by VReg_UV (see Equation 10, Figure 4
and Figure 22), for the lower limit and ~VReg for the upper limit. To ensure tight regulation in the low-power mode,
R2 and R3 values are set accordingly (see discussion on Noise Filter on RST_TH and OV_TH Terminals). The
device operates in both automatic (LPM pin is connected to ground) and digitally controlled (status of LPM pin is
controlled by an external device, for example by a microcontroller) low-power mode. The digital low-power mode
can over-ride the automatic low-power mode function by applying the appropriate signal on the LPM terminal.
The part goes into active mode CCM for at least 100 µs, whenever RST_TH or VReg_UV is tripped.
Table 2. LPM Pin Status
LPM PIN STATUS
MODES OF OPERATION
Device is forced in normal mode.
At light loads, the device operates in DCM with a switching frequency determined by the
external resistor connected to RT pin.
High
At very light loads, the device operates in PSM with a reduced switching frequency (see
Figure 14).
Device automatically changes between normal mode and low-power mode depending on the
load current.
Low or open
Table 3. Modes of Operation
MODES OF OPERATION
DESCRIPTION
All circuits including overvoltage threshold circuit (OV_TH) are enabled.
At heavy loads, the device operates in continuous conduction mode irrespective of the status
of LPM pin.
OR
Normal mode (active mode)
At light loads, the device operates in discontinuous conduction mode (DCM) only if LPM pin
is externally set high.
OV_TH circuit is disabled.
The device is in DCM, and LPM pin should be forced low.
Low-power mode
When the device is operating in low-power mode, and if the output is shorted to ground, a reset is asserted. The
thermal shutdown and current limiting circuitry is activated to protect the device. The LPM pin is active low and is
internally pulled down; therefore, the low-power mode is automatically enabled unless this pin is driven high
externally (for example, by a microcontroller) and the device is in continuous conduction mode. However, the
low-power mode operation is initiated only when the device enters discontinuous mode of operation at light
loads, and the LPM pin is low (or connected to ground).
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5) Hysteretic Mode
The device enters in this mode of operation when the main loop fails to respond during line/ load transients and
regulate within specified tolerances. The device exits this mode of operation when the main control loop
responds, after the error amplifier stabilizes, and controls the output voltage within tighter tolerance.
The power up conditions in different modes of operations are explained in Table 4.
Table 4. Power-Up Conditions
MODE OF OPERATION
CCM
POWER-UP CONDITIONS
VIN > 3.6 V (minimum)
LPM/DCM
VReg < 5.5 V and (VIN - VReg) > 2.5 V (applicable only for fsw > 600 kHz)
Output Tolerances in Different Modes of Operation
Figure 22.
Table 5.
MODE OF OPERATION
Hysteretic mode
VReg LOWER LIMIT
VReg_UV
VReg UPPER LIMIT
VReg_OV
COMMENTS
Minimum to maximum ripple on output
Minimum to maximum ripple on output
Minimum to maximum ripple on output
Low-power mode
VReg_UV
VReg + tolVReg
VReg + tolVReg
Active mode (Normal)
VReg – tolVReg
Table 6.
SUPERVISOR
THRESHOLDS
VReg TYPICAL
VALUE
TOLERANCE
COMMENTS
VReg_OV
Overvoltage threshold setting
Reset threshold setting
VReg_RST
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Enable and Shutdown
The EN pin (pin 5) provides electrical ON/OFF control of the regulator. Once the EN pin voltage exceeds the
upper threshold voltage (VIH), the regulator starts operating and the internal soft start begins to ramp. If the EN
pin voltage is pulled below the lower threshold voltage (VIL), the regulator stops switching and the internal soft
start resets. Connecting this pin to ground or to any voltage less than VIL disables the regulator and causes the
device to shut down. This pin must have an external pullup or pulldown to change the state of the device.
Soft Start
An external soft start capacitor is connected to SS pin (pin 11) to set the minimum time to reach the desired
regulated output voltage (VReg) during power up cycle. This prevents the output voltage from overshooting when
the device is powered up. This is also useful when the load requires a controlled voltage slew rate, and also
helps to limit the current drawn from the input voltage supply line.
For proper operation, the following conditions must be satisfied during power-up and after a short circuit event:
•
•
VIN – VReg > 2.5 V
Load current < 1 A, until RSTgoes high
The current limit foldback is released after the feedback voltage (at VSENSE pin) is high enough such that RST
is asserted high. The recommended value of soft start capacitor is 100 nF (typical) for startup load current of 1 A
(maximum).
Oscillator Frequency
The oscillator frequency can be set by connecting an external resistor (R8 in Figure 4) to RT pin (pin 6) .
Figure 23 shows the relation between the resistor value (RT) and switching frequency (fsw). The switching
frequency can be set in the range 200 kHz to 2200 kHz. In addition, the switching frequency can be imposed
externally by a clock signal (fext) at the SYNC pin.
Selecting the Switching Frequency
A power supply switching at a higher switching frequency allows use of lower value inductor and smaller output
capacitor compared to a power supply that switches at a lower frequency. Typically, the user will want to choose
the highest switching frequency possible since this will produce the smallest solution size. The switching
frequency that can be selected is limited by the following factors:
•
•
•
•
The input voltage
The minimum target regulated voltage
Minimum on-time of the internal switching transistor
Frequency shift limitation
Selecting lower switching frequency results in using an inductor and capacitor of a larger value, where as
selecting higher switching frequency results in higher switching and gate drive power losses. Therefore, a
tradeoff has to be made between physical size of the power supply and the power dissipation at the system/
application level.
The minimum and maximum duty cycles can be expressed in terms of input and output voltage as shown in
Equation 6.
(6)
Where,
DMin = minimum duty cycle
DMax = maximum duty cycle
VINMin = minimum input voltage
VINMax = maximum input voltage
VReg-Min = minimum regulated output voltage
VReg-Max = maximum regulated output voltage
From Equation 6, maximum switching frequency can be calculated in Equation 7.
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(7)
Where,
fsw-Max = maximum switching frequency
tON-Min = minimum on-time of the NMOS switching transistor
Knowing the switching frequency, the value of resistor to be connected at RT pin can be calculated using the
graph shown in Figure 23.
Figure 23. Switching Frequency vs Resistor Value
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Synchronization With External Clock
An external clock signal can be supplied to the device through SYNC pin (pin 3) to synchronize the internal
oscillator frequency with an external clock frequency. The synchronization input overrides the internal fixed
oscillator signal. The synchronization signal has to be valid for approximately two clock cycles before the
transition is made for synchronization with the external frequency input. If the external clock input does not
transition low or high for 32 µs (typical), the system defaults to the internal clock set by the resistor connected to
the RT pin. The SYNC input can have a frequency according to Equation 8.
180 kHz < fsw < fext < 2 × fsw < 2.2 MHz
(8)
(8)
Where,
fsw = oscillator frequency determined by resistor connected to the RT pin
fext = frequency of the external clock fed through SYNC pin
For example, if the resistor connected at RT pin is selected such that the switching frequency (fsw) is 500 kHz,
then the external clock can have a frequency (fext) between 500 kHz and 1000 kHz. But, if the resistor connected
at RT pin is selected such that the switching frequency (fsw) is 1500 kHz, then the external clock can have a
frequency (fext) between 1500 kHz and 2200 kHz only.
If the external clock gets struck for less than 32 µs, the NMOS switching FET is turned off and the output voltage
starts decreasing. Depending upon the load conditions, the output voltage may hit the under voltage threshold
and reset threshold before the external clock appears. The NMOS switching FET stays OFF until the external
clock appears again. If the output voltage hits the reset threshold, the RST pin is asserted low after a deglitch
time of 20 µs (typical).
If the external clock gets struck for more than 32 µs, the NMOS switching FET is turned off and the output
voltage starts decreasing. Under this condition the default internal oscillator clock set by RT pin overrides the
external after 32 µs and the NMOS switching FET resumes switching. When the external clock appears again
(such that 180 kHz < fsw < fext < 2 × fsw < 2.2 MHz), the NMOS switching FET starts switching at the frequency
determined by the external clock.
Slew Rate Control
The slew rate of the NMOS switching FET can be set by using an external resistor (R7 in Figure 4). The range of
rise times and fall times for different values of slew resistor are shown in Figure 24 and Figure 25.
Figure 24. FET Rise Time
Figure 25. FET Fall Time
Reset
The RST pin (pin 8) is an open drain output pin used to indicate external digital devices/ loads if the device has
powered up to a programmed regulated output voltage properly. This pin is asserted low until the regulated
output voltage (VReg) exceeds the programed reset threshold (VREG_RST, see Equation 11) and the reset delay
timer (set by Cdly pin) has expired. Additionally, whenever the EN pin is low or open, RST is immediately
asserted low regardless of the output voltage. There is a reset filter timer to prevent reset being invoked due to
short negative transients on the output line. If thermal shut down occurs due to excessive thermal conditions, this
pin is asserted low when the switching FET is commanded OFF and the output falls below the reset threshold.
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Power On Condition/ Reset Line
Power Down Condition/ Reset Line
VIN
VIN
Css
Css
VReg_RST
VReg
VReg_RST
VReg
Cdly
Cdly
RST
t
delay
RST
20 ms
(Typ-Deglitch Time)
Figure 26.
Figure 27.
Reset Delay
The delay time to assert the RST pin high after the supply has exceeded the programmed VReg_RST voltage
(see Equation 11 to calculate VReg_RST) can be set by external capacitor (C2 in Figure 4) connected to the
Cdly pin (pin 9). The delay may be programmed in the range of 2.2 ms to 200 ms using a capacitor in the range
of 2.2 nF to 200 nF. The delay time is calculated using Equation 9:
(9)
Where,
C = capacitor on Cdly pin
Reset Threshold and Undervoltage Threshold
The undervoltage threshold (VReg_UV) level for proper regulation in low-power mode and the reset threshold
level (VReg_RST) to initiate a reset output signal can be programmed by connecting an external resistor string to
the RST_TH pin (pin 13). The resistor combination of R1, R2, and R3 is used to program the threshold for
detection of undervoltage. Voltage bias on R2 + R3 sets the reset threshold.
Undervoltage threshold for transient and low-power mode operation is given by the Equation 10. The
recommended range for VReg_UV is 73% to 95% of VReg
.
(10)
(11)
Reset threshold is given by Equation 11. The recommended range for VReg_RST is 70% to 92% of VReg
.
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Overvoltage Supervisor
The overvoltage monitoring of the regulated output voltage, VReg can be achieved by connecting an external
resistor string to the OV_TH pin (pin 12). The resistor combination of R1, R2, and R3 is used to program the
threshold for detection of overvoltage. The bias voltage of R3 sets the overvoltage threshold and the accuracy of
regulated output voltage in hysteretic mode during transient events.
(12)
Recommended range for VReg_OV is 106% to 110% of VReg
.
Noise Filter on RST_TH and OV_TH Terminals
External capacitors may be required to filter the noise added to RST_TH and OV_TH terminals. The noise is
more pronounced with fast falling edges on the PH pin. Therefore, selecting a smaller Rslew resistor (R7 in
Figure 4) for a higher slew rate will require more external capacitance to filter the noise.
The RC time constant depends on external components (R2, R3, C9 and C10 in Figure 4) connected to RST_TH
and OV_TH pins. For proper noise filtering, improved loop transient response and better short circuit protection,
Equation 13 must be satisfied.
(R2 + R3) × (C9 + C10) < 2 µs
(13)
(13)
To meet this requirement, it is recommended to use lower values of external capacitors and resistors. The value
of the time constant is also affected by the PCB capacitance and the application setup. Therefore, in some cases
the external capacitors (C9, C10) on RST_TH and OV_TH terminals may not be required. Users can place a
footprint on the application PCB and only populate it if necessary. Also, the external resistors (R1, R2, R3)
should be sized appropriately to minimize any significant effect of board leakage.
For most cases, it is recommended to keep the external capacitors (either from board capacitance or by
connecting external capacitors) between 10 pF to 100 pF; therefore, to meet time constant requirement in
Equation 13, the total external resistance (R1 + R2 + R3) should be less than 200 kΩ.
Boost Capacitor
An external boot strap capacitor (C3 in Figure 4) is connected to pin 20 to provide the gate drive voltage for the
internal NMOS switching FET. X7R or X5R grade dielectrics are recommended due to their stable values over
temperature. The capacitor value may need to be adjusted higher for high VReg and/or low frequencies
applications (e.g., 100 nF for 500 kHz/5 V and 220 nF for 500 kHz/8 V).
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Loop Control Frequency Compensation
Figure 28. Type 3 Compensation
Type 3 Compensation
Type 3 compensation has been used in the feedback loop to improve the stability of the convertor and regulation
in the output in response to the changes in input voltage or load conditions. This becomes important because the
ceramic capacitors used to filter the output have a low Equivalent Series Resistance (ESR). Type 3
compensation is implemented by connecting external resistors and capacitors to the COMP pin (output of the
error amplifier, pin 15) of the device as shown in Figure 28.
The crossover frequency should be less than 1/5th to 1/10th of the switching frequency, and should be greater
than five times the double pole frequency of the LC filter.
fc < fsw × (0.1 to 0.2)
(14)
(14)
Where,
fsw = switching frequency
The modulator break frequencies as a function of the output LC filter are derived from Equation 15 and
Equation 16. The LC output filter gives a double pole that has a –180° phase shift.
1
fLC
=
2pÖLC
(15)
Where,
L = output inductor
C = output capacitor (C4 in functional block diagram)
The ESR of the output capacitor C gives a "ZERO" that has a 90° phase shift.
1
fESR
=
2pC × ESR
(16)
(17)
Where,
ESR = Equivalent series resistance of a capacitor at a specified frequency
The regulated output voltage, VReg is given by Equation 17.
R4
R5
VReg = Vref
1 +
VReg
(18)
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For VIN = 8 V to 50 V, the VIN/Vramp modulator gain is approximately 10 and has a tolerance of about 20%.
VIN
Vramp
Gain = Amod
=
= 10
(19)
(20)
Therefore,
Also, Vramp is fixed for the following range of VIN. Vramp = 1 V for VIN < 8 V, and Vramp = 5 V for VIN > 48 V.
The frequencies for poles and zeros are given by following equations.
(C5 + C8)
fp1 =
2p ´ R6 ´ (C5 ´ C8)
(21)
(22)
(23)
(24)
1
fp2 =
2π × R9 × C7
1
fz1 =
2π × R6 × C5
Guidelines for selecting compensation components selection are provided in the Application Information section
of this document.
Bode Plot of Converter Gain
Open Loop Error
Amp Gain
f
f
Z1 Z2
f
f
P1 P2
20 log R6(R4+R9)/(R4*R9)
20 log (R6/R4)
20 log (10)
Modulator Gain
Compensation
Gain
Closed Loop Gain
f
f
f
C
LC
ESR
f - Frequency - Hz
Figure 29.
Short-Circuit Protection
The TPS54262 features an output short-circuit protection. Short-circuit conditions are detected by monitoring the
RST_TH pin, and when the voltage on this node drops below 0.2 V, the switching frequency is decreased and
current limit is folded back to protect the device. The switching frequency is folded back to approximately 25 kHz
and the current limit is reduced to 30% of the typical current limit value.
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Thermal Shutdown (TSD)
The TPS54262 protects itself from overheating with an internal thermal shutdown (TSD) circuit. If the junction
temperature exceeds the thermal shutdown trip point, the NMOS switching FET is turned off. The device is
automatically restarted under the control of soft-start circuit when the junction temperature drops below the
thermal shutdown hysteretic trip point. During low-power mode operation, the thermal shutdown sensing circuitry
is disabled for reduced current consumption. If VReg drops below VReg_UV, thermal shutdown monitoring is
activated.
Overcurrent Protection
The device features overcurrent protection to protect it from load currents greater than 2 A. Overcurrent
protection is implemented by sensing the current through the NMOS switching FET. The sensed current is
compared to a current reference level representing the overcurrent threshold limit (ICL). If the sensed current
exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The system will ignore the
overcurrent indicator for the leading edge blanking time at the beginning of each cycle to avoid any turn-on noise
glitches.
Once overcurrent indicator is set true, overcurrent protection is triggered. The NMOS switching FET is turned off
for the rest of the cycle after a propagation delay. The overcurrent protection scheme is called cycle-by-cycle
current limiting. If the sensed current continues to increase during cycle-by-cycle current limiting, the temperature
of the part will start rising, the TSD will kick in and shut down switching until the part cools down.
Internal Undervoltage Lockout (UVLO)
This device is enabled on power up once the internal bandgap and bias currents are stable; this happens
typically at VIN = 3.4 V (minimum). On power down, the internal circuitry is disabled at VIN = 2.6 V (maximum).
Power Dissipation and Temperature Considerations
The power dissipation losses are applicable for continuous conduction mode operation (CCM). The total power
dissipated by the device is the sum of the following power losses.
Conduction losses, PCON
(25)
Switching losses, PSW
(26)
Gate drive losses, PGate
PGate = Vdrive × Qg × fsw
Power supply losses, PIC
PIC = VIN × Iq-Normal
(27)
(27)
(28)
(29)
(28)
Therefore, the total power dissipated by the device is given by Equation 29.
PTotal = PCON + PSW + PGate + PIC
(29)
Where,
VIN = unregulated input voltage
ILoad = output load current
tr = FET switching rise time (tr= 40 ns (maximum))
tf = FET switching fall time
fsw = switching frequency
Vdrive = FET gate drive voltage (Vdrive = 6 V (typical), Vdrive = 8 V (maximum))
Qg = 1×10-9
C
Iq-Normal = quiescent current in normal mode (Active Mode CCM)
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For device under operation at a given ambient temperature (TA), the junction temperature (TJ) can be calculated
using Equation 30.
TJ = TA + (Rth × PTotal
)
(30)
(30)
Therefore, the rise in junction temperature due to power dissipation is shown in Equation 31.
ΔT = TJ – TA = (Rth × PTotal
)
(31)
(31)
For a given maximum junction temperature (TJ-Max), the maximum ambient temperature (TA-Max) in which the
device can operate is calculated using Equation 32.
TA-Max = TJ-Max – (Rth × PTotal
)
(32)
(32)
Where,
TJ = junction temperature in °C
TA = ambient temperature in °C
Rth = thermal resistance of package in W/°C
TJ-Max = maximum junction temperature in °C
TA-Max = maximum ambient temperature in °C
There are several other factors that also affect the overall efficiency and power losses. Examples of such factors
are AC and DC losses in the inductor, voltage drop across the copper traces on PCB, power losses in the
flyback catch diode etc. Above discussion does not include such factors.
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
-40
-20
0
20
40
60
80
100
120
140
Ambient Temperture (°C)
Figure 30. Power Dissipation vs Ambient Temperature
NOTE
The output current rating for the regulator may have to be derated for ambient
temperatures above 85°C. The derated value will depend on calculated worst-case power
dissipation and the thermal management implementation in the application.
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APPLICATION INFORMATION
These guidelines address the following topics in detail for TPS54262-Q1.
1. Component selection
2. Design example
3. PCB layout guidelines
Component Selection
This section explains considerations for the external components selection. The following schematic shows the
interconnection between external components and the device for a typical DC/DC step down application.
D1
VIN
C11
C1
+
VBATT
C3
1
2
20
19
18
17
16
15
14
13
12
11
GND
GND
GND
GND
NC
BOOT
VIN
GND
NC
VReg
VReg
3
L1
SYNC
LPM
EN
VIN
R11
R10
4
PH
D2
R9
C7
5
VReg
VREG
COMP
VSENSE
RST_TH
OV_TH
SS
GND
C12
C4
+
R8
C5
6
GND
GND
RT
VOUT
R4
R7
7
RSLEW
RST
CDLY
AGND
C8
R6
R12
C2
8
VReg
VReg
GND
GND
R1
9
GND
10
GND
C6
R5
R2
R3
C10
GND
GND
GND
GND
C9
GND
GND
Figure 31. Typical Application Schematic
1) Input Capacitors (C1, C11)
Input filter capacitor (C11) is used to filter out high frequency noise in the input line. Typical values of C11 are
0.1µF to 0.01µF. For higher frequency noise, low capacitor values are recommended.
To minimize the ripple voltage, input ceramic de-coupling capacitor (C1) of type X5R or X7R should be used.
The DC voltage rating for the input decoupling capacitor must be greater than the maximum input voltage. This
capacitor must have an input ripple current rating higher than the maximum input ripple current of the converter
for the application; and is determined by Equation 33.
(33)
The input capacitors for power regulators are chosen to have a reasonable capacitance-to-volume ratio and fairly
stable over temperature. The value of the input capacitance also determines the input ripple voltage of the
regulator, shown by Equation 34.
(34)
Input ceramic filter capacitors should be located in close proximity to the VIN terminal. Surface mount capacitors
are recommended to minimize lead length and reduce noise coupling.
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2) Output Capacitor (C4, C12)
The selection of the output capacitor will determine several parameters in the operation of the converter, for
example voltage drop on the output capacitor and the output ripple. The capacitor value also determines the
modulator pole and the roll-off frequency due to the LC output filter double pole. This is expressed in
Equation 15.
The minimum capacitance needed to maintain desired output voltage during high to low load transition and
prevent over shoot is given by Equation 35.
2
L × (ILoad-Max2 – ILoad-Min
)
C4 =
2
VReg-Max2 – VReg-Min
(35)
Where,
L = output inductor
ILoad-Max = maximum load current
ILoad-Min = minimum load current
VReg-Max = maximum tolerance of regulated output voltage
VReg-Min = minimum tolerance of regulated output voltage
During a load step from no load to full load or changes in the input voltage, the output capacitor must hold up the
output voltage above a certain level for a specified time and not issue a reset, until the main regulator control
loop responds to the change. The minimum output capacitance required to allow sufficient drop on the output
voltage without issuing a reset is determined by Equation 36.
(36)
Where,
ΔVReg = transient response during load stepping
The minimum capacitance needed for output voltage ripple specification is given by Equation 37.
(37)
Additional capacitance de-ratings for temperature, aging, and DC bias have to be factored in, and so a value of
100 µF with ESR calculated using Equation 38 of less than 100 mΩ should be used on the output stage.
Maximum ESR of the output capacitor is based on output ripple voltage specification in Equation 38 . The output
ripple voltage is a product of the output capacitor ESR and ripple current.
(38)
Output capacitor root mean square (RMS) ripple current is given by Equation 39. This is to prevent excess
heating or failure due to high ripple currents. This parameter is sometimes specified by the manufacturers.
VReg (VINMax – VReg
)
ILoad-RMS
=
Ö12 × VINMax × fsw × L1
(39)
Filter capacitor (C12) of value 0.1 µF (typical) is used to filter out the noise in the output line.
3) Soft-Start Capacitor (C6)
The soft start capacitor determines the minimum time to reach the desired output voltage during a power up
cycle. This is useful when a load requires a controlled voltage slew rate, and helps to limit the current draw from
the input voltage supply line. A 100 nF capacitor is recommended for startup loads of 1A (max.).
4) Bootstrap Capacitor (C3)
A 0.1µF ceramic capacitor must be connected between the PH and BOOT terminals for the converter to operate
and regulate to the desired output voltage. It is recommended to use a capacitor with X5R or better grade
dielectric material, and the voltage rating on this capacitor of at least 25V to allow for derating.
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5) Power-On Reset Delay (PORdly) Capacitor (C2)
The value of this capacitor can be calculated using Equation 9.
6) Output Inductor (L1)
Use a low EMI inductor with a ferrite type shielded core. Other types of inductors may be used; however, they
must have low EMI characteristics and should be located away from the low-power traces and components in the
circuit.
To calculate the minimum value of the inductor, the ripple current should be first calculated using Equation 40.
IRipple = KIND × ILoad
(40)
(40)
Where,
ILoad = maximum output load current
IRipple = allowable peak to peak inductor ripple current, typ. 20% of maximum ILoad
KIND = coefficient that represents the amount of inductor ripple current relative to the maximum output
current. Since, the inductor ripple current is filtered by the output capacitor; therefore KIND is typically in the
range of 0.2 to 0.3, depending on the ESR and the ripple current rating of the output capacitor (C4).
The minimum value of output inductor can be calculated using Equation 41.
(VINMax – VReg) × VReg
LMin
=
fsw × IRipple × VINMax
(41)
Where,
VINMax = maximum input voltage
VReg = regulated output voltage
fsw = switching frequency
The RMS and peak currents flowing in the inductor are given by Equation 42 and Equation 43.
2
IRipple
2
IL,RMS
=
ILoad
+
12
(42)
(43)
IRipple
IL,pk = ILoad
+
2
7) Flyback Schottky Diode (D2)
The TPS54262 requires an external Schottky diode connected between the PH and power ground termination.
The absolute voltage at PH pin should not go beyond the values in Absolute Maximum Ratings. The Schottky
diode conducts the output current during the off state of the internal power switch. This Schottky diode must have
a reverse breakdown voltage higher than the maximum input voltage of the application. A Schottky diode is
selected for its lower forward voltage. The Schottky diode is selected based on the appropriate power rating,
which factors in the DC conduction losses and the AC losses due to the high switching frequencies; this is
determined by Equation 44.
(VINMax – VReg) × ILoad × Vfd
(VIN – Vfd) × fsw × CJ
Pdiode
=
+
VINMax
2
(44)
Where,
Pdiode = power rating
Vfd = forward conducting voltage of Schottky diode
CJ = junction capacitance of the Schottky diode
Recommended part numbers are PDS 360 and SBR8U60P5.
8) Resistor to Set Slew Rate (R7)
The slew rate setting is asymmetrical; i.e., for a selected value of R7, the rise time and fall time are different. R7
can be approximately determined from Figure 24 and Figure 25. The minimum recommended value is 10 kΩ.
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9) Resistor to Select Switching Frequency (R8)
Please refer to the section Selecting Switching Frequency, Figure 23 and Equation 7.
10) Resistors to Select Output Voltage (R4, R5)
To minimize the effect of leakage current on the VSENSE terminal, the current flowing through the feedback
network should be greater than 5 mA to maintain output accuracy. Higher resistor values help improve the
converter efficiency at low output currents, but may introduce noise immunity problems. Please refer to
Equation 1. It is recommended to fix R4 to a standard value (say 187 kΩ) and calculate R5.
11) Resistors to Set Undervoltage, Overvoltage, and Reset Thresholds (R1, R2, R3)
Overvoltage resistor selection
Using Equation 12, the value of R3 can be determined to set the overvoltage threshold at up to 106% to 110% of
VReg. The sum of R1, R2, and R3 resistor network to ground should be is approximately 100 kΩ .
Reset threshold resistor selection
Using Equation 11 the value of R2 + R3 can be calculated, and knowing R3 from the OV_TH setting, R2 can be
determined. Suggested value of reset threshold is 92% of VReg
.
Undervoltage threshold for low-power mode and load transient operation
This threshold is set above the reset threshold to ensure the regulator operates within the specified tolerances
during output load transient of low load to high load and during discontinuous conduction mode. The typical
voltage threshold can be determined using Equation 10. Suggested value of undervoltage threshold is 95% of
VReg
.
Low-Power Mode (LPM) Threshold
An approximation of the output load current at which the converter is operating in discontinuous mode can be
obtained from Equation 4 with ± 30% hysteresis. The values used in Equation 6 for minimum and maximum input
voltage will affect the duty cycle and the overall discontinuous mode load current. These are the nominal values,
and other factors are not taken into consideration like external component variations with temperature and aging.
12) Pullup Resistor for Enable (R12)
An external pull resistor of 30.1 kΩ is recommended to enable the device for operation.
13) Type 3 Compensation Components (R5, R6, R9, C5, C7, C8)
First, make the 'ZEROs' close to double pole frequency, using Equation 15, Equation 16, and Equation 14.
fz1 = (50% to 70%) fLC
fz2 = fLC
Second, make the 'POLEs' above the crossover frequency, using Equation 21 and Equation 22.
fp1 = fESR
fp2 = ½fsw
Resistors
From Equation 1, knowing VReg and R4 (fix to a standard value), R5 can be calculated as shown in Equation 45:
(45)
Using Equation 14 and Equation 18, R6 can be calculated as shown in Equation 46:
(46)
R9 can be calculated as shown in Equation 47:
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(47)
Capacitors
Using Equation 23, C5 can be calculated as shown in Equation 48:
(48)
(49)
(50)
C7 can be calculated as shown in Equation 49:
C8 can be calculated as shown in Equation 50:
14) Noise Filter on RST_TH and OV_TH Terminals (C9, C10)
These capacitors may be required in some applications to filter the noise on RST_TH and OV_TH pins. Typical
capacitor values for RST_TH and OV_TH pins are between 10 pF to 100 pF for total resistance on
RST_TH/OV_TH divider of less than 200 kΩ. See discussion on Noise Filter on RST_TH and OV_TH Terminals.
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DESIGN EXAMPLE
The following examples demonstrate the design of a high frequency switching regulator using ceramic output
capacitors. A few parameters must be known to start the design process. These parameters are typically
determined at the system level.
Example 1
For this example, we will start with the following known and target parameters:
Table 7.
Known
Target
Input voltage, VIN
Output voltage, VReg
Minimum = 8 V, Maximum = 28 V, Typical = 14 V
5 V ± 2%
1.8 A
Maximum output current, ILoad-Max
Ripple/ transient occurring in input voltage, ΔVIN
Reset threshold, VReg_RST
1% of VIN (minimum)
92% of VReg
106% of VReg
95% of VReg
5% of VReg
Overvoltage threshold, VReg_OV
Undervoltage threshold, VReg_UV
Transient response 0.25 A to 2 A load step, ΔVReg
Power on reset delay, PORdly
2.2 ms
Step 1. Calculate the Switching Frequency (fsw
)
To reduce the size of output inductor and capacitor, higher switching frequency can be selected. It is important to
understand that higher switching frequency will result in higher switching losses, causing the device to heat up.
This may result in degraded thermal performance. To prevent this, proper PCB layout guidelines must be
followed (explained in the later section of this document).
Based upon the discussion in section Selecting the Switching Frequency, calculate the maximum and minimum
duty cycle.
Knowing VReg and tolerance on VReg, the VReg-Max and VReg-Min are calculated to be:
VReg-Max = 102% of VReg = 5.1 V and VReg-Min = 98% of VReg = 4.9 V.
Using Equation 6, the minimum duty cycle is calculated to be, DMin = 17.5%
Knowing tON-Min = 150 ns from the device specifications, and using Equation 7, maximum switching frequency is
calculated to be, fsw-Max = 1166 kHz.
Since the oscillator can also vary by ±10%, the switching frequency can be further reduced by 10% to add
margin. Also, to improve efficiency and reduce power losses due to switching, the switching frequency can be
further reduced by about 550 kHz. Therefore fsw = 500 kHz.
From Figure 23, R8 can be approximately determined to be, R8 = 205 kΩ.
Step 2. Calculate the Ripple Current (IRipple
)
Using Equation 40, for KIND = 0.2 (typical), inductor ripple current is calculated to be: IRipple = 0.36 A.
The ripple current is chosen such that the converter enters discontinuous mode (DCM) at 20% of max load. The
20% is a typical value, it could go higher to a maximum of up to 40%.
Step 3. Calculate the Inductor Value (L1)
Using Equation 41, the inductor value is calculated to be, LMin = 22.8 µH. A closest standard inductor value can
be used.
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Step 4. Calculate the Output Capacitor and ESR (C4)
Calculate capacitance
To calculate the capacitance of the output capacitor, minimum load current must be first determined. Typically, in
standby mode the load current is 100 µA, however this really depends on the application. With this value of
minimum load current and using Equation 35, Equation 36, and Equation 37, C4 is calculated to be, C4 > 34 µF .
To allow wider operating conditions and improved performance in low-power mode it is recommended to use a
100 µF capacitor. Higher value of output capacitor allows improved transient response during load stepping.
Calculate ESR
Using Equation 38, ESR is calculated to be, RESR < 555 mΩ.
Capacitors with lowest ESR values should be selected. To meet both the requirements, capacitance and low
ESR, several low ESR capacitors may be connected in parallel. In this example, we will select a capacitor with
ESR value as 30 mΩ.
Filter capacitor (C12) of value 0.1µF can be added to filter out the noise in the output line.
Step 5. Calculate the Feedback Resistors (R4, R5)
To keep the quiescent current low and avoid instability problems, it is recommended to select R4 and R5 such
that, R4 + R5 ~ 250 kΩ.
Using Equation 1 and using a fixed standard value of R4 = 187 kΩ, R5 is calculated to be, R5 = 35.7 kΩ .
Step 6. Calculate Type 3 Compensation Components
Resistances (R6, R9)
Using Equation 19, for VINTyp = 14 V, VRamp is calculated to be, VRamp = 1.4 V.
Using Equation 15, fLC is calculated to be, fLC = 3.33 kHz.
Using VRamp, fLC from above, assuming fc as 1/10th of fsw and Equation 46, R6 is calculated to be, R6 = 280.65
kΩ.
Using Equation 47, R9 is calculated to be, R9 = 2.53 kΩ.
Capacitors (C5, C8, C7)
Using Equation 48, C5 is calculated to be, C5 = 340.45 pF.
Using Equation 16, fESR is calculated to be, fESR = 53.06 kHz.
Using Equation 50, C8 is calculated to be, C8 = 11.04 pF.
Using Equation 49, C7 is calculated to be, C7 = 250.07 pF.
Step 7. Calculate Soft-Start Capacitor (C6)
The recommended value of soft-start capacitor is 100nF (typical).
Step 8. Calculate Bootstrap Capacitor (C3)
The recommended value of bootstrap capacitor is 0.1 µF (typical).
Step 9. Calculate Power-On Reset Delay Capacitor (C2)
To achieve 2.2-ms delay, the reset delay capacitor can be calculated using Equation 9 to be C2 = 2.2 nF.
Step 10. Calculate Input Capacitor (C1, C11)
Typical values for C11 are 0.1 µF and 0.01 µF.
Input capacitor (C1) should be rated more than the maximum input voltage (VINMax). The input capacitor should
be big enough to maintain supply in case of transients in the input line. Using Equation 34, C1 is calculated to
be, C1 = 1.2 µF. For improved transient response, a higher value of C1 such as 220 µF is recommended.
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Step 11. Calculate Resistors to Control Slew Rate (R7)
The value of slew rate resistor (R7) can be approximately determined from Figure 24 and Figure 25 at different
typical input voltages. The minimum recommended value is 10 kΩ. To achieve rise time, tr = 20 ns and fall time,
tf = 35 ns, the slew rate resistor is approximately of value 30 kΩ.
Step 12. Resistors to Select Undervoltage, Overvoltage and Reset Threshold Values (R1, R2, R3)
The sum of these three resistors should be approximately equal to 100 kΩ. In this example,
VReg_OV = 106% of VReg = 5.3 V
VReg_RST = 92% of VReg = 4.6 V
VReg_UV = 95% of VReg = 4.75 V
Using Equation 12, R3 = 15 kΩ.
Using Equation 11, R2 = 2.29 kΩ.
Using Equation 10, R1 = 82.6 kΩ
Step 13. Diode D1 and D2 Selection
Diode D1 is used to protect the IC from the reverse input polarity connection. The diode should be rated at
maximum load current. Only Schottky diode should be connected at the PH pin. The recommended part numbers
are PDS360 and SBR8U60P5.
Step 14. Noise Filter on RST_TH and OV_TH Terminals (C9 and C10)
Typical capacitor values for RST_TH and OV_TH pins are between 10 pF to 100 pF for total resistance on
RST_TH/ OV_TH divider of less than 200 kΩ.
Step 15. Power Budget and Temperature Estimation
Using Equation 25, conduction losses for typical input voltage are calculated to be, PCON = 0.289 W.
Assuming slew resistance R7 = 30 kΩ, from Figure 24 and Figure 25, rise time, tr = 20 ns and fall time, tf = 35
ns. Using Equation 26, switching losses for typical input voltage are calculated to be, PSW = 0.693 W.
Using Equation 27, gate drive losses are calculated to be, PGate = 3 mW.
Using Equation 28, power supply losses are calculated to be, PIC = 1.8 mW.
Using Equation 29, the total power dissipated by the device is calculated to be, PTotal = 987 mW.
Using Equation 31, and knowing the thermal resistance of package = 35°C/W, the rise in junction temperature
due to power dissipation is calculated to be, ∆T = 34.5°C.
Using Equation 32, for a given maximum junction temperature 150°C, the maximum ambient temperature at
which the device can be operated is calculated to be, TA-Max = 115°C (approximately).
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Example 2
For this example, we will start with the following known and target parameters:
Table 8.
minimum=8 V, maximum= 28 V,
typical=14 V
Known
Target
Input voltage, VIN
Output voltage, VReg
Maximum output current, ILoad-Max
Ripple/ transient occurring in input voltage, ΔVIN
Reset threshold, VReg_RST
3.3 V ± 2%
2 A
1% of VIN (minimum)
92% of VReg
106% of VReg
95% of VReg
5% of VReg
Overvoltage threshold, VReg_OV
Undervoltage threshold, VReg_UV
Transient response 0.25 A to 2 A load step, ΔVReg
Power on Reset delay, PORdly
2.2 ms
Step 1. Calculate the Switching Frequency (fsw
)
To reduce the size of output inductor and capacitor, higher switching frequency can be selected. It is important to
understand that higher switching frequency will result in higher switching losses, causing the device to heat up.
This may result in degraded thermal performance. To prevent this, proper PCB layout guidelines must be
followed (explained in the later section of this document).
Based upon the discussion in section Selecting the Switching Frequency, calculate the maximum and minimum
duty cycle.
Knowing VReg and tolerance on VReg, the VReg-Max and VReg-Min are calculated to be:
VReg-Max = 102% of VReg = 3.366 V and VReg-Min = 98% of VReg = 3.234 V.
Using Equation 6, the minimum duty cycle is calculated to be, DMin = 11.55%
Knowing tON-Min = 150 ns from the device specifications, and using Equation 7, maximum switching frequency is
calculated to be, fsw-Max = 770 kHz.
Since the oscillator can also vary by ±10%, the switching frequency can be further reduced by 10% to add
margin. Also, to improve efficiency and reduce power losses due to switching, the switching frequency can be
further reduced by about 100 kHz. Therefore fsw = 593 kHz.
From Figure 23, R8 can be approximately determined to be, R8 = 170 kΩ.
Step 2. Calculate the Ripple Current (IRipple
)
Using Equation 40, for KIND = 0.2 (typical), inductor ripple current is calculated to be: IRipple = 0.4 A.
The ripple current is chosen such that the converter enters discontinuous mode (DCM) at 20% of max load. The
20% is a typical value, it could go higher to a maximum of up to 40%.
Step 3. Calculate the Inductor Value (L1)
Using Equation 41, the inductor value is calculated to be, LMin = 12.3 µH. A closest standard inductor value can
be used.
Step 4. Calculate the Output Capacitor and ESR (C4, C12)
Calculate capacitance
To calculate the capacitance of the output capacitor, minimum load current must be first determined. Typically, in
standby mode the load current is 100 µA, however this really depends on the application. With this value of
minimum load current and using Equation 35, Equation 36, and Equation 37, C4 is calculated to be, C4 > 56 µF .
To allow wider operating conditions and improved performance in low-power mode, it is recommended to use a
100 µF capacitor. Higher value of output capacitor allows improved transient response during load stepping.
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Calculate ESR
Using Equation 38, ESR is calculated to be, RESR < 330 mΩ.
Capacitors with lowest ESR values should be selected. To meet both the requirements, capacitance and low
ESR, several low ESR capacitors may be connected in parallel. In this example, we will select a capacitor with
ESR value as 30 mΩ.
Filter capacitor (C12) of value 0.1µF can be added to filter out the noise in the output line.
Step 5. Calculate the Feedback Resistors (R4, R5)
To keep the quiescent current low and avoid instability problems, it is recommended to select R4 and R5 such
that, R4 + R5 ~ 250 kΩ.
Using Equation 1 and using a fixed standard value of R4 = 187 kΩ, R5 is calculated to be, R5 = 59.8 kΩ .
Step 6. Calculate Type 3 Compensation Components
Resistances (R6, R9)
Using Equation 19, for VINTyp = 14 V, VRamp is calculated to be, VRamp = 1.4 V.
Using Equation 15, fLC is calculated to be, fLC = 4.54 kHz.
Using VRamp, fLC from above, assuming fc as 1/10th of fsw and Equation 46, R6 is calculated to be, R6 = 244 kΩ.
Using Equation 47, R9 is calculated to be, R9 = 2.9 kΩ.
Capacitors (C5, C8, C7)
Using Equation 48, C5 is calculated to be, C5 = 287.04 pF.
Using Equation 16, fESR is calculated to be, fESR = 53.06 kHz.
Using Equation 50, C8 is calculated to be, C8 = 12.84 pF.
Using Equation 49, C7 is calculated to be, C7 = 184.4 pF.
Step 7. Calculate Soft-Start Capacitor (C6)
The recommended value of soft-start capacitor is 100nF (typical).
Step 8. Calculate Bootstrap Capacitor (C3)
The recommended value of bootstrap capacitor is 0.1 µF (typical).
Step 9. Calculate Power-On Reset Delay Capacitor (C2)
To achieve 2.2-ms delay, the reset delay capacitor can be calculated using Equation 9 to be C2 = 2.2 nF.
Step 10. Calculate Input Capacitor (C1, C11)
Typical values for C11 are 0.1 µF and 0.01 µF.
Input capacitor (C1) should be rated more than the maximum input voltage (VINMax). The input capacitor
should be big enough to maintain supply in case of transients in the input line. Using Equation 34, C1 is
calculated to be, C1 = 10.53 µF. For improved transient response, a higher value of C1 such as 220 µF is
recommended.
Step 11. Calculate Resistors to Control Slew Rate (R7)
The value of slew rate resistor (R7) can be approximately determined from Figure 24 and Figure 25 at different
typical input voltages. The minimum recommended value is 10 kΩ. To achieve rise time, tr = 20 ns and fall time,
tf = 35 ns, the slew rate resistor is approximately of value 30 kΩ.
Step 12. Resistors to Select Undervoltage, Overvoltage and Reset Threshold Values (R1, R2, R3)
The sum of these three resistors should be approximately equal to 100 kΩ. In this example,
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VReg_OV = 106% of VReg = 3.498 V
VReg_RST = 92% of VReg = 3.036 V
VReg_UV = 95% of VReg = 3.135 V
Using Equation 12, R3 = 22.87 kΩ.
Using Equation 11, R2 = 3.48 kΩ.
Using Equation 10, R1 = 73.65 kΩ
Step 13. Diode D1 and D2 Selection
Diode D1 is used to protect the IC from the reverse input polarity connection. The diode should be rated at
maximum load current. Only Schottky diode should be connected at the PH pin. The recommended part numbers
are PDS360 and SBR8U60P5.
Step 14. Noise Filter on RST_TH and OV_TH Terminals (C9 and C10)
Typical capacitor values for RST_TH and OV_TH pins are between 10 pF to 100 pF for total resistance on
RST_TH/ OV_TH divider of less than 200 kΩ.
Step 15. Power Budget and Temperature Estimation
Using Equation 25, conduction losses for typical input voltage are calculated to be, PCON = 0.235 W.
Assuming slew resistance R7 = 30 kΩ, from Figure 14 and Figure 15, rise time, tr = 20 ns and fall time, tf = 35
ns. Using Equation 22, switching losses for typical input voltage are calculated to be, PSW = 0.913 W.
Using Equation 26, gate drive losses are calculated to be, PGate = 3.5 mW.
Using Equation 28, power supply losses are calculated to be, PIC = 1.8 mW.
Using Equation 29, the total power dissipated by the device is calculated to be, PTotal = 1.15 W.
Using Equation 31, and knowing the thermal resistance of package = 35°C/W, the rise in junction temperature
due to power dissipation is calculated to be, ∆T = 40.4°C.
Using Equation 32, for a given maximum junction temperature 150°C, the maximum ambient temperature at
which the device can be operated is calculated to be, TA-Max ~105°C (approximately).
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PCB LAYOUT GUIDELINES
The following guidelines are recommended for PCB layout of the TPS54262 device.
Traces and Ground Place Routing
All power (high current) traces should be thick and as short as possible. The inductor and output capacitors
should be as close to each other as possible. This will reduce EMI radiated by the power traces due to high
switching currents. In a two sided PCB, it is recommended to have ground planes on both sides of the PCB to
help reduce noise and ground loop errors. The ground connection for the input and output capacitors and IC
ground should be connected to this ground plane.
In a multilayer PCB, the ground plane is used to separate the power plane (high switching currents and
components are placed) from the signal plane (where the feedback trace and components are) for improved
performance.
Also, it is recommended to arrange the components such that the switching current loops curl in the same
direction. This can be done by placing the high current components such that during conduction, the current
paths are in the same direction. This will prevent magnetic field reversal caused by the traces between the two
half cycles, helping to reduce radiated EMI.
Component Routing for the Feedback Loop
It is recommended to route the feedback traces such that there is minimum interaction with any noise sources
associated with the switching components. Recommended practice is to ensure the inductor is placed away from
the feedback trace to prevent EMI noise source.
Output
Capacitor
Topside Supply Area
Ground
Input Capacitor
Plane
Output
Inductor
Catch Diode
NC
NC
BOOT
VIN
VIN
SYNC
LPM
EN
PH
VReg
Compensation Network
Supervisor Network
RT
COMP
VSENSE
RST_TH
OV_TH
SS
Rslew
RST
Resistor
Divider
Cdly
GND
Signal via to
Ground Plane
Topside Ground Area
Thermal Via
Signal Via
Figure 32. PCB Layout Example
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Product Folder Link(s): TPS54262-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Jun-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS54262QPWPRQ1
ACTIVE
HTSSOP
PWP
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54262QPWPRQ1 HTSSOP PWP
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 20
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
TPS54262QPWPRQ1
2000
Pack Materials-Page 2
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