TPS54339DDA [TI]
4.5 V to 23 V Input, 3-A Synchronous Step-Down SWIFT Converter; 4.5 V至23 V输入， 3 -A同步降压SWIFT转换器
| 型号： | TPS54339DDA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4.5 V to 23 V Input, 3-A Synchronous Step-Down SWIFT Converter |
| 文件： | 总21页 (文件大小：1002K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS54339
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4.5 V to 23 V Input, 3-A Synchronous Step-Down SWIFT™ Converter
Check for Samples: TPS54339
1
FEATURES
DESCRIPTION
The TPS54339 is an adaptive on-time D-CAP2™
mode synchronous buck converter. The TPS54339
enables system designers to complete the suite of
various end-equipment power bus regulators with a
cost effective, low component count, low standby
current solution. The main control loop for the
TPS54339 uses the D-CAP2™ mode control that
provides a fast transient response with no external
compensation components. The TPS54339 also has
a proprietary circuit that enables the device to adopt
to both low equivalent series resistance (ESR) output
capacitors, such as POSCAP or SP-CAP, and ultra-
low ESR ceramic capacitors. The device operates
from 4.5-V to 23-V VIN input. The output voltage can
be programmed between 0.76 V and 7 V. The device
also features an adjustable soft start time. The
TPS54339 is available in the 8-pin DDA package,
and designed to operate from –40°C to 85°C.
23
•
D-CAP2™ Mode Enables Fast Transient
Response
•
Low Output Ripple and Allows Ceramic Output
Capacitor
•
•
•
Wide VIN Input Voltage Range: 4.5 V to 23 V
Output Voltage Range: 0.76 V to 7 V
Highly Efficient Integrated FETs Optimized
for Lower Duty Cycle Applications
– 140 mΩ (High Side) and 70 mΩ (Low Side)
•
•
•
•
•
•
High Efficiency, less than 10 μA at shutdown
High Initial Bandgap Reference Accuracy
Adjustable Soft Start
Pre-Biased Soft Start
600-kHz Switching Frequency (fSW
)
Cycle By Cycle Over Current Limit
APPLICATIONS
•
Wide Range of Applications for Low Voltage
System
–
–
–
–
Digital TV Power Supply
High Definition Blu-ray Disc™ Players
Networking Home Terminal
Digital Set Top Box (STB)
VIN
Vout (50 mV/div)
TPS54339DDA
8
7
6
5
1
2
3
4
VBST
VIN
SS
EN
EN
Iout (2 A/div)
VOUT
SW
VREG5
GND
VFB
VOUT
PwPd
9
100 us/div
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
D-CAP2 is a trademark of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TPS54339
SLVSBT2 –JANUARY 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
TRANSPORT
TA
PACKAGE(2) (3)
ORDERABLE PART NUMBER
PIN
MEDIA
TPS54339DDA
Tube
–40°C to 85°C
DDA
8
TPS54339DDAR
Tape and Reel
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) All package options have Cu NIPDAU lead/ball finish.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–2
MAX
25
VIN, EN
VBST
31
VBST (10 ns transient)
VBST (vs SW)
VFB, SS
33
Input voltage range
Output voltage range
6.5
6.5
25
V
V
SW
SW (10 ns transient)
VREG5
–3
27
–0.3
–0.3
–0.2
6.5
0.3
0.2
2
GND
Voltage from GND to thermal pad, Vdiff
V
kV
V
Human Body Model (HBM)
Charged Device Model (CDM)
Electrostatic discharge
500
150
150
Operating junction temperature, TJ
Storage temperature, Tstg
–40
–55
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
TPS54339
THERMAL METRIC(1)
UNITS
DDA (8 PINS)
46.2
θJA
Junction-to-ambient thermal resistance
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
53.9
29.7
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
10.0
ψJB
29.6
θJCbot
6.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range, (unless otherwise noted)
MIN
4.5
MAX
23
UNIT
VIN
Supply input voltage range
V
VBST
–0.1
–0.1
–0.1
–0.1
–0.1
–0.1
–1.8
–3
29
VBST (10 ns transient)
32
VBST(vs SW)
5.7
5.7
23
SS
VI
Input voltage range
EN
V
VFB
5.5
23
SW
SW (10 ns transient)
GND
26
–0.1
–0.1
0
0.1
5.7
10
VO
IO
Output voltage range
VREG5
V
Output Current range
IVREG5
mA
°C
°C
TA
TJ
Operating free-air temperature
Operating junction temperature
–40
–40
85
150
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IVIN
Operating - non-switching supply current VIN current, TA = 25°C, EN = 5V, VFB = 0.8V
850
3.0
1200
10
μA
μA
IVINSDN
Shutdown supply current
VIN current, TA = 25°C, EN = 0 V
LOGIC THRESHOLD
VENH
VENL
REN
EN high-level input voltage
EN
1.6
V
V
EN low-level input voltage
EN pin resistance to GND
EN
0.6
VEN = 12 V
200
400
800
kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
TA = 25°C, VO = 1.05 V, continuous mode
operation
VFBTH
VFB threshold voltage
749
765
0
781
mV
IVFB
VFB input current
VFB = 0.8 V, TA = 25°C
±0.1
μA
VREG5 OUTPUT
TA = 25°C, 6.0 V < VIN < 23 V,
0 < IVREG5 < 5 mA
VVREG5
VREG5 output voltage
5.2
20
5.5
5.7
V
IVREG5
Output current
VIN = 6 V, VREG5 = 4.0 V, TA = 25°C
mA
MOSFET
RDS(on)h
RDS(on)l
High side switch resistance
Low side switch resistance
25°C, VBST - SW = 5.5 V(1)
25°C(1)
140
70
mΩ
mΩ
CURRENT LIMIT
Iocl
Current limit
L out = 2.2 μH(1)
3.5
4.1
5.7
A
THERMAL SHUTDOWN
(1)
Shutdown temperature
165
40
TSDN
Thermal shutdown threshold
°C
(1)
Hysteresis
ON-TIME TIMER CONTROL
tON
On time
VIN = 12 V, VO = 1.05 V
TA = 25°C, VFB = 0.7 V(1)
160
260
ns
ns
tOFF(MIN)
Minimum off time
310
(1) Not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SOFT START
ISSC
ISSD
SS charge current
VSS = 1.0 V
VSS = 0.5 V
4.2
0.8
6.0
1.5
7.8
μA
SS discharge current
mA
HICCUP AND OVERVOLTAGE PROTECTION
VOVP
Output OVP threshold
Output Hiccup threshold
Output Hiccup delay
OVP Detect (L>H)
Hiccup detect (H>L)
to Hiccup state
125%
65%
6
VUVP
TUVPDEL
TUVPEN
UVLO
µs
V
Output Hiccup Enable delay
Relative to soft-start time
x1.7
Wake up VREG5 voltage
Hysteresis VREG5 voltage
3.45
0.17
3.75
0.33
4.05
0.47
UVLO
UVLO threshold
DEVICE INFORMATION
DDA PACKAGE
(TOP VIEW)
8
1
VBST
SS
2
7
VIN
EN
POWER PAD
TPS54339
DDA
3
HSOP8
6
VREG5
SW
4
5
VFB
GND
PIN FUNCTIONS
PIN
DESCRIPTION
NAME
NO.
Supply input for the high-side FET gate drive circuit. Connect 0.1µF capacitor between VBST and SW pins.
An internal diode is connected between VREG5 and VBST.
VBST
1
VIN
SW
2
3
Input voltage supply pin.
Switch node connection between high-side NFET and low-side NFET.
Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB returns to GND at a
single point.
GND
VFB
4
5
Converter feedback input. Connect to output voltage with feedback resistor divider.
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PIN FUNCTIONS (continued)
PIN
DESCRIPTION
NAME
NO.
5.5 V power supply output. A capacitor (typical 0.47 µF) should be connected to GND. VREG5 is not active
when EN is low.
VREG5
6
EN
SS
7
8
Enable input control. EN is active high and must be pulled up to enable the device.
Soft-start control. An external capacitor should be connected to GND.
Exposed
Thermal Pad
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected to
GND.
Back side
FUNCTIONAL BLOCK DIAGRAM
SS
8
Softstart
SS
VBST
VIN
1
VIN
SGND
EN
EN
7
2
Logic
VREG5
VREG5
Control Logic
1 Shot
6
OV
SW
3
VO
+25%
XCON
PGND
VREG5
Ceramic
Capacitor
Ref
PWM
SS
4
5
GND
VFB
SW
SGND
OCP
PGND
VIN
OV
VREG5
Protection
Logic
UVLO
TSD
UVLO
Ref
REF
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OVERVIEW
The TPS54339 is a 3-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It
operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output
capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low
ESR output capacitors including ceramic and special polymer types.
DETAILED DESCRIPTION
PWM Operation
The main control loop of the TPS54339 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need
for ESR induced output ripple from D-CAP2™ mode control.
PWM Frequency and Adaptive On-Time Control
TPS54339 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54339 runs with a pseudo-constant frequency of 600 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage; therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
Soft Start and Pre-Biased Soft Start
The soft start function is adjustable. When the EN pin becomes high, 6 μA current begins charging the capacitor
which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up.
The equation for the slow start time is shown in Equation 1. VFB voltage is 0.765 V and SS pin source current is
6 μA.
C
(nF) x V
´1.1
C
(nF) x 0.765´1.1
SS
REF
SS
t
(ms) =
=
SS
I
(mA)
6
SS
(1)
The TPS54339 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting
the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-
cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This
scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps
up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal
mode operation.
Current Protection
The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iout. The TPS54339 constantly
monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.
If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented
per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the
voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching
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cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in
the same manner. If the over current condition exists for 7 consecutive switching cycles, the internal OCL
threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the
switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the
higher value.
There are some important considerations for this type of over-current protection. The load current one half of the
peak-to-peak inductor current higher than the over-current threshold. Also when the current is being limited, the
output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. This may cause the output voltage to fall. When the VFB voltage becomes lower than 65% of the
target voltage, the UVP comparator detects it. After 6µs detecting the UVP voltage, device will shut down and re-
start after 7 times SS period for Hiccup.
When the over current condition is removed, the output voltage returns to the regulated value. This protection is
non-latching.
Over Voltage Protection
TPS54339 detects over voltage conditions by monitoring the feedback voltage (VFB). This function is enabled
after approximately 1.7 x times the soft start time.
When the feedback voltage becomes higher than 125% of the target voltage, the OVP comparator output goes
high and both the high-side MOSFET driver and the low-side MOSFET driver turn off. This function is non-latch
operation.
UVLO Protection
Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower
than UVLO threshold voltage, the TPS54339 is shut off. This protection is non-latching.
Thermal Shutdown
TPS54339 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C),
the device is shut off. This is non-latch protection.
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TYPICAL CHARACTERISTICS
VIN = 12 V, TA = 25°C (unless otherwise noted).
1200
1000
800
10
8
6
600
4
400
2
200
0
0
œ50
0
50
100
150
œ50
0
50
100
150
C001
C002
TJ œ Junction Temperature (°C)
TJ œ Junction Temperature (°C)
Figure 1. VIN CURRENT vs JUNCTION TEMPERATURE
Figure 2. VIN SHUTDOWN CURRENT vs
JUNCTION TEMPERATURE
1.100
1.075
1.050
1.025
1.000
80
VIN = 23 V
VIN = 23 V
VIN = 12 V
60
40
20
0
VIN = 5 V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0
5
10
15
20
25
C004
C003
IOUT œ Output Current (A)
EN Input Voltage (V)
Figure 3. EN CURRENT vs EN VOLTAGE
Figure 4. 1.05-V OUTPUT VOLTAGE vs OUTPUT CURRENT
1.07
1.06
1.05
1.04
1.03
IOUT = 0 A
Vout (50 mV/div)
Iout (2 A/div)
IOUT = 1 A
100 us/div
0
5
10
15
20
25
C005
VIN œ Input Voltage (V)
Figure 5. 1.05-V OUTPUT VOLTAGE vs INPUT VOLTAGE
Figure 6. 1.05-V, LOAD TRANSIENT RESPONSE
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TYPICAL CHARACTERISTICS
VIN = 12 V, TA = 25°C (unless otherwise noted).
100
90
EN (10 V/div)
80
VO = 3.3 V
VREG5 (5 V/div)
VO = 5 V
VO = 1.8 V
70
60
50
40
Vout (0.5 V/div)
400 us/div
0.0
0.5
1.0
1.5
2.0
2.5
3.0
C006
IOUT œ Output Current (A)
Figure 7. START-UP WAVE FORM
Figure 8. EFFICIENCY vs OUTPUT CURRENT
900
850
800
750
700
650
600
550
500
450
400
800
700
600
500
400
300
200
100
0
VO = 3.3 V
VO = 3.3 V
VO = 1.8 V
VO = 5 V
VO = 1.8 V
VO = 1.05 V
VO = 1.2 V
VO = 1.05 V
20
0
5
10
15
25
0.0
0.5
1.0
1.5
2.0
2.5
3.0
C007
C008
VIN œ Input Voltage (V)
IOUT œ Output Current (A)
Figure 9. SWITCHING FREQUENCY vs
INPUT VOLTAGE (IO = 1 A)
Figure 10. SWITCHING FREQUENCY vs OUTPUT CURRENT
0.780
0.775
0.770
0.765
0.760
0.755
0.750
IOUT = 1 A
Vo = 1.05 V
Vo (10 mV/div)
SW (5 V/div)
400 ns/div
œ50
0
50
100
150
C009
TJ œ Junction Temperature (°C)
Figure 11. VFB VOLTAGE vs JUNCTION
TEMPERATURE (IO = 1 A)
Figure 12. VOLTAGE RIPPLE AT OUTPUT (IO = 3A)
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TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, TA = 25°C (unless otherwise noted).
Vo = 1.05 V
VIN (50 mV/div)
SW (5 V/div)
400 ns/div
Figure 13. VOLTAGE RIPPLE AT INPUT (IO = 3 A)
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DESIGN GUIDE
Step-By-Step Design Procedure
To begin the design process, the user must know a few application parameters:
•
•
•
•
•
Input voltage range
Output voltage
Output current
Output voltage ripple
Input voltage ripple
VIN
4.5 to 23V
VIN
C2
C1
C3
10μF
10μF
0.1μF
U1
TPS54339DDA
R3 10.0kΩ
7
5
6
8
2
1
EN
EN
VIN
C7 0.1μF
VOUT
1.05V 3A
VOUT
VFB
VREG5
SS
VBST
SW
R1 8.25kΩ
L1
3
4
VOUT
R2
22.1kΩ
2.2μH
C4
1
GND
C8
C9
C10
C5
0.47μF
PwrPAD
1
C6
22μF 22μF
9
8200pF
Not Installed
1
Figure 14. Shows the schematic diagram for this design example.
Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 2 to calculate VOUT
.
To improve efficiency at light loads consider using larger value resistors, high resistance is more susceptible to
noise, and the voltage errors from the VFB input current are more noticeable.
æ
ö
÷
÷
R1
ç
= 0.765 x 1 +
V
OUT
ç
÷
÷
ø
ç
è
R2
(2)
Output Filter Selection
The output filter used with the TPS54339 is an LC circuit. This LC filter has double pole at:
1
F
P
=
2p L
x C
OUT
OUT
(3)
11
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At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS54339. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 3 is located below the high frequency zero but close enough that the phase boost provided be the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 1
Table 1. Recommended Component Values
Output
Voltage R1 (kΩ) R2 (kΩ)
(V)
C4 (pF)(1)
L1 (µH)
Typ
C8 + C9 + C10 (µF)
Min
Typ
Max
Min
Max
Min
Max
1
1.05
1.2
1.5
1.8
2.5
3.3
5
6.81
8.25
12.7
21.5
30.1
49.9
73.2
124
22.1
22.1
22.1
22.1
22.1
22.1
22.1
22.1
22.1
5
5
5
5
5
5
5
5
5
150
150
220
220
100
68
1.5
1.5
1.5
1.5
2.2
2.2
2.2
3.3
3.3
2.2
2.2
2.2
2.2
3.3
3.3
3.3
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
22
22
22
22
22
22
22
22
22
68
68
68
68
68
68
68
68
68
22
22
22
22
6.5
165
22
(1) Optional
Since the DC gain is dependent on the output voltage, the required inductor value increases as the output
voltage increases. Additional phase boost can be achieved by adding a feed forward capacitor (C4) in parallel
with R1. The amount of available phase boost is dependent on the output voltage. Higher output voltages will
allow greater phase boost.
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4,
Equation 5 and Equation 6. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 600 kHz for
fSW
.
Use 600 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS
current of Equation 6.
V
- VOUT
VOUT
IN(MAX)
IlP-P
=
´
V
LO ´ ¦SW
IN(MAX)
(4)
(5)
IlP-P
IlPEAK =IO+
2
1
2
2
ILO(RMS)
=
IO
+
IlP-P
12
(6)
For this design example, the calculated peak current is 3.38 A and the calculated RMS current is 3.01 A. The
inductor used is a TDK CLF7045T-2R2N with a peak current rating of 5.5 A and an RMS current rating of 4.3 A.
For high current designs, TDK SPM6530T-4R7M 4.7µH is also recommended. The SPM6530 series has a higher
current rating than the CLF7045 series.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54339 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 22µF to 68µF. Use Equation 7 to
determine the required RMS current rating for the output capacitor.
V
x (V - V
)
OUT
IN
OUT
I
=
Co(RMS)
12 x V x L
IN
x
fSW
O
(7)
For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.22 A and each output capacitor is rated for 4A.
12
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Product Folder Links: TPS54339
TPS54339
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SLVSBT2 –JANUARY 2013
Input Capacitor Selection
The TPS54339 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1 µF
capacitor from pin 2 to ground is optional to provide additional high frequency filtering. The capacitor voltage
rating needs to be greater than the maximum input voltage.
Bootstrap Capacitor Selection
A 0.1 µF. ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is
recommended to use a ceramic capacitor.
VREG5 Capacitor Selection
A 0.47 µF. ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is
recommended to use a ceramic capacitor.
THERMAL INFORMATION
This 8-pin DDA package incorporates an exposed thermal pad that is designed to be directly to an external
heartsick. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be
used as a heartsick. In addition, through the use of thermal vias, the thermal pad can be attached directly to the
appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a
special heartsick structure designed into the PCB. This design optimizes the heat transfer from the integrated
circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, see the Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No.
SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.
The exposed thermal pad dimensions for this package are shown in the following illustration.
8
5
Exposed Thermal Pad
2,40
1,65
1
4
3,10
2,65
Figure 15. Thermal Pad Dimensions
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TPS54339
SLVSBT2 –JANUARY 2013
www.ti.com
LAYOUT CONSIDERATIONS
1. Keep the input switching current loop as small as possible.
2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin of the device.
3. Keep analog and non-switching components away from switching components.
4. Make a single point connection from the analog ground to power ground.
5. Do not allow switching current to flow under the device.
6. Keep the pattern lines for VIN and PGND broad.
7. Exposed pad of device must be connected to PGND with solder.
8. VREG5 capacitor should be placed near the device, and connected to PGND.
9. Output capacitor should be connected to a broad pattern of the PGND.
10. Voltage feedback loop should be as short as possible, and preferably with ground shield.
11. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to analog ground
trace.
12. Providing sufficient via is preferable for VIN, SW and PGND connection.
13. VIN input bypass capacitor and VIN high frequency bypass capacitor must be placed as near as possible to
the device.
14. Performance based on four layer printed circuit board.
SOFT
START
Additional
CAP
Thermal
Vias
VIN INPUT
BYPASS
TO ENABLE
CONTROL
CAPACITOR
Connection to
POWER GROUND
on internal or
VIN
VBST
VIN
SS
EN
bottom layer
BOOST
CAPACITOR
BIAS
CAP
VOUT
FEEDBACK
RESISTORS
VREG5
VFB
SW
OUTPUT
INDUCTO
EXPOSED
POWERPAD
AREA
GND
VIN INPUT
BYPASS
CAPACITOR
OUTPUT
FILTER
CAPACITOR
Additional
Thermal
Vias
ANALOG
GROUND
TRACE
POWER GROUND
Figure 16. PCB Layout
14
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Product Folder Links: TPS54339
PACKAGE OPTION ADDENDUM
www.ti.com
13-Feb-2013
PACKAGING INFORMATION
Orderable Device
TPS54339DDA
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
ACTIVE SO PowerPAD
DDA
8
8
75
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
TPS54339DDAR
ACTIVE SO PowerPAD
DDA
2500
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Feb-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54339DDAR
SO
Power
PAD
DDA
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Feb-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SO PowerPAD DDA
SPQ
Length (mm) Width (mm) Height (mm)
366.0 364.0 50.0
TPS54339DDAR
8
2500
Pack Materials-Page 2
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