TPS54429PWPR [TI]
7V to 18V Input, 4.5-A Synchronous Step-Down ( SWIFT?) Converter; 7V至18V输入， 4.5 -A同步降压（ SWIFT ™ ）转换器
| 型号： | TPS54429PWPR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 7V to 18V Input, 4.5-A Synchronous Step-Down ( SWIFT?) Converter |
| 文件： | 总22页 (文件大小：655K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS54429
www.ti.com
SLVSAS1 –FEBRUARY 2011
7V to 18V Input, 4.5-A Synchronous Step-Down ( SWIFT™) Converter
Check for Samples: TPS54429
1
FEATURES
DESCRIPTION
23
•
D-CAP2™ Mode Enables Fast Transient
Response
The TPS54429 is an adaptive on-time D-CAP2™
mode synchronous buck converter. The TPS54429
enables system designers to complete the suite of
various end equipment’s power bus regulators with a
cost effective, low component count, low standby
current solution. The main control loop for the
TPS54429 uses the D-CAP2™ mode control which
provides a very fast transient response with no
external compensation components. The TPS54429
also has a proprietary circuit that enables the device
to adopt to both low equivalent series resistance
(ESR) output capacitors, such as POSCAP or
SP-CAP, and ultra-low ESR ceramic capacitors. The
device operates from 7-V to 18-V VIN input. The
output voltage can be programmed between 0.76 V
and 5.5 V. The device also features an adjustable
soft start time and a power good function. The
TPS54429 is available in the 14-pin HTSSOP
package, and designed to operate from –20°C to
85°C.
•
Low Output Ripple and Allows Ceramic Output
Capacitor
•
•
•
Wide VIN Input Voltage Range: 7 V to 18 V
Output Voltage Range: 0.76 V to 5.5 V
Highly Efficient Integrated FET’s Optimized
for Lower Duty Cycle Applications
– 63 mΩ (High Side) and 55 mΩ (Low Side)
•
•
•
•
•
•
•
High Efficiency, less than 10 μA at shutdown
High Initial Bandgap Reference Accuracy
Adjustable Soft Start
Pre-Biased Soft Start
700-kHz Switching Frequency (fSW
)
Cycle By Cycle Over Current Limit
Power Good Output
APPLICATIONS
•
Wide Range of Applications for Low Voltage
System
–
–
–
–
Digital TV Power Supply
High Definition Blu-ray Disc™ Players
Networking Home Terminal
Digital Set Top Box (STB)
U1
TPS54429PWP
Vout (50 mV/div)
Iout (2A/div)
100 ms/div
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
SWIFT, D-CAP2, PowerPAD are trademarks of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
© 2011, Texas Instruments Incorporated
TPS54429
SLVSAS1 –FEBRUARY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
ORDERABLE PART
NUMBER
TRANSPORT
MEDIA
TA
PACKAGE(2) (3)
PIN
ECO PLAN
TPS54429PWP
Tube
PowerPAD™
(HTSSOP) – PWP
Green
(RoHS & no Sb/Br)
–20°C to 85°C
14
TPS54429PWPR
Tape and Reel
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) All package options have Cu NIPDAU lead/ball finish.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
MIN
–0.3
–0.3
–0.3
–0.3
–2
MAX
20
VIN1, VIN2 EN
VBST
26
VBST (10 ns transient)
VFB VO, SS, PG
SW1, SW2
28
Input voltage
range
VI
6.5
20
V
SW1, SW2 (10 ns transient)
VREG5
–3
22
–0.3
–0.3
–0.2
6.5
0.3
0.2
2
Output voltage
range
VO
PGND1, PGND2
Vdiff
Voltage from GND to POWERPAD
Human Body Model (HBM)
Charged Device Model (CDM)
kV
V
ESD
rating
Electrostatic
discharge
500
150
150
TJ
Operating junction temperature
Storage temperature
–20
–55
°C
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
TPS54429
THERMAL METRIC(1)
PWP
14 PINS
55.6
UNITS
θJA
Junction-to-ambient thermal resistance
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
51.3
26.4
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.8
ψJB
20.6
θJCbot
4.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
© 2011, Texas Instruments Incorporated
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SLVSAS1 –FEBRUARY 2011
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
7
MAX
18
UNIT
VIN
Supply input voltage range
V
VBST
–0.3
–0.3
–0.1
–0.1
–0.1
–1.8
–3
24
VBST(10 ns transient)
SS, PG
27
5.7
18
EN
VI
Input voltage range
V
VO, VFB
5.5
18
SW1, SW2
SW1, SW2 (10 ns transient)
PGND1, PGND2
VREG5
21
–0.1
–0.1
0
0.1
5.7
10
VO
IO
Output voltage range
V
Output Current range
IVREG5
mA
°C
°C
TA
TJ
Operating free-air temperature
Operating junction temperature
–20
–20
85
150
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VIN = 12V (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN current, TA = 25°C, EN = 5 V,
VFB = 0.8 V
IVIN
Operating - non-switching supply current
Shutdown supply current
850
1.8
1300
10
μA
μA
IVINSDN
VIN current, TA = 25°C, EN = 0 V
LOGIC THRESHOLD
VENH
VENL
EN high-level input voltage
EN low-level input voltage
EN
EN
2
V
V
0.48
VFB VOLTAGE AND DISCHARGE RESISTANCE
TA = 25°C, VO = 1.05 V, continuous mode
757
753
765
773
777
TA = 0°C to 85°C, VO = 1.05 V, continuous
VFBTH
VFB threshold voltage
mode(1)
mV
TA = –20°C to 85°C, VO = 1.05 V, continuous
751
779
mode(1)
IVFB
VFB input current
VFB = 0.8 V, TA = 25°C
0
±0.1
μA
RDischg
VO discharge resistance
EN = 0 V, VO = 0.5 V, TA = 25°C
50
100
Ω
VREG5 OUTPUT
TA = 25°C, 7.0 V < VIN < 18 V,
0 < IVREG5 < 5 mA
VVREG5
VREG5 output voltage
5.3
5.5
5.7
V
VLN5
Line regulation
Load regulation
Output current
7.0 V < VIN < 18 V, IVREG5 = 5 mA
0 mA < IVREG5 < 5 mA
20
mV
mV
mA
VLD5
100
IVREG5
MOSFET
Rdsonh
Rdsonl
VIN = 7 V, VREG5 = 4 V, TA = 25°C
70
High side switch resistance
Low side switch resistance
25°C, VBST - SW1,2 = 5.5 V
25°C
63
55
mΩ
mΩ
(1) Not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VIN = 12V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT LIMIT
Iocl Current limit
THERMAL SHUTDOWN
LOUT = 1.5 μH(2), TA = -20ºC to 85ºC
5.2
5.9
8.0
A
(2)
Shutdown temperature
165
30
TSDN
Thermal shutdown threshold
°C
(2)
Hysteresis
ON-TIME TIMER CONTROL
TON
On time
VIN = 12 V, VO = 1.05 V
145
260
ns
ns
TOFF(MIN)
Minimum off time
TA = 25°C, VFB = 0.7 V
310
2.6
SOFT START
ISSC SS charge current
ISSD SS discharge current
POWER GOOD
VSS = 0 V
1.4
0.1
2.0
0.2
μA
VSS = 0.5 V
mA
VFB rising (good)
VFB falling (fault)
PG = 0.5 V
85
2.5
115
60
90
85
5
95
%
%
VTHPG
IPG
PG threshold
PG sink current
mA
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
Output OVP trip threshold
Output OVP prop delay
OVP detect
120
10
125
70
%
μs
%
TOVPDEL
UVP detect
Hysteresis
65
VUVP
Output UVP trip threshold
10
%
TUVPDEL
TUVPEN
UVLO
Output UVP delay
0.25
x 1.7
ms
Output UVP enable delay
Relative to soft-start time
Wake up VREG5 voltage
Hysteresis VREG5 voltage
3.5
3.8
4.1
VUVLO
UVLO threshold
V
0.23
0.35
0.47
(2) Not production tested.
4
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SLVSAS1 –FEBRUARY 2011
DEVICE INFORMATION
PWP PACKAGE
(TOP VIEW)
VO
14
1
VIN2
2
VIN1 13
VFB
VREG5
SS
3
4
5
12
VBST
POWER PAD
TPS54429
PWP
11
SW2
HTSSOP14
SW1 10
GND
PG
6
7
PGND2 9
8
EN
PGND1
PIN FUNCTIONS
PIN
DESCRIPTION
NAME
VO
NO.
1
Connect to output of converter. This terminal is used for On-Time Adjustment.
VFB
2
Converter feedback input. Connect to output voltage with feedback resistor divider.
5.5 V power supply output. A capacitor (typical 1 µF) should be connected to GND. VREG5 is not active
when EN is low.
VREG5
3
SS
4
5
6
7
Soft-start control. A external capacitor should be connected to GND.
Signal ground pin
GND
PG
Open drain power good output
EN
Enable control input. EN is active high and must be pulled up to enable the device.
Ground returns for low-side MOSFET. Also serve as inputs of current comparators. Connect PGND and
GND strongly together near the IC.
PGND1, PGND2
SW1, SW2
VBST
8, 9
10, 11
12
Switch node connection between high-side NFET and low-side NFET. Also serve as inputs to current
comparators.
Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to
respective SW1, SW2 terminals. An internal PN diode is connected between VREG5 to VBST pin.
Power input and connected to high side NFET drain. Supply input for 5-V internal linear regulator for the
control circuitry.
VIN1, VIN2
PowerPAD™
13, 14
Back side
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Should be connected
to PGND.
© 2011, Texas Instruments Incorporated
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SLVSAS1 –FEBRUARY 2011
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FUNCTIONAL BLOCK DIAGRAM
-30%
VIN
UV
OV
VIN2
VIN1
14
13
VO
1
+20%
SS
VREG5
Control Logic
VBST
SW
12
Ref
VFB
VO
11
10
2
VREG5
Ceramic
Capacitor
VREG5
3
GND
PGND
SS
9
8
4
SW
SS
Softstart
OCP
PGND
PGND
GND
PGND
5
GND
GND
VIN
Ref
-10%
PG
6
UV
VREG5
REF
OV
UVLO
TSD
Protection
Logic
UVLO
Ref
EN
EN
7
Logic
6
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SLVSAS1 –FEBRUARY 2011
OVERVIEW
The TPS54429 is a 4.5-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It
operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output
capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low
ESR output capacitors including ceramic and special polymer types.
DETAILED DESCRIPTION
PWM Operation
The main control loop of the TPS54429 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need
for ESR induced output ripple from D-CAP2™ mode control.
PWM Frequency and Adaptive On-Time Control
TPS54429 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54429 runs with a pseudo-constant frequency of 700 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage, therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
Soft Start and Pre-Biased Soft Start
The soft start function is adjustable. When the EN pin becomes high, 2-μA current begins charging the capacitor
which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up.
The equation for the slow start time is shown in Equation 1. VFB voltage is 0.765 V and SS pin source current is
2 μA.
C6(nF) • Vref
C6(nF) • 0.765
Tss(ms) =
=
Iss(µA)
2
(1)
The TPS54429 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting
the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a
cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.
This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and
ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to
normal mode operation.
Power Good
The TPS54429 has a power-good open drain output. The power good function is activated after soft start has
finished. The power good function becomes active after 1.7 times soft-start time. When the output voltage is
within -10% of the target value, internal comparators detect power good state and the power good signal
becomes high. If the PG output is pulled up to VREG5, the resister value, which is connected between PG and
VREG5, must be in the range of 20k ohm to 150k ohm. If the feedback voltage goes under 15% of the target
value, the power good signal becomes low after a 5 μs internal delay.
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VREG5
VREG5 is an internally generated voltage source used by the TPS54429. It is derived directly from the input
voltage and is nominally regulated to 5.5 V when the input voltage is above 5.6 V. The output of the VREG5
regulator is the input to the internal UVLO function. VREG5 must be above the UVLO wake up threshold voltage
(3.8 V typical) for the TPS54429 to function. Connect a 1.0 µF capacitor between pin 3 of the TPS54429 and
power ground for proper regulation of the VREG5 output. The VREG5 output voltage is available for external use
and can typically source up to 70 mA. The VREG5 output is disabled when the TPS54429 EN pin is open or
pulled low.
Output Discharge Control
TPS54429 discharges the output when EN is low, or the controller is turned off by the protection functions (OVP,
UVP, UVLO and thermal shutdown). The output is discharged by an internal 50-Ω MOSFET which is connected
from VO to PGND. The internal low-side MOSFET is not turned on during the output discharge operation to
avoid the possibility of causing negative voltage at the output.
Current Protection
The output over-current protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,
Vout, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iout. If the measured voltage is
above the voltage proportional to the current limit, the device constantly monitors the low-side FET switch
voltage, which is proportional to the switch current, during the low-side on-time. The converter maintains the
low-side switch on until the measured voltage is below the voltage corresponding to the current limit at which
time the switching cycle is terminated and a new switching cycle begins. In subsequent switching cycles, the
on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of over-current protection. The load current is one half of
the peak-to-peak inductor current higher than the over-current threshold. Also when the current is being limited,
the output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. This may cause the output under-voltage protection circuit to be activated. When the over current
condition is removed, the output voltage will return to the regulated value. This protection is non-latching.
Over/Under Voltage Protection
The TPS54429 detects over and undervoltage conditions by monitoring the feedback voltage (VFB). This
function is enabled after approximately 1.7 times the soft-start time. When the feedback voltage becomes higher
than 120% of the target voltage, the OVP comparator output goes high and the circuit latches the high-side
MOSFET driver turns off and the low-side MOSFET turns on. When the feedback voltage becomes lower than
65% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins. After
250 µs, the device latches off both internal top and bottom MOSFET.
UVLO Protection
Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower
than UVLO threshold voltage, the TPS54429 is shut off. This is protection is non-latching.
Thermal Shutdown
Thermal protection is self-activating. If the junction temperature exceeds the threshold value (typically 165°C),
the TPS54429 shuts off. This protection is non-latching.
8
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SLVSAS1 –FEBRUARY 2011
TYPICAL CHARACTERISTICS
VIN CURRENT
vs
VIN SHUTDOWN CURRENT
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
1200
1000
800
8
6
4
2
600
400
200
0
0
-50
-50
0
50
- Junction Temperature - °C
100
150
0
50
- Junction Temperature - °C
100
150
T
T
J
J
Figure 1.
Figure 2.
EN CURRENT
vs
1.05-V OUTPUT VOLTAGE
vs
EN VOLTAGE
OUTPUT CURRENT
100
80
1.08
1.07
1.06
1.05
1.04
60
V = 18 V
I
V = 12 V
I
40
V = 7 V
I
20
0
0
5
10
EN - Input Voltage - V
15
20
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
I
- Output Current - A
O
Figure 3.
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
1.05-V OUTPUT VOLTAGE
vs
1.05-V, 50-mA to 2-A LOAD
TRANSIENT RESPONSE
INPUT VOLTAGE
1.08
1.07
1.06
1.05
1.04
Vout (50 mV/div)
I
= 0 A
O
I
= 1 A
O
Iout (2 A/div)
6
8
10
12
14
16
18
V - Input Voltage - V
I
100 ms/div
Figure 5.
Figure 6.
EFFICIENCY
vs
START-UP WAVE FORM
OUTPUT CURRENT
100
90
80
70
60
50
40
V
= 3.3 V
O
EN (10 V/div)
V
= 2.5 V
O
V
= 1.8 V
O
Vout (0.5 V/div)
PG (5 V/div)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
I
- Output Current - A
400 ms/div
Figure 7.
O
Figure 8.
10
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SLVSAS1 –FEBRUARY 2011
TYPICAL CHARACTERISTICS (continued)
SWITCHING FREQUENCY
SWITCHING FREQUENCY
vs
vs
INPUT VOLTAGE (IO = 1 A)
OUTPUT CURRENT
800
700
600
500
400
800
700
600
500
400
V
= 1.8 V
O
V = 2.5 V
O
V
= 1.8 V
V
= 2.5 V
O
O
V = 3.3 V
O
V
= 3.3 V
O
0
1
2
3
4
6
8
10
12
14
16
18
I
- Output Current - A
V - Input Voltage - V
I
O
Figure 9.
Figure 10.
VOLTAGE RIPPLE AT OUTPUT (IO = 2 A)
VOLTAGE RIPPLE AT INPUT (IO = 2 A)
V
= 1.05 V
V
= 1.05 V
O
O
V (50 mV/div)
I
V
(10 mV/div)
O
SW (5 V/div)
SW (5 V/div)
Figure 11.
Figure 12.
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DESIGN GUIDE
Step By Step Design Procedure
To begin the design process, you must know a few application parameters:
•
•
•
•
•
Input voltage range
Output voltage
Output current
Output voltage ripple
Input voltage ripple
U1
TPS54429PWP
Figure 13. Shows the schematic diagram for this design example.
Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 2 and Equation 3 to calculate VOUT
.
To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more
susceptible to noise and voltage errors from the VFB input current will be more noticeable.
For output voltage from 0.76 V to 2.5 V:
R1
−
1 +
VOUT = 0.765 •
(
)
R2
(2)
(3)
For output voltage over 2.5 V:
R1
R2
¾
VOUT = (0.763 + 0.0017 · VOUT_SET) ·
(1 +
)
Where:
VOUT_SET = Target VOUT voltage.
Output Filter Selection
The output filter used with the TPS54429 is an LC circuit. This LC filter has double pole at:
1
FP =
2p LOUT ´COUT
(4)
12
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At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS54429. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a -40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that
reduces the gain roll off to -20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 4 is located below the high frequency zero but close enough that the phase boost provided be the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 1
Table 1. Recommended Component Values
Output Voltage (V)
R1 (kΩ)
6.81
8.25
12.7
23.2
30.1
49.9
73.2
121
R2 (kΩ)
22.1
22.1
22.1
22.1
22.1
22.1
22.1
22.1
C4 (pF)(1)
L1 (µH)
1.5
C8 + C9 (µF)
22 - 68
22 - 68
22 - 68
22 - 68
22 - 68
22 - 68
22 - 68
22 - 68
1
1.05
1.2
1.5
1.8
2.5
3.3
5
1.5
1.5
1.5
10 - 22
10 - 22
10 - 22
10 - 22
2.2
2.2
2.2
3.3
(1) Optional
For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed forward
capacitor (C4) in parallel with R1
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5,
Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 700 kHz for
fSW
.
Use 700 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 6 and the RMS
current of Equation 7.
VIN (max) - VOUT
VOUT
VIN (max)
•
Ilp - p =
LO • fSW
(5)
(6)
(7)
Ilp - p
2
Ilpeak = IO +
2
IO +
2
1
−
12
ILo(RMS)
=
Ilp - p
For this design example, the calculated peak current is 4.97A and the calculated RMS current is 4.508 A. The
inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating of 11
A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54429 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 22uF to 68uF. Use Equation 8 to
determine the required RMS current rating for the output capacitor.
• (VIN - VOUT)
VOUT
√12 •
ICO(RMS)
=
−
•
• fSW
VIN
LO
(8)
For this design two TDK C3216X5R0J226M 22uF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.271A and each output capacitor is rated for 4A.
Input Capacitor Selection
The TPS54429 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1 µF
capacitor from pin 14 to ground is recommended to improve the stability of the over-current limit function. The
capacitor voltage rating needs to be greater than the maximum input voltage.
© 2011, Texas Instruments Incorporated
13
Product Folder Link(s) :TPS54429
TPS54429
SLVSAS1 –FEBRUARY 2011
www.ti.com
Bootstrap Capacitor Selection
A 0.1 µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is
recommended to use a ceramic capacitor.
VREG5 Capacitor Selection
A 1.0 µF ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is
recommended to use a ceramic capacitor.
THERMAL INFORMATION
This PowerPad™ package incorporates an exposed thermal pad that is designed to be directly to an external
heartsick. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be
used as a heartsick. In addition, through the use of thermal vias, the thermal pad can be attached directly to the
appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a
special heartsick structure designed into the PCB. This design optimizes the heat transfer from the integrated
circuit (IC).
For additional information on the PowerPAD™ package and how to use the advantage of its heat dissipating
abilities, refer to Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No.
SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.
The exposed thermal pad dimensions for this package are shown in the following illustration.
8
14
Thermal Pad
2.46
°
7
1
2.31
Figure 14. Thermal Pad Dimensions
14
© 2011, Texas Instruments Incorporated
Product Folder Link(s) :TPS54429
TPS54429
www.ti.com
SLVSAS1 –FEBRUARY 2011
LAYOUT CONSIDERATIONS
1. Keep the input switching current loop as small as possible.
2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin of the device.
3. Keep analog and non-switching components away from switching components.
4. Make a single point connection from the signal ground to power ground.
5. Do not allow switching current to flow under the device.
6. Keep the pattern lines for VIN and PGND broad.
7. Exposed pad of device must be connected to PGND with solder.
8. VREG5 capacitor should be placed near the device, and connected PGND.
9. Output capacitor should be connected to a broad pattern of the PGND.
10. Voltage feedback loop should be as short as possible, and preferably with ground shield.
11. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to SGND.
12. Providing sufficient via is preferable for VIN, SW and PGND connection.
13. PCB pattern for VIN, SW, and PGND should be as broad as possible.
14. VIN Capacitor should be placed as near as possible to the device.
VIN
Additional
Thermal
Vias
VIN
INPUT
BYPASS
CAPACITOR
VIN OVER
CURRENT
STABILITY
CAPACITOR
EXPOSED
POWERPAD
AREA
FEEDBACK
RESISTORS
VOUT
VFB
VREG5
SS
VIN2
VIN1
BOOST
CAPACITOR
VBST
SW1
VOUT
BIAS
CAP
GND
PG
SW2
OUTPUT
INDUCTOR
OUTPUT
FILTER
CAPACITOR
PGND1
PGND2
SLOW
START
CAP
EN
Connection to
POWER GROUND
on internal or
ANALOG
GROUND
TRACE
Additional
Thermal
Vias
bottom layer
To Enable
Control
POWER GROUND
VIA to Ground Plane
Etch on Bottom Layer
or Under Component
Figure 15. PCB Layout
© 2011, Texas Instruments Incorporated
15
Product Folder Link(s) :TPS54429
PACKAGE OPTION ADDENDUM
www.ti.com
17-Jun-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS54429PWP
ACTIVE
ACTIVE
HTSSOP
HTSSOP
PWP
PWP
14
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TPS54429PWPR
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jun-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54429PWPR
TPS54429PWPR
HTSSOP PWP
HTSSOP PWP
14
14
2000
2000
330.0
330.0
12.4
12.4
6.9
6.9
5.6
5.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jun-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS54429PWPR
TPS54429PWPR
HTSSOP
HTSSOP
PWP
PWP
14
14
2000
2000
346.0
346.0
346.0
346.0
29.0
29.0
Pack Materials-Page 2
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