TPS54622-EP [TI]
增强型产品 17V、6A 同步降压转换器;
| 型号： | TPS54622-EP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 增强型产品 17V、6A 同步降压转换器 转换器 |
| 文件： | 总45页 (文件大小：2424K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS54622-EP
ZHCSMS3 –DECEMBER 2020
TPS54622-EP 17V 输入、6A 输出同步降压转换开关
1 特性
3 说明
• 集成26mΩ和19mΩ金属氧化物半导体场效应晶
体管(MOSFET)
• 分离电源轨：PVIN 上的电压为1.6V 至17V
• 200kHz 至1.6MHz 开关频率
• 与外部时钟同步
• 过热条件下具有0.6V ±1% 的电压基准
• 断续电流限制
• 单调启动至预偏置输出
• 可调节慢启动和电源排序
• 针对欠压和过压问题的电源正常输出监控
• 可调输入欠压锁定
TPS54622-EP 器件采用热增强型 3.5mm × 3.5mm
VQFN 封装，是一款功能齐全的 17V、6A 同步降压转
换器； 该器件具有高效率且集成了高侧和低侧
MOSFET，经过优化可实现小型设计。通过采用电流
模式控制来减少元件数量，同时选择高开关频率来缩小
电感器尺寸，从而进一步节省空间。
输出电压启动斜坡由 SS/TR 引脚控制，该引脚既支持
独立电源运行，又支持跟踪模式。此外，正确配置使能
与开漏电源良好引脚也可实现电源定序。
高侧 FET 的逐周期电流限制可在过载情况下保护器
件，并通过低侧拉电流限制防止电流失控，增强限制效
果。此外，还提供可关闭低侧 MOSFET 的低侧灌电流
限制，防止反向电流过大。当过流持续时间超出预设时
间时，将触发间断保护。当裸片温度超过热关断温度
时，热断续保护功能将禁用该器件，并在内置热关断断
续时间后重新启用该部件。
• 与TPS54620 引脚兼容
• 要查看SWIFT™ 文档，请访问http://www.ti.com/
swift
• 使用TPS54622-EP 并借助WEBENCH® Power
Designer 创建定制设计方案
2 应用
器件信息
封装(1)
• 高密度分布式电源系统
• 高性能负载点稳压
封装尺寸（标称值）
器件型号
• 宽带、网络及光纤通信基础设施
• 支持国防、航天和医疗应用
– 受控基线
TPS54622-EP
VQFN (14)
3.50mm × 3.50mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 同一组装和测试场所
– 同一制造场所
– 额定温度为–55°C 至125°C
– 延长的产品生命周期
– 延长的产品变更通知
– 产品可追溯性
100
90
VIN
CBOOT
VIN
BOOT
PH
LO
VOUT
EN
80
PWRGD
R1
VSENSE
70
SS
RT/CLK
COMP
R2
R3
60
VIN = 8V
VIN = 12V
VIN = 17V
GND
PowerPad
CSS RRT C1
50
C2
0
0.5
1
1.5
2
2.5
3
3.5
Load Current (A)
4
4.5
5
5.5 6
效率与负载电流间的关系
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSFN6
TPS54622-EP
ZHCSMS3 –DECEMBER 2020
www.ti.com.cn
Table of Contents
8.1 Application Information............................................. 24
8.2 Typical Application.................................................... 24
9 Power Supply Recommendations................................33
10 Layout...........................................................................33
10.1 Layout Guidelines................................................... 33
10.2 Layout Examples.................................................... 34
10.3 Estimated Circuit Area............................................ 35
11 Device and Documentation Support..........................36
11.1 Device Support........................................................36
11.2 Documentation Support.......................................... 36
11.3 接收文档更新通知................................................... 36
11.4 支持资源..................................................................36
11.5 Trademarks............................................................. 36
11.6 静电放电警告...........................................................36
11.7 术语表..................................................................... 36
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configurations and Functions.................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................5
6.6 Typical Characteristics................................................8
7 Detailed Description......................................................11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram.........................................12
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................20
8 Application and Implementation..................................24
Information.................................................................... 37
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
December 2020
*
Initial release.
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5 Pin Configurations and Functions
RT/CLK
1
PWRGD
14
GND 2
GND 3
PVIN 4
PVIN 5
VIN 6
13 BOOT
12 PH
Exposed
Thermal Pad
(15)
11 PH
10 EN
9 SS/TR
8
7
VSENSE
COMP
图5-1. RHL Package 14-Pin VQFN With Exposed Thermal Pad Top View
表5-1. Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
NO.
A bootstrap cap is required between BOOT and PH. The voltage on this cap carries the gate drive
voltage for the high-side MOSFET.
BOOT
13
I
Error amplifier output, and input to the output switch current comparator. Connect frequency
compensation to this pin.
COMP
8
O
EN
10
2, 3
I
Enable pin. Float to enable. Adjust the input undervoltage lockout with two resistors.
Return for control circuitry and low-side power MOSFET.
The switch node.
GND
PH
G
O
P
11, 12
4, 5
PVIN
Power input. Supplies the power switches of the power converter.
Power Good fault pin. Asserts low if output voltage is low due to thermal shutdown, dropout, over-
voltage, EN shutdown or during slow start.
PWRGD
RT/CLK
14
1
G
I
Automatically selects between RT mode and CLK mode. An external timing resistor adjusts the switching
frequency of the device; In CLK mode, the device synchronizes to an external clock.
Slow start and tracking. An external capacitor connected to this pin sets the internal voltage reference
rise time. The voltage on this pin overrides the internal reference. It can be used for tracking and
sequencing.
SS/TR
9
O
VIN
6
7
P
I
Supplies the control circuitry of the power converter.
Inverting input of the gm error amplifier.
VSENSE
Exposed
Thermal
PAD
15
G
Thermal pad of the package and signal ground and it must be soldered down for proper operation.
(1) I = input, O = output, G = GND, P = Power
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating junction temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0
MAX
UNIT
VIN
20
PVIN
EN
20
6
BOOT
27
Input Voltage
VSENSE
COMP
3
V
3
PWRGD
6
SS/TR
3
RT/CLK
6
BOOT-PH
PH
7.5
20
–1
Output Voltage
V
PH 10-ns Transient
PH 5-ns Transient
20
–3
20
0.2
–4
Vdiff (GND to exposed thermal pad)
RT/CLK
V
µA
A
–0.2
±100
Source Current
PH
Current Limit
Current Limit
Current Limit
±200
PH
A
PVIN
COMP
PWRGD
A
Sink Current
µA
mA
°C
°C
5
–0.1
–55
–65
Operating Junction Temperature
Storage Temperature, Tstg
150
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-
C101(2)
500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
4.5
1.6
0
NOM
MAX UNIT
Input voltage
VIN
17
17
V
V
Power stage input voltage
Output current
PVIN
6
A
Operating junction temperature, TJ
150
°C
–55
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6.4 Thermal Information
TPS54622-EP
THERMAL METRIC(1) (2)
RHL (VQFN)
14 PINS
47.2
UNIT
RθJA
RθJA
RθJCtop
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-ambient thermal resistance (3)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
32
64.8
14.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.5
14.7
ψJB
RθJCbot
3.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below
150°C for best performance and long-term reliability. See the power dissipation estimate in the application section of this datasheet for
more information.
(3) Test Board Conditions:
•
•
•
•
2.5 inches × 2.5 inches, 4 layers, thickness: 0.062 inch
2 oz. copper traces located on the top of the PCB
2 oz. copper ground planes on the 2 internal layers of and the bottom layer
4 0.010 inch thermal vias located under the device package
6.5 Electrical Characteristics
TJ = –55°C to 150°C, VIN = 4.5 V to 17 V, PVIN = 1.6 V to 17 V (unless otherwise noted)
PARAMETER
SUPPLY VOLTAGE (VIN AND PVIN PINS)
VIN internal UVLO threshold
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN rising
4
150
2
4.5
V
VIN internal UVLO hysteresis
mV
μA
μA
VIN shutdown supply Current
EN = 0 V
5
VSENSE = 810 mV
600
800
VIN operating –non switching supply current
ENABLE AND UVLO (EN PIN)
Enable threshold
Rising
1.22
1.18
1.08
3.2
1.26
V
Enable threshold
Falling
1.1
Input current
EN = 1.1 V
EN = 1.3 V
μA
μA
Hysteresis current
VOLTAGE REFERENCE
Voltage reference
0.594
0.6
0.606
V
0 A ≤IOUT ≤6 A
MOSFET
High-side switch resistance
High-side switch resistance(1)
Low-side Switch Resistance(1)
ERROR AMPLIFIER
BOOT-PH = 3 V
BOOT-PH = 6 V
VIN = 12 V
32
26
19
60
40
30
mΩ
mΩ
mΩ
–2 μA < ICOMP < 2 μA, V(COMP)
1 V
=
Error amplifier Transconductance (gm)
Error amplifier dc gain
1300
3100
±125
0.25
μMhos
V/V
VSENSE = 0.6 V
1000
V(COMP) = 1 V, 100-mV input
overdrive
Error amplifier source/sink
Start switching threshold
μA
V
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6.5 Electrical Characteristics (continued)
TJ = –55°C to 150°C, VIN = 4.5 V to 17 V, PVIN = 1.6 V to 17 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
COMP to Iswitch gm
16
A/V
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6.5 Electrical Characteristics (continued)
TJ = –55°C to 150°C, VIN = 4.5 V to 17 V, PVIN = 1.6 V to 17 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT LIMIT
High-side switch current limit threshold
Low-side switch sourcing current limit
Low-side switch sinking current limit
Hiccup wait time
8
6.5
2
11
10
14
15
4
A
A
3
A
512
16384
Cycles
Cycles
Hiccup time before re-start
THERMAL SHUTDOWN
Thermal shutdown(2)
Thermal shutdown hysteresis(2)
Thermal shutdown hiccup time(2)
160
175
10
°C
°C
16384
Cycles
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Minimum switching frequency
Switching frequency
160
400
200
480
1600
20
240
560
kHz
kHz
kHz
ns
Rrt = 240 kΩ (1%)
Rrt = 100 kΩ (1%)
Rrt = 29 kΩ (1%)
Maximum switching frequency
Minimum pulse width
1500
1900
RT/CLK high threshold
RT/CLK low threshold
2
V
0.7
V
Measure at 500 kHz with RT resistor
in series
RT/CLK falling edge to PH rising edge delay
66
ns
Switching frequency range (RT mode set point
and CLK mode)
200
1600
kHz
PH (PH PIN)
Measured at 90% to 90% of VIN,
25°C, IPH = 2A
Minimum on-time
100
2.3
145
3
ns
V
BOOT (BOOT PIN)
BOOT-PH UVLO
SLOW START AND TRACKING (SS/TR PIN)
SS charge current
2.14
16
μA
SS/TR to VSENSE matching
POWER GOOD (PWRGD PIN)
V(SS/TR) = 0.4 V
60
mV
VSENSE falling (Fault)
VSENSE rising (Good)
VSENSE rising (Fault)
VSENSE falling (Good)
VSENSE = Vref, V(PWRGD) = 5.5 V
V(PWRGD) = 0.3V
92
94
% Vref
% Vref
% Vref
% Vref
nA
VSENSE threshold
111
109
30
Output high leakage
100
Output low sink current
2
mA
Minimum VIN for valid output
Minimum SS/TR voltage for PWRGD
0.6
1
V
V(PWRGD) < 0.5 V at 100 μA
1.4
V
(1) Measured at pins.
(2) Specified by design. Not production tested.
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6.6 Typical Characteristics
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
VIN = 12V ; VBOOT-SW = 6V
VIN = 12V
-75
-50
-25
0
Junction Temperature (°C)
25
50
75
100 125 150
-75
-50
-25
0
Junction Temperature (°C)
25
50
75
100 125 150
图6-1. High-Side RDS(on) vs Temperature
图6-2. Low-Side RDS(on) vs Temperature
0.606
0.605
0.604
0.603
0.602
0.601
0.6
490
485
480
475
470
0.599
0.598
0.597
0.596
0.595
0.594
RT = 100kW
100 125 150
-75
-50
-25
0
25
50
Junction Temperature (°C)
75
100 125 150
-75
-50
-25
0
25
Junction Temperature (°C)
50
75
图6-3. Voltage Reference vs Temperature
图6-4. Oscillator Frequency vs Temperature
3.5
3.25
3
3.4
3.35
3.3
2.75
2.5
2.25
2
3.25
3.2
1.75
1.5
1.25
1
VIN = 4.5V ; VEN = 0V
VIN = 12V ; VEN = 0V
VIN = 17V ; VEN = 0V
3.15
3.1
0.75
VIN = 12V ; VEN = 1.3V
0.5
-75
-50
-25
0
Junction Temperature (°C)
25
50
75
100 125 150
-75
-50
-25
0
Junction Temperature (°C)
25
50
75
100 125 150
图6-5. Shutdown Quiescent Current vs Temperature
图6-6. EN Pin Hysteresis Current vs Temperature
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6.6 Typical Characteristics (continued)
1.2
1.18
1.16
1.14
1.12
1.1
1.25
1.24
1.23
1.22
1.21
1.2
1.08
1.06
1.04
1.02
1.19
1.18
1.17
1.16
1.15
Rising
Falling
VIN = 12V ; VEN = 1.1V
1
-75
-50
-25
0
Junction Temperature (°C)
25
50
75
100 125 150
-75
-50
-25
0
Junction Temperature (°C)
25
50
75
100 125 150
图6-7. EN Pin Pullup Current vs Temperature
图6-8. EN Pin UVLO Threshold vs Temperature
2.2
800
750
700
650
600
550
500
450
400
2.15
2.1
2.05
2
VIN = 4.5V
VIN = 12V
VIN = 17V
-75
-50
-25
0
25
50
Junction Temperature (°C)
75
100 125 150
-75
-50
-25
0
25
50
Junction Temperature (°C)
75
100 125 150
图6-10. Slow Start Charge Current vs Temperature
图6-9. Non-Switching Operating Quiescent Current vs
Temperature
26
24
22
20
18
16
14
12
10
120
115
110
105
100
95
90
85
Low Rising
High Rising
High Falling
Low Falling
80
75
70
-75
-50
-25
0
Junction Temperature (°C)
25
50
75
100 125 150
-75
-50
-25
0
Junction Temperature (°C)
25
50
75
100 125 150
图6-11. (SS/TR - VSENSE) Offset vs Temperature
图6-12. PWRGD Threshold vs Temperature
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6.6 Typical Characteristics (continued)
13
12.8
12.6
12.4
12.2
12
120
110
100
90
11.8
11.6
11.4
11.2
11
10.8
10.6
VIN = 4.5V
VIN = 12V
VIN = 17V
10.4
10.2
10
VIN = 12V
80
-75
-75
-50
-25
0
25
50
Junction Temperature (°C)
75
100 125 150
-50
-25
0
25
50
Junction Temperature (°C)
75
100 125 150
图6-13. High-Side Current Limit Threshold vs Temperature
图6-14. Minimum Controllable On-Time vs Temperature
8
7.5
7
2.4
2.38
2.36
2.34
2.32
2.3
6.5
6
2.28
2.26
2.24
2.22
2.2
5.5
5
2.18
2.16
2.14
2.12
2.1
4.5
RT = 100kW ; VIN = 12V
4
-75
-50
-25
0
25
50
Junction Temperature (°C)
75
100 125 150
-75
-50
-25
0
25
50
Junction Temperature (°C)
75
100 125 150
图6-15. Minimum Controllable Duty Ratio vs Temperature
图6-16. BOOT-PH UVLO Threshold vs Temperature
12
10
8
6
VIN = 12V, TA = 25èC
4
0
2
4
6
8
10
Input voltage PVIN (V)
12
14
16 17
图6-17. Overcurrent Threshold vs Input Voltage
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7 Detailed Description
7.1 Overview
The TPS54622-EP device is a 17-V, 6-A, synchronous step-down (buck) converter with two integrated N-
channel MOSFETs. To improve performance during line and load transients the device implements a constant
frequency, peak current mode control which also simplifies external frequency compensation. The wide switching
frequency of 200 kHz to 1600 kHz allows for efficiency and size optimization when selecting the output filter
components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The device also
has an internal phase lock loop (PLL) controlled by the RT/CLK pin that can be used to synchronize the
switching cycle to the falling edge of an external system clock.
The device has been designed for safe monotonic start-up into prebiased loads. The default start-up is when
VIN is typically 4 V. The EN pin has an internal pullup current source that can be used to adjust the input voltage
undervoltage lockout (UVLO) with two external resistors. In addition, the EN pin can be floating for the device to
operate with the internal pullup current. The total operating current for the device is approximately 600 μA when
not switching and under no load. When the device is disabled, the supply current is typically less than 2 μA.
The integrated MOSFETs allow for high-efficiency power supply designs with continuous output currents up to 6
amperes. The MOSFETs have been sized to optimize efficiency for lower duty cycle applications.
The device reduces the external component count by integrating the boot recharge circuit. The bias voltage for
the integrated high-side MOSFET is supplied by a capacitor between the BOOT and PH pins. The boot capacitor
voltage is monitored by a BOOT to PH UVLO (BOOT-PH UVLO) circuit allowing PH pin to be pulled low to
recharge the boot capacitor. The device can operate at 100% duty cycle as long as the boot capacitor voltage is
higher than the preset BOOT-PH UVLO threshold which is typically 2.1 V. The output voltage can be stepped
down to as low as the 0.6-V voltage reference (Vref).
The device has a power good comparator (PWRGD) with hysteresis which monitors the output voltage through
the VSENSE pin. The PWRGD pin is an open-drain MOSFET which is pulled low when the VSENSE pin voltage
is less than 92% or greater than 106% of the reference voltage Vref and asserts high when the VSENSE pin
voltage is 94% to 104% of the Vref.
The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor or resistor divider should be coupled to the pin for slow start or critical
power supply sequencing requirements.
The device is protected from output overvoltage, overload, and thermal fault conditions. The device minimizes
excessive output overvoltage transients by taking advantage of the overvoltage circuit power good comparator.
When the overvoltage comparator is activated, the high-side MOSFET is turned off and prevented from turning
on until the VSENSE pin voltage is lower than 104% of the Vref. The device implements both high-side MOSFET
overload protection and bidirectional low-side MOSFET overload protections which help control the inductor
current and avoid current runaway. The device also shuts down if the junction temperature is higher than thermal
shutdown trip point. The device is restarted under control of the slow start circuit automatically after the built-in
thermal shutdown hiccup time.
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7.2 Functional Block Diagram
PWRGD EN
VIN
PVIN
UV
Thermal
Shutdown
UVLO
i1
iHYS
Logic
Enable
Comparator
OV
Shutdown
Logic
Boot
Charge
Hiccup
Shutdown
Voltage
Reference
Enable
Threshold
Boot
UVLO
VSENSE
SS
+
+
BOOT
OV
Minimum
COMP Clamp
Shutdown
Logic
HS FET
Current
Comparator
Dead Time
Logic and
PWM Latch
COMP
PH
Slope
Compensation
VIN
Regulator
LS FET
Current
Limit
Overload
Recovery
Maximum
Clamp
OSC with
PLL
GND
Hiccup
Shutdown
RT/CLK
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Fixed-Frequency PWM Control
The device uses a adjustable fixed-frequency, peak current mode control. The output voltage is compared
through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives
the COMP pin. An internal oscillator initiates the turnon of the high-side power switch. The error amplifier output
is converted into a current reference which compares to the high-side power switch current. When the power
switch current reaches current reference generated by the COMP voltage level the high-side power switch is
turned off and the low-side power switch is turned on.
7.3.2 Continuous Current Mode Operation (CCM)
As a synchronous buck converter, the device normally works in continuous conduction mode (CCM) under all
load conditions.
7.3.3 VIN and Power VIN Pins (VIN and PVIN)
The device allows for a variety of applications by using the VIN and PVIN pins together or separately. The VIN
pin voltage supplies the internal control circuits of the device. The PVIN pin voltage provides the input voltage to
the power converter system.
If tied together, the input voltage for VIN and PVIN can range from 4.5 V to 17 V. If using the VIN separately from
PVIN, the VIN pin must be from 4.5 V to 17 V, and the PVIN pin can range from as low as 1.6 V to 17 V. A
voltage divider connected to the EN pin can adjust the either input voltage UVLO appropriately. Adjusting the
input voltage UVLO on the PVIN pin helps to provide consistent power-up behavior.
7.3.4 Voltage Reference
The voltage reference system produces a precise ±1% voltage reference overtemperature by scaling the output
of a temperature stable bandgap circuit.
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7.3.5 Adjusting the Output Voltage
The output voltage is set with a resistor-divider from the output (VOUT) to the VSENSE pin. TI recommends
using 1% tolerance or better divider resistors. Referring to the application schematic of 图8-1, start with a 10 kΩ
for R6 and use 方程式 1 to calculate R5. To improve efficiency at light loads, consider using larger value
resistors. If the values are too high, the regulator is more susceptible to noise and voltage errors from the
VSENSE input current and are noticeable.
Vo - Vref
R5 =
R6
Vref
(1)
where
• Vref = 0.6 V
The minimum output voltage and maximum output voltage can be limited by the minimum on-time of the high-
side MOSFET and bootstrap voltage (BOOT-PH voltage) respectively. More discussions are located in Minimum
Output Voltage and Bootstrap Voltage (BOOT) and Low Dropout Operation.
7.3.6 Safe Start-Up Into Prebiased Outputs
The device has been designed to prevent the low-side MOSFET from discharging a prebiased output. During
monotonic prebiased startup, the low-side MOSFET is not allowed to sink current until the SS/TR pin voltage is
higher than 1.4 V.
7.3.7 Error Amplifier
The device uses a transconductance error amplifier. The error amplifier compares the VSENSE pin voltage to
the lower of the SS/TR pin voltage or the internal 0.6-V voltage reference. The transconductance of the error
amplifier is 1300 μA/V during normal operation. The frequency compensation network is connected between the
COMP pin and ground.
7.3.8 Slope Compensation
The device adds a compensating ramp to the switch current signal. This slope compensation prevents sub-
harmonic oscillations. The available peak inductor current remains constant over the full duty cycle range.
7.3.9 Enable and Adjusting Undervoltage Lockout
The EN pin provides electrical on/off control of the device. Once the EN pin voltage exceeds the threshold
voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters low Iq state.
The EN pin has an internal pullup current source, allowing the user to float the EN pin for enabling the device. If
an application requires controlling the EN pin, use open-drain or open collector output logic to interface with the
pin.
The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage
falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 150 mV.
If an application requires either a higher UVLO threshold on the VIN pin or a secondary UVLO on the PVIN, in
split rail applications, then the EN pin can be configured as shown in 图 7-1, 图 7-2, and 图 7-3. When using the
external UVLO function, TI recommends setting the hysteresis to be greater than 500 mV.
The EN pin has a small pullup current Ip which sets the default state of the pin to enable when no external
components are connected. The pullup current is also used to control the voltage hysteresis for the UVLO
function since it increases by Ih once the EN pin crosses the enable threshold. The UVLO thresholds can be
calculated using Equation 2 and Equation 3.
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VIN
IP
IH
R1
R2
EN
+
Copyright © 2016, Texas Instruments Incorporated
图7-1. Adjustable VIN Undervoltage Lockout
PVIN
IP
IH
R1
R2
EN
+
Copyright © 2016, Texas Instruments Incorporated
图7-2. Adjustable PVIN Undervoltage Lockout, VIN ≥4.5 V
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VIN
IP
IH
R1
R2
EN
+
Copyright © 2016, Texas Instruments Incorporated
图7-3. Adjustable VIN and PVIN Undervoltage Lockout
æ
ç
è
ö
÷
ø
VENFALLING
VENRISING
VSTART
- VSTOP
R1 =
æ
ö
÷
ø
VENFALLING
I
1-
+I
p ç
h
VENRISING
è
(2)
(3)
R1´ VENFALLING
VSTOP - VENFALLING + R1(Ip + Ih )
R2 =
where
• Ih = 3.4 μA
• Ip = 1.15 μA
• VENRISING = 1.21 V
• VENFALLING = 1.17 V
7.3.10 Adjustable Switching Frequency and Synchronization (RT/CLK)
The RT/CLK pin can be used to set the switching frequency of the device in two modes.
In RT mode, a resistor (RT resistor) is connected between the RT/CLK pin and GND. The switching frequency of
the device is adjustable from 200 kHz to 1600 kHz by placing a maximum of 240 kΩ and minimum of 29 kΩ
respectively. In CLK mode, an external clock is connected directly to the RT/CLK pin. The device is synchronized
to the external clock frequency with PLL.
The CLK mode overrides the RT mode. The device is able to detect the proper mode automatically and switch
from the RT mode to CLK mode.
7.3.11 Slow Start (SS/TR)
The device uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the reference
voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow start
time. The device has an internal pullup current source of 2.3 μA that charges the external slow-start capacitor.
The calculations for the slow start time (tSS, 10% to 90%) and slow-start capacitor (Css) are shown in Equation
4. The voltage reference (Vref) is 0.6 V and the slow start charge current (Iss) is 2.3 μA.
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Css (nF) ´ Vref (V)
tSS (ms) =
Iss (µA)
(4)
When the input UVLO is triggered, the EN pin is pulled below 1.21 V, or a thermal shutdown event occurs the
device stops switching and enters low current operation. At the subsequent power up, when the shutdown
condition is removed, the device does not start switching until it has discharged its SS/TR pin to ground ensuring
proper soft start behavior.
7.3.12 Power Good (PWRGD)
The PWRGD pin is an open-drain output. Once the VSENSE pin is between 94% and 104% of the internal
voltage reference the PWRGD pin pulldown is deasserted and the pin floats. TI recommends using a pullup
resistor from the values of 10 kΩ to 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD is in a defined
state once the VIN input voltage is greater than 1 V but with reduced current sinking capability. The PWRGD
achieves full current sinking capability once the VIN input voltage is above 4.5 V.
The PWRGD pin is pulled low when VSENSE is lower than 92% or greater than 106% of the nominal internal
reference voltage. Also, the PWRGD is pulled low, if the input UVLO or thermal shutdown are asserted, the EN
pin is pulled low or the SS/TR pin is below 1.4 V.
7.3.13 Output Overvoltage Protection (OVP)
The device incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot. For
example, when the power supply output is overloaded the error amplifier compares the actual output voltage to
the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a
considerable time, the output of the error amplifier demands maximum output current. Once the condition is
removed, the regulator output rises and the error amplifier output transitions to the steady state voltage. In some
applications with small output capacitance, the power supply output voltage can respond faster than the error
amplifier. This leads to the possibility of an output overshoot. The OVP feature minimizes the overshoot by
comparing the VSENSE pin voltage to the OVP threshold. If the VSENSE pin voltage is greater than the OVP
threshold the high-side MOSFET is turned off preventing current from flowing to the output and minimizing
output overshoot. When the VSENSE voltage drops lower than the OVP threshold, the high-side MOSFET is
allowed to turn on at the next clock cycle.
7.3.14 Overcurrent Protection
The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side
MOSFET and the low-side MOSFET.
7.3.14.1 High-Side MOSFET Overcurrent Protection
The device implements current mode control which uses the COMP pin voltage to control the turnoff of the high-
side MOSFET and the turnon of the low-side MOSFET on a cycle-by-cycle basis. Each cycle the switch current
and the current reference generated by the COMP pin voltage are compared, when the peak switch current
intersects the current reference the high-side switch is turned off.
7.3.14.2 Low-Side MOSFET Overcurrent Protection
While the low-side MOSFET is turned on its conduction current is monitored by the internal circuitry. During
normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side
MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side
sourcing current is exceeded the high-side MOSFET is not turned on and the low-side MOSFET stays on for the
next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing
current limit at the start of a cycle.
The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded the
low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are
off until the start of the next cycle.
Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than
the hiccup wait time which is programmed for 512 switching cycles, the device will shut down itself and restart
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after the hiccup time of 16384 cycles. The hiccup mode helps to reduce the device power dissipation under
severe overcurrent conditions.
7.3.15 Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
175°C typically. Once the junction temperature drops below 165°C typically, the internal thermal hiccup timer will
start to count. The device reinitiates the power-up sequence after the built-in thermal shutdown hiccup time
(16384 cycles) is over.
7.3.16 Small Signal Model for Loop Response
图 7-4 shows an equivalent model for the device control loop which can be modeled in a circuit simulation
program to check frequency response and transient responses. The error amplifier is a transconductance
amplifier with a gm of 1300 μA/V. The error amplifier can be modeled using an ideal voltage controlled current
source. The resistor ROUT(ea) (2.38 MΩ) and capacitor COUT(ea) (20.7 pF) model the open loop gain and
frequency response of the error amplifier. The 1-mV AC voltage source between the nodes a and b effectively
breaks the control loop for the frequency response measurements. Plotting a/c and c/b show the small signal
responses of the power stage and frequency compensation respectively. Plotting a/b shows the small signal
response of the overall loop. The dynamic loop response can be checked by replacing the RL with a current
source with the appropriate load step amplitude and step rate in a time domain analysis.
PH
VOUT
Power Stage
16 A/V
a
RESR
b
R1
RLOAD
VSENSE
COUT
COMP
c
+
0.6 V
R2
COUT(ea)
gM
1300 µA/V
R3
C1
C2
ROUT(ea)
Copyright © 2016, Texas Instruments Incorporated
图7-4. Small Signal Model for Loop Response
7.3.17 Simple Small Signal Model for Peak Current Mode Control
图 7-5 is a simple small signal model that can be used to understand how to design the frequency
compensation. The device power stage can be approximated to a voltage controlled current source (duty cycle
modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is
shown in Equation 5 and consists of a DC gain, one dominant pole and one ESR zero. The quotient of the
change in switch current and the change in COMP pin voltage (node c in 图 7-4) is the power stage
transconductance (gmps) which is 16 A/V for the device. The DC gain of the power stage is the product of gmps
and the load resistance RL) as shown in Equation 6 with resistive loads. As the load current increases, the DC
gain decreases. This variation with load may seem problematic at first glance, but fortunately the dominant pole
moves with load current (see Equation 7). The combined effect is highlighted by the dashed line in 图7-6. As the
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load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover
frequency the same for the varying load conditions which makes it easier to design the frequency compensation.
VC
RESR
RLOAD
COUT
gm(ps)
Copyright © 2016, Texas Instruments Incorporated
图7-5. Simplified Small Signal Model for Peak Current Mode Control
Adc
f
P
f
Z
Frequency
图7-6. Simplified Frequency Response for Peak Current Mode Control
æ
ç
è
s
ö
÷
ø
1+
2p ´ ¦z
VOUT
VC
= Adc ´
æ
ö
÷
ø
s
1+
ç
2p ´ ¦p
è
(5)
(6)
Adc = gmps ´ RL
where
• gmps is the power stage gain (16 A/V).
• RL is the load resistance.
1
¦p =
C
´ R ´ 2p
L
O
(7)
where
• CO is the output capacitance.
• RL is the load resistance.
1
¦z =
C
´ R
´ 2p
ESR
O
(8)
where
• CO is the output capacitance.
• RESR is the equivalent series resistance of the output capacitor.
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7.3.18 Small Signal Model for Frequency Compensation
The device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly
used Type II compensation circuits and a Type III frequency compensation circuit, as shown in 图 7-7. In Type
2A, one additional high-frequency pole, C6, is added to attenuate high frequency noise. In Type III, one
additional capacitor, C11, is added to provide a phase boost at the crossover frequency. See Designing Type III
Compensation for Current Mode Step-Down Converters for a complete explanation of Type III compensation.
The design guidelines below are provided for advanced users who prefer to compensate using the general
method. The following equations only apply to designs whose ESR zero is above the bandwidth of the control
loop. This is usually true with ceramic output capacitors. See Application and Implementation for a step-by-step
design procedure using higher ESR output capacitors with lower ESR zero frequencies.
VOUT
R8
R9
C11
VSENSE
COMP
gM(ea)
Type III
+
VREF
R4
C4
R4
C4
C6
COUT(ea) ROUT(ea)
Type IIB
Type IIA
Copyright © 2016, Texas Instruments Incorporated
图7-7. Types of Frequency Compensation
The general design guidelines for device loop compensation are as follows:
1. Determine the crossover frequency, fc. A good starting point is 1/10th of the switching frequency, fsw.
2. R4 can be determined by:
2p ´ ¦c ´ VOUT ´ Co
R4 =
gmea ´ Vref ´ gmps
(9)
where
• gmea is the GM amplifier gain (1300 μA/V).
• gmps is the power stage gain (16 A/V).
• Vref is the reference voltage (0.6 V).
æ
ç
è
ö
÷
ø
1
¦p =
CO ´ RL ´ 2p
3. Place a compensation zero at the dominant pole:
C4 can be determined by:
RL ´ Co
C4 =
R4
(10)
4. C6 is optional. It can be used to cancel the zero from the equivalent series resistance (ESR) of the output
capacitor CO.
RESR ´ Co
C6 =
R4
(11)
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5. Type III compensation can be implemented with the addition of one capacitor, C11. This allows for slightly
higher loop bandwidths and higher phase margins. If used, C11 is calculated from Equation 12.
1
C11=
2×p ×R8×fc
(
)
(12)
7.4 Device Functional Modes
7.4.1 Adjustable Switching Frequency (RT Mode)
To determine the RT resistance for a given switching frequency, use Equation 13 or the curve in 图 7-8. To
reduce the solution size one would set the switching frequency as high as possible, but tradeoffs of the supply
efficiency and minimum controllable on-time should be considered.
-0.997
)
Rrt(kW) = 48000 ×Fsw kHz
(
- 2
(13)
250
200
150
100
50
0
200
400
600
800
1000
1200
1400
1600
Fsw − Oscillator Frequency − kHz
图7-8. RT Set Resistor vs Switching Frequency
7.4.2 Synchronization (CLK Mode)
An internal phase locked loop (PLL) has been implemented to allow synchronization from 200 kHz to 1600 kHz,
and to easily switch from RT mode to CLK mode.
To implement the synchronization feature, connect a square wave clock signal to the RT/CLK pin with a duty
cycle from 20% to 80%. The clock signal amplitude must transition lower than 0.8 V and higher than 2 V. The
start of the switching cycle is synchronized to the falling edge of RT/CLK pin.
In applications where both RT mode and CLK mode are needed, the device can be configured as shown in 图
7-9. Before the external clock is present, the device works in RT mode and the switching frequency is set by RT
resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the SYNC pin
is pulled above the RT/CLK high threshold (2 V), the device switches from the RT mode to the CLK mode and
the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. TI
does not recommended switching from the CLK mode back to the RT mode because the internal switching
frequency drops to 100 kHz first before returning to the switching frequency set by RT resistor.
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RT/CLK Mode Select
RT/CLK
RRT
Copyright © 2016, Texas Instruments Incorporated
图7-9. Works With Both RT Mode and CLK Mode
7.4.3 Bootstrap Voltage (BOOT) and Low Dropout Operation
The device has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH
pins to provide the gate drive voltage for the high-side MOSFET. The boot capacitor is charged when the BOOT
pin voltage is less than VIN and BOOT-PH voltage is below regulation. The value of this ceramic capacitor
should be between 0.1 μF and 1 μF. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric
with a voltage rating of 10 V or higher because of the stable characteristics over temperature and voltage.
To improve drop out, the device is designed to operate at 100% duty cycle as long as the BOOT to PH pin
voltage is greater than the BOOT-PH UVLO threshold which is typically 2.1 V. When the voltage between BOOT
and PH drops below the BOOT-PH UVLO threshold, the high-side MOSFET is turned off and the low-side
MOSFET is turned on allowing the boot capacitor to be recharged. In applications with split input voltage rails,
100% duty cycle operation can be achieved as long as (VIN –PVIN) > 4 V.
7.4.4 Sequencing (SS/TR)
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD
pins.
The sequential method is illustrated in 图 7-10 using two TPS54622-EP-EP devices. The power good of the first
device is coupled to the EN pin of the second device which enables the second power supply once the primary
supply reaches regulation.
TPS54622-EP
PWRGD
TPS54622-EP
EN
EN
SS/TR
PWRGD
SS/TR
Copyright © 2020, Texas Instruments Incorporated
图7-10. Sequential Start-Up Sequence
图 7-11 shows the method implementing ratiometric sequencing by connecting the SS/TR pins of two devices
together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow start
time the pullup current source must be doubled in Equation 4.
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TPS54622-EP
EN
TPS54622-EP
EN
SS
SS
PWRGD
PWRGD
CSS
Copyright © 2020, Texas Instruments Incorporated
图7-11. Ratiometric Start-Up Sequence
Ratiometric and simultaneous power supply sequencing can be implemented by connecting the resistor network
of R1 and R2 shown in 图 7-12 to the output of the power supply that needs to be tracked or another voltage
reference source. Using Equation 14 and Equation 15, the tracking resistors can be calculated to initiate the
Vout2 slightly before, after or at the same time as Vout1. Equation 16 is the voltage difference between Vout1
and Vout2.
To design a ratiometric start-up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2
reaches regulation, use a negative number in Equation 14 and Equation15 for deltaV. Equation 16 results in a
positive number for applications where the Vout2 is slightly lower than Vout1 when Vout2 regulation is
achieved. .
The deltaV variable is zero volt for simultaneous sequencing. To minimize the effect of the inherent SS/TR to
VSENSE offset (Vssoffset, 29 mV) in the slow start circuit and the offset created by the pullup current source
(Iss, 2.3 μA) and tracking resistors, the Vssoffset and Iss are included as variables in the equations.
To ensure proper operation of the device, the calculated R1 value from Equation 14 must be greater than the
value calculated in Equation 17.
Vout2 + DV
Vssoffset
Iss
R1 =
´
Vref
(14)
Vref ´ R1
Vout2 + DV - Vref
R2 =
(15)
(16)
(17)
DV = Vout1 - Vout2
R1> 2800´ Vout1-180´DV
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TPS54622-EP
EN
VOUT(1)
SS
PWRGD
CSS
TPS54622-EP
VOUT(2)
EN
SS
R1
R3
R4
R2
PWRGD
Copyright © 2020, Texas Instruments Incorporated
图7-12. Ratiometric and Simultaneous Start-Up Sequence
There are two final considerations when using a resistor divider to the SS/TR pin for simultaneous start-up. First,
as described in Power Good (PWRGD), for the PWRGD output to be active the SS/TR voltage must be above
1.4 V. The external divider may prevent the SS/TR voltage from charging above the threshold. For the SS/TR pin
to charge above the threshold, an external MOSFET may be needed to disconnect the resistor divider or modify
the resistor divider ratio after start-up is complete. The PWRGD pin of the VOUT(1) converter could be used to
turn on or turn off the external MOSFET. Second, a pre-bias on VOUT(1) may prevent VOUT(2) from turning on.
When the TPS54622-EP is enabled, an internal 700-Ω MOSFET at the SS/TR pin turns on to discharge the
SS/TR voltage as described in Slow Start (SS/TR). The SS/TR pin voltage must discharge below 20 mV before
the TPS54622-EP starts up. If the upper resistor at the SS/TR pin is too small, the SS/TR pin does not discharge
below the threshold, and VOUT(2) does not ramp up. The upper resistor in the SS/TR divider may need to be
increased to allow the SS/TR pin to discharge below the threshold.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPS54622-EP device is a highly integrated synchronous step-down DC-DC converter. This device is used
to convert a higher DC input voltage to a lower DC output voltage with a maximum output current of 6 A.
8.2 Typical Application
The application schematic of 图 8-1 was developed to meet the requirements above. This circuit is available as
the TPS54622-EP evaluation module. The design procedure is given in this section. For more information about
Type II and Type III frequency compensation circuits, see Designing Type III Compensation for Current Mode
Step-Down Converters and design calculator (SLVC219).
U1
TPS54622-EP
R3
100k
C3
0.1 µF
1
2
3
4
5
6
7
14
13
12
11
10
9
L1
3.3 ꢀH
RT/CLK
PWRGD
BOOT
PH
GND
GND
PVIN
PVIN
VIN
VOUT = 3.3V, 6A
VOUT
VIN = 8-17V
PH
R5
10k
C8
Optional
EN
EN
C7
100 µF
SS/TR
COMP
C1
10 µF
8
VSNS
VSNS
VSNS
R1
35.7k
R3
3.74k
15
R7
2.21k
EN
C2
4.7 µF
C5
47pF
C6
0.022 µF
R2
8.06k
C4
0.01 µF
图8-1. Typical Application Circuit
8.2.1 Design Requirements
This example details the design of a high-frequency switching regulator design using ceramic output capacitors.
A few parameters must be known to start the design process. These parameters are typically determined at the
system level. For this example, begin with the known parameters listed in 表8-1.
表8-1. Design Parameters
DESIGN PARAMETER
Output voltage
EXAMPLE VALUE
3.3 V
Output current
6 A
Transient response 1-A load step
Input voltage
ΔVOUT = 5%
12 V nominal, 8 V to 17 V
33 mV p-p
Output voltage ripple
Start input voltage (rising VIN)
Stop input voltage (falling VIN)
Switching frequency
6.528 V
6.190 V
480 kHz
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8.2.2 Detailed Design Procedures
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS54622-EP device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Operating Frequency
The first step is to decide on a switching frequency for the regulator. There is a trade off between higher and
lower switching frequencies. Higher switching frequencies may produce smaller a solution size using lower
valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency.
However, the higher switching frequency causes extra switching losses, which hurt the converter’s efficiency
and thermal performance. In this design, a moderate switching frequency of 480 kHz is selected to achieve both
a small solution size and a high-efficiency operation.
8.2.2.3 Output Inductor Selection
To calculate the value of the output inductor, use Equation 18. KIND is a coefficient that represents the amount
of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the
output capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor
since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In
general, the inductor ripple value is at the discretion of the designer; however, KIND is normally from 0.1 to 0.3
for the majority of applications.
Vinmax - Vout
Io ×Kind
Vout
L1 =
×
Vinmax × f sw
(18)
For this design example, use KIND = 0.3 and the inductor value is calculated to be 3.08 µH. For this design, a
nearest standard value was chosen: 3.3 µH. For the output filter inductor, it is important that the RMS current
and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation
20 and Equation 21.
Vinmax - Vout
Vout
Iripple =
×
L1
Vinmax × f sw
(19)
æ
ö2
V × Vinmax - Vo
(
)
1
o
ILrms = Io2 +
ILpeak = Iout +
×
ç
ç
÷
÷
12
Vinmax×L1× f sw
è
ø
(20)
(21)
Iripple
2
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For this design, the RMS inductor current is 6.02 A and the peak inductor current is 6.84 A. The chosen inductor
is a Coilcraft MSS1048 series 3.3 µH. It has a saturation current rating of 7.38 A and a RMS current rating of
7.22 A.
The current flowing through the inductor is the inductor ripple current plus the output current. During power-up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
8.2.2.4 Output Capacitor Selection
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the more stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator can not. This situation would occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator is also temporarily not able to supply
sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from
no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change
in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be
sized to supply the extra current to the load until the control loop responds to the load change. The output
capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a
tolerable amount of droop in the output voltage. Equation 22 shows the minimum output capacitance necessary
to accomplish this.
2×DIout
Co >
f sw ×DVout
(22)
where
• ΔIout is the change in output current.
• fSW is the regulators switching frequency.
• ΔVout is the allowable change in the output voltage.
For this example, the transient load response is specified as a 5% change in Vout for a load step of 1 A. For this
example, ΔIout = 3 A and ΔVout = 0.05 × 3.3 = 0.165 V. Using these numbers gives a minimum capacitance of
75.8 μF. This value does not take the ESR of the output capacitor into account in the output voltage change.
For ceramic capacitors, the ESR is usually small enough to ignore in this calculation.
Equation 23 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fsw is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. In this case, the maximum output voltage ripple is 33 mV. Under this requirement,
Equation 23 yields 13.2 µF.
1
1
Co >
×
Voripple
Iripple
8× f sw
(23)
Equation 24 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 24 indicates the ESR should be less than 19.7 mΩ. In this case, the ESR of the ceramic
capacitors is much smaller than 19.7 mΩ.
Voripple
Resr <
Iripple
(24)
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Additional capacitance deratings for aging, temperature and DC bias should be factored in which increases this
minimum value. For this example, a 100-μF, 6.3-V X5R ceramic capacitor with 3 mΩ of ESR is be used.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 25 can be used
to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 25 yields
485 mA.
Vout × Vinmax - Vout
(
12 ×Vinmax×L1× f sw
)
Icorms =
(25)
8.2.2.5 Input Capacitor Selection
The TPS54622-EP requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7
µF of effective capacitance on the PVIN input voltage pins and 4.7 µF on the Vin input voltage pin. In some
applications, additional bulk capacitance may also be required for the PVIN input. The effective capacitance
includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input
voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the
TPS54622-EP. The input ripple current can be calculated using Equation 26.
Vinmin - Vout
(
)
Vout
Icirms = Iout ×
×
Vinmin
Vinmin
(26)
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor
decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at
least a 25 V voltage rating is required to support the maximum input voltage. For this example, one 10 μF and
one 4.7 µF 25-V capacitors in parallel have been selected as the VIN and PVIN inputs are tied together so the
TPS54622-EP may operate from a single supply. The input capacitance value determines the input ripple
voltage of the regulator. The input voltage ripple can be calculated using Equation 27. Using the design example
values, Ioutmax = 6 A, Cin = 14.7 μF, Fsw = 480 kHz, yields an input voltage ripple of 213 mV and a RMS input
ripple current of 2.95 A.
Ioutmax ×0.25
DVin =
Cin× f sw
(27)
8.2.2.6 Slow-Start Capacitor Selection
The slow-start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is very large and would require large amounts of current to quickly charge
the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS54622-EP reach the current limit or excessive current draw from the input power supply may cause the input
voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The soft-start capacitor
value can be calculated using Equation 28. For the example circuit, the soft-start time is not too critical since the
output capacitor value is 100 μF which does not require much current to charge to 3.3 V. The example circuit
has the soft-start time set to an arbitrary value of 6 ms which requires a 22-nF capacitor. In TPS54622-EP, Iss is
2.3 uA and Vref is 0.6 V.
Tss(ms)×Iss(mA)
C6(nF) =
Vref(V)
(28)
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8.2.2.7 Bootstrap Capacitor Selection
A 0.1-µF to 1-μF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. TI
recommends using a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10-V or
higher voltage rating.
8.2.2.8 Undervoltage Lockout Setpoint
The undervoltage lockout (UVLO) can be adjusted using the external voltage divider network of R3 and R4. R3
is connected between VIN and the EN pin of the TPS54622-EP and R4 is connected between EN and GND. The
UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or
brownouts when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 6.528 V (UVLO start or enable). After the regulator starts
switching, it should continue to do so until the input voltage falls below 6.19 V (UVLO stop or disable). Equation
2 and Equation 3 can be used to calculate the values for the upper and lower resistor values. For the stop
voltages specified, the nearest standard resistor value for R3 is 35.7 kΩ and for R4 is 8.06 kΩ.
8.2.2.9 Output Voltage Feedback Resistor Selection
The resistor-divider network R5 and R6 is used to set the output voltage. For the example design, 10 kΩ was
selected for R5. Using Equation 29, R6 is calculated as 2.22 kΩ. The nearest standard 1% resistor is 2.21 kΩ.
R5×Vref
R6 =
Vo - Vref
(29)
8.2.2.9.1 Minimum Output Voltage
Due to the internal design of the TPS54622-EP, there is a minimum output voltage limit for any given input
voltage. The output voltage can never be lower than the internal voltage reference of 0.6 V. Above 0.6 V, the
output voltage may be limited by the minimum controllable on-time. The minimum output voltage in this case is
given by Equation 30:
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Voutmin = Ontimemin×Fsmax Vinmax +Ioutmin RDS2min -RDS1min -Ioutmin RL +RDS2min
(
(
)
)
)
(
(30)
where
• Voutmin = minimum achievable output voltage
• Ontimemin = minimum controllable on-time (135-ns maximum)
• Fsmax = maximum switching frequency including tolerance
• Vinmax = maximum input voltage
• Ioutmin = minimum load current
• RDS1min = minimum high-side MOSFET ON-resistance (36-32-mΩ typical)
• RDS2min = minimum low-side MOSFET ON-resistance (19-mΩ typical)
• RL = series resistance of output inductor
8.2.2.10 Compensation Component Selection
There are several industry techniques used to compensate DC-DC regulators. The method presented here is
easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin from 60
to 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the
TPS54622-EP. Since the slope compensation is ignored, the actual crossover frequency is usually lower than
the crossover frequency used in the calculations.
First, the modulator pole, fpmod, and the ESR zero, fzmod, must be calculated using Equation 31 and Equation
32. For Cout, use a derated value of 75 µF. Use Equation 33 and Equation 34 to estimate a starting point for the
closed loop crossover frequency, fco. Then the required compensation components may be derived. For this
design example, fpmod is 3.86 kHz and fzmod is 707.4 kHz. Equation 33 is the geometric mean of the modulator
pole and the ESR zero and Equation 34 is the geometric mean of the modulator pole and one half the switching
frequency. Use a frequency near the lower of these two values as the intended crossover frequency, fco. In this
case Equation 33 yields 52.2 kHz and Equation 34 yields 30.4 kHz. The lower value is 30.4 kHz. A slightly higher
frequency of 30 kHz is chosen as the intended crossover frequency.
Iout
f pmod =
2×p ×Vout ×Cout
(31)
1
f zmod =
2 ×p ×RESR ×Cout
(32)
(33)
f co = f pmod× f zmod
f sw
f co = f pmod×
2
(34)
Now the compensation components can be calculated. First calculate the value for R2 which sets the gain of the
compensated network at the crossover frequency. Use Equation 35 to determine the value of R2.
2p × f c × Vout×Cout
R4 =
gmea ×Vref ×gmps
(35)
Next calculate the value of C3. Together with R2, C3 places a compensation zero at the modulator pole
frequency. Equation 36 to determine the value of C3.
Vout ×Cout
C4 =
Iout ×R4
(36)
Using Equation 35 and Equation 36 the standard values for R4 and C4 are 3.74 kΩ and 0.01 µF.
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An additional high-frequency pole can be used if necessary by adding a capacitor in parallel with the series
combination of R4 and C4. The pole frequency can be placed at the ESR zero frequency of the output capacitor
as given by Equation 8. Use Equation 37 to calculate the required capacitor value for C5.
RESR×Cout
C5 =
R4
(37)
8.2.2.11 Fast Transient Considerations
In applications where fast transient responses are very important, Type III frequency compensation can be used
instead of the traditional Type II frequency compensation.
For more information about Type II and Type III frequency compensation circuits, see Designing Type III
Compensation for Current Mode Step-Down Converters and design calculator (SLVC219).
8.2.3 Application Curves
VOUT = 100 mV / div (dc coupled, -3.13 V offset)
VIN = 5 V / div
IOUT = 2 A / div
VOUT = 1 V / div
Load step = 1.5 A to 4.5 A Slew rate = 100 mA / µsec
Time = 200 µsec / div
Time = 2 msec / div
图8-2. Load Transient
图8-3. Start-Up With VIN
VIN = 5 V / div
VIN = 10 V / div
VOUT = 2 V / div
EN = 2 V / div
VOUT = 2 V / div
PH = 10 V / div
Time = 2 msec / div
Time = 2 msec / div
图8-5. Start-Up With PRE-BIAS
图8-4. Start-Up With EN
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VOUT = 20 mV / div (ac coupled)
VIN = 500 mV / div
PH = 5 V / div
PH = 5 V / div
Time = 1 µsec / div
Time = 1 µsec / div
图8-6. Output Voltage Ripple With No Load
图8-7. Input Voltage Ripple With Full Load
60
50
180
0.4
150
120
90
0.3
Phase
40
30
0.2
IOUT = 3 A
20
60
0.1
0
10
30
0
0
Gain
-10
-20
-30
-40
-50
-60
-30
-60
-90
-120
-150
-180
-0.1
-0.2
-0.3
-0.4
100
1000
10000
100000
1000000
8
9
10
11
12
13
14
15
16
17
Frequency - Hz
Input Voltage - V
图8-8. Closed Loop Response
图8-9. Line Regulation
0.4
0.3
0.2
0.1
0
10
1
10
Vout
1
VIN = 12 V
0.1
0.1
Ideal Vsense
Vsense
0.01
0.01
0.001
-0.1
-0.2
-0.3
-0.4
0.001
0.0001
0.00001
0.0001
0.00001
0.001
0.01
0.1
Track In Voltage - V
1
10
0
1
2
3
4
5
6
Output Current - A
图8-10. Load Regulation
图8-11. Tracking Performance
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100
90
80
70
60
50
VIN = 8V
VIN = 12V
VIN = 17V
0
0.5
1
1.5
2
2.5
3
3.5
Load Current (A)
4
4.5
5
5.5
6
VIN = 12 V
IOUT = 6 A
图8-13. Thermal Image
图8-12. Efficiency vs Load Current
150
150
125
100
T
= room temperature,
A
no air flow
125
100
75
50
25
75
50
25
V
V
= 12 V,
IN
= 3.3 V,
OUT
Fsw = 480 kHz,
room temp, no air flow
0
0.5
1
1.5
2
2.5
3
Pic - IC Power Dissipation - W
3.5
4
0
1
2
3
4
Load Current - A
5
6
图8-14. Junction Temperature vs IC Power
图8-15. Maximum Ambient Temperature vs Load
Dissipation
Current
150
Tjmax = 150 °C,
no air flow
VOUT = 2 V / div
125
100
PH = 10 V / div
Inductor Current = 5 A / div
75
50
25
Time = 20 msec / div
0
0.5
1
1.5
2
2.5
3
- IC Power Dissipation - W
3.5
4
图8-17. Hiccup Mode Current Limit
P
D
图8-16. Maximum Ambient Temperature vs IC
Power Dissipation
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9 Power Supply Recommendations
The TPS54622-EP is designed to operate from an input voltage supply range from 4.5 V to 17 V. This supply
voltage must be well regulated. Power supplies must be well bypassed for proper electrical performance. This
includes a minimum of one 4.7-µF (after derating) ceramic capacitor, type X5R or better from PVIN to GND, and
from VIN to GND. Additional local ceramic bypass capacitance may be required in systems with small input
ripple specifications, in addition to bulk capacitance if the TPS54622-EP device is located more than a few
inches away from its input power supply. In systems with an auxiliary power rail available, the power stage input,
PVIN, and the analog power input, VIN, may operate from separate input supplies. See 图 10-1 for
recommended bypass capacitor placement.
10 Layout
10.1 Layout Guidelines
• Layout is a critical portion of good power supply design. See 图10-1 for a PCB layout example.
• The top layer contains the main power traces for VIN, VOUT, and VPHASE. Also on the top layer are
connections for the remaining pins of the TPS54622-EP and a large top-side area filled with ground.
• Connect the top layer ground area to the internal ground layers using vias at the input bypass capacitor, the
output filter capacitor, and directly under the TPS54622-EP device to provide a thermal path from the
exposed thermal pad land to ground.
• Tie the GND pin directly to the power pad under the IC and the power pad.
• For operation at full rated load, the top side ground area together with the internal ground plane, must provide
adequate heat dissipating area.
• There are several signals paths that conduct fast changing currents or voltages that can interact with stray
inductance or parasitic capacitance to generate noise or degrade the power supplies performance.
• To help eliminate these problems, the PVIN pin should be bypassed to ground with a low ESR ceramic
bypass capacitor with X5R or X7R dielectric.
• Care should be taken to minimize the loop area formed by the bypass capacitor connections, the PVIN pins,
and the ground connections.
• The VIN pin must also be bypassed to ground using a low ESR ceramic capacitor with X5R or X7R dielectric.
• Make sure to connect this capacitor to the quite analog ground trace rather than the power ground trace of
the PVIn bypass capacitor.
• Since the PH connection is the switching node, the output inductor should be located close to the PH pins,
and the area of the PCB conductor minimized to prevent excessive capacitive coupling.
• The output filter capacitor ground should use the same power ground trace as the PVIN input bypass
capacitor.
• Try to minimize this conductor length while maintaining adequate width.
• The small signal components should be grounded to the analog ground path as shown.
• The RT/CLK pin is sensitive to noise so the RT resistor must be located as close as possible to the IC and
routed with minimal lengths of trace.
• The additional external components can be placed approximately as shown.
• It may be possible to obtain acceptable performance with alternate PCB layouts, however, this layout has
been shown to produce good results and is meant as a guideline.
• Land pattern and stencil information is provided in the data sheet addendum.
• The dimension and outline information is for the standard RHL (S-PVQFN-N14) package.
• There may be slight differences between the provided data and actual lead frame used on the TPS54622-
EPRHL package.
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10.2 Layout Examples
TOPSIDE
GROUND
AREA
FREQUENCY SET RESISTOR
OUTPUT
FILTER
CAPACITOR
PVIN
INPUT
BYPASS
CAPACITOR
RT/CLK
PWRGD
BOOT
CAPACITOR
GND
GND
PVIN
PVIN
VIN
BOOT
PH
OUTPUT
INDUCTOR
EXPOSED THERMAL
PAD AREA
PH
VOUT
PH
EN
SS/TR
COMP
VSENSE
PVIN
VIN
SLOW START
CAPACITOR
UVLO SET
RESISTORS
VIN
INPUT
BYPASS
CAPACITOR
COMPENSATION
NETWORK
FEEDBACK
RESISTORS
ANALOG GROUND TRACE
0.010 in. Diameter
Thermal VIA to Ground Plane
VIA to Ground Plane
Etch Under Component
图10-1. PCB Layout
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图10-2. Ultra-Small PCB Layout Using TPS54622-EP (PMP4854-2)
10.3 Estimated Circuit Area
The estimated printed-circuit-board area for the components used in the design of 图 8-1 is 0.58 in2 (374 mm2).
This area does not include test points or connectors.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
For the Design Calculator, see SLVC219.
11.1.2 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS54622-EP-EP device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
Designing Type III Compensation for Current Mode Step-Down Converters
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2021 Texas Instruments Incorporated
36
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Product Folder Links: TPS54622-EP
TPS54622-EP
ZHCSMS3 –DECEMBER 2020
www.ti.com.cn
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: TPS54622-EP
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS54622RHLREP
V62/20607-01XE
ACTIVE
ACTIVE
VQFN
VQFN
RHL
RHL
14
14
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-55 to 125
-55 to 125
4622EP
4622EP
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Dec-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54622RHLREP
VQFN
RHL
14
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Dec-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RHL 14
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
TPS54622RHLREP
3000
Pack Materials-Page 2
PACKAGE OUTLINE
RHL0014A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
3.65
3.35
B
A
PIN 1 INDEX AREA
3.65
3.35
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2.05 0.1
2X 1.5
SYMM
(0.2) TYP
7
8
2X (0.325)
6
9
SYMM
15
2X 2
8X 0.5
13
0.30
0.18
14X
2
0.1
C A B
C
PIN 1 ID
(45 X 0.3)
0.05
1
14
0.5
0.3
4X 0.2
2X 0.55
14X
4228405/A 01/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHL0014A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.05)
(0.845)
4X (0.2)
1
METAL UNDER
SOLDER MASK
14
14X (0.6)
SOLDER MASK OPENING
13
2
14X (0.24)
4X
(R0.12)
(0.845)
8X (0.5)
15
SYMM
(3.3)
(2.05)
(
0.2) TYP
VIA
(R0.05) TYP
6
9
2X (0.525)
7
8
SYMM
(0.55)
(1.5)
(3.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4228405/A 01/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHL0014A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X (0.2)
2X (0.73)
1
(0.56)
14
14X (0.6)
2X (0.205)
4X (R0.12)
13
2
14X (0.24)
4X (0.92)
(0.56)
SYMM
8X (0.5)
15
(3.3)
4X (0.92)
(R0.05) TYP
6
9
7
8
SYMM
(0.55)
(1.5)
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
79% PRINTED COVERAGE BY AREA
SCALE: 25X
4228405/A 01/2022
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
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TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
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Copyright © 2022，德州仪器 (TI) 公司
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