TPS54678RTER [TI]
2.95 V to 6 V INPUT, 6 A OUTPUT, 2 MHz, SYNCHRONOUS STEP DOWN SWITCHER WITH INTEGRATED FET ( SWIFTâ¢); 2.95 V至6 V输入， 6 A输出， 2兆赫，具有集成FET的同步降压切换器（ SWIFTâ ?? ¢ ）
| 型号： | TPS54678RTER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.95 V to 6 V INPUT, 6 A OUTPUT, 2 MHz, SYNCHRONOUS STEP DOWN SWITCHER WITH INTEGRATED FET ( SWIFTâ¢) |
| 文件： | 总37页 (文件大小：1647K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS54678
www.ti.com
SLVSBF3 –JUNE 2012
2.95 V to 6 V INPUT, 6 A OUTPUT, 2 MHz, SYNCHRONOUS STEP DOWN SWITCHER WITH
INTEGRATED FET ( SWIFT™)
Check for Samples: TPS54678
1
FEATURES
DESCRIPTION
TPS54678 device is a full featured 6 V, 6 A,
synchronous step down current mode converter with
two integrated MOSFETs.
2
•
Two 12 mΩ (typical) MOSFETs for High
Efficiency 6 A Continuous Output Current
•
•
200 kHz to 2 MHz Switching Frequency
TPS54678 enables small designs by integrating the
MOSFETs, implementing current mode control to
reduce external component count, reducing inductor
size by enabling up to 2 MHz switching frequency,
and minimizing the IC footprint with a small 3 mm x 3
mm thermally enhanced QFN package.
0.6 V ±1% Voltage Reference Over
Temperature (-40°C to 150°C)
•
•
•
•
•
Synchronizes to External Clock
Start up with Pre-Biased Voltage
Power Good Output
TPS54678 provides accurate regulation for a variety
of loads with an accurate ±1% Voltage Reference
(VREF) over temperature.
Adjustable Slow Start and Sequencing
Cycle-by-Cycle Current Limit and Hiccup
Current Protection
Efficiency is maximized through the integrated 12 mΩ
MOSFETs. Using the enable pin, shutdown supply
current is reduced by disabling the device.
•
•
Adjustable Input Voltage UVLO
Thermally Enhanced 16-Pin 3 mm x 3 mm QFN
(RTE)
The output voltage startup ramp is controlled by the
soft start pin that can also be configured for
sequencing or tracking. Monotonic startup is achieved
with pre-biased voltage. Under voltage lockout can be
increased by programming the threshold with a
resistor divider on the enable pin. An open drain
power good signal indicates the output is within 93%
to 105% of its nominal voltage.
APPLICATIONS
•
•
Low-Voltage, High-Density Power Systems
Point of Load Regulation for High Performance
DSPs, FPGAs, ASICs and Microprocessors
•
•
•
Broadband, Networking and Optical
Communications Infrastructure
Gaming, DTV and Set-Top Boxes
Cycle-by-cycle current limit, hiccup overcurrent
protection and thermal shutdown protect the device
during an overcurrent condition.
95
94
93
92
91
90
89
88
VIN
VIN
TPS54678
CI
CBOOT
BOOT
EN
LO
VOUT
PH
PWRGD
CO
R1
VOUT = 1.8 V
Fsw = 500 KHz
DCR = 7.5 mΩ
87
86
85
VIN = 3.3 V
VIN = 5 V
VSENSE
GND
SS/TR
RT/CLK
COMP
1
2
3
4
5
6
R2
Current (A)
G020
CSS
R3
RT
C1
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
SWIFT, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
TPS54678
SLVSBF3 –JUNE 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TJ
PACKAGE
PART NUMBER
-40°C to 150°C
3 x 3 mm QFN
TPS54678RTE
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
MAX
7
UNIT
MIN
-0.3
-0.3
VIN
V
V
EN
7
BOOT
PH + 7
3
V
VSENSE
-0.3
-0.3
-0.3
-0.3
-0.3
V
Input Voltage
COMP
3
V
PWRGD
SS/TR
6
V
3
V
RT/CLK
BOOT-PH
6
V
7
V
PH
Output Voltage
-0.7
-2
7
V
PH 20ns Transient
10
V
PH 5ns Transient
-4
12
V
EN
Source Current
100
100
100
10
µA
µA
µA
mA
µA
kV
V
RT/CLK
COMP
Sink Current
PWRGD
SS/TR
100
2
Human Body Model (HBM)
Charged device Model (CDM)
Electrostatic Discharge
500
150
150
Operating Junction Temperature
Storage Temperature
-40
-65
ºC
ºC
(1) Stresses beyond those listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “ELECTRICAL
SPECIFICATIONS” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
THERMAL INFORMATION
TPS54678
THERMAL METRIC(1)
UNITS
RTE (16 PINS)
θJA
Junction-to-ambient thermal resistance
43.2
38.5
14.5
0.4
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
14.5
3.4
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
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SLVSBF3 –JUNE 2012
ELECTRICAL CHARACTERISTICS
TJ = –40°C to +150°C, VIN = 2.95 to 6 V (unless otherwise noted)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating Input Voltage
Shutdown Supply Current
2.95
6
3
V
EN = 0 V, 25°C, 2.95 V ≤ VIN ≤ 6 V
1
µA
Operating– Non switching Supply
Current
VSENSE = 0.6 V, VIN = 5 V, 25°C, fSW = 500 kHz
570
800
µA
ENABLE AND UVLO (EN PIN)
Enable threshold
Rising
1.3
1.18
-3.5
V
V
Enable threshold
Falling
Input current
Enable threshold + 50 mV
Enable threshold – 50 mV
µA
µA
Input current
-0.70
VOLTAGE REFERENCE
Voltage Reference
2.95 V ≤ VIN ≤ 6 V, –40°C < TJ < 150°C
0.594
0.600
0.606
V
MOSFET
High Side Switch Resistance
High Side Switch Resistance
Low Side Switch Resistance
Low Side Switch Resistance
ERROR AMPLIFIER
Input Current
BOOT-PH = 5 V
BOOT-PH = 2.95 V
BOOT-PH = 5 V
BOOT-PH = 2.95 V
12
17
12
17
25
33
25
33
mΩ
mΩ
7
nA
Error amplifier Transconductance (gm)
–2 µA < I(COMP) < 2 µA V(COMP) = 1 V
245
umhos
Error amplifier Transconductance (gm)
during slow start
–2 µA < I(COMP) < 2 µA V(COMP) = 1 V, V(VSENSE)
0.4 V
=
80
umhos
Error amplifier source and sink
COMP to Iswitch gm
V(COMP) = 1V 100 mV Overdrive
±20
20
µA
A/V
CURRENT LIMIT
Current limit threshold
Fs = 500 KHz
9.5
7
10.5
512
16384
8.5
11.5
10.5
A
cycles
cycles
A
Cycles before entering hiccup during OC
Hiccup cycles
Low side sourcing current threshold
Low side Fet reverse current protection
THERMAL SHUTDOWN
Thermal Shutdown
4
A
170
15
°C
°C
Hysteresis
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching Frequency Range using RT
mode
200
400
300
2000
600
kHz
kHz
kHz
Switching Frequency
Rt = 82.5 kΩ
500
Switching Frequency Range using CLK
mode
2000
Minimum CLK Pulse width
RT/CLK voltage
75
0.5
1.6
0.6
ns
V
R(RT/CLK) = 82.5 kΩ
RT/CLK high threshold
RT/CLK low threshold
2.2
V
0.4
V
RT/CLK falling edge to PH rising edge
delay
Measure at 500 kHz with RT resistor in series
Measure at 500 kHz
55
40
ns
us
PLL lock in time
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ELECTRICAL CHARACTERISTICS (continued)
TJ = –40°C to +150°C, VIN = 2.95 to 6 V (unless otherwise noted)
DESCRIPTION
PH (PH PIN)
CONDITIONS
MIN
TYP
MAX
UNIT
Measured at 50% points on PH. IOUT = 3 A
Measured at 50% points on PH. IOUT = 0 A
85
110
ns
ns
Minimum On time
Minimum Off time
100
Prior to skipping off pulses,
BOOT-PH = 3 V, IOUT = 3 A
70
ns
Rise and fall dV/dT
BOOT (BOOT PIN)
Charging Resistor
BOOT-PH UVLO
BOOT-PH = 3V; IO = 6 A
1.5
V/ns
VIN = 6V, BOOT-PH = 6 V
VIN = 3.3 V
7
Ω
2.2
V
SLOW START AND TRACKING (SS/TR PIN)
V(SS/TR) < 0.15 V
47
2.2
60
Charge Current
µA
V(SS/TR) > 0.15 V
VIN = 3.3 V
SS/TR to VSENSE matching
mV
V
SS/TR to Reference Crossover
SS/TR Discharge Voltage (Overload)
SS/TR Discharge to current (Overload)
98% nominal
0.8
4.5
95
VSENSE = 0 V
mV
µA
VSENSE = 0 V; V(SS/TR) = 4 V;
SS/TR Discharge Current (UVLO, EN,
Thermal Fault)
VIN = 3 V; V(SS/TR) = 4 V;
925
µA
POWER GOOD (PWRGD PIN)
VSENSE falling (Fault)
VSENSE rising (Good)
VSENSE rising (Fault)
VSENSE falling (Good)
VSENSE = VREF, V(PWRGD) = 5.5 V
VIN = 5 V
91
93
% VREF
% VREF
% VREF
% VREF
nA
VSENSE Threshold
105
103
2
Output high leakage
On Resistance
65
120
0.3
1.5
Ω
Output low
I(PWRGD) = 2.5 mA
0.2
1.2
V
Minimum VIN for valid output
V(PWRGD) < 0.5V at 100 µA
V
4
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DEVICE INFORMATION
RTE PACKAGE
(TOP VIEW)
16
15
14
13
1
VIN
VIN
12
PH
2
3
11
10
Thermal
Pad
PH
PH
GND
4
9
GND
SS/TR
5
6
7
8
PIN FUNCTIONS
PIN NAME
AGND
NUMBER
DESCRIPTION
5
Analog Ground should be tied to GND close to the device.
BOOT
13
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
minimum required by the output device, the output is forced to switch off until the capacitor is refreshed.
COMP
EN
7
Error amplifier output, and input to the output switch current comparator. Connect frequency
compensation components to this pin.
15
Enable pin, internal pull-up current source. Pull below 1.18 V to disable. Float to enable. Adjust the input
under voltage lockout with two additional resistors.
GND
PH
3, 4
Ground. This pin should be tied directly to the power pad under the IC.
10, 11, 12
The source of the internal high side power MOSFET, and drain of the internal low side
(synchronous)MOSFET.
PowerPAD™
PWRGD
17
14
GND pin must be connected to the exposed power pad for proper operation. This power pad should be
connected to any internal PCB ground plane using multiple vias.
An open drain output. Active if output voltage is low due to thermal shutdown, dropout, over-voltage or
EN shut down.
RT/CLK
SS/TR
8
9
Resistor Timing and External Clock input pin.
Slow-start and Tracking. An external capacitor connected to this pin sets the output rise time. Since the
voltage on this pin overrides the internal reference, it can be used for tracking and sequencing.
VIN
1, 2, 16
6
Input supply voltage, 2.95 V to 6 V.
VSENSE
Inverting node of the (gm) error amplifier.
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FUNCTIONAL BLOCK DIAGRAM
PWRGD
EN
VIN
Shutdown
93%
Thermal
Shutdown
UVLO
Enable
Comparator
Logic
Shutdown
Shutdown
Logic
Enable
Threshold
105 %
Boot
Charge
Voltage
Reference
Boot
UVLO
Current
Sense
Minimum
COMP Clamp
ERROR
AMPLIFIER
PWM
Comparator
VSENSE
SS/TR
BOOT
PWM
Latch
R
Q
Logic
Logic
S
Shutdown
Logic
Slope
Compensation
S
PH
COMP
Maximum
Clamp
Overload
Recovery
Oscillator
with PLL
PGND
TPS54678 Block Diagram
GND
RT/CLK
POWERPAD
Overview
The TPS54678 is a 6-V, 6-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs.
To improve the performance during line and load transients the device implements a constant frequency, peak
current mode control which reduces output capacitance and simplifies external frequency compensation design.
The wide switching frequency range of 200 kHz to 2000 kHz allows for efficiency and size optimization when
selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the
RT/CLK pin. The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the
power switch turn on to a falling edge of an external system clock.
The TPS54678 has a typical default start up voltage of 2.4 V. The EN pin has an internal pull-up current source
that can be used to adjust the input voltage under voltage lockout (UVLO) with two external resistors. In addition,
the pull up current provides a default condition when the EN pin is floating for the device to operate. The total
operating current for the TPS54678 is typically 570 µA when not switching and under no load. When the device
is disabled, the supply current is less than 3 µA.
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The integrated 12 mΩ MOSFETs allow for high efficiency power supply designs with continuous output currents
up to 6 amperes. The TPS54678 reduces the external component count by integrating the boot recharge diode.
The bias voltage for the integrated high side MOSFET is supplied by a capacitor between the BOOT and PH
pins. The boot capacitor voltage is monitored by an UVLO circuit and turns off the high side MOSFET when the
voltage falls below a preset threshold. This BOOT circuit allows the TPS54678 to operate approaching 100%.
The output voltage can be stepped down to as low as the 0.60 V reference.
TPS54678 features monotonic startup under pre-bias conditions. The low side Fet turns on for a short time
period every cycle before the output voltage reaches the pre-biased voltage. This ensures the boot cap has
enough charge to turn on the top Fet when the output voltage reaches the pre-biased voltage.
The TPS54678 has a power good comparator (PWRGD) with 2% hysteresis.
The TPS54678 minimizes excessive output overvoltage transients by taking advantage of the overvoltage power
good comparator. When the regulated output voltage is greater than 105% of the nominal voltage, the
overvoltage comparator is activated, and the high side MOSFET is turned off and masked from turning on until
the output voltage is lower than 103%.
The SS/TR (slow start or tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor should be coupled to the pin for slow start. The SS/TR pin is
discharged before the output power up to ensure a repeatable restart after an overtemperature fault, UVLO fault
or disabled condition. To optimize the output startup waveform, two levels of SS current are implemented.
To reduce the power dissipation of TPS54678 during overcurrent event, the hiccup protection is implemented
beyond the cycle-by-cycle protection.
DETAILED DESCRIPTION
Fixed Frequency PWM Control
The TPS54678 uses a settable fixed frequency, peak current mode control. The output voltage is compared
through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives
the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output
is compared to the high side power switch current. When the power switch current reaches the COMP voltage
level the high side power switch is turned off and the low side power switch is turned on. The COMP pin voltage
will increase and decrease as the output current increases and decreases. The device implements a current limit
by clamping the COMP pin voltage to a maximum level and implements a sleep mode with a minimum clamp.
Slope Compensation and Output Current
The TPS54678 adds a compensating ramp to the switch current signal. This slope compensation prevents sub-
harmonic oscillations. The available peak inductor current maintains constant over the full duty cycle range.
Bootstrap Voltage (BOOT) and Low Dropout Operation
The TPS54678 has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and
PH pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be
0.1 µF. A ceramic capacitor with an X7R or X5R grade dielectric is recommended because of the stable
characteristics over temperature and voltage.
To improve drop out, the TPS54678 is designed to operate at 100% duty cycle as long as the BOOT to PH pin
voltage is greater than 2.2 V. The high side MOSFET is turned off using an UVLO circuit, allowing for the low
side MOSFET to conduct, when the voltage from BOOT to PH drops below 2.2 V. Since the supply current
sourced from the BOOT pin is low, the high side MOSFET can remain on for more switching cycles than are
required to refresh the capacitor, thus the effective duty of the switching regulator is high.
Error Amplifier
The TPS54678 has a transconductance amplifier for the error amplifier. The error amplifier compares the
VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.6 V voltage reference. The
transconductance of the error amplifier is 245 µA/V during normal operation. During the slow start operation, the
transconductance is a fraction of the normal operating gm. The frequency compensation components are added
to the COMP pin to ground.
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Voltage Reference
The voltage reference system produces a precise ±1% voltage reference over temperature by scaling the output
of a temperature stable bandgap circuit. During production, the bandgap and scaling circuits are trimmed to
produce 0.6 V at the amplifier output.
Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to
use 1% tolerance or better divider resistors. Start with a 20 KΩ for the R1 resistor and use the Equation 1 to
calculate R2. To improve efficiency at light loads consider using larger value resistors. If the values are too high
the regulator will be more susceptible to noise and voltage errors from the VSENSE input current will be
noticeable.
æ
ç
ö
÷
0.6 V
- 0.6 V
R2 = R1 ×
ç
÷
V
O
è
ø
(1)
TPS54678
VO
R1
VSENSE
-
R2
0.6 V
+
Figure 1. Voltage Divider Circuit
Enable and Set Up Adjusting Undervoltage Lockout
The EN pin provides electrical on and off control of the device. Once the EN pin voltage exceeds the threshold
voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters low Iq state. If an application requires controlling the EN pin, use open drain or open
collector output logic to interface with the pin.
For input undervoltage lockout (UVLO), use the EN pin as shown in Figure 2 to set up the UVLO by using the
two external resistors. Once the EN pin voltage exceeds 1.3 V, an additional 2.8 µA of hysteresis is added. This
additional current facilitates input voltage hysteresis. Use Equation 2 to set the external hysteresis for the input
voltage. Use Equation 3 to set the input startup voltage. It is recommended that the minimum input shutdown
voltage be set at 2.45 V or higher to ensure proper operation before shutdown.
TPS54678
ih
VIN
2.8 mA
ip
R1
0.7 mA
+
EN
R2
Vena
-
Figure 2. Set Up Input Undervoltage Lock Out.
8
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V
VSTART
(
EN_FALLING ) - VSTOP
VEN_RISING
R1 =
V
I (1 - EN_FALLING ) + I
p
h
VEN_RISING
R1 × VEN_FALLING
VSTOP - VEN_FALLING + R1 × (I + I )
(2)
(3)
R2 =
p
h
Where R1 and R2 are in Ω, Ih = 2.8 µA, Ip = 0.7 µA, VEN_RISING = 1.3 V, VEN_FALLING = 1.18 V.
Slow Start or Tracking Pin (SS/TR)
TPS54678 effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the
power supply’s reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground
will implement a slow start time. The TPS54678 has an internal pull-up current source of 47 µA when V(SS/TR) is
less than 0.15 V and 2.2 µA when V(SS/TR) is higher than 0.15 V. The ISS charges the external slow start
capacitor. The equation for the slow start time is shown in Equation 4 considering the fact the first 47 µA charges
the SS to 0.15 V. The 2.2 µA then charges the SS from 0.15 V to about 0.8 V for the handoff of the SS voltage to
reference voltage.
Css(nF) = 3 ´ Tss(mS)
(4)
If during normal operation, the VIN UVLO is exceeded, EN pin pulled below 1.2 V, or a thermal shutdown event
occurs, the TPS54678 will stop switching and the SS/TR must be discharged to about 60 mV before reinitiating a
powering up sequence.
The VSENSE voltage will follow the SS/TR pin voltage up to 90% of the internal voltage reference. When the
SS/TR voltage is greater than 90% of the internal voltage, the effective system reference voltage will transit from
the SS/TR voltage to the internal voltage reference.
Sequencing
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD
pins. The sequential method can be implemented using an open drain or collector output of a power on reset pin
of another device. The sequential method is illustrated in Figure 3. The power good is coupled to the EN pin on
the TPS54678 which will enable the second power supply once the primary supply reaches regulation.
TPS54678
PWRGD
EN
EN
SS/TR
SS/TR
PWRGD
Figure 3. Sequential Start-Up Sequence
Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS54678 is adjustable over a wide range from approximately 200 kHz to 2000
kHz by placing a maximum of 210 kΩ and minimum of 18 kΩ, respectively, on the RT/CLK pin. The RT/CLK is
typically 0.5 V. To determine the timing resistance for a given switching frequency, use the curve in Figure 4. To
reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of the
supply efficiency, maximum input voltage and minimum controllable on time should be considered.
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The minimum controllable on time is typically 85 ns at 3 A current load and 100 ns at no load, and will limit the
maximum operating input voltage or output voltage.
56183
R (kΩ) =
T
é
ë
ù1.052
û
F
(KHz)
SW
(5)
1800
1600
1400
1200
1000
800
600
400
200
0
0
20
40
60
80 100 120 140 160 180 200
RT Resistance (KΩ)
G009
Figure 4. Switching Frequency vs RT Set Resistor
Overcurrent Protection
The TPS54678 implements current mode control which uses the COMP pin voltage to turn off the high side
MOSFET and turn on the low side MOSFET on a cycle-by-cycle basis. Each cycle the switch current and the
COMP pin voltage are compared, when the peak switch current intersects the COMP voltage the high side
switch is turned off.
High-Side Overcurrent Protection
During overcurrent conditions that pull the output voltage low, the error amplifier will respond by driving the
COMP pin high, increasing the switch current. The error amplifier output is clamped internally. This clamp
functions as a high-side switch current limit. When the high-side switch current limit occurs consecutively for 512
CLK cycles, the converter enters hiccup mode in which no switching action happens for about 16000 cycles. This
helps to reduce the power consumption during an overcurrent event.
Low-Side Overcurrent Protection
The low-side MOSFET’s conduction current is also monitored by TPS54678. During normal operation, the low-
side sources current into the load. When the sourcing current reaches the internally set low-side sourcing
(forward) current limit, the high-side is not turned on and skipped during the next clock cycle. Under this
condition, the low-side is kept on until the sourcing current becomes less than the internally set current limit and
then the high-side is turned on at the beginning of the following clock cycle. This ensures protection under an
output short condition; thereby, preventing current run-away.
The low-side can also sink current from the load. If the low-side sinking (reverse) current limit is exceeded, the
low-side is turned off immediately for the rest of the clock cycle. Under this condition, both the high-side and low-
side are off until the start of the next cycle.
Safe Start-Up into Pre-Biased Outputs
The TPS54678 allows monotonic startup into pre-biased output. The low side Fet turns on for a short time period
every cycle before the output voltage reaches the pre-biased voltage. This ensures the boot cap has enough
charge to turn on the top Fet when the output voltage reaches the pre-biased voltage.
The TPS54678 also implements low side current protection by detecting the voltage over the low side MOSFET.
When the converter sinks current through the low side FET and if the current exceeds 4 A, the control circuit
turns the low side Fet off. Due to the implemented prebias function, the low side Fet reverse current protection
should not be reached, but it provides another layer of protection.
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Synchronize using the RT/CLK pin
The RT/CLK pin is used to synchronize the converter to an external system clock. See Figure 5. To implement
the synchronization feature in a system connect a square wave to the RT/CLK pin with on time at least 75 ns.
The square wave amplitude at this pin must transition lower than 0.6 V and higher than 1.6 V. The
synchronization frequency range is 300 kHz to 2000 kHz. The rising edge of the PH will be synchronized to the
falling edge of RT/CLK pin.
TPS54678
PLL
RT/CLK
Clock
Source
Rfset
Figure 5. Synchronizing to a System Clock
Power Good (PWRGD Pin)
The PWRGD pin is an open drain output and pulls the PWRGD pin low when the VSENSE voltage is less than
91% or greater than 105% of the nominal internal reference voltage.
There is a 2% hysteresis, so once the VSENSE pin is within 93% to 103% of the internal voltage reference the
PWRGD pin is de-asserted and the pin floats. It is recommended to use a pull-up resistor between the values of
1 kΩ and 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD is in a valid state once the VIN input
voltage is greater than 1.2 V.
Overvoltage Transient Protection
The TPS54678 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot
when recovering from output fault conditions or strong unload transients. The OVTP feature minimizes the output
overshoot by implementing a circuit to compare the VSENSE pin voltage to OVTP threshold which is 105% of
the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the high side
MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the
VSENSE voltage drops lower than the OVTP threshold the high side MOSFET is allowed to turn on the next
clock cycle.
Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 170°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds thermal trip
threshold. Once the die temperature decreases below 155°C, the device reinitiates the power up sequence by
discharging the SS/TR pin to about 60 mV. The thermal shutdown hysteresis is 15°C.
Small Signal Model for Loop Response
The Figure 6 shows an equivalent model for the TPS54678 control loop which can be modeled in a circuit
simulation program to check frequency response and dynamic load response. The error amplifier is a
transconductance amplifier with a gm of 245 µA/V. The error amplifier can be modeled using an ideal voltage
controlled current source. The resistor RO and capacitor CO model the open loop gain and frequency response of
the amplifier.
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PH
Power Stage
20 A/V
VO
a
b
RESR
A/V
R1
C
COMP
RL
COUT
C
VSENSE
R2
0.6 V
R3
C1
CO RO
gm
245 mA/V
C2
Figure 6. Small Signal Model for Loop Response
Simple Small Signal Model for Peak Current Mode Control
Figure 6 is a simple small signal model that can be used to understand how to design the frequency
compensation. The TPS54678 power stage can be approximated to a voltage controlled current source (duty
cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer
function is shown in Equation 6 and consists of a dc gain, one dominant pole and one ESR zero. The quotient of
the change in switch current and the change in COMP pin voltage (node c in figure) is the power stage
transconductance. The gm for the TPS54678 is 20 A/V. The low frequency gain of the power stage frequency
response is the product of the transconductance and the load resistance as shown in Equation 7. As the load
current increases and decreases, the low frequency gain decreases and increases, respectively. This variation
with load may seem problematic at first glance, but fortunately the dominant pole moves with load current (see
Equation 8). The combined effect is highlighted by the dashed line in the right half of Figure 7. As the load
current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the
same for the varying load conditions which makes it easier to design the frequency compensation.
VO
RESR
Adc
VC
fp
RL
gmps
COUT
fz
Figure 7. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
ö
çæ1 +
è
s
2p ´ fz ÷ø
VO
VC
= Adc x
ö
çæ1 +
è
s
2p ´ fp ÷ø
(6)
Adc = gm ´ R
ps
L
(7)
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1
fp =
COUT ´ RL ´ 2p
(8)
(9)
1
fz =
COUT ´ RESR ´ 2p
Small Signal Model for Frequency Compensation
The TPS54678 uses a transconductance amplifier for the error amplifier and readily supports two of the
commonly used frequency compensation circuits. The compensation circuits are shown in Figure 8. The Type 2
circuits are normally implemented in high bandwidth power supply designs using low ESR output capacitors. In
Type 2A, one additional high frequency pole is added to attenuate high frequency noise.
VO
R1
VSENSE
gmea
Type 2A
C2
Type 2B
COMP
VREF
R3
C1
CO
5 pF
R3
R2
RO
C1
Figure 8. Types of Frequency Compensation
The design guidelines for TPS54678 loop compensation are as follows:
1. Set up cross over frequency fc.
2. R3 can be determined by
2p ´ fc ´ V ´ C
O
OUT
R3 =
gm
´ V
´ gm
ps
REF
ea
(10)
Where gmea is the GM amplifier gain, gmPS is the power stage gain (20 A/V).
1
fp =
COUT ´ RL ´ 2p
3. Place a compensation zero at the dominant pole
RL ´ COUT
C1 =
C1 can be determined by
R3
(11)
(12)
4. C2 is optional. It can be used to cancel the zero from Co’s ESR.
RESR ´ COUT
C2 =
R3
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Typical Characteristics
SHUTDOWN SUPPLY CURRENT vs TEMPERATURE
VIN OPERATING CURRENT vs TEMPERATURE
1.4
1.3
1.2
1.1
1
590
580
570
560
550
VIN = 5 V
VIN = 3.3 V
VIN =5 V
VIN = 3.3 V
0.9
0.8
0.7
0.6
−40
0
40
80
120
160
−40
0
40
80
120
160
Temperature (°C)
Temperature (°C)
G001
G002
Figure 9.
Figure 10.
EN PIN VOLTAGE vs TEMPERATURE
EN PIN CURRENT vs TEMPERATURE
1.32
1.3
−0.5
−1
1.28
1.26
1.24
1.22
1.2
−1.5
−2
Threshold−50 mV,VIN = 3.3 V
Threshold−50 mV,VIN = 5 V
Threshold+50 mV,VIN = 3.3 V
Threshold+50 mV,VIN = 5 V
−2.5
−3
Rising, VIN = 3.3 V
Rising, VIN = 5 V
Falling, VIN = 3.3 V
Falling, VIN = 5 V
−3.5
−4
1.18
−40
0
40
80
120
160
−40
0
40
80
120
160
Temperature (°C)
Temperature (°C)
G003
G004
Figure 11.
Figure 12.
VOLTAGE REFERENCE vs TEMPERATURE
MOSFET RDS(on) vs TEMPERATURE
600.2
600.1
600
22.25
20.25
18.25
16.25
14.25
12.25
VIN = 5 V
Lowside, VIN = 3.3 V
Highside, VIN = 3.3 V
Lowside, VIN = 5 V
Highside, VIN = 5 V
599.9
599.8
599.7
599.6
599.5
−40
0
40
80
120
160
−40
0
40
80
120
160
Temperature (°C)
Temperature (°C)
G005
G006
Figure 13.
Figure 14.
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Typical Characteristics (continued)
TRANSCONDUCTANCE vs TEMPERATURE
HIGH SIDE FET CURRENT LIMIT vs TEMPERATURE
258
10.3
VIN = 3.3 V
VIN = 5 V
10.2
10.2
10.2
10.1
10.1
248
238
228
218
VIN = 3.3 V
120 160
−40
0
40
80
120
160
−40
0
40
80
Temperature (°C)
Temperature (°C)
G007
G008
Figure 15.
Figure 16.
SWITCHING FREQUENCY vs RT RESISTANCE
SWITCHING FREQUENCY vs TEMPERATURE
490
488
486
484
482
480
1800
VIN = 5 V
RT = 85 kΩ
1600
1400
1200
1000
800
600
400
200
0
0
20
40
60
80 100 120 140 160 180 200
−40
0
40
80
120
160
Temperature (°C)
RT Resistance (KΩ)
G009
G010
Figure 17.
Figure 18.
VSS VOLTAGE THRESHOLD VSSTHR vs TEMPERATURE
SS CHARGE CURRENT vs TEMPERATURE
152.8
−2.21
−2.22
−2.23
−2.24
−2.25
−2.26
−2.27
−2.28
VIN = 3.3 V
VIN = 5 V
152.6
152.4
152.2
VSS TR > 0.15 V
VIN = 3.3 V
VIN = 5 V
152
−40
0
40
80
120
160
−40
0
40
80
120
160
Temperature (°C)
Temperature (°C)
G011
G012
Figure 19.
Figure 20.
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Typical Characteristics (continued)
SS CHARGE CURRENT vs TEMPERATURE
PWRGD RDS(on) vs TEMPERATURE
−44.5
−45
80
75
70
65
60
55
VIN = 3.3 V
VIN = 5 V
−45.5
−46
−46.5
−47
VSS TR = < 0.15 V
−47.5
−48
VIN = 5 V
120 160
−40
0
40
80
120
160
−40
0
40
80
Temperature (°C)
Temperature (°C)
G013
G014
Figure 21.
Figure 22.
PWRGD THRESHOLD vs TEMPERATURE
PWRGD LEAKAGE CURRENT vs TEMPERATURE
107
105
103
101
99
4
VIN = 5 V
3
2
1
0
Fault Rising
Good Rising
Fault Falling
Good Falling
97
95
−1
93
91
−40
−2
−40
0
40
80
120
160
0
40
80
120
160
Temperature (°C)
Temperature (°C)
G015
G016
Figure 23.
Figure 24.
EFFICIENCY vs CURRENT
EFFICIENCY vs CURRENT
98
96
94
92
90
88
86
84
82
80
78
96
94
92
90
88
86
84
82
80
78
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.2 V
VOUT = 1 V
VIN = 5 V
VIN = 3.3 V
VOUT = 1.8 V
VOUT = 1.2 V
VOUT = 1 V
Fsw = 500 KHz
DCR = 7.5 mΩ
TA = 25°C
Fsw = 500 KHz
DCR = 7.5 mΩ
TA = 25°C
1
2
3
4
5
6
1
2
3
4
5
6
Current (A)
Current (A)
G017
G018
Figure 25.
Figure 26.
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Typical Characteristics (continued)
EFFICIENCY vs CURRENT
EFFICIENCY vs CURRENT
98
96
94
92
90
88
86
84
82
80
78
96
94
92
90
88
86
84
82
80
78
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.2 V
VOUT = 1 V
VIN = 3.3 V
VIN = 5 V
VOUT = 1.8 V
VOUT = 1.2 V
VOUT = 1 V
Fsw = 1 MHz
DCR = 7.5 mΩ
TA = 25°C
Fsw = 1 MHz
DCR = 7.5 mΩ
TA = 25°C
1
2
3
4
5
6
1
2
3
4
5
6
Current (A)
Current (A)
G019
G020
Figure 27.
Figure 28.
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APPLICATION INFORMATION
DESIGN GUIDE – STEP-BY-STEP DESIGN PROCEDURE
This example details the design of a high frequency switching regulator design using ceramic output capacitors.
This design is available as the TPS54678EVM-155 (PWR155) evaluation module (EVM). A few parameters must
be known in order to start the design process. These parameters are typically determined at the system level.
For this example, we start with the following known parameters:
PARAMETER
VALUE
Output Voltage
1.2V
Transient Response 50% load step
Maximum Output Current
Input Voltage
ΔVOUT < 5%
6A
3 V to 6 V, 5 V nominal
< 30 mVPP
500 kHz
Output Voltage Ripple
Switching Frequency (Fsw)
Step by Step Design
1. SELECTING THE SWITCHING FREQUENCY
The first step is to decide on a switching frequency for the regulator. Typically, it is desirable to choose the
highest switching frequency possible since this produces the smallest component solution size. The high
switching frequency allows for lower value inductors and smaller output capacitors compared to a power
supply that switches at a lower frequency. However, the higher switching frequency causes extra switching
losses, which degrade the performance of the converter. This SWIFT™ converter is capable of running from
200 kHz to 2 MHz. Unless a small solution size is the top priority, a moderate switching frequency of 500kHz
is selected to achieve both a small solution size and high efficiency operation. Using Equation 13, RT is
calculated to be 81.34 kΩ. A standard 1% 82.5 kΩ value was chosen for the design.
56183
56183
(500)1.052
R (kΩ) =
T
=
= 81.34 kΩ
1.052
(F
)
SW
(13)
Where:
– RT is in kΩ
– FSW is in kHz
2. OUTPUT INDUCTOR SELECTION
The inductor selected works for the entire TPS54678 input voltage range. To calculate the value of the
output inductor, use Equation 14. KIND is a coefficient that represents the amount of inductor ripple current
relative to the maximum output current. The inductor ripple current is filtered by the output capacitor.
Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor since the
output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In
general, the inductor ripple value is at the discretion of the designer, however KIND is usually chosen between
0.1 to 0.3 for the majority of applications.
For this design example, a value of KIND = 0.3 was used at 6 VIN and 6 AOUT, and the inductor value is
calculated to be 1.06 μH. For this design, the nearest standard value of 1.2 μH was chosen. For the output
filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS
and peak inductor current can be found from Equation 16 and Equation 17.
For this design, the RMS inductor current is 6.02 A and the peak inductor current is 6.8 A. The chosen
inductor is a Coilcraft XAL5030-122ME. It has a saturation current rating 0f 11.8 A (20% inductance loss)
and a RMS current rating of 8.7 A (20°C temperature rise). The series resistance is 6.78 mΩ typical.
The current flowing through the inductor is the inductor ripple current plus the output current. During power
up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor
current level calculated above. In transient conditions, the inductor current can increase up to the switch
current limit of the device. For this reason, the most conservative approach is to specify an inductor with a
saturation current rating equal to or greater than the switch current limit rather than the peak inductor current.
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V
- VOUT
VOUT
IN_MAX ´FSW
- VOUT
IN_MAX
L1=
´
Io ´KIND
V
(14)
(15)
V
VOUT
VIN_MAX ´FSW
IN_MAX
IRIPPLE
=
´
L1
2
æ
ç
ç
è
ö
VOUT ´ V
- VOUT
(
)
IN_MAX
1
÷
I
= Io2 +
´
IND _RMS
÷
ø
12
VIN_MAX ´L1´FSW
(16)
(17)
IRIPPLE
I
=Io +
IND _peak
3. OUTPUT CAPACITOR
There are three primary considerations for selecting the value of the output capacitor. Along with the
inductor, the output capacitor determines the output voltage ripple, and also how the regulator responds to a
large change in load current. The output capacitance needs to be selected based on the more stringent of
these two criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator can not due to limited control speed. The regulator is
temporarily not able to supply sufficient change in output current if there is a large, fast increase or decrease
in the current needs of the load such as transitioning from no load to full load. The regulator usually needs
two or more clock cycles for the control loop to see the change in load current and output voltage and adjust
the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the
load until the control loop responds to the load change, or conversely, absorb the excess current from the
inductor. Since the output voltage is less than half the input voltage, the worst case deviation in output
voltage occurs when the load has an extremely rapid reduction in current, or a load dump. The desired
specification is a 50% or 3A load step, and a resulting voltage deviation of no more than 5%, or 60mV. When
a load dump occurs, the excess stored current in the inductor will tend to charge the output capacitors, and
the best the converter can achieve to limit the increase in output voltage is to fold back the duty cycle to
zero. Under these circumstances, the amount of rise in output voltage is defined by the energy from the
choke being fully absorbed by the capacitor bank. Equation 18 through Equation 20 can be used to calculate
the required capacitor bank value.
For this example, the transient load response is specified as a 5% change in Vout for a 50% load step from 3
A to 0 A. So, ΔIOUT = 3 A and ΔVOUT = 0.05 × 1.2 = 0.06 V. Using these numbers gives a minimum
capacitance of 73.2 μF. This calculation does not take the ESR of the output capacitor into account in the
output voltage change, and it does not account for latency in control loop speed. For ceramic capacitors, the
ESR is usually small enough to ignore in this calculation.
2
2
EnergyIND = 0.5 ´L ´I = 0.5 ´1.2m ´3 = 5.4mJoule
(18)
2
2
EnergyCAPInitial = 0.5´C´ V = 0.5 ´C´1.2
2
)
2
EnergyCAPFinal = 0.5´C´1.2 + EnergyIND = 0.5 ´C´ 1.2 + 0.06
(
(19)
Solving for C:
5.4mJ
CBank
=
= 73.17mF
0.7938 - 0.72
(
)
(20)
This 73.17 µF defines the minimum capacitance required to meet the transient spec, however, since the
control loop speed is finite, more capacitance than this will be required to meet desired performance.
Equation 21 calculates the minimum output capacitance needed to meet the output voltage ripple
specification. Where FSW is the switching frequency, VRIPPLE is the maximum allowable output voltage ripple,
and Iripple is the inductor ripple current. In this case, the maximum output voltage ripple is 60 mV. Under this
requirement, Equation 21 yields 13.33 µF.
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1
1
CBank
=
´
= 13.33mF
VRIPPLE
8´F
(
)
SW
IRIPPLE
(21)
Equation 22 calculates the maximum ESR for the capacitor bank to meet the output voltage ripple
specification. Equation 22 indicates the ESR should be less than 37.5 mΩ. In this case, the ESR of the
ceramic capacitor bank is less than 37.5 mΩ.
VRIPPLE
RESR
<
IRIPPLE
(22)
Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases
the minimum value calculated in Equation 20. For this example, five 47 μF 10 V X5R ceramic capacitors with
3 mΩ of ESR are used. The estimated capacitance after derating is 5 x 47 μF x 0.9 = 211.5 μF.
4. INPUT CAPACITOR
The TPS54678 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 10
μF of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes
any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input
voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of
the TPS54678. The input ripple current can be calculated using Equation 23.
V
IN_MIN - VOUT
(
)
VOUT
IRMS = IOUT
´
´
V
V
IN_MIN
IN_MIN
(23)
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to
the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric
material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power
regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over
temperature. The output capacitor must also be selected with the DC bias taken into account. The
capacitance value of a capacitor decreases as the DC bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 10V voltage rating is required to support the
maximum input voltage. For this example, three 47 μF and one 0.1 μF 10 V capacitors in parallel have been
selected. In addition to these low ESR capacitors, an input bulk cap of 220 µF electrolytic is included so as to
provide low source impedance at low frequencies for instances where the input voltage source is connected
with a lossy feed.
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can
be calculated using Equation 24. Using the design example values, IOUT_MAX = 6 A, CIN = 141 μF (neglecting
the electrolytic due to high ESR), FSW = 500 kHz, yields an input voltage ripple of 21.3 mV and an rms input
ripple current of 2.94 A.
I
OUT _MAX ´ 0.25
DV
=
IN
CIN ´FSW
(24)
5. SLOW START CAPACITOR
The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach the
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate.
This is also used if the output capacitance is very large and would require large amounts of current to quickly
charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may
cause the TPS54678 to trip OCP, or excessive current draw from the input power supply may cause the
input voltage rail to sag. Limiting the output voltage slew rate mitigates both of these issues.
The slow start capacitor value can be calculated using Equation 25. For the example circuit, the slow start
time is not critical since the output capacitor value is 5 x 47 μF which does not require much current to
charge to 1.2 V. The example circuit has the slow start time set to an arbitrary value of 3.33 ms which
requires a 10nF capacitor.
CSS = 3´ TSS
(25)
6. BOOTSTRAP CAPACITOR SELECTION
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A 0.1 μF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10
V or higher voltage rating.
7. OUTPUT VOLTAGE AND FEEDBACK RESISTOR SELECTION
For the example design, 20 kΩ was selected for R10. Using Equation 26, R9 is calculated also as 20 kΩ.
æ
ç
è
ö
VOUT
R9 = R10
´
-1
÷
VREF
ø
(26)
Due to the internal design of the TPS54678, there is a minimum output voltage limit for any given input
voltage. The output voltage can never be lower than the internal voltage reference of 0.6 V. Above 0.6 V, the
output voltage may be limited by the minimum controllable on time. The minimum output voltage in this case
is given by Equation 27.
VOUT _MIN = tON_MIN ´FSW _MAX
V
(
-IOUT _MIN ´RDS(ON)MIN -I
)
´ R + R
(
OUT _MIN L DS(ON)MIN
)
IN_MAX
(27)
Where:
VOUT_MIN = minimum achievable output voltage
tON_MIN = minimum controllable on-time (100 ns typical, 120 ns no load)
FSW_MAX = maximum switching frequency including tolerance
VIN_MAX = maximum input voltage
IOUT_MIN = minimum load current
RDS(ON)_MIN = minimum high-side MOSFET on resistance (See Electrical Characteristics)
RL = series resistance of output inductor
There is also a maximum achievable output voltage which is limited by the minimum off time. The maximum
output voltage is given by Equation 28
tOFF _MAX
Period
æ
ö
VOUT _MAX = V ´ 1-
-I
´ R
(
+ RL - 0.7 -IOUT _MAX ´RDS(ON)MAX
ç
÷
÷
) (
)
OUT _MAX
DS(ON)MAX
IN
ç
è
ø
t
æ
ç
è
ö
÷
DEAD
´
Period
ø
(28)
Where:
VOUT_MAX = maximum achievable output voltage
VIN = minimum input voltage
tOFF_MAX = maximum off time (180 ns typical for adequate margin)
Period = 1/Fs
IOUT_MAX = maximum current
RDS(ON)_MAX = maximum high-side MOSFET on resistance (See Electrical Characteristics)
RL = DCR of the inductor
tDEAD = dead time (40 ns)
8. COMPENSATION
There are several possible methods to design closed loop compensation for dc/dc converters. For the ideal
current mode control, the design equations can be easily simplified. The power stage gain is constant at low
frequencies, and rolls off at –20 dB/decade above the modulator pole frequency. The power stage phase is 0
degrees at low frequencies and starts to fall one decade below the modulator pole frequency reaching a
minimum of –90 degrees one decade above the modulator pole frequency. In this case the modulator pole is
a simple pole shown in Equation 29.
1
F
=
PMOD
2pCOUTRLOAD
(29)
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For the TPS54678 most circuits will have relatively high amounts of slope compensation. As more slope
compensation is applied, the power stage characteristics will deviate from the ideal approximations. The phase
loss of the power stage will extend beyond –90 degrees and can approach –180 degrees, making compensation
more difficult. The power stage transfer function can be solved but it is a tedious hand calculation that does not
lend itself to simple approximations. It is easier to either simulate the circuit or to actually measure the plant
transfer function so that a reliable compensation circuit can be designed. The latter technique used in this design
procedure. The power stage plant was measured and is shown below in Figure 29.
30
20
135
90
Gain
Phase
10
45
0
0
−10
−20
−30
−40
−50
−45
−90
−135
−180
−225
100
1000
10000
100000
1000000
Frequency (Hz)
G001
Figure 29. Measured Plant Bode
For this design, the desired crossover frequency Fc is 50 kHz. From the power stage gain and phase plot above,
the gain at 50 kHz is -10.6 dB and the phase is –123.3 degrees. Since the plant phase loss is greater than -90
degrees, to achieve at least 60 degrees of phase margin, additional phase boost from a feed forward capacitor in
parallel with the upper resistor of the voltage set point divider is required.
See the Schematic in Figure 47. R3 sets the gain of the compensated error amplifier to be equal and opposite (in
dB) to the power stage gain at Fc, so +10.6 dB is needed. The required value of R3 can be calculated from
Equation 30.
-G
æ
ö
Plant
ç
÷
20
è
ø
VOUT
VREF
10
R3 =
´
gmEA
(30)
The compensator zero formed by R3 and C6 is placed at the plant pole, as shown approximately 2.5 kHz. The
required value for C6 is given by Equation 31.
1
C6 =
2pR3Fplantpole
(31)
The high frequency noise pole formed by C5 and R3 is not used in this design. If the resulting design shows
noise susceptibility, the value of C5 can be calculated per Equation 32.
1
C5 =
2pR3Fpole
(32)
To avoid a penalty in loop phase, the Fpole in Equation 32 should be placed a decade above Fc or higher, and is
intended to reject noise at FSW
.
The feed forward capacitor C15 is used to increase the phase boost at crossover above what is normally
available from Type II compensation. It places an additional zero/pole pair with the zero located at Equation 33
and the pole at Equation 34.
1
Fz =
2pC15R9
(33)
1
F =
p
2pC15 R || R
(
)
9
10
(34)
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This zero and pole pair is not independent since R9 and R10 are set by the desired VOUT. Once the zero location
is chosen, the pole is fixed as well. For optimum performance, the zero and pole should be located symmetrically
about the intended crossover frequency. The required value for C15 can be calculated from Equation 35.
1
C15
=
VREF
VOUT
2pR9Fc
(35)
The above compensation equations yield the following values:
REF DES
R3
CALCULATED VALUE
19.6 kΩ
CHOSEN VALUE
26.7 kΩ
C6
2.38 nF
2.2 nF
C15
225 pF
150 pF
Application Curves
All following measurements are given for an ambient temperature of 25°C.
96
94
92
90
88
86
84
82
80
3 V
4 V
5 V
6 V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Output Current (A)
G002
Figure 30. TPS54678EVM-155 Efficiency
The efficiency may be lower at higher ambient temperatures, due to temperature variation in the drain-to-source
resistance RDS(ON) of the internal MOSFETs.
1.2100
3 V
4 V
1.2095
1.2090
1.2085
1.2080
1.2075
1.2070
1.2065
1.2060
1.2055
1.2050
5 V
6 V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Output Current (A)
G003
Figure 31. TPS54678EVM-155 Load Regulation
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1.2100
1.2095
1.2090
1.2085
1.2080
1.2075
1.2070
1.2065
1.2060
1.2055
1.2050
3 A
4 A
5 A
6 A
3
3.5
4
4.5
5
5.5
6
Input Voltage (V)
G003
Figure 32. TPS54678EVM-155 Line Regulation
Figure 33 shows the TPS54678EVM-155 response to load transients. The current step is from 0% to 50% of
maximum rated load at 3 V input. Total peak-to-peak voltage variation is as shown.
V
= 50 mV / div (ac coupled)
OUT
I
= 1 A / div
OUT
Load step = 0 - 3 A
Time = 100 ms/div
Figure 33. TPS54678EVM-155 Transient Response
Figure 34 shows the TPS54678EVM-155 loop-response characteristics. Gain and phase plots are shown for VIN
voltage of 5 V. Load current for the measurement is 6 A.
50
150
120
90
Gain
Phase
40
30
20
60
10
30
0
0
−10
−20
−30
−60
100
1000
10000
100000
1000000
Frequency (Hz)
G005
Figure 34. TPS54678EVM-155 Loop Response
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Figure 35 shows the TPS54678EVM-155 output voltage ripple. The output current is the rated full load of 6 A and
VIN = 3 V. Figure 36 shows the ripple at 6 A and VIN = 6 V. The voltage is measured directly across the output
capacitors.
V
= 3 V
= 6 A
IN
I
OUT
V
= 20 mV / div (ac coupled)
OUT
SW Node = 5 V / div
Time = 500 ns/div
Figure 35. TPS54678EVM-155 Output Ripple, 3 V 6 A
V
= 6 V
= 6 A
IN
I
OUT
V
= 20 mV / div (ac coupled)
OUT
SW Node = 5 V / div
Time = 500 ns/div
Figure 36. TPS54678EVM-155 Output Ripple, 6 V 6 A
Figure 37 shows the TPS54678EVM-155 input voltage ripple. The output current is the rated full load of 6 A and
VIN = 3 V. The ripple voltage is measured directly across the input capacitors.
V
= 3 V
= 6 A
IN
I
OUT
V
= 50 mV / div
IN
(ac coupled)
20 MHZ BW Limited
SW Node = 5 V / div
Time = 500 ns/div
Figure 37. TPS54678EVM-155 Input Ripple at 3 VIN and 6 A
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V
= 6 V
= 6 A
IN
V
= 50 mV / div (ac coupled)
I
IN
OUT
20 MHZ BW Limited
SW Node = 5 V / div
Time = 500 ns/div
Figure 38. TPS54678EVM-155 Input Ripple at 6 VIN and 6 A
Figure 39 and Figure 40 show the start-up waveforms for the TPS54678EVM-155. In Figure 39, the output
voltage ramps up as soon as the input voltage reaches the UVLO threshold as set by the R1 and R2 resistor
divider network. In Figure 40, the input voltage is initially applied and the output is inhibited by using a jumper at
JP1 to tie EN to GND. When the jumper is removed, EN is released. When the EN voltage reaches the enable-
threshold voltage, the start-up sequence begins and the output voltage ramps up to the externally set value of
1.2 V.
I
= 1 A / div (inverted for clarity)
OUT
V
= 1 V / div
IN
I
= 4.6 A
OUT
V
= 200 mV / div
OUT
Time = 500 ms/div
Figure 39. FTPS54678EVM-155 Start-Up Relative to VIN
V
= 1 V / div
IN
I
= 1 A / div
OUT
(inverted for clarity)
I
= 4.6 A
OUT
V
= 200 mV / div
OUT
Time = 500 ms/div
Figure 40. TPS54678EVM-155 Start-up Relative to Enable
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The TPS54678 is designed to start up into pre-biased outputs. Figure 41 shows the output voltage start up
waveform when the output is prebiased with 550 mV at no load.
V
= 1 V / div
IN
V
= 200 mV / div
OUT
Pre-Bias = 0.55 V
= 0 A
I
OUT
Time = 500 ms/div
Figure 41. TPS54678EVM-155 Start-up into Pre-bias at no load
Figure 42 and Figure 43 show the shut down waveforms for the TPS54678EVM-155. In Figure 42, the output
voltage ramps down as soon as the input voltage falls below the UVLO stop threshold as set by the R1 and R2
resistor divider network. At the point of shutdown, the input voltage rises slightly due to the resistive drop in the
input feed impedance. In Figure 43, the output is inhibited by using a jumper at JP1 to tie EN to GND.
V
= falling, 200 mV / div
OUT
V
IN
= 1 V / div (near 2.7 V)
I
= 6.6 A
OUT
I
= 1 A / div (invertey for clarity)
OUT
Time = 100 ms/div
Figure 42. TPS54678EVM-155 Shut-down Relative to VIN
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V
= falling, 200 mV / div
OUT
V
= 1 V / div
IN
V
I
= 5 V
IN
= 6.6 A
OUT
I
= 1 A / div (inverted for clarity)
OUT
Time = 100 ms/div
Figure 43. TPS54678EVM-155 Shut-down Relative to EN
The TPS54678 has hiccup mode current limit. When the peak switch current exceeds the current limit threshold,
the device shuts down and restarts. Hiccup mode current limit operation is shown in Figure 44 and Figure 45.
Figure 44 shows the hiccup mode current limit with a slight resistive overload. When the peak current limit is
exceeded, the output voltage is disabled. Figure 45 shows the operation of the TPS54678 with the output
shorted to ground. The device continuously resets until the fault condition is removed.
V
= 1 V / div
IN
V
I
= 5 V
IN
= 9.2 A
OUT
I
= 1 A / div
OUT
V
= 200 mV / div
OUT
Time = 5 ms/div
Figure 44. TPS54678EVM-155 Hiccup Mode Current Limit Shut-down
V
I
= 6 V
IN
= short
OUT
V
= 100 mV / div
OUT
I
= 5 A / div
OUT
Time = 5 ms/div
Figure 45. TPS54678EVM-155 Hiccup Mode Current Limit Re-start into Short Circuit
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POWER DISSIPATION ESTIMATE
The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM)
operation. The power dissipation of the IC (Ptot) includes conduction loss (Pcon), dead time loss (Pd), switching
loss (Psw), gate drive loss (Pgd) and supply current loss (Pq).
Pcon = IO2 × RDS(on) (temperature dependent)
Pd = ƒsw × IO × 0.7 × (20 nS + 20 nS)
Psw = 0.5 × VIN × IO × ƒsw× 7 × 10–9
Pgd = 2 × VIN × ƒsw× 6 × 10–9
Pq = VIN × 500 × 10–6
Where:
IO is the output current (A).
RDS(on) is the on-resistance of the high-side MOSFET with given temperature (Ω).
VIN is the input voltage (V).
ƒsw is the switching frequency (Hz).
So
Ptot = Pcon + Pd + Psw + Pgd + Pq
For given TA,
TJ = TA + Rth × Ptot
For given TJ max = 150°C
TA max = TJ max – Rth × Ptot
Where:
Ptot is the total device power dissipation (W).
TA is the ambient temperature (°C).
TJ is the junction temperature (°C).
Rth is the thermal resistance of the package (°C/W).
TJ max is maximum junction temperature (°C).
TA max is maximum ambient temperature (°C).
There are additional power losses in the regulator circuit due to the inductor AC and DC losses and trace
resistance that impact the overall efficiency of the regulator.
LAYOUT
Component placement and copper layout are two of the most critical portions of good power supply design.
Unfortunately, these two design parameters do not show up in the schematic, so proper layout rules must be
described and followed. There are several signal paths that conduct fast changing currents or voltages that can
interact with stray inductance or parasitic capacitance to generate noise or degrade the power supply's
performance. Care should be taken to minimize the loop area formed by the bypass capacitor connections and
the VIN pins. See Figure 46 for a PCB layout example. The GND pins and AGND pin should be tied directly to
the power pad under the IC. The power pad should be connected to any internal PCB ground planes using
multiple vias directly under the IC. Additional vias can be used to connect the top side ground area to the internal
planes near the input and output capacitors. For operation at full rated load, the top side ground area along with
any additional internal ground planes must provide adequate heat dissipating area.
Locate the input bypass capacitor as close to the IC as possible. The PH pin should be routed to the output
inductor. Since the PH connection is the switching node, the output inductor should be located close to the PH
pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The boot capacitor
must also be located close to the device. The sensitive analog ground connections for the feedback voltage
divider, compensation components, slow start capacitor and frequency set resistor should be connected to a
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separate analog ground trace as shown. The RT/CLK pin is particularly sensitive to noise so the RT resistor
should be located as close as possible to the IC and routed with minimal trace lengths. The additional external
components can be placed approximately as shown. It may be possible to obtain acceptable performance with
alternate PCB layout; however, this layout has been shown to produce good results and is intended as a
guideline.
Figure 46. TPS54678EVM-155 Top-Side Assembly
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Figure 47. TPS54678 Schematic
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Aug-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS54678RTER
TPS54678RTET
ACTIVE
ACTIVE
WQFN
WQFN
RTE
RTE
16
16
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54678RTER
TPS54678RTET
WQFN
WQFN
RTE
RTE
16
16
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Aug-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS54678RTER
TPS54678RTET
WQFN
WQFN
RTE
RTE
16
16
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
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