TPS548B28_技术文档

TPS548B28

ZHCSMV4A –DECEMBER 2020 –REVISED DECEMBER 2022

具有遥感功能、3V 内部LDO 和断续电流限制功能的

TPS548B28 2.7V 至16V 输入、20A 同步降压转换器

1 特性

2 应用

• 输入范围为4V 至16V，电流高达20A，无外部偏

压

• 输入范围为2.7V 至16V，电流高达20A，外部偏

压范围为3.13V 至3.6V

• 机架式服务器和刀片式服务器

• 硬件加速卡和插件卡

• 数据中心交换机

• 工业PC

• 输出电压范围：0.6V 至5.5V

• 集成7.7mΩ和2.4mΩMOSFET，支持20A 持续

输出电流

3 说明

TPS548B28 器件是一款具有自适应导通时间 D-CAP3

控制模式的高效率、小尺寸同步降压转换器。该器件不

需要外部补偿，因此易于使用并且仅需要很少的外部元

件。该器件非常适合空间受限的数据中心应用。

• 在D-CAP3^™控制模式下可提供超快负载阶跃响应

• 支持所有陶瓷输出电容器

• 在–40°C 至+125°C 结温下实现差分遥感，V_REF

为0.6V ±1%

• 可选FCCM 或自动跳跃Eco-mode^™可实现较高的

轻负载效率

• 通过R_TRIP实现可编程电流限制

• 引脚可选开关频率：600kHz、800kHz、1MHz

• 可实现高输出精度的差分遥感功能

• 可编程软启动时间

• 外部基准输入，用于跟踪

• 预偏置启动功能

TPS548B28 器件具有差分遥感功能和高性能集成

MOSFET，在整个工作结温范围具有高精度 (±1%)

0.6V 电压基准。该器件具有快速负载瞬态响应、精确

负载调节和线路调节、跳跃模式或 FCCM 运行模式以

及可编程软启动功能。

TPS548B28 是一款无铅器件，完全符合 RoHS 标准，

无需豁免。

封装信息

封装⁽¹⁾

• 开漏电源正常状态输出

• 在发生OC 和UV 故障时进入断续模式，在发生

OV 故障时进入闭锁模式

封装尺寸（标称值）

器件型号

RWW（VQFN-HR，

21）

TPS548B28

4.00mm × 3.00mm

• 4mm × 3mm 21 引脚QFN 封装

• 引脚与15A TPS548A28 兼容

• 完全符合RoHS 标准，无需豁免

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

100

95

90

85

80

75

V_IN

10

21

1

VIN

BOOT

V_OUT

8

20

EN

SW

TPS548B28

19

9

VCC

Vosns+

V_OUT= 0.9 V

V_OUT= 1.0 V

7

FB

70

PGOOD

MODE

TRIP

65

60

55

50

V_OUT= 1.2 V

V_OUT= 1.8 V

V_OUT= 2.5 V

V_OUT= 3.3 V

V_OUT= 5.0 V

4

Vosns-

6

5

VSNS-

3

SS/

2

REFIN

AGND

0

2

4

6

8

10

12

Output Current (A)

14

16

18

20

PGND

Net-tie

效率图，12V_IN，800 kHz，

DCM，内部VCC

简化原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVSBC5

TPS548B28

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ZHCSMV4A –DECEMBER 2020 –REVISED DECEMBER 2022

Table of Contents

7.4 Device Functional Modes..........................................23

8 Application and Implementation..................................26

8.1 Application Information............................................. 26

8.2 Typical Application.................................................... 26

8.3 Power Supply Recommendations.............................37

8.4 Layout....................................................................... 37

9 Device and Documentation Support............................41

9.1 Documentation Support............................................ 41

9.2 接收文档更新通知..................................................... 41

9.3 支持资源....................................................................41

9.4 Trademarks...............................................................41

9.5 Electrostatic Discharge Caution................................41

9.6 术语表....................................................................... 41

10 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................6

6.5 Electrical Characteristics.............................................6

6.6 Typical Characteristics..............................................10

7 Detailed Description......................................................13

7.1 Overview...................................................................13

7.2 Functional Block Diagram.........................................13

7.3 Feature Description...................................................14

Information.................................................................... 42

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (December 2020) to Revision A (December 2022)

Page

• Changed transient time 10 ns to 20 ns in Absolute Maximum Ratings.............................................................. 5

• Updated ESD Ratings (CDM) to current standards............................................................................................5

• Corrected Overvoltage and Undervoltage Protection procedure......................................................................22

2

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ZHCSMV4A –DECEMBER 2020 –REVISED DECEMBER 2022

5 Pin Configuration and Functions

VIN

21

SW

20

SW

20

VIN

21

BOOT

1

19 VCC

VCC

19

1

BOOT

AGND

TRIP

2

3

4

5

6

7

8

18 PGND

17 PGND

16 PGND

15 PGND

14 PGND

13 PGND

12 PGND

PGND

18

17

16

15

14

13

12

2

3

4

5

6

7

8

AGND

TRIP

MODE

SS/REFIN

VSNS-

FB

MODE

SS/REFIN

VSNS-

FB

EN

PGOOD

9

11 PGND

PGND

11

9

PGOOD

10

VIN

图5-1. RWW Package 21-Pin VQFN-HR Top View

图5-2. RWW Package 21-Pin VQFN-HR Bottom

View

表5-1. Pin Functions

NO.

NAME

BOOT

AGND

TRIP

I/O⁽¹⁾

I/O

G

DESCRIPTION

Supply rail for the high-side gate driver (boost terminal). Connect the bootstrap capacitor from

this pin to SW node.

1

2

3

Ground pin. Reference point for the internal control circuits

Current limit setting pin. Connect a resistor to AGND to set the current limit trip point. ±1%

tolerance resistor is highly recommended. See 节7.3.9 for details on OCL setting.

I/O

The MODE pin sets the forced continuous-conduction mode (FCCM) or skip-mode operation. It

also selects the operating frequency by connecting a resistor from MODE pin to AGND pin.

±1% tolerance resistor is recommended. See 表7-1 for details.

4

5

MODE

I

Dual-function pin. Soft-start function: Connecting a capacitor to VSNS–pin programs soft-start

time. Minimum soft-start time (1.5 ms) is fixed internally. A minimum 1-nF capacitor is required

for this pin to avoid overshoot during the charge of soft-start capacitor. REFIN function: The

device always looks at the voltage on this SS/REFIN pin as the reference for the control loop.

The internal reference voltage can be overridden by an external DC voltage source on this pin

for tracking application.

SS/REFIN

I/O

The return connection for a remote voltage sensing configuration. It is also used as ground for

the internal reference. Short to AGND for single-end sense configuration

6

7

I

VSNS–

Output voltage feedback input. A resistor divider from the V_OUTto VSNS–(tapped to FB pin)

sets the output voltage.

FB

Enable pin. The enable pin turns the DC/DC switching converter on or off. Floating EN pin

before start-up disables the converter. The recommended operating condition for EN pin is

maximum 5.5-V. Do not connect EN pin to VIN pin directly.

8

9

EN

I

Open-drain power-good status signal. When the FB voltage moves outside the specified limits,

PGOOD goes low after 2-µs delay.

PGOOD

VIN

O

P

Power-supply input pins for both integrated power MOSFET pair and the internal LDO. Place

the decoupling input capacitors from VIN pins to PGND pins as close as possible.

10, 21

11, 12,

13, 14,

15, 16,

17, 18

Power ground of internal low-side MOSFET. At least six PGND vias are required to be placed

as close as possible to the PGND pins. This minimizes parasitic impedance and also lowers

thermal resistance.

PGND

G

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表5-1. Pin Functions (continued)

NO.

NAME

VCC

SW

I/O⁽¹⁾

I/O

O

DESCRIPTION

Internal 3-V LDO output. An external bias with 3.3-V or higher voltage can be connected to this

pin to save the power losses on the internal LDO. The voltage source on this pin powers both

the internal circuitry and gate driver. Requires a 2.2-µF, at least 6.3-V, rating ceramic capacitor

from VCC pin to PGND pins as the decoupling capacitor and the placement is required to be

as close as possible.

19

20

Output switching terminal of the power converter. Connect this pin to the output inductor.

(1) I = Input, O = Output, P = Supply, G = Ground

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6 Specifications

6.1 Absolute Maximum Ratings

Over operating junction temperature range (unless otherwise noted) ⁽¹⁾

MIN

–0.3

–1.5

–0.3

–5

MAX

18

25

18

21.5

22

4

UNIT

V

Pin voltage

VIN

V

VIN –SW, DC

VIN –SW, < 20 ns transient

SW –PGND, DC

SW –PGND, < 20 ns transient

BOOT –PGND

BOOT –SW

V

–0.3

V

VCC

4

V

EN, PGOOD

6

V

MODE

4

V

TRIP, SS/REFIN, FB

VSNS–

3

V

0.3

10

150

V

Sinking current Power Good sinking current capability

Operating junction temperature, T_J

mA

°C

–40

–55

Storage temperature, T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/

JEDEC JS-001 ⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per ANSI/ESDA/

JEDEC JS-002⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating junction temperature range (unless otherwise noted)

MIN

2.7

NOM

MAX

16

UNIT

V

V_IN

Input voltage range when VCC pin is powered by a valid external bias

Input voltage range when using the internal VCC LDO

4.0

16

V

Minimum VIN before enabling the converter when using the internal VCC

LDO

V_IN

3.3

V

V_OUT

Output voltage range

0.6

3.13

–0.1

–50

0

5.5

3.6

5.5

VCC

1.5

50

V

Pin voltage External VCC bias

Pin voltage BOOT to SW

Pin voltage EN, PGOOD

Pin voltage MODE

V

Pin voltage TRIP, SS/REFIN, FB

V

Pin voltage

I_PG

mV

mA

VSNS–(refer to AGND)

Power Good input current capability

10

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Over operating junction temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

IL_PEAK

Maximum peak inductor current

Minimum R_TRIP

35

A

0

Ω

T_J

Operating junction temperature

125

°C

–40

6.4 Thermal Information

TPS548B28

THERMAL METRIC⁽¹⁾

RWW (QFN, JEDEC)

RWW (QFN, TI EVM)

UNIT

21 PINS

49.0

23.0

9.2

21 PINS

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

24.1

°C/W

Not applicable ⁽²⁾

0.7

Junction-to-top characterization parameter

Junction-to-board characterization parameter

0.5

9.0

8.7

ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Not applicable to an EVM layout.

6.5 Electrical Characteristics

T_J= –40°C to +125°C, VCC = 3 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SUPPLY

V_IN= 12 V, V_EN= 2 V, V_FB= V_INTREF

50mV (non-switching), no external

bias on VCC pin

+

I_Q(VIN)

VIN quiescent current

910

9.5

680

40

1007

20

µA

V_IN= 12 V, V_EN= 0 V, no external bias

on VCC pin

I_SD(VIN)

I_Q(VCC)

I_SD(VCC)

VIN shutdown supply current

VCC quiescent current

VCC shutdown current

T_J= 25°C, V_IN= 12 V, V_EN= 2 V, V_FB

= V_INTREF+ 50mV (non-switching), 3.3

V external bias on VCC pin

820

60

V_EN= 0 V, V_IN= 0 V, 3.3 V external

bias on VCC pin

UVLO

VIN_UVLO(rise)

VIN_UVLO(fall)

ENABLE

V_EN(rise)

VIN UVLO rising threshold

VIN UVLO falling threshold

VIN rising, VCC = 3.3 V external bias

VIN falling, VCC = 3.3 V external bias

2.1

2.4

2.7

V

1.55

1.85

2.15

EN voltage rising threshold

EN voltage falling threshold

EN voltage hysteresis

EN rising, enable switching

EN falling, disable switching

1.17

0.97

1.22

1.02

0.2

1.27

1.07

V

V_EN(fall)

V_EN(hyst)

V_EN(LKG)

V

Input leakage current into EN pin

V_EN= 3.3 V

0.5

5

µA

EN pin to AGND. EN floating disables

the converter.

EN internal pull-down resistance

6500

kΩ

INTERNAL LDO (VCC PIN)

Internal LDO output voltage

V_IN= 12 V, I_VCC(Load)= 2 mA

VCC rising

2.90

2.80

2.62

3.02

2.87

2.70

0.17

3.12

2.94

2.77

V

VCC_UVLO(rise)

VCC_UVLO(fall)

VCC_UVLO(hys)

VCC UVLO rising threshold

VCC UVLO falling threshold

VCC UVLO hysteresis

VCC falling

V

T_J= 25°C, V_IN= 4.0 V, I_VCC(Load)= 20

mA, non-switching

VCC LDO dropout voltage, 20mA load

VCC LDO short-circuit current limit

1.037

158

V_IN= 12 V, all temperature

52

105

mA

6

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6.5 Electrical Characteristics (continued)

T_J= –40°C to +125°C, VCC = 3 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

VCC LDO turn-off is controlled by FB

voltage during EN shutdown event

FB Threshold to turn off VCC LDO

REFERENCE VOLTAGE

90

146

mV

V_INTREF

Internal voltage reference

T_J= 25°C

600

1

mV

nA

Internal voltage reference range

Input leakage current into FB pin

T_J= 0°C to 85°C

T_J= –40°C to 125°C

V_FB= V_INTREF

597

594

603

606

40

I_FB(LKG)

T_J= -40°C to 125°C, V_SS/REFIN= 0.6 V,

VSNS- = AGND, refer to V_INTREF

SS/REFIN-to-FB Accuracy

0.6%

–0.6%

–3.6

PSEUDO REMOTE SENSE

SS/REFIN-to-FB Accuracy

SWITCHING FREQUENCY

T_J= -40°C to 125°C, V_SS/REFIN= 0.6 V,

VSNS- = AGND, refer to V_INTREF

3.6

mV

T_J= 25°C, V_IN= 12 V, V_OUT=1.25V,

R_MODE= 0 Ωto AGND

0.5

0.6

0.7

T_J= 25°C, V_IN= 12 V, V_OUT=1.25V,

R_MODE= 30.1 kΩto AGND

SW switching frequency, FCCM

operation

f_SW

0.8 MHz

1.0

T_J= 25°C, V_IN= 12 V, V_OUT=1.25V,

R_MODE= 60.4 kΩto AGND

0.70

0.85⁽²⁾

STARTUP

The delay from EN goes high to the

first SW rising edge with internal LDO

configuration. C_VCC= 2.2 µF. C_SS/REFIN

= 220 nF.

EN to first switching delay, internal

LDO

0.93

2

ms

The delay from EN goes high to the

first SW rising edge with external VCC

bias configuration. VCC bias should

reach regulation before EN ramp up.

C_SS/REFIN= 220 nF.

EN to first switching delay, external

VCC bias

0.55

1.5

0.9

ms

V_Orising from 0 V to 95% of final

setpoint, C_SS/REFIN= 1nF

t_SS

Internal fixed Soft-start time

1

SS/REFIN sourcing current

SS/REFIN sinking current

V_SS/REFIN= 0 V

V_SS/REFIN= 1 V

36

12

µA

POWER STAGE

R_DSON(HS)

R_DSON(LS)

High-side MOSFET on-resistance

Low-side MOSFET on-resistance

Minimum on-time

7.7

2.4

70

T_J= 25°C, BOOT–SW = 3 V

T_J= 25°C, VCC = 3 V

mΩ

ns

t_ON(min)

TJ = 25°C, VCC = Internal LDO

85

TJ = 25°C, VCC = Internal LDO, HS

FET Gate falling to rising

t_OFF(min)

Minimum off-time

220

ns

BOOT CIRCUIT

I_BOOT(LKG)

BOOT leakage current

T_J= 25°C, V_BOOT-SW= 3.3 V

35

50

µA

V

V_{BOOT-SW(UV_F)}

BOOT-SW UVLO falling threshold

T_J= 25°C, V_IN= 12 V, V_BOOT-SWfalling

2.0

OVERCURRENT PROTECTION

R_TRIP

TRIP pin resistance range

0

20

25

kΩ

Valley current on LS FET, 0-Ω ≤

Current limit clamp

19.2

22.9

120000

22.9

A

R_TRIP≤5.24-kΩ

K_OCL

Constant for R_TRIPequation

Current limit threshold

A×Ω

Valley current on LS FET, R_TRIP

AGND

=

I_{OCL (valley)}

19.2

25

A

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6.5 Electrical Characteristics (continued)

T_J= –40°C to +125°C, VCC = 3 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Valley current on LS FET, R_TRIP= 5.23

kΩ

I_{OCL (valley)}

Current limit threshold

22.9

A

Valley current on LS FET, R_TRIP= 6.04

kΩ

19.9

16

12

8.2

6

A

Valley current on LS FET, R_TRIP= 7.5

kΩ

Valley current on LS FET, R_TRIP= 10

kΩ

Valley current on LS FET, R_TRIP= 14.7

kΩ

Valley current on LS FET, R_TRIP= 20

kΩ

K_OCL

I_NOCL

Constant KOCL tolerance

Negative current limit threshold

-16.4%

-12%

-18%

-21%

–12

9%

12%

18%

21%

R_TRIP= 5.23 kΩ

6.04 kΩ ≤R_TRIP≤10 kΩ

R_TRIP= 14.7 kΩ

R_TRIP= 20 kΩ

All VINs

A

–10

–8

Zero-cross detection current threshold,

open loop

I_ZC

V_IN= 12 V, VCC = Internal LDO

400

mA

OUTPUT OVP AND UVP

Output Overvoltage-protection (OVP)

threshold voltage

V_OVP

113%

77%

116%

400

80%

68

119%

83%

t_OVP(delay)

V_UVP

Output OVP response delay

With 100-mV overdrive

ns

µs

Output Undervoltage-protection (UVP)

threshold voltage

t_UVP(delay)

Output UVP filter delay

PGOOD threshold

POWER GOOD

PGOOD high, FB rising

PGOOD low, FB rising

PGOOD low, FB falling

PGOOD high, FB rising

89%

113%

77%

92.5%

116%

80%

95%

119%

83%

V_PGTH

OOB (Out-Of-Bounds) threshold

PGOOD sink current

103% 105.5%

108%

V_PGOOD= 0.4 V, V_IN= 12 V, VCC =

Internal LDO

I_PG

17

mA

mV

I_PGOOD= 5.5 mA, V_IN= 12 V, VCC =

Internal LDO

V_PG(low)

PGOOD low-level output voltage

400

t_PGDLY(rise)

t_PGDLY(fall)

Delay for PGOOD from low to high

Delay for PGOOD from high to low

1.06

0.5

1.33

5

ms

µs

PGOOD leakage current when pulled T_J= 25°C, V_PGOOD= 3.3 V, V_FB

=

I_PG(LKG)

5

µA

high

V_INTREF

V_IN= 0 V, VCC = 0 V, V_EN= 0 V,

PGOOD pulled up to 3.3 V through a

100-kΩresistor

710

850

mV

PGOOD clamp low-level output

voltage

V_IN= 0 V, VCC = 0 V, V_EN= 0 V,

PGOOD pulled up to 3.3 V through a

10-kΩresistor

1000

1.5

mV

V

Min VCC for valid PGOOD output

V

_PGOOD≤0.4 V

OUTPUT DISCHARGE

R_DischgOutput discharge resistance

V_IN= 12 V, VCC = Internal LDO, V_SW

= 0.5 V, power conversion disabled

70

Ω

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6.5 Electrical Characteristics (continued)

T_J= –40°C to +125°C, VCC = 3 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

THERMAL SHUTDOWN

T_SDN

Thermal shutdown threshold⁽¹⁾

Thermal shutdown hysteresis⁽¹⁾

Temperature rising

150

165

30

°C

T_HYST

(1) Specified by design. Not production tested.

(2) Fsw variates with Vout due to D-CAP3 control mode.

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6.6 Typical Characteristics

100

95

90

85

80

75

100

95

90

85

80

75

70

65

60

55

50

V_OUT= 0.9 V

V_OUT= 1.0 V

V_OUT= 1.2 V

V_OUT= 1.8 V

V_OUT= 2.5 V

V_OUT= 3.3 V

V_OUT= 5.0 V

70

65

60

55

50

V_OUT= 1.0 V

V_OUT= 1.2 V

V_OUT= 1.8 V

V_OUT= 2.5 V

V_OUT= 3.3 V

V_OUT= 5.0 V

0

2

4

6

8

Output Current (A)

10

12

14

16

18

20

0

2

4

6

8

Output Current (A)

10

12

14

16

18

20

图6-1. Efficiency vs Output Current, 12 V_IN, 800 kHz, DCM, VCC 图6-2. Efficiency vs Output Current, 12 V_IN, 800 kHz, DCM, VCC

= Int

= EXT 3.3 V

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

55

50

V_OUT= 0.9 V

V_OUT= 1.0 V

V_OUT= 1.2 V

V_OUT= 1.8 V

V_OUT= 2.5 V

V_OUT= 3.3 V

V_OUT= 5.0 V

V_OUT= 0.9 V

V_OUT= 1.0 V

V_OUT= 1.2 V

V_OUT= 1.8 V

V_OUT= 2.5 V

V_OUT= 3.3 V

V_OUT= 5.0 V

0

2

4

6

8

Output Current (A)

10

12

14

16

18

20

0

2

4

6

8

Output Current (A)

10

12

14

16

18

20

图6-3. Efficiency vs Output Current, 12 V_IN, 800 kHz, FCCM,

图6-4. Efficiency vs Output Current, 12 V_IN, 800 kHz, FCCM,

VCC = Int

VCC = EXT 3.3 V

115

105

95

115

105

95

85

75

65

55

Nat Conv

100 LFM

Nat Conv

100 LFM

45

200LFM

400LFM

200LFM

400LFM

35

25

0

2

4

6

8

10

12

Output Current (A)

14

16

18

20

0

2

4

6

8

10

12

Output Current (A)

14

16

18

20

D002

D001

Vin = 12 V

800 nH

Vout = 5 V

600 kHz

Int Vcc

Vin = 12 V

300 nH

Vout = 1 V

800 kHz

Int Vcc

图6-6. Safe Operating Area, V_OUT= 5 V

图6-5. Safe Operating Area, V_OUT= 1.0 V

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6.6 Typical Characteristics (continued)

115

105

95

115

105

95

85

75

65

55

45

35

25

85

75

65

55

Nat Conv

100 LFM

200LFM

400LFM

45

35

25

100 LFM

200LFM

400LFM

0

2

4

6

8

Output Current (A)

10

12

14

16

18

20

0

2

4

6

8

Output Current (A)

10

12

14

16

18

20

D003

D004

Vin = 12 V

300 nH

Vout = 1 V

800 kHz

Ext Vcc 3.3 V

Vin = 12 V

800 nH

Vout = 5 V

600 kHz

Ext Vcc 3.3 V

图6-7. Safe Operating Area, V_OUT= 1 V

图6-8. Safe Operating Area, V_OUT= 5 V

3.355

3.35

1100

1050

1000

950

900

850

800

750

700

650

600

550

500

450

400

350

300

Vin = 8V

Vin = 12V

Vin = 16V

800 nH

600 kHz

VCC = Int

FCCM

3.345

3.34

3.335

3.33

3.325

3.32

3.315

3.31

600 kHz

800 kHz

1000 kHz

3.305

3.3

0

2

4

6

8

10

12

Output Current (A)

14

16

18

20

1

1.4 1.8 2.2 2.6 3

Output Voltage (V)

3.4 3.8 4.2 4.6

5

D010

图6-10. Output Voltage vs Output Current

图6-9. Switching Frequency vs Output Voltage

20

15

10

5

3.04

3.03

3.02

3.01

3

0

2.99

-50

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

Junction Temperature (èC)

D014

D015

V_IN= 12 V

V_EN= 0 V

Internal VCC LDO

V_IN= 12 V I_VCC= 2 mA

图6-12. VCC LDO vs Junction Temperature

图6-11. I_SD(VIN)vs Junction Temperature

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6.6 Typical Characteristics (continued)

0.904

40

39

38

37

36

35

34

33

32

0.902

0.9

0.898

0.896

-50

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

Junction Temperature (èC)

D016

D020

V_IN= 12 V

图6-13. V_INTREFvs Junction Temperature

图6-14. I_SS(source)vs Junction Temperature

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7 Detailed Description

7.1 Overview

The TPS548B28 device is a high-efficiency, single-channel, small-sized, synchronous-buck converter. The

device suits low output voltage point-of-load applications with 20-A or lower output current in server, storage, and

similar computing applications. The TPS548B28 features proprietary D-CAP3 control mode combined with

adaptive on-time architecture. This combination builds modern low-duty-ratio and ultra-fast load-step-response

DC/DC converters in an ideal fashion. The output voltage ranges from 0.6 V to 5.5 V. The conversion input

voltage ranges from 2.7 V to 16 V and the VCC input voltage ranges from 3.13 V to 3.6 V. The D-CAP3 control

mode uses emulated current information to control the modulation. An advantage of this control scheme is that it

does not require a phase-compensation network outside which makes the device easy-to-use and also allows

low external component count. Another advantage of this control scheme is that it supports stable operation with

all low-ESR output capacitors (such as ceramic capacitor and low ESR polymer capacitor). Adaptive on-time

control tracks the preset switching frequency over a wide range of input and output voltages while increasing

switching frequency as needed during load-step transient.

7.2 Functional Block Diagram

PGOOD

SS/

REFIN

Soft-start

generator

PG Falling

Threshold

+

UV

Internal

Soft-start

VIN

EN

PGOOD Driver

LDO

+

OV

VCC

Reference

generator

VCC

PG Rising

Threshold

FB

BOOT

REG

PGOOD

+

VCCOK

Control Logic

VINOK

BOOT

VIN

VCC UVLO

VSNS-

VIN

PWM

+

VIN UVLO

ñ

t_ONgenerator

Minimum On/Off

Light Load

FCCM/Skip

Internal

Ramp

VCC UVLO

VIN UVLO

SW

XCON

EN

Enable

Output OVP/UVP

Thermal Shutdown

EN

+

1.22V / 1.02V

SW

Valley Current

Limit & ZCD

OC

Limit

TRIP

MODE

AGND

PGND

MODE

Selection

Fsw &

Mode

+

ThermalOK

165°C /

135°C

Output Soft

Discharge

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7.3 Feature Description

7.3.1 Internal VCC LDO And Using External Bias On VCC Pin

The TPS548B28 has an internal 3.0-V LDO, featuring input from VIN and output to VCC. When the EN voltage

rises above the enable threshold (typically 1.22 V), the internal LDO is enabled and starts regulating output

voltage on the VCC pin. The VCC voltage provides the bias voltage for the internal analog circuitry and also

provides the supply voltage for the gate drives.

The VCC pin must be bypassed with a 2.2-µF, at least 6.3-V rating ceramic capacitor. An external bias that is

above the output voltage of the internal LDO can override the internal LDO. This enhances the efficiency of the

converter because the VCC current now runs off this external bias instead of the internal linear regulator.

The VCC UVLO circuit monitors the VCC pin voltage and disables the whole converter when VCC falls below the

VCC UVLO falling threshold. Maintaining a stable and clean VCC voltage is required for a smooth operation of

the device.

Considerations when using an external bias on the VCC pin are as follows:

• When the external bias is applied on the VCC pin early enough (for example, before EN signal comes in), the

internal LDO will be always forced off and the internal analog circuits will have a stable power supply rail at

their power enable.

• (Not recommended) When the external bias is applied on the VCC pin late (for example, after EN signal

comes in), any power-up and power-down sequencing can be applied as long as there is no excess current

pulled out of the VCC pin. Understand that an external discharge path on the VCC pin, which can pull a

current higher than the current limit of the internal LDO from the VCC pin, can potentially turn off VCC LDO,

thereby shutting down the converter output.

• A good power-up sequence is when at least one of VIN UVLO rising threshold or EN rising threshold is

satisfied later than VCC UVLO rising threshold. For example, a practical power-up sequence is: VIN applied

first, then the external bias applied, and then EN signal goes high.

7.3.2 Enable

When the EN pin voltage rises above the enable threshold voltage (typically 1.22 V) and VIN rises above the VIN

UVLO rising threshold, the device enters its internal power-up sequence. The EN to first switching delay is

specified in Start-up section in 节6.5.

When using the internal VCC LDO, the internal power-up sequence includes three sequential steps. During the

first period, the VCC voltage is charged up on a VCC bypass capacitor by an 11-mA current source. The length

of this VCC LDO start-up time varies with the capacitance on VCC pin. However, if the VIN voltage ramps up

very slowly, the VCC LDO output voltage will be limited by the VIN voltage level, thus the VCC LDO start-up time

can be extended longer. Because the VCC LDO start-up time is relatively long, the internal V_INTREFbuild-up

happens and finishes during this period. After the VCC voltage crosses above the VCC UVLO rising threshold

(typically 2.87 V), the device moves to the second step, power-on delay. The MODE pin setting detection, SS/

REFIN pin detection, and control loop initialization are finished within this 285-μs delay. Soft-start ramp starts

when the 285-μs power-on delay finishes. During the soft-start ramp power stage, switching does not happen

until the SS/REFIN pin voltage reaches 50 mV. This introduces a SS delay that varies with the external

capacitance on SS/REFIN pin.

图 7-1 shows an example where the VIN UVLO rising threshold is satisfied earlier than the EN rising threshold.

In this scenario, the VCC UVLO rising threshold becomes the gating signal to start the internal power-up

sequence, and the sequence between VIN and EN does not matter.

When using an external bias on the VCC pin, the internal power-up sequence still includes three sequential

steps. The first period is much shorter because VCC voltage is built up already. A 100-µs period allows the

internal references to start up and reach regulation points. This 100-µs period includes not only the 0.6-V

V_INTREF, but also all of the other reference voltages for various functions. The device then moves to the second

step, power-on delay. The MODE pin setting detection, SS/REFIN pin detection, and control loop initialization

are finished within this 285-μs delay. Soft-start ramp starts when the 285-μs power-on delay finishes. During

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the soft-start ramp power stage, switching does not happen until the SS/REFIN pin voltage reaches 50 mV. This

introduces a SS delay that varies with the external capacitance on SS/REFIN pin.

图 7-2 shows an example where the VIN UVLO rising threshold and EN rising threshold are satisfied later than

the VCC UVLO rising threshold. In this scenario, the VIN UVLO rising threshold or EN rising threshold, whoever

is satisfied later, becomes the gating signal to start the internal power-up sequence.

2.4V

VIN

1.22V

EN

2.87V

VCC LDO

Power-on

delay

VCC LDO

Startup

50mV

SS/REFIN

SS delay

FB

SW pulses are omitted to

simplify the illustration

……

SW

图7-1. Internal Power-up Sequence Using Internal LDO

2.87V

VCC

External

3.3V Bias

2.4V

VIN

EN

1.22V

Power-on

delay

V_REF

Build-up

SS/REFIN

50mV

SS delay

FB

SW pulses are omitted to

simplify the illustration

……

SW

图7-2. Internal Power-up Sequence Using External Bias

The EN pin has an internal filter to avoid unexpected ON or OFF due to small glitches. The time constant of this

RC filter is 5 µs. For example, when applying 3.3-V voltage source on the EN pin that jumps from 0 V to 3.3 V

with an ideal rising edge, the internal EN signal will reach 2.086 V after 5 µs, which is 63.2% of applied 3.3-V

voltage level.

A internal pulldown resistor is implemented between the EN pin and AGND pin. To avoid impact to the EN rising/

falling threshold, this internal pulldown resistor is set to 6.5 MΩ. With this pulldown resistor, floating the EN pin

before start-up keeps the device under disabled state. During nominal operation when the power stage switches,

this large internal pulldown resistor can not have enough noise immunity to hold EN pin low.

The recommended operating condition for EN pin is maximum 5.5 V. Do not connect the EN pin to the VIN pin

directly.

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7.3.3 Output Voltage Setting

The output voltage is programmed by the voltage-divider resistors, R_{FB_HS}and R_{FB_LS}. Connect R_{FB_HS}between

the FB pin and the positive node of the load, and connect R_{FB_LS}between the FB pin and VSNS– pin. The

recommended R_{FB_LS}value is 10 kΩ, ranging from 1 kΩto 20 kΩ. Determine R_{FB_HS}by using 方程式1.

V_O- V

INTREF

R_{FB _HS}

=

ìR_{FB _LS}

V

INTREF

(1)

The FB accuracy is determined by two elements. The first element is the accuracy of the internal 600-mV

reference, which will be applied to the SS/REFIN pin unless an external V_REFis applied. The TPS548B28 device

offers ±0.5% V_INTREFaccuracy from a 0°C to 85°C temperature range, and ±1.0% V_INTREFaccuracy from –40°C

to 125°C temperature range. The second element is the SS/REFIN-to-FB accuracy which tells how accurately

the control loop regulates FB node to SS/REFIN pin. The TPS548B28 device offers ±0.6% SS/REFIN-to-FB

accuracy from –40°C to 125°C temperature range. For example, when operating from a 0°C to 85°C

temperature range, the total FB accuracy is ±1.1% which includes the impact from chip junction temperature and

also the variation from part to part.

To improve the overall V_OUTaccuracy, using a ±1% accuracy or better resistor for the FB voltage divider is highly

recommended.

Regardless of remote sensing or single-end sensing connection, the FB voltage divider, R_{FB_HS}and R_{FB_LS}

,

must be always placed as close as possible to the device.

7.3.3.1 Remote Sense

The TPS548B28 device offers remote sense function through FB and VSNS– pins. Remote sense function

compensates a potential voltage drop on the PCB traces thus helps maintain V_OUTtolerance under steady state

operation and load transient event. Connecting the FB voltage divider resistors to the remote location allows

sensing to the output voltage at a remote location. The connections from the FB voltage divider resistors to the

remote location must be a pair of PCB traces with at least 12-mil trace width, and must implement Kelvin sensing

across a high bypass capacitor of 0.1 μF or higher. The ground connection of the remote sensing signal must

be connected to the VSNS– pin. The V_OUTconnection of the remote sensing signal must be connected to the

feedback resistor divider with the lower feedback resistor, R_{FB_LS}, terminated at VSNS– pin. To maintain stable

output voltage and minimize the ripple, the pair of remote sensing lines must stay away from any noise sources

such as inductor and SW nodes, or high frequency clock lines. TI recommends to shield the pair of remote

sensing lines with ground planes above and below.

Single-ended Vo sensing is often used for local sensing. For this configuration, connect the higher FB resistor,

R_{FB_HS}, to a high-frequency local bypass capacitor of 0.1 μF or higher, and short VSNS–to AGND.

The recommended VSNS–operating range (refer to AGND pin) is –50 mV to +50 mV.

7.3.4 Internal Fixed Soft Start and External Adjustable Soft Start

The TPS548B28 implements a circuit to allow both internal fixed soft start and external adjustable soft start. The

internal soft-start time is typically 1.5 ms. The soft-start time can be increased by adding a soft-start (SS)

capacitor between the SS/REFIN and VSNS- pins. The total SS capacitor value can be determined by Equation

2. The device follows the longer SS ramp among the internal SS time and the SS time determined by the

external SS capacitors. The recommended maximum SS capacitor is 1 µF. A minimum 1-nF SS capacitor is

required.

The device does not require a capacitor from SS/REFIN pin to AGND, thus TI does not recommend to place a

capacitor from the SS/REFIN pin to AGND. If both C_SS/REFIN-to-VSNS– and C_SS/REFIN-to-AGND capacitors

exist, place C_SS/REFIN-to-VSNS–more closely with shortest trace back to VSNS–pin.

t

_SS(ms)ì36(mA )

C_SS(nF)=

V_INTREF( V)

(2)

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The TPS548B28 provides an analog input pin (SS/REFIN) to accept an external reference. When an external

voltage signal is applied between SS/REFIN pin and VSNS- pin, it acts as the reference voltage thus FB voltage

follows this external voltage signal exactly. Apply this external reference to the SS/REFIN pin before the EN high

signal is recommended. The external reference must be equal to or higher than the internal reference level to

ensure correct Power Good thresholds during soft start.

With an external reference applied, the internal fixed soft start controls output voltage ramp during start-up. After

soft start finishes, the external voltage signal can be in a range of 0.5 V to 1.2 V.

When driving the SS/REFIN pin with an external resistor divider, the resistance must be low enough so that the

external voltage source can overdrive the internal current source.

7.3.5 External REFIN For Output Voltage Tracking

The TPS548B28 provides an analog input pin (SS/REFIN) to accept an external reference (that is a DC voltage

source). The device always looks at the voltage on this SS/REFIN pin as the reference for the control loop.

When an external voltage reference is applied between the SS/REFIN pin and VSNS– pin, it acts as the

reference voltage thus FB voltage follows this external voltage reference exactly. The same ±0.6% SS/REFIN-to-

FB accuracy from -40°C to 125°C temperature range applies here too.

In the middle of internal power-on delay, a detection circuit senses the voltage on the SS/REFIN pin to tell

whether an active DC voltage source is applied. Before the detection happens, the SS/REFIN pin tries to

discharge any energy on SS/REFIN capacitors through an internal 120-Ωresistor to AGND. This discharge lasts

for 125 µs. Then, within a 32-µs window, the detection circuit compares the SS/REFIN pin voltage with an

internal reference equal to 89% of V_INTREF. This discharge operation ensure a SS capacitor with left-over energy

will not be wrongly detected as a voltage reference. If the external voltage reference failed to supply sufficient

current and hold voltage level higher than 89% of V_INTREF, the SS/REFIN detection circuit will provide wrong

detection result.

If the detection result is that SS/REFIN pin voltage falls below 89% of V_INTREFwhich tells no external reference is

connected, the device first uses the internal fixed V_INTREFas the reference for PGOOD, V_OUTOVP, and V_OUT

UVP threshold. On this configuration, given SS/REFIN pin sees a soft-start ramp on this pin, the slower ramp

among the internal fixed soft start and the external soft start determines the start-up of FB. After both the internal

and external soft-start ramp finishes, the power-good signal becomes high after a 1.06-ms internal delay. The

whole internal soft-start ramp takes 2 ms to finish. The external soft-start done signal goes high when FB

reaches a threshold equal to V_INTREF– 50 mV. The device waits for the PGOOD status transition from low to

high, then starts using the SS/REFIN pin voltage, instead of the internal V_INTREFas the reference for PGOOD,

V_OUTOVP, and V_OUTUVP threshold.

If the detection result is that SS/REFIN pin voltage holds higher than 89% of V_INTREFwhich tells an active DC

voltage source is used as an external reference, the device always uses the SS/REFIN pin voltage instead of the

internal V_INTREFas the reference for PGOOD, V_OUTOVP, and V_OUTUVP threshold. On this configuration,

because the SS/REFIN pin sees a DC voltage and no soft-start ramp on this pin, the internal fixed soft start is

used for start-up. After the internal soft-start ramp finishes, the power-good signal becomes high after a 1.06-ms

internal delay. The whole internal soft-start ramp takes 2 ms to finish because the soft-start ramp goes beyond

V_INTREF

.

On this external REFIN configuration, applying a stabilized DC external reference to the SS/REFIN pin before

EN high signal is recommended. During the internal power-on delay, the external reference must be capable of

holding the SS/REFIN pin equal to or higher than 89% of V_INTREF, so that the device can correctly detect the

external reference and choose the right thresholds for power good, V_OUTOVP, and V_OUTUVP. After the power

good status transits from low to high, the external reference can be set in a range of 0.5 V to 1.2 V. To overdrive

the SS/REFIN pin during nominal operation, the external reference has to be able to sink more than 36-µA

current if the external reference is lower than the internal V_INTREF, or source more than 12-µA current if the

external reference is higher than the internal V_INTREF. When driving the SS/REFIN pin by an external reference

through a resistor divider, the resistance of the divider must be low enough to provide the sinking, or sourcing

current capability.

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The configuration of applying EN high signal first, then applying an external ramp on the SS/REFIN pin as a

tracking reference can be achieved, as long as design considerations for power good, V_OUTOVP, and V_OUTUVP

have been taken. Please contact Texas Instruments for detailed information about this configuration.

If the external voltage source must transition up and down between any two voltage levels, the slew rate must be

no more than 1 mV/μs.

7.3.6 Frequency and Operation Mode Selection

The TPS548B28 provides forced CCM operation for tight output ripple application and auto-skip Eco-mode for

high light-load efficiency. The TPS548B28 allows users to select the switching frequency and operation mode by

connecting a resistor from the MODE pin to AGND pin. 表7-1 lists the resistor values for the switching frequency

and operation mode selection. TI recommends ±1% tolerance resistors with a typical temperature coefficient of

±100 ppm/°C.

The MODE state will be set and latched during the internal power-on delay period. Changing the MODE pin

resistance after the power-on delay will not change the status of the device. The internal circuit will set the

MODE pin status to 600 kHz / skip-mode if MODE pin is left open during the power-on delay period.

To make sure the internal circuit detects the desired option correctly, do not place any capacitor on the MODE

pin.

表7-1. MODE Pin Selection

MODE PIN

CONNECTIONS

OPERATION MODE UNDER LIGHT

LOAD

SWITCHING FREQUENCY

(f_SW) (kHz)⁽¹⁾

Short to VCC

Skip-mode

600

800

243-kΩ± 10% to AGND

121-kΩ± 10% to AGND

60.4-kΩ±10% to AGND

30.1-kΩ±10% to AGND

Short to AGND

Skip-mode

1000

800

Forced CCM

600

(1) Switch frequency is based on 3.3 Vout. Frequency varies with Vout.

7.3.7 D-CAP3^™Control Mode

R_R

SW

To comparator

C_R

V_OUT

图7-3. Internal RAMP Generation Circuit

The TPS548B28 uses D-CAP3 control mode to achieve the fast load transient while maintaining the ease-of-use

feature. The D-CAP3 control mode architecture includes an internal ripple generation network enabling the use

of very low-ESR output capacitors such as multi-layered ceramic capacitors (MLCC) and low-ESR polymer

capacitors. No external current sensing network or voltage compensators are required with D-CAP3 control

mode architecture. The role of the internal ripple generation network is to emulate the ripple component of the

inductor current information and then combine it with the voltage feedback signal to regulate the loop operation.

The amplitude of the ramp is determined by V_IN, V_OUT, operating frequency, and the R-C time-constant of the

internal ramp circuit. At different switching frequency settings (see 表 7-1), the R-C time-constant varies to

maintain relatively constant ramp amplitude. Also, the device uses internal circuitry to cancel the dc offset

caused by injected ramp, and significantly reduces the dc offset caused by the output ripple voltage, especially

under light load condition.

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For any control topologies supporting no external compensation design, there is a minimum range, maximum

range, or both, of the output filter it can support. The output filter used with the TPS548B28 is a low-pass L-C

circuit. This L-C filter has double pole that is described in 方程式3.

1

f

=

P

2´ p´ L

´ C

OUT

(3)

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal

gain of the TPS548B28. The low frequency L-C double pole has a 180-degree drop in phase. At the output filter

frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. The internal ripple

generation network introduces a high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per

decade and increases the phase by 90 degrees per decade above the zero frequency.

After identifying the application requirements, the output inductance must be designed so that the inductor peak-

to-peak ripple current is approximately between 15% and 40% of the maximum output current.

The inductor and capacitor selected for the output filter must be such that the double pole of 方程式 3 is located

no higher than 1/30th of operating frequency. Choose very small output capacitance leads to relatively high

frequency L-C double pole, which allows that overall loop gain stays high until the L-C double frequency. Given

the zero from the internal ripple generation network is relatively high frequency as well, the loop with very small

output capacitance can have too high crossover frequency which is not desired. Use 表 7-2 to help locate the

internal zero based on the selected switching frequency.

表7-2. Locating the Zero

SWITCHING FREQUENCIES

ZERO (f_Z) LOCATION (kHz)

(f_SW) (kHz)

600

800

84.5

106

1000

In general, where reasonable (or smaller) output capacitance is desired, output ripple requirement and load

transient requirements can be used to determine the necessary output capacitance for stable operation.

For the maximum output capacitance recommendation, select the inductor and capacitor values so that the L-C

double pole frequency is no less than 1/100th of operating frequency. With this starting point, verify the small

signal response on the board using the phase margin at the loop crossover is greater than 50 degrees.

The actual maximum output capacitance can go higher as long as phase margin is greater than 50 degrees.

However, small signal measurement (bode plot) must be done to confirm the design.

If MLCC is used, consider the derating characteristics to determine the final output capacitance for the design.

For example, when using an MLCC with specifications of 10 µF, X5R and 6.3 V, the derating by DC bias and AC

bias are 80% and 50%, respectively. The effective derating is the product of these two factors, which in this case

is 40% and 4 µF. Consult with capacitor manufacturers for specific characteristics of the capacitors to be used in

the system/applications.

For higher output voltage at or above 2 V, additional phase boost can be required to secure sufficient phase

margin due to phase delay/loss for higher output voltage (large on-time (t_ON)) setting in a fixed-on-time topology

based operation. A feedforward capacitor placed in parallel with R_{FB_HS}is found to be very effective to boost the

phase margin at loop crossover. Refer to the Optimizing Transient Response of Internally Compensated dc-dc

Converters With Feedforward Capacitor application report for details.

Besides boosting the phase, a feedforward capacitor feeds more V_OUTnode information into FB node by the AC

coupling. This feedforward during load transient event enables the control loop a faster response to V_OUT

deviation. However, this feedforward during steady state operation also feeds more V_OUTripple and noise into

FB. High ripple and noise on FB usually leads to more jitter, or even double pulse behavior. To determine the

final feedforward capacitor value, impacts to phase margin, load transient performance, and ripple and nosie on

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FB must be all considered. Using Frequency Analysis equipment to measure the crossover frequency and the

phase margin is recommended.

7.3.8 Low-side FET Zero-Crossing

The TPS548B28 uses a zero-crossing circuit to perform the zero inductor-current detection during skip-mode

operation. The function compensates the inherent offset voltage of the Z-C comparator and delay time of the Z-C

detection circuit. The zero-crossing threshold is set to a positive value to avoid negative inductor current. As a

result, the device delivers better light-load efficiency.

7.3.9 Current Sense and Positive Overcurrent Protection

For a buck converter, during the on-time of the high-side FET, the switch current increases at a linear rate

determined by input voltage, output voltage, the on-time, and the output inductor value. During the on-time of the

low-side FET, this current decreases linearly. The average value of the switch current equals to the load current.

The output overcurrent limit (OCL) in the TPS548B28 device is implemented using a cycle-by-cycle valley

current detect control circuit. The inductor current is monitored during the on-time of the low-side FET by

measuring the low-side FET drain-to-source current. If the measured drain-to-source current of the low-side FET

is above the current limit threshold, the low-side FET stays ON until the current level becomes lower than the

current limit threshold. This type of behavior reduces the average output current sourced by the device. During

an overcurrent condition, the current to the load exceeds the current to the output capacitors, thus the output

voltage tends to decrease. Eventually, when the output voltage falls below the undervoltage-protection threshold

(80%), the UVP comparator detects it and shuts down the device after a wait time of 68 µs. The device then

enters a hiccup sleep period for approximately 14 ms. After this waiting period, the device attempts to start up

again. 图 7-4 shows the cycle-by-cycle valley current limit behavior as well as the wait time before the device

shuts down.

If an OCL condition happens during start-up, the device still has cycle-by-cycle current limit based on low-side

valley current. After soft start is finished, the UV event which is caused by the OC event shuts down the device

and enters hiccup mode mode with a wait time of 68 µs.

The resistor, R_TRIPconnected from the TRIP pin to AGND sets current limit threshold. A ±1% tolerance resistor

is highly recommended because a worse tolerance resistor provides less accurate OCL threshold. Equation 4

calculates the R_TRIPfor a given overcurrent limit threshold on the device. To simplify the calculation, use a

constant, K_OCL, to replace the value of 12x10⁴. Equation 4 calculates the overcurrent limit threshold for a given

R_TRIPvalue. The tolerance of K_OCLis listed in 节 6.5 to help you analyze the tolerance of the overcurrent limit

threshold.

To protect the device from unexpected connection on TRIP pin, an internal fixed OCL clamp is implemented.

This internal OCL clamp limits the maximum valley current on LS FET when TRIP pin has too small resistance to

AGND, or is accidentally shorted to ground.

(4)

where

• I_OCLIMis overcurrent limit threshold for load current in A

• R_TRIPis TRIP resistor value in Ω

• K_OCLis a constant for the calculation

• V_INis input voltage value in V

• V_Ois output voltage value in V

• L is output inductor value in µH

• f_SWis switching frequency in MHz

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V -V ì V

K_OCL

(

)

1

2

1

IN

O

I_OCLIM

=

+

ì

R_TRIP

V

L ì f_SW

IN

(5)

where

• I_OCLIMis overcurrent limit threshold for load current in A

• R_TRIPis TRIP resistor value in Ω

• K_OCLis a constant for the calculation

• V_INis input voltage value in V

• V_Ois output voltage value in V

• L is output inductor value in µH

• f_SWis switching frequency in MHz

图7-4. Overcurrent Protection

7.3.10 Low-side FET Negative Current Limit

The device has a fixed, cycle-by-cycle negative current limit. Similar with the positive overcurrent limit, the

inductor current is monitored during the on-time of the low-side FET. To prevent too large negative current

flowing through low-side FET, when the low-side FET detects a –10-A current (typical threshold), the device

turns off low-side FET and then turns on the high-side FET for a proper on-time (determined by V_IN/V_O/f_SW).

After the high-side FET on-time expires, the low-side FET turns on again.

The device must not trigger the –10-A negative current limit threshold during nominal operation, unless a small

inductor value that is too small is chosen or the inductor becomes saturated. This negative current limit is utilized

to discharge output capacitors during an output OVP or an OOB event. See 节7.3.12 and 节7.3.13 for details.

7.3.11 Power Good

The device has power-good output that indicates high when the converter output is within the target. The power-

good output is an open-drain output and must be pulled up to the VCC pin or an external voltage source (<5.5 V)

through a pullup resistor (typically 30.1 kΩ). The recommended power-good pullup resistor value is 1 kΩto 100

kΩ.

After both the internal and external soft-start ramp finishes, the power-good signal becomes high after a 1.06-ms

internal delay. The whole internal soft-start ramp takes 2 ms to finish. The external soft-start done signal goes

high when FB reaches threshold equal to V_INTREF– 50 mV. If the FB voltage drops to 80% of the V_INTREF

voltage or exceeds 116% of the V_INTREFvoltage, the power-good signal latches low after a 2-µs internal delay.

The power-good signal can only be pulled high again after re-toggling EN or a reset of VIN.

If the input supply fails to power up the device, for example VIN and VCC both stay at zero volt, the power-good

pin clamps low by itself when this pin is pulled up through an external resistor.

After VCC voltage level rises above the minimum VCC threshold for valid PGOOD output (maximum 1.5 V),

internal power-good circuit is enabled to hold the PGOOD pin to the default status. By default, PGOOD is pulled

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low and this low-level output voltage is no more than 400 mV with 5.5-mA sinking current. The power-good

function is fully activated after the soft-start operation is completed.

7.3.12 Overvoltage and Undervoltage Protection

The device monitors a resistor-divided feedback voltage to detect overvoltage and undervoltage events. When

the FB voltage becomes lower than 80% of the V_INTREFvoltage, the UVP comparator detects and an internal

UVP delay counter begins counting. After the 68-µs UVP delay time, the device enters hiccup mode and re-

starts with a sleep time of 14 ms. The UVP function enables after the soft-start period is complete.

When the FB voltage becomes higher than 116% of the V_INTREFvoltage, the OVP comparator detects and the

circuit latches OFF the high-side MOSFET driver and turns on the low-side MOSFET until reaching a negative

current limit I_NOCL. Upon reaching the negative current limit, the low-side FET is turned off, and the high-side

FET is turned on again for a proper on-time (determined by V_IN/V_O/f_SW). The device operates in this cycle until

the output voltage is pulled down under the UVP threshold voltage for 68 µs. After the 68-µs UVP delay time,

both the high-side FET and the low-side FET are latched OFF. The fault is cleared with a reset of VIN or by

retoggling the EN pin.

During the 68-μs UVP delay time, if the output voltage becomes higher than the UV threshold, thus is not

qualified for UV event, the timer will be reset to zero. When the output voltage triggers UV threshold again, the

timer of the 68 μs re-starts.

7.3.13 Out-Of-Bounds (OOB) Operation

The device has an out-of-bounds (OOB) overvoltage protection that protects the output load at a much lower

overvoltage threshold of 5% above the V_INTREFvoltage. OOB protection does not trigger an overvoltage fault, so

the device is on non-latch mode after an OOB event. OOB protection operates as an early no-fault overvoltage-

protection mechanism. During the OOB operation, the controller operates in forced CCM mode. Turning on the

low-side FET beyond the zero inductor current quickly discharges the output capacitor thus helping the output

voltage to fall quickly towards the setpoint. During the operation, the cycle-by-cycle negative current limit is also

activated to ensure the safe operation of the internal FETs.

7.3.14 Output Voltage Discharge

When the device is disabled through EN, it enables the output voltage discharge mode. This mode forces both

high-side and low-side FETs to latch off, but turns on the discharge FET, which is connected from SW to PGND,

to discharge the output voltage. After the FB voltage drops below 90 mV, the discharge FET is turned off.

The output voltage discharge mode is activated by any of the following fault events:

1. EN pin goes low to disable the converter.

2. Thermal shutdown (OTP) is triggered.

3. VCC UVLO (falling) is triggered.

4. VIN UVLO (falling) is triggered.

7.3.15 UVLO Protection

The device monitors the voltage on both the VIN and the VCC pins. If the VCC pin voltage is lower than the

VCC_UVLOfalling threshold voltage, the device shuts off. If the VCC voltage increases beyond the VCC_UVLOrising

threshold voltage, the device turns back on. VCC UVLO is a non-latch protection.

When the VIN pin voltage is lower than the VIN_UVLOfalling threshold voltage but the VCC pin voltage is still

higher than VCC_UVLOrising threshold voltage, the device stops switching and discharges SS/REFIN pin. After

the VIN voltage increases beyond the VIN_UVLOrising threshold voltage, the device re-initiates the soft start and

switches again. VIN UVLO is a non-latch protection.

7.3.16 Thermal Shutdown

The device monitors internal junction temperature. If the temperature exceeds the threshold value (typically

165°C), the device stops switching and discharges SS/REFIN pin. When the temperature falls approximately

30°C below the threshold value, the device turns back on with a re-initiated soft start. Thermal shutdown is a

non-latch protection.

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7.4 Device Functional Modes

7.4.1 Auto-Skip Eco-mode^™Light Load Operation

While the MODE pin is pulled to VCC directly or connected to AGND pin through a resistor larger than 121 kΩ,

the device automatically reduces the switching frequency at light-load conditions to maintain high efficiency. This

section describes the operation in detail.

As the output current decreases from heavy load condition, the inductor current also decreases until the rippled

valley of the inductor current touches zero level. Zero level is the boundary between the continuous-conduction

and discontinuous-conduction modes. The synchronous MOSFET turns off when this zero inductor current is

detected. As the load current decreases further, the converter runs into discontinuous-conduction mode (DCM).

The on-time is maintained to a level approximately the same as during continuous-conduction mode operation

so that discharging the output capacitor with a smaller load current to the level of the reference voltage requires

more time. The transition point to the light-load operation I_O(LL)(for example: the threshold between continuous-

and discontinuous-conduction mode) is calculated as shown in Equation 5.

V

- V

´ V

(

)

OUT OUT

V

IN

1

IN

I

=

´

OUT LL

( )

2´L ´ f

SW

(6)

where

• f_SWis the switching frequency

Using only ceramic capacitors is recommended for skip-mode.

7.4.2 Forced Continuous-Conduction Mode

When the MODE pin is tied to the AGND pin through a resistor less than 60.4 kΩ, the controller operates in

continuous conduction mode (CCM) during light-load conditions. During CCM, the switching frequency is

maintained to an almost constant level over the entire load range which is suitable for applications requiring tight

control of the switching frequency at the cost of lower efficiency.

7.4.3 Powering the Device From a 12-V Bus

The device works well when powering from a 12-V bus with single VIN configuration. As a single VIN

configuration, the internal LDO is powered by a 12-V bus and generates a 3.0-V output to bias the internal

analog circuitry and also powers up the gate drives. The VIN input range under this configuration is 4 V to 16 V

for up to 20-A load current. 图7-5 shows an example for this single VIN configuration.

VIN and EN are the two signals to enable the part. For start-up sequence, any sequence between the VIN and

EN signals can power the device up correctly.

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V_IN: 4V œ 16V

C_BOOT

10

21

1

VIN

BOOT

SW

C_IN

L_OUT

V_OUT

20

EN

8

9

EN

C_FF, Optional

PGOOD

Vosns+

C_OUT

R_{PG_pullup}

7

FB

19

4

VCC

R_{FB_HS}

R_{FB_LS}

C_VCC

R_MODE

MODE

TRIP

Vosns-

R_TRIP

6

5

VSNS-

3

C_SS

SS/

REFIN

2

AGND

PGND

图7-5. Single VIN Configuration For 12-V Bus

7.4.4 Powering the Device From a 3.3-V Bus

The device can also work for up to a 20-A load current when powering from a 3.3-V bus with a single VIN

configuration. To ensure the internal analog circuitry and the gate drives are powered up properly, VCC pin must

be shorted to VIN pins with low impedance trace. A trace with at least 24-mil width is recommended. A 2.2-µF, at

least 6.3-V rating, VCC-to-PGND decoupling capacitor is still recommended to be placed as close as possible to

VCC pin. Due to the maximum rating limit on VCC pin, the VIN input range under this configuration is 3 V to 3.6

V. The input voltage must stay higher than both VIN UVLO and VCC UVLO, otherwise the device will shut down

immediately. 图7-6 shows an example for this single VIN configuration.

VIN and EN are the two signals to enable the part. For start-up sequence, any sequence between the VIN and

EN signals can power the device up correctly.

V_IN: 3.3V bus

C_BOOT

10

21

1

VIN

BOOT

SW

C_IN

L_OUT

V_OUT

20

EN

8

9

EN

C_FF, Optional

PGOOD

Vosns+

C_OUT

R_{PG_pullup}

7

FB

19

4

VCC

R_{FB_HS}

R_{FB_LS}

C_VCC

R_MODE

MODE

TRIP

Vosns-

R_TRIP

6

5

VSNS-

3

C_SS

SS/

REFIN

2

AGND

PGND

图7-6. Single VIN Configuration For 3.3-V Bus

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7.4.5 Powering the Device From a Split-rail Configuration

When an external bias, which is at a different level from main VIN bus, is applied onto the VCC pin, the device

can be configured to split-rail by utilizing both the main VIN bus and VCC bias. Connecting a valid VCC bias to

VCC pin overrides the internal LDO, thus saves power loss on that linear regulator. This configuration helps to

improve overall system level efficiency but requires a valid VCC bias. A 3.3-V rail is the common choice as VCC

bias. With a stable VCC bias, the VIN input range under this configuration can be as low as 2.7 V and up to 16 V.

The noise of the external bias affects the internal analog circuitry. To ensure a proper operation, a clean, low-

noise external bias and good local decoupling capacitor from VCC pin to PGND pin are required. 图 7-7 shows

an example for this split rail configuration.

The VCC external bias current during nominal operation varies with the bias voltage level and also the operating

frequency. For example, by setting the device to skip-mode, the VCC pins draw less and less current from the

external bias when the frequency decreases under light load condition. The typical VCC external bias current

under FCCM operation is listed in 节6.5 to help you prepare the capacity of the external bias.

Under split rail configuration, VIN, VCC bias, and EN are the signals to enable the part. For start-up sequence,

TI recommends that at least one of VIN UVLO rising threshold and EN rising threshold is satisfied later than

VCC UVLO rising threshold. A practical start-up sequence example is: VIN applied first, the external bias

applied, and then EN signal goes high.

V_IN: 2.7V œ 16V

C_BOOT

10

21

1

VIN

BOOT

SW

C_IN

L_OUT

V_OUT

20

EN

8

9

EN

C_FF, Optional

PGOOD

Vosns+

C_OUT

R_{PG_pullup}

VCC bias

7

FB

19

4

VCC

R_{FB_HS}

R_{FB_LS}

R_MODE

C_VCC

MODE

TRIP

Vosns-

R_TRIP

6

5

VSNS-

3

C_SS

SS/

REFIN

2

AGND

PGND

图7-7. Split Rail Configuration With External VCC Bias

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The TPS548B28 device is a high-efficiency, single-channel, small-sized, synchronous-buck converter. The

device suits low output voltage point-of-load applications with 20-A or lower output current in server, storage, and

similar computing applications. The TPS548B28 features proprietary D-CAP3 control mode combined with

adaptive on-time architecture. This combination builds modern low-duty-ratio and ultra-fast load-step-response

DC/DC converters in an ideal fashion. The output voltage ranges from 0.6 V to 5.5 V. The conversion input

voltage ranges from 2.7 V to 16 V, and the VCC input voltage ranges from 3.13 V to 3.6 V. The D-CAP3 control

mode uses emulated current information to control the modulation. An advantage of this control scheme is that it

does not require an external phase-compensation network, which makes the device easy-to-use and also allows

for a low external component count. Another advantage of this control scheme is that it supports stable operation

with all low-ESR output capacitors (such as ceramic capacitor and low-ESR polymer capacitor). Adaptive on-

time control tracks the preset switching frequency over a wide range of input and output voltages while

increasing switching frequency as needed during a load-step transient.

8.2 Typical Application

The schematic shows a typical application for TPS548B28. This example describes the design procedure of

converting an input voltage range of 8 V to 14 V down to 1 V with a maximum output current of 20 A.

图8-1. TPS548B28 Application Circuit Diagram

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8.2.1 Design Requirements

This design uses the parameters listed in 表8-1.

表8-1. Design Example Specifications

DESIGN PARAMETER

Voltage range

CONDITION

MIN

TYP

12

MAX

UNIT

V

V_IN

8

14

V_OUT

I_LOAD

V_RIPPLE

Output voltage

1.0

V

Output load current

Output voltage ripple

20

A

V_IN= 12 V, I_OUT= 20 A

I_OUT= 25% to 75% step, 2 A/µs slew rate

10

mV_PP

Output voltage undershoot

and overshoot after load

step

V _TRANS

+/- 50

mV

I_OVER

t_SS

f_SW

Output overcurrent

Soft-start time

24

A

3.7

ms

Switching frequency

800

kHz

Operating mode

FCCM

25

T_A

Operating temperature

°C

8.2.2 Detailed Design Procedure

The external component selection is a simple process using D-CAP3 control mode. Select the external

components using the following steps.

8.2.2.1 Output Voltage Setting Point

The output voltage is programmed by the voltage-divider resistors, R1 and R2, shown in 方程式 7. Connect R1

between the FB pin and the output, and connect R2 between the FB pin and VSNS–. The recommended R2

value is 10 kΩ, but it can also be set to another value between the range of 1 kΩ to 20 kΩ. Determine R1 for

TPS548B28 by using 方程式7.

≈

∆

«

’

÷

◊

V_OUT- V_REF

V_REF

1.0 V - 0.6 V

0.6 V

≈

’

R = R ì

= 10 kWì

= 6.67 kW

1

2

∆

«

÷

◊

(7)

8.2.2.2 Choose the Switching Frequency and the Operation Mode

The switching frequency and operation mode are configured by the resistor on the MODE pin. Select one of

three switching frequencies: 600 kHz, 800 kHz, or 1 MHz. Refer to 表 7-1 for the relationship between the

switching frequency, operation mode, and R_MODE

.

Switching frequency selection is a tradeoff between higher efficiency and smaller system solution size. Lower

switching frequency yields higher overall efficiency but relatively larger external components. Higher switching

frequencies cause additional switching losses which impact efficiency and thermal performance. For this design,

connect the MODE pin to AGND through a 30.1-kΩ resistor to set the switching frequency to 800 kHz and set

operation mode as FCCM.

When selecting the switching frequency of a buck converter, the minimum on-time and minimum off-time must

be considered. 方程式 8 calculates the maximum f_SWbefore being limited by the minimum on-time. When hitting

the minimum on-time limits of a converter with D-CAP3 control mode, the effective switching frequency will

change to keep the output voltage regulated. This calculation ignores resistive drops in the converter to give a

worst case estimation.

V_OUT

max t_{ON_MIN}max

1

1.0 V

1

f_SWmax =

ì

=

ì

= 840 kHz

(

)

V

14 V 85 ns

(

)

(

)

IN

(8)

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方程式 8 calculates the maximum f_SWbefore being limited by the minimum off-time. When hitting the minimum

off-time limits of a converter with D-CAP3 control mode, the operating duty cycle will max out and the output

voltage will begin to drop with the input voltage. This equation requires the DC resistance of the inductor, R_DCR

,

selected in the following step so this preliminary calculation assumes a resistance of 2.2 mΩ. If operating near

the maximum f_SWlimited by the minimum off-time, the variation in resistance across temperature must be

considered when using 方程式9. The selected f_SWof 800 kHz is below the two calculated maximum values.

V

min - V

-I_OUTmax ì R

+ R

DCR

DS ON _HS

(

)

(

)

(

)

(

IN

OUT

(

)

f_SWmax =

(

)

t_{OFF_MIN}max ì V min -I

max ì R

-R_{DS ON _LS}

(

)

(

)

(

)

(

)

IN

OUT

)

(

DS ON _HS

(

)

8 V -1.0 V - 20 A ì 2.2 mW + 7.2 mW

(

)

f_SWmax =

= 3918 kHz

(

)

220 nsì 8 V - 20 A ì 7.2 mW - 2.3 mW

)

(

(9)

8.2.2.3 Choose the Inductor

To calculate the value of the output inductor (L_OUT), use 方程式10. The output capacitor filters the inductor-ripple

current (I_IND(ripple)). Therefore, selecting a high inductor-ripple current impacts the selection of the output

capacitor because the output capacitor must have a ripple-current rating equal to or greater than the inductor-

ripple current. On the other hand, larger ripple current increases output ripple voltage, but improves signal-to-

noise ratio and helps to stabilize operation. Generally speaking, the inductance value must set the ripple current

at approximately 15% to 40% of the maximum output current for a balanced performance.

For this design, the inductor-ripple current is set to 30% of 20-A output current. With a 800-kHz switching

frequency, 14 V as maximum V_IN, and 1.0 V as the output voltage, the calculated inductance is 0.290 µH.

V

max - V

ì V

(

)

14 V -1.0 V ì1.0 V

(

)

(

)

IN

OUT

L =

=

= 0.290 ꢀH

I_RIPPLEì V max ì f

0.2ì 20A ì14 V ì800 kHz

(

)

IN

SW

(10)

The inductor requires a low DCR to achieve good efficiency. The inductor also requires enough room above

peak inductor current before saturation. The peak inductor current is estimated using 方程式 11. For this design,

by selecting 6.04 kΩ as the R_TRIP, I_OC(valley)is set to 20 A, thus peak inductor current under maximum V_INis

calculated as 3.869 A.

V

max - V

ì V

(

)

14 V -1.0 V ì1.0 V

(

)

(

)

IN

OUT

I_RIPPLE

=

= 3.869 A

Lì V max ì f

0.3ꢀHì14 V ì800 kHz

(

)

IN

SW

(11)

(12)

I_RIPPLE

3.869 A

2

I_{L PEAK}= I_OUT

+

= 20 A +

= 21.93 A

(

)

2

3.869 A²

I_RIPPLE

2

I_{L RMS}= I_OUT

+

=

20 A²+

= 20.03 A

(

)

12

(13)

The selected inductance is a Coilcraft XAL7070-301MEB. This has a saturation current rating of 55.6 A, RMS

current rating of 26.1 A, and a DCR of 1.17-mΩmax. This inductor was selected for its low DCR to get high

efficiency.

8.2.2.4 Set the Current Limit (TRIP)

The R_TRIPresistor sets the valley current limit. 方程式 14 calculates the recommended current limit target as

18.18 A. The value was rounded up to 20 A. Use 方程式 15 to calculate the R_TRIPresistor to set the current limit.

The typical valley current limit target is 20 A and the closest standard value for R_TRIPis 6.04 kΩ.

28

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≈

’

V

min - V

ì V

(

)

(

)

OUT OUT

1

2

IN

∆

÷

◊

I_{LIM_ VALLEY}= I_OUT

-

ì

∆

Lì V min ì f

(

)

IN

SW

«

≈

’

8 V -1.0 V ì1.0 V

(

)

1

2

I_{LIM_ VALLEY}= 20A -

= 18.18 A

∆

÷

∆

«

0.3 µHì8 V ì800 kHz

◊

(14)

(15)

120000

20 A

R_TRIP

=

= 6.0 kW

I_{LIM_ VALLEY}

With the current limit set, 方程式 16 calculates the typical maximum output current at current limit. 方程式 17

calculates the typical peak current at current limit. As mentioned in 节 8.2.2.3, the saturation behavior of the

inductor at the peak current during current limit must be considered. For worst case calculations, the tolerance of

the inductance and the current limit must be included.

V

min - V

ì V

(

)

8 V -1.0 V ì1.0 V

(

)

OUT OUT

(

)

1

2

1

IN

I_{OUT_LIM}min = I

+

ì

= 20 A +

ì

= 21.82 A

(

)

LIM_ VALLEY

Lì V min ìf

2 0.3 µHì8 Vì800 kHz

(

)

IN

SW

(16)

V

(

max - V

ì V

OUT

(

)

14 V -1.0 V ì1.0 V

)

(

)

IN

OUT

I_{L PEAK}= I_{LIM_ VALLEY}

+

= 20 A +

= 21.935 A

(

)

Lì V max ì f

0.3 µHì14 V ì800 kHz

(

)

IN

SW

(17)

8.2.2.5 Choose the Output Capacitor

There are three considerations for selecting the value of the output capacitor:

1. Stability

2. Steady state output voltage ripple

3. Regulator transient response to a change load current

First, the minimum output capacitance must be calculated based on these three requirements. 方程式 18

calculates the minimum capacitance to keep the LC double pole below 1/30th the f_SWto meet stability

requirements. This requirement helps keep the LC double pole close to the internal zero. 方程式 19 calculates

the minimum capacitance to meet the steady state output voltage ripple requirement of 10 mV. This calculation is

for CCM operation and does not include the portion of the output voltage ripple caused by the ESR or ESL of the

output capacitors.

2

≈

∆

«

’

÷

30

1

L

30

1

≈

’

C_{OUT _STABILITY}

>

ì

=

ì

= 118.7 µF

∆

«

÷

◊

2pì f_{SW ◊}

2pì800 kHz

0.3 µH

(18)

(19)

I_RIPPLE

3.869 A

C_{OUT _RIPPLE}

>

=

= 60.5 µF

8ì V_RIPPLEì f_SW8ì10 mV ì800 kHz

方程式 20 and 方程式 21 calculate the minimum capacitance to meet the transient response requirement of 50

mV with a 10-A step. These equations calculate the necessary output capacitance to hold the output voltage

steady while the inductor current ramps up or ramps down after a load step.

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≈

’

V_OUT

LìI_STEP²ì

+ t_{OFF_MIN}max

(

)

∆

÷

∆

V

min ì f

(

)

IN

SW

«

◊

C_{OUT _UNDERSHOOT}

>

≈

’

V

min - V

(

IN

)

IN

OUT

2ì V_TRANSì V_OUT

0.3 µHì10 A²ì

ì

- t_{OFF_MIN}max

(

)

∆

÷

V

min ì f

(

1.0 V

)

SW

«

◊

≈

’

◊

+ 220 ns

∆

÷

8 V ì800 kHz

8 V -1.0 V

8 V ì800 kHz

«

C_{OUT _UNDERSHOOT}

= 129.2 µF

≈

’

2ì50 mV ì1.0 V ì

- 220 ns

∆

«

÷

◊

(20)

(21)

2

0.3 µHì10A²

LìI_STEP

C_{OUT _OVERSHOOT}

>

=

= 300 µF

2ì V_TRANSì V_OUT2ì50 mV ì1.0 V

The output capacitance needed to meet the overshoot requirement is the highest value so this sets the required

minimum output capacitance for this example. Stability requirements can also limit the maximum output

capacitance and 方程式 22 calculates the recommended maximum output capacitance. This calculation keeps

the LC double pole above 1/100th the f_SW. It can be possible to use more output capacitance but the stability

must be checked through a bode plot or transient response measurement. The selected output capacitance is 8

x 47-µF 6.3-V ceramic capacitors. When using ceramic capacitors, the capacitance must be derated due to DC

and AC bias effects. The selected capacitors derate to 85% their nominal value giving an effective total

capacitance of 320 μF. This effective capacitance meets the minimum and maximum requirements.

2

≈

∆

«

’

÷

50

1

L

50

1

≈

’

C_{OUT _STABILITY}

<

ì

=

ì

= 1319.3 µF

∆

«

÷

◊

pì f_{SW ◊}

pì800 kHz

0.3 µH

(22)

This application uses all ceramic capacitors so the effects of ESR on the ripple and transient were ignored. If

using non-ceramic capacitors, as a starting point, the ESR must be below the values calculated in 方程式 23 to

meet the ripple requirement and 方程式 24 to meet the transient requirement. For more accurate calculations or

if using mixed output capacitors, the impedance of the output capacitors must be used to determine if the ripple

and transient requirements can be met.

V_RIPPLE

10 mV

R_{ESR_RIPPLE}

<

=

= 2.58 mW

I_RIPPLE

3.869 A

(23)

(24)

V_TRANS

50 mV

R_{ESR _ TRANS}

<

=

= 5 mW

I_STEP

10 A

8.2.2.6 Choose the Input Capacitors (C_IN)

The device requires input bypass capacitors between the VIN and PGND pins to bypass the power-stage. The

bypass capacitors must be placed as close as possible to the pins of the IC as the layout will allow. At least 10

µF of ceramic capacitance and 1-µF high frequency ceramic bypass capacitors are required. A 1-μF, 16-V X6S

size 0402 ceramic capacitor on VIN pin 10 and pin 21 is required. A 1-μF 16-V X6S ceramic capacitor on the

bottom layer is recommended for high current applications. The high frequency bypass capacitor minimizes high

frequency voltage overshoot across the power-stage. The ceramic capacitors must be a high-quality dielectric of

X6S or better for their high capacitance-to-volume ratio and stable characteristics across temperature. In

addition to this, more bulk capacitance can be needed on the input depending on the application to minimize

variations on the input voltage during transient conditions.

The input capacitance required to meet a specific input ripple target can be calculated with 方程式 25. A

recommended target input voltage ripple is 5% the minimum input voltage, which is 400 mV in this example. The

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calculated input capacitance needed is 6.84 μF and four 22-µF ceramic capacitors are recommended for this

example.

≈

’

V_OUT

min

1.0V

8

≈

«

’

◊

V_OUTìI_OUTì 1-

∆

÷

1.0 V ì 20 A ì 1-

∆

÷

V

(

)

IN

«

◊

C_IN

>

=

= 6.84 ꢀF

f_SWì V min ì V

800 kHzì8 V ì 400 mV

(

)

IN

IN_RIPPLE

(25)

The capacitor must also have an RMS current rating greater than the maximum input RMS current in the

application. The input RMS current the input capacitors must support is calculated by 方程式 26 and is 6.625 A

in this example. The ceramic input capacitors have a current rating greater than this.

Iripple²

12

≈

’

V

min - V

OUT

(

)

min

(

)

ìI_OUT

V_OUT

min

IN

2

∆

«

÷

◊

I_{CIN RMS}

=

ì

+

=

(

)

V

(

)

(

)

IN

3.646²

12

≈

’

8 V -1.0 V

(

)

ì 20²+

1.0 V

8 V

I_{CIN RMS}

ì

= 6.625 A

∆

÷

(

8 V

«

◊

(26)

For applications requiring bulk capacitance on the input, such as ones with low input voltage and high current,

the selection process in this article is recommended.

8.2.2.7 Soft Start Capacitor (SS/REFIN Pin)

The capacitor placed on the SS/REFIN pin can be used to extend the soft-start time past the internal 1.5-ms soft

start. This example uses a 3.7-ms soft-start time and the required external capacitance can be calculated with 方

程式27. In this example, a 220-nF capacitor is used.

I_SSì t_SS

V_REF

36 µA ì3.7 ms

0.6 V

C_SS

=

= 200 nF

(27)

A minimum capacitor value of 1 nF is required at the SS/REFIN pin. The SS/REFIN capacitor must use the

VSNS–pin for its ground.

8.2.2.8 EN Pin Resistor Divider

A resistor divider on the EN pin can be used to increase the input voltage the converter begins its start-up

sequence. To set the start voltage, first select the bottom resistor (R_{EN_B}). The recommended value is between 1

kΩand 100 kΩ. There is an internal pulldown resistance with a nominal value of 6 MΩ, which must be included

for the most accurate calculations. This is especially important when the bottom resistor is a higher value, near

100 kΩ. This example uses a 10-kΩ resistor and combined with the internal resistance in parallel results in an

equivalent bottom resistance of 9.98 kΩ. The top resistor value for the target start voltage is calculated with 方程

式28. In this example, the nearest standard value of 20 kΩis selected for R_{EN_T}. When selecting a start voltage

in a wide input range application, be cautious that the EN pin absolute maximum voltage of 6 V is not exceeded.

R_{EN_B}ì V_START

10 kWì3.7 V

1.22 V

R_{EN_ T}

=

-R_{EN_B}

=

-10 kW = 20 kW

V_ENH

(28)

The start and stop voltages with the selected EN resistor divider can be calculated with 方程式 29 and 方程式

30.

R_{EN_B}+ R_{EN_ T}

10 kW + 20 kW

10 kW

V_START= V_ENH

ì

= 1.22 V ì

= 3.66V

R_{EN_B}

(29)

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R_{EN_B}+ R_{EN_ T}

10 kW + 20 kW

10 kW

V_STOP= V_ENL

ì

= 1.02 V ì

= 3.06 V

R_{EN_B}

(30)

8.2.2.9 VCC Bypass Capacitor

At a minimum, a 2.2-µF, at least 6.3-V rating, X5R ceramic bypass capacitor is needed on VCC pin located as

close to the pin as the layout will allow.

8.2.2.10 BOOT Capacitor

At a minimum, a 0.1-µF 10-V X5R ceramic bypass capacitor is needed between the BOOT and SW pins located

as close to the pin as the layout will allow. It is good practice to use a 0-Ω resistor in series with the BOOT

capacitor.

8.2.2.11 PGOOD Pullup Resistor

The PGOOD pin is open-drain so a pullup resistor is required when using this pin. The recommended value is

between 1 kΩand 100 kΩ.

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8.2.3 Application Curves

90

88

86

84

82

80

100

96

92

88

84

80

76

72

68

64

60

78

Vin = 12 V

800 kHz

300 nH

VCC = INT

Skip

Vin = 12 V

800 kHz

300 nH

VCC = INT

FCCM

76

74

72

70

Vout = 1.0V

Vout = 1.0 V

16 18 20

0

2

4

6

8

10

12

Output Current (A)

14

16

18

20

0

2

4

6

8

10

Output Current (A)

12

14

D002

D001

图8-3. Efficiency vs Output Current, Internal VCC

图8-2. Efficiency vs Output Current, Internal VCC

Bias

100

96

92

88

84

80

1000

920

840

760

680

600

520

76

VIN = 12 V

Vout = 1.0 V

800 nH

VCC = Int

CCM

Vin = 12 V

800 kHz

300 nH

VCC = 3.3 V

FCCM

440

360

280

200

72

68

64

60

600 kHz

800 kHz

1000 kHz

Vout = 1.0 V

16 18 20

0

2

4

6

8

10

12

Output Current (A)

14

16

18

20

0

2

4

6

8

10

Output Current (A)

12

14

D005

D003

图8-5. Switching Frequency vs Output Current

图8-4. Efficiency vs Output Current, VCC = 3.3V

External VCC Bias

1.005

1100

1000

900

Vin = 8V

Vin = 12V

Vin = 16V

300 nH

1.00375

1.0025

1.00125

1

800 kHz

VCC = Int

Skip

800

700

600

0.99875

0.9975

0.99625

0.995

500

VIN = 12 V

Vout = 1.0 V

800 nH

VCC = Int

CCM

400

300

200

100

600 kHz

800 kHz

1000 kHz

0

2

4

6

8

10

12

Output Current (A)

14

16

18

20

5

6

7

8

9

10 11 12 13 14 15 16

D008

Input Voltage (V)

D006

图8-7. Output Voltage vs Output Current

图8-6. Switching Frequency vs Input Voltage

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1.005

1.00375

1.0025

1.00125

1

Vin = 8V

Vin = 12V

Vin = 16V

Vin = 8V

Vin = 12V

Vin = 16V

300 nH

800 kHz

VCC = Int

FCCM

800 kHz

VCC = 3.3 V

Skip

1.00375

1.0025

1.00125

1

0.99875

0.9975

0.99625

0.995

0.99875

0.9975

0.99625

0.995

0

2

4

6

8

10

12

Output Current (A)

14

16

18

20

0

2

4

6

8

10

12

Output Current (A)

14

16

18

20

D010

D011

图8-8. Output Voltage vs Output Current

图8-9. Output Voltage vs Output Current, VCC =

3.3-V External Bias

1.005

1.01

Vin = 8V

Vin = 12V

Vin = 16V

Skip 0 A

FCCM 0 A

FCCM 5 A

FCCM 10 A

FCCM 20A

300 nH

800 kHz

VCC = 3.3 V

FCCM

1.00375

1.0025

1.00125

1

1.006

1.002

0.998

0.994

0.99

0.99875

0.9975

0.99625

0.995

0

2

4

6

8

10

12

Output Current (A)

14

16

18

20

5

7

9 11

Input Voltage (V)

13

15 16

D012

D013

图8-10. Output Voltage vs Output Current, VCC =

图8-11. Output Voltage vs Input Voltage VCC = Int

3.3-V External Bias

1.01

0.018

0.016

0.014

0.012

0.01

Skip 0 A

FCCM 0 A

FCCM 5 A

FCCM 10 A

FCCM 20A

1.006

1.002

0.998

0.994

0.99

0.008

0.006

VIN = 12 V

Vout = 3.3 V

Iout = 5 A

800 nH

0.004

0.002

0

600 kHz

800 kHz

1000 kHz

5

7

9 11

Input Voltage (V)

13

15 16

3.2 3.24 3.28 3.32 3.36 3.4 3.44 3.48 3.52 3.56 3.6

VCC Voltage (V)

D014

D015

图8-12. Output Voltage vs Input Voltage VCC = 3.3-

图8-13. ICC Current vs External VCC Voltage

V External Bias

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图8-14. Enable Start-Up, Prebias

图8-15. Prebias Power-Down

图8-16. Enable Power Up, Skip

图8-17. Enable Power Down, Skip

图8-18. Enable Power Up into Pre-bias, Skip

图8-19. Enable Power Down with Pre-bias, Skip

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图8-20. Load Transient

图8-22. Output Voltage Ripple

图8-24. Output Voltage Ripple

图8-26. Output Voltage Ripple, Skip

图8-21. Unload Transient

图8-23. Output Voltage Ripple

图8-25. Output Voltage Ripple, Skip

图8-27. Over Temperature Protection in FCCM

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图8-29. Enabled into Overcurrent

图8-28. Exiting Overtemperature Protection in

FCCM

图8-30. Hiccup Overcurrent

8.3 Power Supply Recommendations

The device is designed to operate from a wide input voltage supply range between 2.7 V and 16 V when VCC

pin is powered by external bias ranging from 3.13 V to 3.6 V. Both input supplies (VIN and VCC bias) must be

well regulated. Proper bypassing of input supplies (VIN and VCC bias) is also critical for noise performance, as

are PCB layout and grounding scheme. See the recommendations in 节8.4.

8.4 Layout

8.4.1 Layout Guidelines

Before beginning a design using the device, consider the following:

• Place the power components (including input and output capacitors, the inductor, and the IC) on the top side

of the PCB. To shield and isolate the small signal traces from noisy power lines, insert at least one solid

ground inner plane.

• VIN decoupling capacitors are important for FET robustness. A 1-μF/25-V/X6S/0402 ceramic capacitor on

VIN pin 21 is required. The PGND vias for this decoupling capacitor must be placed so that the decoupling

capacitor is closer to IC than the PGND vias. To lower ESL from via connection, two 8-mil vias are

recommended for the PGND connection to inner PGND plane.

• A 1-μF/25-V/X6S/0402 ceramic capacitor on VIN pin 10 is highly recommended. If this 0402 size capacitor is

not used, the bigger size VIN decoupling capacitors (0603 or 0805 size) are required to be placed as close as

possible to IC pin 10 and pin 11.

• Two 1-μF/25-V/X6S/0402 ceramic capacitors on the bottom layer are recommended for high current

applications (Iout > 13 A). One of these two capacitors must be centered between VIN pin 10 and pin 21. To

have good connection for this capacitor, a VIN copper on bottom layer and two VIN vias are needed. The

other one can be placed close to IC package just like a mirrored copy to the 0402 capacitor on top layer.

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• At least six PGND vias are required to be placed as close as possible to the PGND pins (pin 11 to pin 15).

This minimizes parasitic impedance and also lowers thermal resistance.

• Place the VCC decoupling capacitor (2.2-μF/6.3-V/X6S/0402 or 2.2-μF/6.3-V/X7R/0603) as close as

possible to the device. Ensure the VCC decoupling loop is smallest.

• Place BOOT capacitor as close as possible to the BOOT and SW pins. Use traces with a width of 12 mil or

wider to route the connection. TI recommends using a 0.1-µF to 1-µF bootstrap capacitor with 10-V rating.

• The PCB trace, which connects the SW pin and high-voltage side of the inductor, is defined as switch node.

The switch node must be as short and wide as possible.

• Always place the feedback resistors near the device to minimize the FB trace distance, no matter single-end

sensing or remote sensing.

– For remote sensing, the connections from the FB voltage divider resistors to the remote location must be a

pair of PCB traces with at least 12-mil trace width, and must implement Kelvin sensing across a high

bypass capacitor of 0.1 μF or higher. The ground connection of the remote sensing signal must be

connected to VSNS–pin. The V_OUTconnection of the remote sensing signal must be connected to the

feedback resistor divider with the lower feedback resistor terminated at VSNS–pin. To maintain stable

output voltage and minimize the ripple, the pair of remote sensing lines must stay away from any noise

sources such as inductor and SW nodes, or high frequency clock lines. TI recommends to shield the pair

of remote sensing lines with ground planes above and below.

– For single-end sensing, connect the higher FB resistor to a high-frequency local bypass capacitor of 0.1

μF or higher, and short VSNS–to AGND with shortest trace.

• This device does not require a capacitor from SS/REFIN pin to AGND, thus TI does not recommend to place

a capacitor from SS/REFIN pin to AGND. If both C_SS/REFIN-to-VSNS–and C_SS/REFIN-to-AGND capacitors

exist, place C_SS/REFIN-to-VSNS–more closely with shortest trace to VSNS–pin.

• Pin 2 (AGND pin) must be connected to a solid PGND plane on inner layer. Use the common AGND via to

connect the resistors to the inner ground plane if applicable.

• See 节8.4.2 for the layout recommendation.

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8.4.2 Layout Example

Vosns+

Vosns-

Via down to connect to solid

PGND plane on inner layer

8/20

0402

8/20

2x VIN-to-PGND decoupling

capacitors on bottom layer

8/20

PGND

8/20

SW

VIN

SW

8/20

0603

L_OUT

8/20

0402

8/20

PGND

0805

VOUT

图8-31. Layout Recommendation

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8.4.2.1 Thermal Performance On TI EVM

Test conditions:

f_SW= 800-kHz, V_IN= 12-V, VCC = Int LDO, V_OUT= 1-V, I_OUT= 20-A, Inductor L_OUT= 0.3-µH (1.06-mΩ typ),

C_OUT= 8 × 47-µF (1206/6.3V/X6S), no R_BOOT, no RC Snubber

SP1 (IC): 88.0°C, SP2 (Inductor): 58.7°C

图8-32. Thermal Image At 25°C Ambient

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ZHCSMV4A –DECEMBER 2020 –REVISED DECEMBER 2022

9 Device and Documentation Support

9.1 Documentation Support

9.1.1 Related Documentation

• Texas Instruments, Optimizing Transient Response of Internally Compensated DC-DC Converters with

Feedforward Capacitor application note

• Texas Instruments, Non-isolated Point-of-load Solutions for VR13.HC in Rack Server and Datacenter

Applications application note

9.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

9.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

9.4 Trademarks

D-CAP3^™, Eco-mode^™, and TI E2E^™are trademarks of Texas Instruments.

所有商标均为其各自所有者的财产。

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

9.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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41

Product Folder Links: TPS548B28

TPS548B28

www.ti.com.cn

ZHCSMV4A –DECEMBER 2020 –REVISED DECEMBER 2022

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

42

Submit Document Feedback

Product Folder Links: TPS548B28

PACKAGE OUTLINE

VQFN-HR - 1 mm max height

PLASTIC QUAD FLAT-NO LEAD

RWW0021A

3.1

2.9

A

B

4.1

3.9

PIN 1

INDEX AREA

C0.15

PIN 1 IDENTIFICATION

(OPTIONAL)

1 MAX

C

SEATING PLANE

0.08 C

0.05

0.00

PKG

0.4

0.3

0.35

0.25

REF 0.15

3X

10

(0.2) TYP

9

8

11

12X 0.4

1.8

3X

1.6

3.25

3.05

2X

3.4

0.25

PKG

14X

2X

2.4

0.15

0.1

C A B

C

0.05

2

1

18

19

4X 0.5

21

0.35

0.25

20

4X

PIN 1 ID

(OPTIONAL)

3X 0.3

0.1

C A B

C

0.6

0.4

18X

0.05

4223950/C 04/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN-HR - 1 mm max height

PLASTIC QUAD FLAT-NO LEAD

RWW0021A

(2.7)

3X (0.3)

18X (0.7)

4X (0.3)

20

21

1

2

19

14X (0.2)

4X (0.5)

18

EXPOSED METAL

PKG

2X

(3.4) (2.4)

3X

(1.9)

12

8

9

12X (0.4)

11

(0.35)

(R0.05) TYP

10

3X (0.3)

PKG

LAND PATTERN EXAMPLE

SOLDER MASK DEFINED

SCALE: 20X

0.05 MAX

ALL AROUND

0.05 MAX

ALL AROUND

EXPOSED METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL EDGE

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4223950/C 04/2019

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN-HR - 1 mm max height

PLASTIC QUAD FLAT-NO LEAD

RWW0021A

(2.7)

PKG

18X (0.7)

4X (0.3)

20

21

1

2

19

4X (0.5)

18

14X (0.2)

PKG

2X

(3.4) (2.4)

3X

(0.73)

3X

(1.05)

12

11

8

9

12X (0.4)

(0.35)

(R0.05) TYP

6X

(0.85)

10

6X (0.3)

(0.3)

SOLDER PASTE EXAMPLE

BASED ON 0.1mm THICK STENCIL

EXPOSED PAD

89% PRINTED COVERAGE BY AREA

SCALE: 20X

4223950/C 04/2019

NOTES: (continued)

5.

Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS548B28
厂家：	TEXAS INSTRUMENTS
描述：	具有遥感功能和断续限流功能的 2.7V 至 16V 输入 20A 同步降压转换器转换器
文件：	总49页 (文件大小：2551K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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