TPS548C26RXXR_技术文档

TPS548C26

ZHCSPA4 –MARCH 2023

TPS548C26 具有差分遥感的4V 至16V 输入、35A 同步降压转换器

1 特性

2 应用

• 集成4.0mΩ 和1.0mΩ MOSFET，可实现35A 持续

电流运行

• 支持5V 外部偏置，可提高效率并实现2.7V 最小输

入电压

• 服务器和云计算POL

• 硬件加速器

• 数据中心交换机

3 说明

• 0.8V 至5.5V 输出电压范围

TPS548C26 器件是一款高度集成的降压转换器，采用

D-CAP+ 控制拓扑，可实现快速瞬态响应。该器件不需

要外部补偿，因此易于使用并且仅需要很少的外部元

件。该器件非常适合空间受限的数据中心应用。

• 提供精密电压基准和差分遥感，可实现高输出精度

– 0°C 至85°C T_J时V_OUT容差为±0.5%

– -40°C 至125°C T_J时V_OUT容差为±1%

• D-CAP+^™具有快速瞬态响应的控制拓扑，支持所

有陶瓷输出电容器

• 可通过SS 引脚选择内部环路补偿

• 提供可选逐周期谷值电流限制

• 在DCM 或FCCM 运行模式下，可选工作频率为

0.6MHz 至1.2MHz

• 提供安全启动至预偏置输出

• 可编程软启动时间为1ms 至8ms

• 开漏电源正常输出(PG)

TPS548C26 器件具有真差分遥感功能和高性能集成

MOSFET，在整个工作结温范围具有高精度 (±1%)

0.8V 电压基准。该器件具有快速负载瞬态响应、精确

负载调节和线路调节、跳跃模式或 FCCM 运行模式以

及可编程软启动时间。提供具有可选断续或闭锁响应的

过流、过压、欠压、过热保护。

TPS548C26 是一款无铅器件，符合RoHS 标准，无需

豁免。

• 具有可选断续或闭锁响应的过流、过压、欠压、过

热保护

• 5mm × 6mm、37 引脚WQFN-FCRLF 封装

• TPS544C26 采用相同封装的SVID/I²C 转换器

封装信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

RXX（WQFN-FCRLF，

37）

TPS548C26

5.00mm × 6.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

95

90

85

80

75

70

65

60

V_IN

PVIN

AVIN

BOOT

PHASE

SW

V_OUT

VCC

Load

VDRV

PGND

6

DNC

NC

37

VOSNS

EN

FB

MODE

ILIM

SS

GOSNS

Power Good

PG

55

PVIN=12V

V_OUT=1.1V

f_SW=800kHz

33

34

35

NC

Use the internal LDO

Use an external 5V bias

50

45

AGND

0

5

10

15

Iout (A)

20

25

30

简化版原理图

典型效率

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSGM2

TPS548C26

ZHCSPA4 –MARCH 2023

www.ti.com.cn

Table of Contents

7.3 Feature Description...................................................11

7.4 Device Functional Modes..........................................19

8 Application and Implementation..................................22

8.1 Application Information............................................. 22

8.2 Typical Application.................................................... 22

8.3 Power Supply Recommendations.............................26

8.4 Layout....................................................................... 26

9 Device and Documentation Support............................30

9.1 接收文档更新通知..................................................... 30

9.2 支持资源....................................................................30

9.3 Trademarks...............................................................30

9.4 静电放电警告............................................................ 30

9.5 术语表....................................................................... 30

10 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions ..................................3

6 Specifications.................................................................. 5

6.1 绝对最大额定值...........................................................5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................6

6.5 Electrical Characteristics.............................................6

6.6 Typical Characteristics..............................................10

7 Detailed Description......................................................11

7.1 Overview .................................................................. 11

7.2 Functional Block Diagram......................................... 11

Information.................................................................... 31

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

DATE

REVISION

NOTES

March 2023

*

Initial release

2

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Product Folder Links: TPS548C26

English Data Sheet: SLVSGM2

TPS548C26

ZHCSPA4 –MARCH 2023

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5 Pin Configuration and Functions

36

35

34

33

32

31

30

29

30

31

32

33

34

35

36

ILIM

PG

1

2

3

4

5

6

7

8

9

28 VOSNS

27 EN

VOSNS 28

EN 27

1

2

3

4

5

6

7

8

9

ILIM

PG

AVIN

VCC

26 BOOT

25 PHASE

24 PVIN

23 PVIN

22 PVIN

21 PVIN

20 PVIN

19 PGND

BOOT 26

PHASE 25

PVIN 24

PVIN 23

PVIN 22

PVIN 21

PVIN 20

PGND 19

AVIN

VCC

VDRV

DNC

VDRV

DNC

PGND

NC

37

NC

37

PGND

10 PGND

PGND 10

18

17

16

15

14

13

12

11

12

13

14

15

16

17

18

图5-1. RXX 37-pin WQFN-FCRLF Package (Top

图5-2. RXX 37-pin WQFN-FCRLF Package (Bottom

View)

表5-1. Pin Functions

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

AGND

AVIN

32

G

P

Ground pin, reference point for internal control circuitry.

Supply rail for the internal VCC LDO. Connect a 1 μF, 25V ceramic capacitor to AGND to

bypass this pin.

3

Supply rail for the high-side gate driver (boost terminal). Connect the bootstrap capacitor

from this pin to PHASE pin. A high temperature (X7R) 0.1 μF or greater value ceramic

capacitor is recommended.

BOOT

DNC

26

P

Do Not Connect (DNC) pin. This pin is the output of internal circuitry and must be floating.

Pin 6 and pin 37 can be shorted together but NO any other PCB connection is allowed on

pin 6.

6

—

Enable pin, an active-high input pin that, when asserted high, causes the converter to

begin the soft-start sequence for the output voltage rail. When de-asserted low, the

converter de-asserts PG pin and begins the shutdown sequence of the output voltage rail

and continue to completion.

EN

FB

27

30

I

Positive input of the differential remote sense amplifier, connect to the center point of an

external voltage divider. The voltage divider must be connected to output remote sense

point.

Negative input of the differential remote sense circuit, connect to the ground sense point

on the load side.

GOSNS

ILIM

31

I

Overcurrent limit selection pin. Connect a resistor to AGND to select the overcurrent limit

threshold.

1

36

The MODE pin selects the switching frequency and sets the operation mode to FCCM or

DCM, by connecting a resistor to AGND.

MODE

SS

I

The SS pin selects the soft-start time, internal compensation and the fault response, by

connecting a resistor to AGND.

29

I

No connection (NC) pin. There is no active circuit connected inside the IC. These pins can

be connected to ground plane or left open.

NC

33, 34, 35

—

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Product Folder Links: TPS548C26

English Data Sheet: SLVSGM2

TPS548C26

ZHCSPA4 –MARCH 2023

www.ti.com.cn

表5-1. Pin Functions (continued)

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

No connection (NC) pin. This pin is floating internally. Pin 37 and pin 6 can be shorted

together.

NC

PG

37

—

Power-good output signal. The PG indicator is asserted when the output voltage reaches

the regulation. The PG indicator de-asserts low when the EN pin is pulled low or a

shutdown fault occurs. This open-drain output requires an external pullup resistor.

2

O

G

PGND

PHASE

PVIN

SW

Power ground for the internal power stage.

7–10, 19

25

Return for high-side MOSFET driver. Shorted to SW internally. Connect the bootstrap

capacitor from BOOT pin to this pin.

—

P

Power input for both the power stage. PVIN is the input of the internal VCC LDO as well.

20–24

11–18

Output switching terminal of the power converter. Connect these pins to the output

inductor.

O

Internal VCC LDO output and also the input for the internal control circuitry. A 2.2 μF (or 1

μF), at least 6.3 V rating ceramic capacitor is required to be placed from VCC pin to

AGND for decoupling.

VCC

4

5

P

Power supply input for gate driver circuit. A 2.2 μF (or 4.7 μF), at least 6.3 V rating

ceramic capacitor is required to be placed from VDRV pin to PGND pins to decouple the

noise generated by driver circuitry. An external 5 V bias can be connected to this pin to

save the power losses on the internal LDO.

VDRV

Output voltage sense point for internal on-time generation circuitry. Shorting this pin

directly to VOUT sense point is recommended. Adding any resistance higher than 51 Ω

between VOUT sense point and the VOSNS pin shifts switching frequency higher than the

desired setting. Contact Texas Instruments if a resistor has to be placed between VOUT

sense point and the VOSNS pin.

VOSNS

28

I

4

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Product Folder Links: TPS548C26

English Data Sheet: SLVSGM2

TPS548C26

ZHCSPA4 –MARCH 2023

www.ti.com.cn

6 Specifications

6.1 绝对最大额定值

在工作结温范围内测得（除非另有说明）⁽¹⁾

最小值

–0.3

–1.5

–0.3

–3.0

-0.3

最大值

单位

PVIN

18

V

引脚电压

AVIN

18

V

引脚电压

PVIN –SW，直流

引脚电压

26

V

PVIN - SW，瞬态值< 10ns

引脚电压

18

V

SW –PGND，直流

引脚电压

21.5

23.5

5.5

18

V

SW –PGND，瞬态值< 10ns

引脚电压

V

BOOT –PGND

BOOT –SW

VCC、VDRV

引脚电压

V

–0.3

0

V

阶段

5.5

0.3

1.9

10

V

EN、VOSNS、ILIM、MODE、SS、FB、PG

V

GOSNS –AGND

DNC、NC

PG

V

mA

°C

灌电流

T_J

-40

150

工作结温

T_stg

-55

存储温度

(1) 超出绝对最大额定值运行可能会对器件造成永久损坏。绝对最大额定值并不表示器件在这些条件下或在建议运行条件以外的任何其他条

件下能够正常运行。如果超出建议运行条件但在绝对最大额定值范围内使用，器件可能不会完全正常运行，这可能影响器件的可靠性、

功能和性能并缩短器件寿命。

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC

JS-001 ⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per ANSI/ESDA/JEDEC

JS-002 ⁽⁽²⁾⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating junction temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V_OUT

Output voltage range

Input voltage

0.8

5.5

V

PVIN when VCC and VDRV are powered

by the internal LDO

4.0

2.7

16

V

V_IN

PVIN when VCC and VDRV are powered

by an external 5 V bias

V_IN

Input voltage

AVIN

4.0

16

5.3

35

V

V_BIAS

I_OUT

Input voltage

VCC and VDRV external bias

4.75

Output current range

Pin voltage

A

EN, PG

5.3

10

V

–0.1

–40

I_PG

T_J

Power good input current capability

Operating junction temperature

mA

°C

125

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Product Folder Links: TPS548C26

English Data Sheet: SLVSGM2

TPS548C26

ZHCSPA4 –MARCH 2023

www.ti.com.cn

6.4 Thermal Information

DEVICE

THERMAL METRIC⁽¹⁾

RXX (QFN, JEDEC)

RXX (QFN, TI EVM)

37 PINS

UNIT

37 PINS

25.4

3.6

R_θJA

Junction-to-ambient thermal resistance

Junction-to-board thermal resistance

15.7

°C/W

R_θJB

Not applicable⁽²⁾

2.0⁽⁴⁾

R_θJC(top)

R_θJC(bot)

ψ_JT

Junction-to-case (top) thermal resistance

Junction-to-case (bottom) thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

6.6

3.1

0.1⁽³⁾

3.6

5.7

ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) The thermal test or simulation setup is not applicable to a TI EVM layout.

(3) The power dissipation is evenly distributed across all the silicon areas inside the package on the thermal simulation based on the

JEDEC standard, resulting in the hot spot being centered in the package.

(4) The power dissipation is concentrated on the power FET area on the thermal simulation based on the TI EVM layout, resulting in the

hot spot being offset inside the package.

6.5 Electrical Characteristics

T_J= –40°C to +125°C. PVIN = 4 V to 16 V, V_VCC= 4.5 V to 5.0 V (unless otherwise noted). Typical values are at T_J= 25°C,

PVIN = 12 V and V_VCC= 4.5 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY

PVIN operating input range

AVIN operating input range

4

16

V

Non-switching, PVIN = 12 V, AVIN = 12 V,

V_EN= 2 V, V_FB= V_REF+ 50 mV, no bias on

VCC and VDRV pin

I_Q(AVIN)

I_SD(PVIN)

I_VCC

AVIN quiescent current

5

6.3

20

7.5

mA

µA

PVIN = 12 V, AVIN = 12 V, V_EN= 0 V, no

bias on VCC and VDRV pin

PVIN shutdown supply current

VCC and VDRV external bias current

External 5 V bias on VCC and VDRV pin,

regular switching. T_J= 25°C, PVIN = 12 V,

I_OUT= 35 A, V_EN= 2 V, f_SW= 0.6 MHz

32.7

mA

External 5 V bias on VCC and VDRV pin,

regular switching. T_J= 25°C, PVIN = 12 V,

I_OUT= 35 A, V_EN= 2 V, f_SW= 0.8 MHz

I_VCC

VCC and VDRV external bias current

39.7

48.7

mA

External 5 V bias on VCC and VDRV pin,

regular switching. T_J= 25°C, PVIN = 12 V,

I_OUT= 35 A, V_EN= 2 V, f_SW= 1.0 MHz

I_VCC

External 5 V bias on VCC and VDRV pin,

regular switching. T_J= 25°C, PVIN = 12 V,

I_OUT= 35 A, V_EN= 2 V, f_SW= 1.2 MHz

I_VCC

VCC and VDRV external bias current

VCC + VDRV shutdown supply current

57.3

6.3

mA

External 5 V bias on VCC and VDRV pin,

PVIN = 12 V, V_EN= 0 V

I_{SD(VCC_VDRV)}

5

7.5

UVLO

PVIN_OV

PVIN overvoltage rising threshold

PVIN overvoltage falling threshold

PVIN rising

18.0

12.9

18.6

13.4

19.2

13.9

V

PVIN falling. PVIN_OVF status bit, once it is

set, cannot be cleared unless PVIN falls

below the PVIN overvoltage falling threshold

PVIN_OV

PVIN rising, external 5 V bias on VCC and

VDRV pin

PVIN_UVLO(R)

PVIN_UVLO(F)

PVIN UVLO rising threshold

2.35

2.10

2.55

2.75

2.50

V

PVIN falling, external 5 V bias on VCC and

VDRV pin

PVIN UVLO falling threshold

PVIN UVLO hysteresis

2.30

0.25

V

PVIN_UVLO(H)

ENABLE

V_EN(R)

EN voltage rising threshold

EN voltage falling threshold

EN rising, enable switching

EN falling, disable switching

1.14

0.94

1.19

0.98

1.24

1.02

V

V_EN(F)

English Data Sheet: SLVSGM2

6

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6.5 Electrical Characteristics (continued)

T_J= –40°C to +125°C. PVIN = 4 V to 16 V, V_VCC= 4.5 V to 5.0 V (unless otherwise noted). Typical values are at T_J= 25°C,

PVIN = 12 V and V_VCC= 4.5 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

V_EN(H)

EN voltage hysteresis

EN Deglitch Time

0.21

t_EN(DIG)

0.2

µs

EN internal pulldown resistor

V_EN= 2 V, EN pin to AGND

110

125

140

kΩ

INTERNAL VCC LDO

VCC LDO output voltage

VCC LDO dropout voltage

AVIN= 4 V, I_VCC(load)= 5 mA

3.925

4.28

3.97

4.44

4.0

4.55

280

V

AVIN= 5 V to 16 V, I_VCC(load)= 5 mA

AVIN –V_VCC, AVIN = 4 V, I_VCC(load)= 50 mA

160.8

mV

T_J= –40°C to 85°C. VCC rising, enabling

initial power-on including re-loading default

values from NVM

VCC_OK rising threshold

3.0

3.15

3.10

3.3

V

T_J= –40°C to 85°C. VCC falling, disabling

controller circuit including the memory and

the digital engine

VCC_OK falling threshold

2.95

150

3.25

V

VCC LDO short-circuit current limit

mA

REFERENCE VOLTAGE

V_FB

FB voltage

T_J= 0°C to 85°C

T_J= –40°C to 125°C

V_FB= 800 mV

792

788

800

10

804

808

mV

nA

V_FB

FB voltage

I_FB(LKG)

FB input leakage current

SWITCHING FREQUENCY

T_J= –40°C to 125°C, PVIN = 12 V, V_OUT

1.1 V, no load, R_MODE= 0 Ω

=

f_SW(FCCM)

Switching frequency, FCCM operation

540

720

600

800

660

880

kHz

T_J= –40°C to 125°C, PVIN = 12 V, V_OUT

1.1 V, no load, R_MODE= 1.5 kΩ

Switching frequency, FCCM operation

T_J= –40°C to 125°C, PVIN = 12 V, V_OUT

1.1 V, no load, R_MODE= 14 kΩ

900

1000

1200

800

1100

1320

880

T_J= –40°C to 125°C, PVIN = 12 V, V_OUT

1.1 V, no load, R_MODE= 16.2 kΩ

1080

720

T_J= –40°C to 125°C, PVIN = 12 V, V_OUT

1.1 V, no load, R_MODE= float

STARTUP AND SHUTDOWN

t_ON(DLY)

Power on sequence delay

V_VCC= 4.5 V

0.5

1.0

2.0

4.0

8.0

4.0

0.55

1.1

2.2

4.4

8.8

4.4

ms

t_ON(Rise)

Soft-start time

V_VCC= 4.5 V, R_SS= AGND

V_VCC= 4.5 V, R_SS= 5.76 kΩ

V_VCC= 4.5 V, R_SS= 14 kΩ

V_VCC= 4.5 V, R_SS= 28.7 kΩ

V_VCC= 4.5 V, R_SS= open

t_ON(Rise)

POWER STAGE

R_DSON(HS)

R_DSON(LS)

t_ON(min)

High-side MOSFET on-resistance

Low-side MOSFET on-resistance

Minimum ON pulse width

T_J= 25°C, PVIN = 12 V, V_BOOT-SW= 4.5 V

T_J= 25°C, PVIN = 12 V, V_BOOT-SW= 5.0 V

T_J= 25°C, PVIN = 12 V, V_VDRV= 4.5 V

T_J= 25°C, PVIN = 12 V, V_VDRV= 5 V

V_VCC= 4.5 V

4

3.91

1

mΩ

ns

0.98

60

V_VCC= 4.5 V, I_OUT= 1.5 A, V_VOSNS

=

t_OFF(min)

Minimum OFF pulse width

210

250

150

ns

V

_{OUT_Setting}–20 mV, SW falling edge to

rising edge

BOOT CIRCUIT

I_BOOT(LKG)

BOOT leakage current

V_EN= 2 V, V_BOOT-SW= 5 V

µA

V

V_{BOOT-SW(UV_F)}

BOOT-SW UVLO falling threshold

2.60

2.76

OVERCURRENT LIMIT

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Product Folder Links: TPS548C26

English Data Sheet: SLVSGM2

TPS548C26

ZHCSPA4 –MARCH 2023

www.ti.com.cn

6.5 Electrical Characteristics (continued)

T_J= –40°C to +125°C. PVIN = 4 V to 16 V, V_VCC= 4.5 V to 5.0 V (unless otherwise noted). Typical values are at T_J= 25°C,

PVIN = 12 V and V_VCC= 4.5 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Valley current limit on LS FET, R_ILIM= 7.5

kΩ

Low-side valley overcurrent limit

(TPS548C26)

I_LS(OCL)

10.2

12

13.8

A

Valley current limit on LS FET, R_ILIM= 12.1

kΩ

Low-side valley overcurrent limit

(TPS548C26)

17.1

23.4

29.7

19

26

33

39

20.9

28.6

36.3

A

Valley current limit on LS FET, R_ILIM= 16.2

kΩ

Low-side valley overcurrent limit

(TPS548C26)

Valley current limit on LS FET, R_ILIM= 21.5

kΩ

Low-side valley overcurrent limit

(TPS548C26)

Valley current limit on LS FET, R_ILIM= 24.9

kΩ

Low-side valley overcurrent limit

(TPS548C26)

I_LS(OCL)

I_LS(NOC)

I_ZC

35.1

42.9

A

Low-side negative overcurrent limit

Zero-cross detection current threshold

Sinking current limit on LS FET

–18

–16

–14

ZC comparator threshold, enter DCM. PVIN

= 12 V, V_VCC= 4.5 V

1200

mA

Response delay before entering Hiccup

Hiccup sleep time before a restart

16

56

20

59

µs

49

ms

OUTPUT OVP AND UVP

V_OUTOvervoltage-protection (OVP)

V_OVF

113.8%

118.8%

100

122.5%

(V_FB– V_GOSNS) and rising

threshold

From OVF detection to the start of the NOC

operation

OVF response delay

ns

µs

V_OUTUndervoltage-protection (UVP)

threshold

V_UVF

70%

75%

16

80%

20

(V_FB– V_GOSNS) and falling

From UVF detection to tri-state of the power

FETs

UVF response delay

English Data Sheet: SLVSGM2

8

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6.5 Electrical Characteristics (continued)

T_J= –40°C to +125°C. PVIN = 4 V to 16 V, V_VCC= 4.5 V to 5.0 V (unless otherwise noted). Typical values are at T_J= 25°C,

PVIN = 12 V and V_VCC= 4.5 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER GOOD

V_OL(PG)

PG pin output low-level voltage

I_PG= 10 mA, PVIN = 12 V, V_VCC= 4.5 V

R_pullup= 10 kΩ, V_PG= 5 V

300

5

mV

µA

PG pin Leakage current when open drain

output is high

I_LKG(PG)

PVIN = 0 V, V_EN= 0 V, R_pullup= 10 kΩ,

Minimum VCC for valid PG pin output

1.2

V

_PG≤0.3 V

OUTPUT DISCHARGE

PVIN = 12 V, V_VCC= 4.5 V, V_VOSNS= 0.5 V,

EN=0V

Output discharge on VOSNS pin

455

Ω

THERMAL SHUTDOWN

Thermal shutdown (Analog OTP) threshold

T_J(SD)

Junction temperature rising

153

166

30

°C

((1))

Thermal shutdown (Analog OTP) hysteresis

T_J(HYS)

((1))

(1) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purpose of TI's

product warranty.

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6.6 Typical Characteristics

100

90

80

70

60

50

40

30

20

10

0

9

8

7

6

5

4

3

2

1

0

600 kHz

800 kHz

1.0 MHz

1.2 MHz

600 kHz

800 kHz

1.0 MHz

1.2 MHz

0

5

10

15

20

25

30

35

0

5

10

15

20

25

30

35

Load Current (A)

PVIN = 12 V

VCC = Internal LDO

V_OUT= 1.1 V

PVIN = 12 V

VCC = Internal LDO

V_OUT= 1.1 V

MODE = FCCM

图6-1. Efficiency vs Output Current

图6-2. Power Dissipation vs Output Current

100

90

80

70

60

50

40

30

20

10

0

7

6

5

4

3

2

1

0

600 kHz

800 kHz

1.0 MHz

1.2 MHz

600 kHz

800 kHz

1.0 MHz

1.2 MHz

0

5

10

15

20

25

30

35

0

5

10

15

20

25

30

35

Load Current (A)

PVIN = 12 V

VCC = External 5 V Bias V_OUT= 1.1 V

PVIN = 12 V

VCC = External 5 V Bias V_OUT= 1.1 V

MODE = FCCM

图6-3. Efficiency vs Output Current

图6-4. Power Dissipation vs Output Current

100

90

80

70

60

50

40

30

20

10

0

7

6

5

4

3

2

1

0

600 kHz

800 kHz

1.0 MHz

1.2 MHz

600 kHz

800 kHz

1.0 MHz

1.2 MHz

0

5

10

15

20

25

30

35

0

5

10

15

20

25

30

35

Load Current (A)

PVIN = 12 V

VCC = External 5 V Bias V_OUT= 1.1 V

PVIN = 12 V

VCC = External 5 V Bias V_OUT= 1.1 V

MODE = DCM

图6-5. Efficiency vs Output Current

图6-6. Power Dissipation vs Output Current

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7 Detailed Description

7.1 Overview

The TPS548C26 device is highly integrated buck converter. The device uses D-CAP+ control topology for fast

transient response, and accurate load and line regulation. The device is well-suited for space-constrained

applications such as data center applications, hardware accelerator, server and cloud computing POLs. The

device is easy to use and requires only few external components.

The TPS548C26 has low RDS_ONand supported external 5-V bias to provide high efficiency up to 35 A of

continuous current operation. the device has true differential remote sense through VOSNS and GOSNS pins,

and an accurate ±1%, with 0.8-V reference over the full operating junction temperature range. The device uses

selectable pin strap internal loop compensation. There is no external compensation required. The device

provides flexibility to select skip-mode or FCCM operation and programmable soft-start time. The device support

overcurrent, overvoltage, undervoltage, and overtemperature protections TPS548C26 is a lead-free device. The

device is fully RoHS compliant without exemption.

7.2 Functional Block Diagram

VDRV

On-die

Temperature sense

OT Fault

BOOT switch

DNC

NC

BOOT

PVIN

VOUT OV/UV

Detection

VDIFF

OVF/UVF

VCC

EN_PWM

+

–

FB

Integration

Loop Compensation

GOSNS

PHASE

SW

Driver Logic,

Anti-cross-

conduction,

VOSNS

VCOMP

Vramp

+

–

PWM

Ramp

Generator

PWM

Control logic

VDRV

BOOT-SW

UVLO

VIsns

Current Sense

gain

Isense

Valley current limit

Negative OC

Zero-cross detection

Isense

Low-side current sense

Adaptive

On-time

PGND

Generator

AVIN

VCC

VCC LDO

33

34

35

NC

EN_PWM

Pin Strap,

Housekeeping,

and

DVDD LDO

SS

ILIM

OVF/UVF

PG

Memory

AGND

MODE

AGND

EN

PG

7.3 Feature Description

7.3.1 Internal VCC LDO and Using an External Bias on VCC and VDRV Pin

The TPS548C26 device has an internal 4.5-V LDO featuring input from the AVIN pin and output to the VCC pin.

When the AVIN voltage rises, the internal LDO is enabled automatically and starts regulating the LDO output

voltage on the VCC pin. The VCC voltage provides the bias voltage for the internal analog circuitry on the

controller side, and the VDRV voltage provides the supply voltage for the power stage side.

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Either the VCC or VDRV pin must be bypassed with a 2.2 μF, at least 6.3-V rating ceramic capacitor.

Connecting the VCC pin decoupling capacitor to AGND is required to provide a clean ground for the analog

circuitry on the controller side. Referring the VDRV pin decoupling capacitor to PGND is required to minimize the

parasitic loop inductance for the driver circuitry in the power stage. Placing a 1-Ω resistor between the VCC pin

and VDRV pin forms a RC filter on VCC pin, which greatly reduces the noise impact from power stage driver

circuit.

An external bias ranging from 4.75 V to 5.30 V can be connected to the VDRV and VCC pin and power the IC.

This enhances the efficiency of the converter because the VCC and VDRV power supply current now runs off

this external bias instead of the internal linear regulator.

A VDRV UVLO circuit monitors the VDRV pin voltage and disables the switching when the VDRV voltage level

falls below the VDRV UVLO falling threshold. Maintaining a stable and clean VDRV voltage is required for a

smooth operation of the device.

Considerations when using an external bias on the VDRV and VCC pin are shown below:

• Connect the external bias to VDRV pin directly. Place a 1-Ω resistor between the VCC pin and VDRV pin,

then VCC is powered through the 1-Ω filtering resistor.

• For a configuration that the VCC pin and AVIN pin are shorted together, the internal LDO is always forced off.

A valid external bias is required to be connected to VDRV pin (VCC pin and AVIN pin are also powered by the

same external bias through the 1-Ω filtering resistor) so that the internal analog circuits have a stable power

supply rail at their power enable.

• For a configuration that the AVIN pin is not shorted to VCC pin, when the external bias is applied on the

VDRV pin earlier than AVIN rail (VCC pin is also powered by the same external bias through the 1-Ω filtering

resistor), the internal LDO is always forced off and the internal analog circuits have a stable power supply rail

at their power enable.

• The VCC and VDRV pins must be powered by the same source, either the internal VCC LDO, or the same

external bias.

• (Not recommended) When the external bias is applied on the VDRV pin late (for example, after AVIN rail

ramp-up), any power-up and power-down sequencing can be applied as long as there is no excess current

pulled out of the VCC pin. Understand that an external discharge path on the VCC or VDRV pin, which can

pull a current higher than the current limit of the internal LDO, can potentially turn off VCC LDO thereby

shutting off the converter output.

• A good configuration is: Place a 1-Ω resistor between the VCC pin and VDRV pin, and shorting the AVIN pin

to VCC pin.

• A good power-up sequence with above configuration is: The external 5-V bias is applied to VDRV pin first

(VCC pin is also powered by the same external bias through the 1-Ω filtering resistor), then the 12-V bus

applied on PVIN pin, and then the EN signal goes high.

7.3.2 Input Undervoltage Lockout (UVLO)

The TPS548C26 device provides four independent UVLO functions for the broadest range of flexibility in start-up

control. While only the fixed VCC_OK UVLO is required to enable the internal memory initialization, all four

UVLO functions must be met before the switching can be enabled.

7.3.2.1 Fixed VCC_OK UVLO

The TPS548C26 device has an internally fixed UVLO of 3.15 V (typical) on VCC to enable the digital core and

initiate power-on reset, including pin strap detection. The off-threshold on VCC is 3.1 V (typical). After VCC level

rises above 3.15 V (typical) and stays above 3.1 V (typical), the I²C communication is enabled.

7.3.2.2 Fixed VDRV UVLO

The TPS548C26 device has an internally fixed UVLO of 3.6 V (typical) on VDRV to enable drivers for power

FETs and output voltage conversion. The off-threshold on VDRV is 3.4 V (typical).

English Data Sheet: SLVSGM2

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7.3.2.3 Fixed PVIN UVLO

A PVIN UVLO circuit monitors the PVIN level and turns of switching when PVIN level is insufficient. When the

PVIN pin voltage is lower than the PVIN_UVLOfalling threshold voltage (typically 2.30 V), the device stops

switching and discharges the internal DAC reference. After the PVIN voltage increases beyond the PVIN_UVLO

rising threshold voltage (typically 2.55 V), the device re-initiates the soft-start and switches again. This PVIN

UVLO is a non-latch protection.

When the internal VCC LDO is used to power the VCC and VDRV pins, the device switching is not gated by this

PVIN UVLO. When the PVIN drops below the level of VDRV UVLO falling threshold plus the LDO dropout

voltage, the VDRV UVLO is triggered and the switching stops. When PVIN rises, the PVIN level has to rise

above the VDRV UVLO rising threshold to enable the switching. This means using the internal VCC LDO does

not allow power conversion under ultra-low PVIN condition.

While, power conversion under ultra-low PVIN condition can be enabled with an external 5-V bias on VCC and

VDRV pins. This configuration allows power conversion under ultra-low PVIN condition down to 2.7 V, as long as

the external bias maintains at a 5-V level to satisfy both the VCC_OK UVLO and the VDRV UVLO.

7.3.2.4 Enable

The TPS548C26 device offers precise enable, disable threshold on the EN pin. The power stage switching is

held off until EN pin voltage rises above the logic high threshold (typically 1.2 V). The power stage switching is

turned off after EN pin voltage drops below the logic low threshold (typically 1 V).

The EN pin has an internal filter to avoid unexpected ON or OFF due to short glitches. The deglitch time is set to

0.2 µs.

The recommended operating condition for EN pin is up to 5.3 V and the absolute maximum rating is 5.5 V. Do

not connect the EN pin to PVIN pin directly.

The TPS548C26 device remains disabled state when EN pin floats. The EN pin is internally pulled down to

AGND through a 125-kΩ resistor.

7.3.3 Set the Output Voltage

The output voltage is programmed by the FB voltage divider resistors, R_{FB_top}and R_{FB_bot}. Connect R_{FB_top}

between the FB pin and the positive node of the load, and connect R_{FB_bot}between the FB pin and GOSNS pin.

The recommended R_{FB_bot}value is 10 kΩ, ranging from 1 kΩ to 20 kΩ. Determine R_{FB_top}by using the below

equation:

V

− V

INTREF

OUT

V

R

=

− R

(1)

FB_top

FB_bot

INTREF

Where

• V_OUTis the desired output voltage in V.

• V_INTREFis 0.8 V.

To achieve the overall VOUT accuracy, using ±1% or better accuracy resistor for the FB voltage divider is highly

recommended.

The output voltage sensed on the VOSNS pin is fed into the internal on-time generation circuitry. TI recommends

shorting the VOSNS pin directly to VOUT sense point (that is, where the R_{FB_top}is connected). Adding any

resistance higher than 51 Ω between VOUT sense point and the VOSNS pin shifts switching frequency higher

than the desired setting. Contact Texas Instruments if a resistor has to be placed between VOUT sense point

and the VOSNS pin.

7.3.4 Differential Remote Sense and Feedback Divider

The TPS548C26 device offers true differential remote sense function which is implemented between FB pin and

GOSNS pin. The output of the differential remote sense amplifier is internally fed into the control loop and does

not come out to a package pin.

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Differential remote sense function compensates a potential voltage drop on the PCB traces thus helps maintain

VOUT accuracy under steady state operation and load transient event. Connecting the FB voltage divider

resistors to the remote location allows sensing the output voltage at a remote location. The connections from FB

voltage divider resistors to the remote location must be a pair of PCB traces with at least 12 mil trace width, and

must implement Kelvin sensing across a high bypass capacitor of 0.1 μF or higher on the sensing location. The

ground connection of the remote sensing signal must be connected to the GOSNS pin. The VOUT connection of

the remote sensing signal must be connected to the VOSNS pin and the top feedback resistor R_{FB_top}. To

maintain stable output voltage and minimize the ripple, the pair of remote sensing lines must stay away from any

noise sources such as inductor and SW node, or high frequency clock lines. TI recommends to shield the pair of

remote sensing lines with ground planes above and below.

The recommended GOSNS operating range (refer to AGND pin) is −100 mV to +100 mV. In case of local sense

(no remote sensing), short GOSNS pin to AGND.

7.3.5 Start-up and Shutdown

Start-up

The start-up sequence includes three sequential periods. During the first period, the device does initialization

which includes building up internal LDOs and references, internal memory initialization, pin strap detection, and

so forth. The initialization, which is not gated by EN pin voltage, starts as long as VCC pin voltage is above the

VCC_OK UVLO rising threshold (3.15 V typical). The length of this period is about 300 μs for TPS548C26

device. The pin strap detection result is locked in after the initialization is finished and as long as VCC voltage

stays above VCC_OK falling threshold. Changing the external resistor value does not affect the existing pin strap

detection result unless the IC is power cycled.

After the EN pin voltage crosses above EN high threshold (typically 1.2 V) the device moves to the second

period, power-on delay. The power-on delay is 0.5 ms to activate the control loop and the driver circuit.

The V_OUTsoft start is the third period. A soft-start ramp, which is an internal signal, starts right after the power-on

delay. When starting up without pre-bias on the output, the internal reference ramps up from 0 V to 0.8 V, and

the VOUT ramps up from 0 V to the setting value (by FB voltage divider). A proper soft-start time helps to avoid

the inrush current by the output capacitor charging, and also minimize VOUT overshoot. The soft-start time can

be selected among 4 options of 1 ms, 2 ms, 4 ms, and 8 ms by connecting a resistor from pin 29 SS to AGND.

表 7-1 lists the resistor values and the corresponding soft-start time. TI recommends ±1% tolerance resistors

with a typical temperature coefficient of ±100 ppm/°C.

For the start-up with a pre-biased output the device limits the discharge current from the pre-biased output

voltage by preventing the low-side FET from forcing the SW node low until after the first PWM pulse turns on the

high-side FET. After the increasing reference voltage exceeds the feedback voltage which is divided down from

the pre-biased output voltage, the SW pulses start. This enables a smooth startup with a pre-biased output.

After VOUT reaches the regulation value, a 1-ms PG delay starts. The converter then asserts PG pin when the

1-ms PG delay expires.

表7-1. SS Pin Strap for the Soft-start Time, Fault Response, and Internal Compensation

SS Pin to AGND Resistor

Soft-start time (ms)

Internal Compensation

VOUT OV, UV Fault Response

(kΩ)

0

1

2

4

8

1

2

4

8

1.50

2.49

3.48

4.53

5.76

7.32

8.87

Compensation1

Latch-off

Compensation2

English Data Sheet: SLVSGM2

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表7-1. SS Pin Strap for the Soft-start Time, Fault Response, and Internal Compensation (continued)

SS Pin to AGND Resistor

Soft-start time (ms)

Internal Compensation

VOUT OV, UV Fault Response

(kΩ)

10.5

1

2

4

8

1

2

4

8

4

12.1

Compensation1

14.0

16.2

Hiccup

18.7

21.5

Compensation2

24.9

28.7

Floating

Compensation1

Latch-off

备注

The pin strap detection happens at the first stage of power-up sequence. After the detection finishes,

the detection results are latched in and do not change during the following operation. If a new

selection is desired, toggling VCC (or AVIN) is required. Toggling the EN pin does not affect the pin

strap detection results.

Shutdown

The TPS548C26 device features a simple shutdown sequence. Both high-side and low-side FET drivers are

turned off immediately at the time when the EN pin is pulled low, and the output voltage discharge slew rate is

controlled by the external load. The internal reference is discharged down to zero to get ready for the next soft

start.

7.3.6 Loop Compensation

The TPS548C26 device features D-CAP+ control topology with internal loop compensation for fast transient

response. As listed in 表 7-1, two sets of loop compensation are provided for tuning the output voltage feedback

and response to transients. Compensation1 is the recommended compensation for any application using relative

large inductor (for example, 400 nH or higher). Compensation2 is the recommended compensation for any

application using relative small inductor (for example, 200 nH or lower). TI does not recommend electing

Compensation2 for a large inductor design because the control loop does not receive the right amount of current

sensing signal when the low-side FET conduction time is approaching t_OFF(min)

.

To avoid wrong pin strap detection, TI recommends ±1% tolerance resistors with a typical temperature coefficient

of ±100 ppm/°C.

7.3.7 Set Switching Frequency and Operation Mode

TPS548C26 device provides programmable operation mode including the forced CCM operation for tight output

voltage ripple and auto-skipping Eco-mode for high light-load efficiency. The TPS548C26 device allows users to

select the switching frequency and operation mode through the pin strap detection on MODE pin. 表 7-2 lists the

resistor values for the switching frequency and operation mode selections. TI recommends ±1% tolerance

resistors with a typical temperature coefficient of ±100 ppm/°C.

The FCCM bit is set during initial power-on and latched after the power conversion is enabled (EN=high). While

the device is enabled, a write to FCCM bit is acknowledged but the operation mode does not change until an EN

toggle happens.

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表7-2. MODE Pin Strap for Switching Frequency and Operation MODE

MODE Pin to AGND Resistor

Switching Frequency (kHz)

Operation Mode

(kΩ)

0

1.50

2.49

3.48

10.5

12.1

14

600

800

FCCM

1000

1200

600

800

Auto-skipping Eco-mode (DCM)

FCCM

1000

1200

800

16.2

Floating

备注

The pin strap detection happens at the first stage of power-up sequence. After the detection finishes,

the detection results are latched in and do not change during the following operation. If a new

selection is desired, toggling VCC (or AVIN) is required. Toggling the EN pin does not affect the pin

strap detection results.

7.3.8 Switching Node (SW)

The SW pins connect to the switching node of the power conversion stage. The SW pins act as the return path

for the high-side gate driver. During nominal operation, the voltage swing on SW normally traverses from below

ground to above the input voltage. Parasitic inductance in the PVIN to PGND loop (including the component

from the PCB layout and also the component inside the package) and the output capacitance (COSS) of both

power FETs form a resonant circuit that can produce high frequency (> 100 MHz) ringing on this node. The

voltage peak of this ringing, if not controlled, can be significantly higher than the input voltage. TPS548C26 high-

side gate driver is fine tuned to minimize the peak ringing amplitude so that a RC snubber on SW node is usually

not needed. However, TI highly recommends for the user to measure the voltage stress across either the high-

side or low-side FET and ensure that the peak ringing amplitude does not exceed the absolute maximum rating

limit listed in the Absolute Maximum Ratings table.

7.3.9 Overcurrent Limit and Low-side Current Sense

For a synchronous buck converter, the inductor current increases at a linear rate determined by the input

voltage, the output voltage, and the output inductor value during the high-side MOSFET on-time (ON time).

During the low-side MOSFET on-time (OFF time), this inductor current decreases linearly per slew rate

determined by the output voltage and the output inductor value. The inductor during the OFF time, even with a

negative slew rate, usually flows from the device SW node to the load the device which is said to be sourcing

current and the output current is declared to be positive. This section describes the overcurrent limit feature

based on the positive low-side current. The next section describes the overcurrent limit feature based on the

negative low-side current.

The positive overcurrent limit (OCL) feature in the TPS548C26 device is implemented to clamp low-side valley

current on a cycle-by-cycle basis. The inductor current is monitored during the OFF time by sensing the current

flowing through the low-side MOSFET. When the sensed low-side MOSFET current remains above the selected

OCL threshold, the low-side MOSFET stays ON until the sensed current level becomes lower than the selected

OCL threshold. This operation extends the OFF time and pushes the next ON time (where the high-side

MOSFET turns on) out. As a result, the average output current sourced by the device is reduced. As long as the

load pulls a heavy load where the sensed low-side valley current exceeds the selected OCL threshold, the

device continuously operates in this clamping mode which extends the current OFF time and pushes the next

ON time out. The device does not implement a fault response circuit directly tied to the overcurrent limit circuit,

instead, the VOUT UVF function is used to shuts the device down under an overcurrent fault.

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During an overcurrent event, the current sunk by the load (I_OUT) exceeds the current sourced by the device to

the output capacitors, thus, the output voltage tends to decrease. Eventually, when the output voltage falls below

the selected undervoltage fault threshold, the VOUT UVF comparator detects and shuts down the device after

the UVF Response Delay (typically 16 µs). The device then responds to the VOUT UVF trigger per fault

response selected through SS pin. With the Latch-off response selected, the device latches OFF both high-side

and low-side drivers. The latch is cleared with a reset of VCC or by toggling the EN pin. With the Hiccup

response selected, the device enters hiccup mode and re-starts automatically after a hiccup sleep time of 56 ms,

without limitation on the number of restart attempts. In other words, the response to an overcurrent fault is set by

the selected UVF response.

If an OCL condition happens during a soft-start ramp the device still operates with the cycle-by-cycle current limit

based on the sensed low-side valley current. This operation can limit the energy charged into the output

capacitors thus the output voltage likely ramps up slower than the desired soft-start slew rate. During the soft-

start, the VOUT UVF comparator is disabled thus the device does not respond to an UVF event. Upon the

completion of the soft-start, the VOUT UVF comparator is enabled, then the device starts responding to the UVF

event.

The resistor, R_ILIM, connected from the ILIM pin to AGND sets the overcurrent limit threshold (see the following

table). TI recommends ±1% tolerance resistors with a typical temperature coefficient of ±100 ppm/°C.

表7-3. ILIM Pin Strap for Overcurrent Limit Threshold

OCL Threshold (Valley Current Detection)

ILIM Pin to AGND Resistor (kΩ)

7.5

12 A

19 A

26 A

33 A

39 A

12.1

16.2

21.5

24.9

备注

The pin strap detection happens at the first stage of power-up sequence. After the detection finishes,

the detection results are latched in and do not change during the following operation. If a new

selection is desired, toggling VCC (or AVIN) is required. Toggling the EN pin does not affect the pin

strap detection results.

7.3.10 Negative Overcurrent Limit

The TPS548C26 device is a synchronous buck converter, thus the current can flow from the device to the load or

from the load into the device through SW node. When the current is flowing from the device SW node to the load

the device is said to be sourcing current and the output current declared to be positive. When the current is

flowing into the device SW node from the load, the device is said to be sinking current and the current is

declared to be negative.

The device offers a fixed, cycle-by-cycle negative overcurrent (NOC) limit which is set to −16 A. Similar with the

positive overcurrent limit, the inductor current is monitored during the low-side FET on period. To prevent too

large negative current and a damage of low-side FET, the device turns off the low-side FET after the detected

negative current through the low-side FET exceeds the NOC limit. And then the high-side FET is turned on for

an on-time determined by PVIN, VOUT, and f_SWsetting. After the high-side FET on-time expires, the low-side

FET turns on again.

The device is unlikely to trigger the −16-A negative current limit during the nominal operation unless too small

inductor value is chosen or the inductor becomes saturated. This NOC operation feature is used to discharge

output capacitors during an overvoltage event.

7.3.11 Zero-Crossing Detection

TPS548C26 device implements an internal circuit for the zero inductor-current detection during skip-mode

operation. The fixed Z-C detection threshold is set to a slightly positive value such as 300 mA to compensate the

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delay time of the Z-C detection circuit and avoid too-late detection. Depending on the inductor value, frequency,

VIN and Vout conditions, this can result diode conduction for a short period.

7.3.12 Input Overvoltage Protection

The TPS548C26 device actively monitors the PVIN input voltage. When the PVIN voltage level is above the

input overvoltage threshold, TPS548C26 device stops switching and pulls PG signal low. The PVIN OV rising

threshold is typically 18.6 V while the PVIN OV falling threshold is typically 13.4 V.

After the PVIN overvoltage fault is triggered, the device latches off both the high-side and low-side FETs until the

EN pin is toggled or PVIN is reset.

7.3.13 Output Undervoltage and Overvoltage Protection

The TPS548C26 device monitors the FB node voltage (V_FB− V_GOSNS) to provide overvoltage (OV) and

undervoltage (UV) protection.

VOUT UVF

When the FB node voltage (V_FB− V_GOSNS) drops to 600 mV or lower, the UVF comparator detects and an

internal UVF Response Delay counter begins. When the 16 µs UVF Response Delay expires, the device

responds per the fault response selected through SS pin. With the Latch-off response selected, the device

latches OFF both high-side and low-side FETs. The latch is cleared with a reset of VCC or by toggling the EN

pin. With the Hiccup response selected, the device enters hiccup mode and re-starts automatically after a hiccup

sleep time of 56 ms, without limitation on the number of restart attempts.

The UVF function is enabled only after the soft-start period completes.

During the UVF Response Delay, if the FB node voltage (V_FB− V_GOSNS) rises above the UVF threshold, thus not

qualified for a UVF event, the UVF response delay timer resets to zero. When the VOUT drops below the UVF

threshold again, the UVF response delay timer re-starts from zero.

VOUT OVF

When the FB node voltage (V_FB− V_GOSNS) rises to 950 mV or higher, the OVF comparator detects and the

device immediately latches OFF the high-side FET and turns on the low-side FET until the current flowing

through low-side FET exceeds the negative overcurrent (NOC) limit. Upon reaching the −16-A NOC limit, the

low-side FET is turned off, and the high-side FET is turned on again for an on-time determined by PVIN, VOUT,

and f_SWsetting. The device operates in this cycle until the output voltage is fully discharged. After VOUT is fully

discharged, the high-side FET is latched OFF and the low-side FET is latched ON. With the Latch-off response

selected, the device is kept under the state of the high-side FET latched OFF and the low-side FET latched ON.

The latch is cleared with a reset of VCC or by toggling the EN pin. With the Hiccup response selected, the device

still discharges output voltage by running the NOC operation. However, the device re-starts automatically after a

hiccup sleep time of 56 ms, without limitation on the number of restart attempts. The hiccup sleep time counter

starts right after the OVF trigger.

The OVF function is enabled only after the soft-start period completes.

7.3.14 Overtemperature Protection

To have full coverage for a potential overtemperature event, the TPS548C26 device implements two

overtemperature protection circuitries - one on the Controller side and one on the Power Stage (PS) side.

OTP by Monitoring the Power Stage Temperature

A temperature sensing circuit is implemented in the Power Stage (PS) side. This sensed temperature is fed into

an OTP circuit on the PS side to be compared with a fixed threshold (rising 166°C typical). The device stops the

SW switching when the sensed IC temperature goes beyond the fixed threshold. After the PS die temperature

falls 30°C below the rising threshold, the device automatically restarts with an initiated soft-start. This OTP on

power stage side is a non-latch protection.

English Data Sheet: SLVSGM2

18

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OTP by Monitoring the Controller Temperature

The Controller features an internal on-die temperature sensing circuit. The sensed temperature signal is fed into

an OTP comparator on the Controller side and compared with a fixed threshold (rising 166°C typical). The

device stops the SW switching when the sensed Controller temperature goes beyond the fixed threshold. The

device response to an OTP event is set by the SS pin strap detection. With the Latch-off response selected, the

device latches OFF both high-side and low-side FETs. The latch is cleared with a reset of VCC or by toggling the

EN pin. With the Hiccup response selected, the device enters hiccup mode and re-starts automatically after a

hiccup sleep time of 56 ms, without limitation on the number of restart attempts.

Given the power loss on the controller side is much less than the power loss on the power stage side, the OTP

on controller side is unlikely to trigger during the nominal operation.

7.3.15 Power Good

The TPS548C26 device offers a power-good output on PG pin, which asserts high when the converter output is

within the target. The PG output stays low when the switching is disabled by EN pin or insufficient PVIN level.

The PG output is an open-drain output and must be pulled up externally through a pull-up resistor (usually 10

kΩ). The recommended PG pull-up resistor value is from 1 kΩ to 100 kΩ.

The PG function is activated after VCC voltage level reaches the minimum VCC threshold for a valid PG output

(maximum 1.2V). When VCC is lower than 1.2V, the PG circuit does not have sufficient power supply and the

open-drain output is always high-Z. The power-good function is fully activated after the soft-start ramp is

completed and also the 1 ms PG delay expires.

7.4 Device Functional Modes

7.4.1 Forced Continuous-Conduction Mode

When the operation mode is set to FCCM, the controller operates in continuous conduction mode (CCM) during

light-load conditions. During CCM, the switching frequency maintained to an almost constant level over the entire

load range which is suitable for applications requiring tight control of the switching frequency at the cost of lower

efficiency.

When FCCM is selected, the TPS548C26 device operates at CCM during the whole soft-start period as well as

the nominal operation.

7.4.2 Auto-Skip Eco-mode Light Load Operation

When the operation mode is set to DCM, the device automatically reduces the switching frequency at light-load

conditions to maintain high efficiency. This section describes the operation in detail.

As the output current decreases from heavy load condition, the inductor current also decreases until the rippled

valley of the inductor current touches zero level. Zero level is the boundary between the continuous-conduction

and discontinuous-conduction modes. The synchronous MOSFET turns off when this zero inductor current is

detected. As the load current decreases further, the converter runs into discontinuous-conduction mode (DCM).

The on-time is maintained to a level approximately the same as during continuous-conduction mode operation

so that discharging the output capacitor with a smaller load current to the level of the reference voltage requires

more time. The transition point to the light-load operation IOUT(LL) (for example: the threshold between

continuous- and discontinuous-conduction mode) is calculated as shown in below equation.

V

- V

´ V

(

)

OUT OUT

V

IN

1

IN

I

=

´

OUT LL

( )

2´L ´ f

SW

(2)

Where

• f_SWis the switching frequency

TI recommends sing low ESR capacitors (such as ceramic capacitor) for skip-mode.

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7.4.3 Powering the Device from a 12-V Bus

The device works well when powering from a 12-V bus with a single V_INconfiguration. As a single V_IN

configuration, the internal LDO is powered by the 12-V bus and generates 4.5-V output to bias the internal

analog circuitry and also powers up the gate drives. The V_INinput range under this configuration is 4 V to 16 V

for up to 35-A load current. 图7-1 shows an example for this single V_INconfiguration.

V_INand EN are the two signals to enable the part. For start-up sequence, any sequence between the V_INand

EN signals can power the device up correctly.

V_IN: 4 V to 16 V

PVIN

AVIN

BOOT

PHASE

SW

V_OUT

VCC

Load

VDRV

PGND

6

DNC

NC

37

VOSNS

EN

FB

MODE

ILIM

SS

GOSNS

Power Good

PG

33

34

35

NC

AGND

图7-1. Single V_INConfiguration with 12-V Bus

7.4.4 Powering the Device From a Split-rail Configuration

When an external bias that is at a different level from the main V_INbus, is applied to the VDRV pin, the device

can be configured to split rail by using both the main V_INbus and the VDRV bias. Connecting a valid bias rail to

the VDRV pin overrides the internal VCC LDO, saving power loss on that linear regulator. This configuration

helps improve overall system-level efficiency but requires a valid VCC bias. A 5.0-V rail is the common choice for

the VDRV bias. With a stable VDRV bias, the V_INinput range under this configuration can be as low as 2.7 V

and up to 16 V.

The noise of the external bias affects the internal analog circuitry. To ensure a proper operation, a clean, low-

noise external bias, and a local decoupling capacitor from the VDRV pin to PGND pin are required. 图7-2 shows

an example for this split rail configuration.

The VDRV external bias current during nominal operation varies with the bias voltage level and the switching

frequency. For example, by setting the device to skip mode, the VDRV pin draws less and less current from the

external bias when the switching frequency decreases under light load condition. The typical VDRV external bias

current under FCCM operation is listed in the Electrical Characteristics table to help the user prepare the

capacity of the external bias.

Under split rail configuration, PVIN, VDRV bias, and EN are the signals to enable the part. For the start-up

sequence, it is recommended that the external bias is applied on the VDRV pin earlier than PVIN rail. A practical

start-up sequence example is the external 5-V bias is applied first, then the 12-V bus is applied on PVIN, and

then EN signal goes high.

English Data Sheet: SLVSGM2

20

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V_IN: 4 V to 16 V

PVIN

AVIN

BOOT

PHASE

SW

V_OUT

VCC

Load

PGND

VDRV

Ext bias: 4.75 V to 5.3 V

6

DNC

NC

37

VOSNS

EN

FB

MODE

ILIM

SS

GOSNS

Power Good

PG

33

34

35

NC

AGND

图7-2. Split Rail Configuration with External VCC Bias

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The TPS548C26 device is a highly-integrated, synchronous, step-down DC/DC converter. The TPS548C26 has

a simple design procedure where programmable parameters can be configured through pin strap detections.

8.2 Typical Application

8.2.1 Application

This design describes a 3.3 V, 35 A application for the TPS548C26EVM.

图8-1. TPS548C26EVM 3.3-V Output Application

English Data Sheet: SLVSGM2

22

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8.2.2 Design Requirements

This design uses the parameters listed in Design Requirements.

表8-1. Design Parameters

PARAMETER

VALUE

Input voltage

10.8 V –13.2 V

Output Voltage

Output current

3.3 V

35 A

Switching frequency

800 kHz

8.2.3 Detailed Design Procedure

This design example leverages the requirements for the TPS548C26EVM. The default settings for this device

are optimal for this application. The following steps illustrate how to select key components.

8.2.3.1 Inductor Selection

In general, a smaller inductance increases loop bandwidth leading to better transient response at the expense of

higher current and voltage ripple. The inductor must be selected such that the transient performance and ripple

requirements are balanced for a particular design. The recommendation is that the inductor ripple current is kept

within the range of 20% to 40% of the desired output current. In this example, a 400-nH, 0.8-mΩ inductor is

used.

8.2.3.2 Input Capacitor Selection

Input capacitors must be selected to provide reduction in input voltage ripple and high-frequency bypassing,

which in return reduces switching stress on the power stage MOSFETs internal to the device. In this example, a

0.1-µF, 25-V, 0402 ceramic capacitor must be placed as close as possible to pin 20 of the device on the same

layer as the IC on the PCB. In addition, 6pcs 10-µF ceramic capacitors are used and an optional 270-µF bulk

capacitor is used on the input.

8.2.3.3 Output Capacitor Selection

To meet the output voltage ripple and load transient requirements, use a 1-µF and 2pcs 22-µF ceramic

capacitors local to the output of the inductor. Additionally, use 2pcs 220-µF bulk capacitors on the top-side of the

PCB combined with 4pcs 22-µF ceramic capacitors on the bottom-side of the PCB.

8.2.3.4 VCC and VRDV Bypass Capacitor

Connect a 2.2-µF, 6.3-V (or 10 V) rated ceramic capacitor to AGND for bypassing of the VCC pin.

Connect a 2.2-µF, 6.3-V (or 10 V) rated ceramic capacitor to PGND for bypassing of the VDRV pin. This bypass

capacitor must refer to PGND pin 7 - 10 to minimize the length of high-frequency driving current path.

Placing a 1-Ω resistor between the VCC and VDRV pin forms a RC filter on VCC pin, which greatly reduces the

noise impact from power stage driver circuit.

8.2.3.5 BOOT Capacitor Selection

Use a minimum of a 0.1-µF capacitor connected from Phase (pin 25) to Boot (pin 26). An optional series boot

resistor of 0 Ω or 2.2 Ω can be added.

8.2.3.6 PG Pullup Resistor Selection

The PG output is an open-drain output and must be pulled up externally through a pullup resistor. Place a pullup

resistor, within a 1-kΩ to 100-kΩ range, at the PG pin (pin 2). In this example, PG is pulled up to VCC/VDRV with

a 10-kΩ resistor.

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8.2.4 Application Curves

100

90

80

70

60

50

40

30

20

10

0

9

8

7

6

5

4

3

2

1

0

600 kHz

800 kHz

1.0 MHz

1.2 MHz

600 kHz

800 kHz

1.0 MHz

1.2 MHz

0

5

10

15

20

25

30

35

0

5

10

15

20

25

30

35

Load Current (A)

PVIN = 12 V

V_OUT= 1.1 V

PVIN = 12 V

V_OUT= 1.1 V

图8-2. Efficiency, FCCM, Internal LDO

图8-3. Power Dissipation, FCCM, Internal LDO

100

90

80

70

60

50

40

30

20

10

0

7

6

5

4

3

2

600 kHz

800 kHz

1.0 MHz

1.2 MHz

600 kHz

800 kHz

1.0 MHz

1.2 MHz

1

0

5

10

15

20

25

30

35

0

5

10

15

20

25

30 35

Load Current (A)

PVIN = 12 V

V_OUT= 1.1 V

PVIN = 12 V

V_OUT= 1.1 V

图8-4. Efficiency, FCCM, External 5-V Bias

图8-5. Power Dissipation, FCCM, External 5-V Bias

100

90

80

70

60

50

40

7

6

5

4

3

30

2

600 kHz

800 kHz

600 kHz

20

800 kHz

1.0 MHz

1.2 MHz

1.0 MHz

1.2 MHz

1

10

0

5

10

15

20

25

30

35

0

5

10

15

20

25

30 35

Load Current (A)

PVIN = 12 V

V_OUT= 1.1 V

PVIN = 12 V

V_OUT= 1.1 V

图8-6. Efficiency, DCM, External 5-V Bias

图8-7. Power Dissipation, DCM, External 5-V Bias

24

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3.32

3.319

3.318

3.317

3.316

3.315

3.314

3.313

3.312

3.311

3.32

3.319

3.318

3.317

3.316

3.315

3.314

3.313

3.312

3.311

3.31

600 kHz

800 kHz

1.0 MHz

1.2 MHz

600 kHz

800 kHz

1.0 MHz

1.2 MHz

3.31

0

5

10

15

20

25

30

35

0

5

10

15

20

25

30

35

Load Current (A)

PVIN = 12 V

No DC Load Line (DCLL)

V_OUT= 3.3 V

PVIN = 12 V

No DC Load Line (DCLL)

V_OUT= 3.3 V

图8-8. Load Regulation, FCCM, Internal LDO

图8-9. Load Regulation, FCCM, External 5-V Bias

3.32

3.319

3.318

3.317

3.316

3.315

3.314

3.32

3.319

3.318

3.317

3.316

3.315

3.314

3.313

600 kHz

800 kHz

1.0 MHz

1.2 MHz

800 kHz

1.0 MHz

1.2 MHz

3.312

3.311

3.31

3.312

3.311

3.31

0

5

10

15

20

25

30

35

0

5

10

15

20

25

30

35

Load Current (A)

PVIN = 12 V

No DC Load Line (DCLL)

V_OUT= 3.3 V

PVIN = 12 V

No DC Load Line (DCLL)

V_OUT= 3.3 V

图8-10. Load Regulation, DCM, Internal VCC LDO 图8-11. Load Regulation, DCM, External 5-V Bias

图8-12. ENABLE Start-Up Waveform, PVIN = 12 V, 图8-13. ENABLE Shutdown Waveform, PVIN = 12

VOUT = 1.8 V

V, VOUT = 1.8 V

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图8-14. Output Voltage Ripple, 800 kHz FCCM, 35 图8-15. Output Voltage Ripple, 800 kHz FCCM, No

A Load, PVIN = 12 V, VOUT = 3.3 V load, PVIN = 12 V, VOUT = 3.3 V

图8-16. Output Voltage Ripple, DCM, No load, PVIN = 12 V, VOUT = 3.3 V

8.3 Power Supply Recommendations

The device is designed to operate from a wide input voltage supply range between 2.7 V and 16 V when the

VDRV pin is powered by an external bias ranging from 4.75 V to 5.3 V. Both input supplies (PVIN and VDRV

bias) must be well regulated. Proper bypassing of input supplies (PVIN and VDRV) is also critical for noise

performance, as are PCB layout and grounding scheme. See the recommendations in Layout Guidelines.

8.4 Layout

8.4.1 Layout Guidelines

Layout is critical for good power supply design. Layout example shows the recommended PCB layout

configuration. A list of PCB layout considerations using the device is listed as follows:

• Place the power components (including input and output capacitors, the inductor, and the IC) on the top side

of the PCB. To shield and isolate the small signal traces from noisy power lines, insert at least one solid

ground inner plane.

• PVIN-to-PGND decoupling capacitors are important for FET robustness. Besides the large volume 0603 or

0805 ceramic capacitors, TI highly recommends a 0.1-µF, 0402 ceramic capacitor with 25-V / X7R rating on

PVIN pin 20 (top layer) to bypass any high frequency current in PVIN to PGND loop. TI recommends the 25-

V rating, but can be lowered to 16-V rating for an application with tightly regulated 12-V input bus.

• When one or more PVIN-to-PGND decoupling capacitors are placed on bottom layer, extra impedance is

introduced to bypass IC PVIN node to IC PGND node. Placing at least 3 times PVIN vias on PVIN pad

English Data Sheet: SLVSGM2

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(formed by pin 20 to pin 24) and at least nine times PGND vias on the thermal pad (underneath of the IC) is

important to minimize the extra impedance for the bottom layer bypass capacitors.

• Except the PGND vias underneath the thermal pad, at least four PGND vias are required to be placed as

close as possible to the PGND pin 7 to pin 10. At least two PGND vias are required to be placed as close as

possible to the PGND pin 19. This action minimizes PGND bounces and also lowers thermal resistance.

• Place the VDRV-to-PGND decoupling capacitor as close as possible to the device. TI recommends a 2.2-

µF/6.3 V/X7R/0603 or 4.7-µF/6.3 V/X6S/0603 ceramic capacitor. The voltage rating of this bypass capacitor

must be at least 6.3 V but no more than 10 V to lower ESR and ESL. The recommended capacitor size is

0603 to minimize the capacitance drop due to DC bias effect. Ensure the VDRV to PGND decoupling loop is

the smallest and ensure the routing trace is wide enough to lower impedance.

• As the input of VCC LDO, connect a 1-µF, 25-V rated ceramic capacitor to AGND for the bypassing of the

AVIN pin. TI recommends the 25-V rating is recommended but can be lowered to 16-V rating for an

application with tightly regulated 12-V input bus.

• Connect a 2.2-µF, 6.3-V (or 10 V) rated ceramic capacitor to AGND for the bypassing of the VCC pin. Placing

a 1-Ω resistor between the VCC pin and VDRV pin forms a RC filter on VCC pin, which greatly reduces the

noise impact from power stage driver circuit.

• For remote sensing, the connections from FB voltage divider resistors to the remote location must be a pair of

PCB traces with at least 12 mil trace width, and must implement Kelvin sensing across a high bypass

capacitor of 0.1 μF or higher on the sensing location. The ground connection of the remote sensing signal

must be connected to the GOSNS pin. The VOUT connection of the remote sensing signal must be

connected to the VOSNS pin and the top feedback resistor R_{FB_top}. To maintain stable output voltage and

minimize the ripple, the pair of remote sensing lines must stay away from any noise sources such as inductor

and SW node, or high frequency clock lines. TI recommends to shield the pair of remote sensing lines with

ground planes above and below.

• For single-end sensing, connect the FB voltage divider resistors to a high-frequency local bypass capacitor of

0.1 μF or higher, and short GOSNS to AGND with shortest trace.

• The AGND pin 32 must be connected to a solid PGND plane. TI recommends to place AGND via close to pin

32 to route AGND from top layer to bottom layer, and then connect the AGND trace to the PGND vias

(underneath IC) through either a net-tie or a 0-Ω resistor on the bottom layer.

• Connecting a resistor from pin 1 (ILIM) to AGND sets the OCL threshold. Connecting a resistor from pin 29

(SS) to AGND sets soft-start time, internal compensation, and fault response. Connecting a resistor from pin

36 (MODE) to AGND sets the switching frequency and the operation mode. TI requires not to have any

capacitor on these 3 pins (ILIM, SS, and MODE). A capacitor on any of these 3 pins likely leads to a wrong

detection result.

• Pin 6 (DNC) is a Do-Not-Connect pin. Pin 6 can be shorted to pin 37, which is an NC pin (No internal

Connection). Do not connect pin 6 to any other net including ground.

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8.4.2 Layout Example

8/20

0402

Ground sense

VOUT sense

FB divider

8/20

Short pin 33 –

35 to AGND, or

kept them open

CFF,

op onal

8/20

0402

8/20

AGND

PG Pullup

source

PG signal

8/20

0402

8/20

Enable

ILIM

PG

VOSNS

AGND

8/20

0402

EN

0402

PVIN Bypass capacitors:

8/20

1x 0402 capacitors on top layer;

2x 0805 capacitors on top layer;

2x 0805 capacitors on bo om layer

AVIN

VCC

BOOT

PHASE

PVIN

PGND

0402

8/20

Filtering resistor

on bo om layer

0402

VDRV

DNC

8/20

NC

8/20

PGND

8/20

08

Ground sense

VOUT sense

8 / 2 0

VOUT

Notes for VOUT Bypass capacitors:

Place ceramic capacitors on top

layer; Bulk capacitors are op onal

and can be placed on bo om layer

图8-17. Layout Recommendation

English Data Sheet: SLVSGM2

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8.4.2.1 Thermal Performance on TPS548C26 Evaluation Board

Below are thermal results captured on the TPS548C26 evaluation board with PVIN = 12 V, V_OUT= 3.3 V

conditions.

图8-18. Thermal Characteristics, 600-kHz FCCM, Internal LDO, 35-A Load

图8-19. Thermal Characteristics, 600-kHz FCCM, Internal LDO, 35-A Load

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9 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,

generate code, and develop solutions are listed below.

9.1 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

9.2 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

9.3 Trademarks

D-CAP+^™and TI E2E^™are trademarks of Texas Instruments.

所有商标均为其各自所有者的财产。

9.4 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

9.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

English Data Sheet: SLVSGM2

30

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Product Folder Links: TPS548C26

TPS548C26

ZHCSPA4 –MARCH 2023

www.ti.com.cn

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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31

Product Folder Links: TPS548C26

English Data Sheet: SLVSGM2

GENERIC PACKAGE VIEW

RXX 37

5 x 6, 0.5 mm pitch

VQFN-FCRLF - 1.05 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4228557/A

www.ti.com

PACKAGE OUTLINE

WQFN-FCRLF - 0.7 mm max height

PLASTIC QUAD FLAT PACK- NO LEAD

A

RXX0037A

5.1

4.9

B

6.1

5.9

PIN 1 INDEX AREA

0.7

0.6

C

SEATING PLANE

0.01

0.00

0.08

(0.2)

C

0.45

0.35

(0.20) TYP

(0.25) TYP

11

18

19

20

2.34±0.1

10

2.089±0.1

1.839±0.1

0.5

0.4

39

7

6

0.3

0.2

0.625±0.1

0.15±0.1

0.000 PKG ℄

38

2X 4.5

37

24

25

0.306±0.1

0.626±0.1

0.325±0.1

28

2.25±0.1

1

PIN 1 ID

(OPTIONAL)

36

29

0.45

18X

0.3

0.2

37X

0.35

32X 0.5

2X 3.5

0.1

C

A

B

0.05

C

4226301/D 11/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

WQFN-FCRLF - 0.7 mm max height

PLASTIC QUAD FLAT PACK- NO LEAD

RXX0037A

29

36

10X (R0.1)

(2.9)

(0.05) MIN

ALL AROUND

TYP

(R 0.05) TYP

28

(2.25)

1

(1.938)

18X (0.6)

(0.938)

25

(0.363)

(0.325)

(0.626)

(0.306)

24

37

0.000 PKG ℄

2X (4.5)

(0.15)

6

(0.45)

(0.625)

2X (0.767)

(Ø0.2) TYP

7

2X (0.672)

(1.483)

20

(1.839)

(2.089)

(2.34)

19

10

(2.6)

(2.8)

(3.2)

11

18

37X (0.25)

32X (0.5)

2X (3.5)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 15X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

NON- SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4226301/D 11/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

WQFN-FCRLF - 0.7 mm max height

PLASTIC QUAD FLAT PACK- NO LEAD

RXX0037A

2X (1)

37X (0.25)

3X (1)

18X (0.6)

36

29

(2.9)

(R 0.05) TYP

28

1

(1.438)

(1.47)

2X (1.318)

2X (1.71)

25

24

37

2X (4.5)

0.000 PKG ℄

(0.84)

(0.155)

(0.187)

6

7

(1.47)

10X (0.45)

2X (0.96)

(1.347)

2X (1.547)

20

(2.09)

19

2X (1.55)

(1.2)

2X (1.05)

10

(2.6)

(2.8)

(3.2)

18

11

(1.17)

32X (0.5)

2X (3.5)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SOLDER COVERAGE :

Thermal Pad connected to pin 7-10, 19 : 80%

Thermal Pad connected to pin 20-24 : 86%

SCALE: 15X

4226301/D 11/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS548C26RXXR
厂家：	TEXAS INSTRUMENTS
描述：	采用 5mm x 6mm QFN 封装的 4V 至 16V、35A 同步 D-CAP+™ 降压转换器 \| RXX \| 37 \| -40 to 125 转换器
文件：	总37页 (文件大小：2482K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS548C26RXXR [TI]

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