TPS54900PWRG4 [TI]

SPECIALTY ANALOG CIRCUIT, PDSO16, GREEN, PLASTIC, TSSOP-16;


型号：	TPS54900PWRG4
厂家：	TEXAS INSTRUMENTS
描述：	SPECIALTY ANALOG CIRCUIT, PDSO16, GREEN, PLASTIC, TSSOP-16 光电二极管
文件：	总16页 (文件大小：270K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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SLVS405 − OCTOBER 2001

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FEATURES

DESCRIPTION

Four Independent 100-mA Channels

Programmable Over 4-Wire Serial Port

The TPS54900 four-channel step-down converter uses

voltage mode PWM control to provide four

independently programmable output voltages. Each

regulated channel includes a high-side PMOSFET

Converter Regulation Range:

7.5 V to 13.1 V in 400-mV Steps, Plus

Unregulated Pass-Through Mode to Shunt VIN

to any Output

switch with a typical r

of 0.8 Ω, which makes it

DS(ON)

suitable for high efficiency, low current applications.

Commands sent to the TPS54900 over the four-wire

serial port programs the outputs independently or

globally to supply voltages from 7.5 V to 13.1 V in 0.4-V

increments. When the input voltage is desired at an

output, a bypass mode can be activated which fully

enhances the PMOSFET switch and disables the

switching circuitry of the selected channel.

Internally Compensated PWM Controller and

Integrated PMOS Power Switches

Global and Per Channel Status Available

Through Serial Port

External Synchronization of PWM With

System Clock

Per Channel Current Limit and Global Thermal

Shutdown

The TPS54900 is an ideal companion device to power

THS7102 ADSL line drivers as a part of the AC5 central

office ADSL chipset. With the AC5 chipset controlling

the TPS54900 output voltages, significant power

savings are realized by reducing the excess supply

headroom on a per line basis.

−40°C to 85°C Ambient Temperature Range

APPLICATIONS

ADSL Central Office Line Drivers

Software Line Card Provisioning

EFFICIENCY

DRIVER SUPPLY VOLTAGE

TSSOP (PW) PACKAGE

(TOP VIEW)

100

LX0

LX1

GND

SFS

SDI

FB0

FB1

LX3

LX2

VIN

SDO

SCLK

CBS

FB3

FB2

Efficiency

Driver Current

Driver Supply Voltage − V

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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SLVS405 − OCTOBER 2001

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

‡

Supply voltage range , VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 18 V

‡

Input voltage range , EN, CBS, FB0, FB1, FB2, FB3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VIN + 0.3 V

Input voltage range , SCLK, SDI, SFS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 5 V

Output voltage range‡, LX0, LX1, LX2, LX3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VIN + 0.3 V

‡

Output voltage range , SDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 5 V

Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

Operating junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C

stg

Lead soldering temperature, 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

All voltages values are with respect to device GND terminal.

‡

DISSIPATION RATING TABLE−FREE-AIR TEMPERATURES§

AIR FLOW

(CFM)

≤ 25°C

DERATING FACTOR

= 70°C

T = 85°C

PACKAGE

POWER RATING

ABOVE T = 25°C

POWER RATING POWER RATING

500 mW

5 mW/°C

275 mW 200 mW

Low-K PWB

recommended operating conditions (unless otherwise noted)

MIN

14.25

NOM

MAX UNITS

Supply voltage, VIN

Output current, LX0, LX1, LX2, LX3

Synchronized PWM frequency (see Note 1)

Inductor

100

kHz

µH

µF

552

225

200

−40

250

125

Output capacitor

Operating junction temperature, T

°C

NOTE 1: Synchronized PWM frequency equal to one eighth of SCLK frequency.

electrical characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER

SUPPLY CURRENT

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V disable current

EN > V , all outputs software disabled

1.7

0.7

2.16

(qq)

V quiescent current

EN pin < V

(q)

CUMULATIVE REGULATION

Voltage codes 12.3 V, 12.7 V, 13.1 V

Voltage codes < 12.3 V

−2%

Regulation accuracy

−2.5%

2.5%

OSCILLATOR

Free-run frequency

350

550

450

550

750

kHz

(osc)

Sync frequency range

= SCLK / 8

(sync)

Phase difference after initialization command

(see Note 2)

Phase stagger count

SCLK

UVLO

Undervoltage lockout threshold

UVLO hysteresis

13.5

1.6

(UVLO)

1.3

1.45

hys(UVLO)

NOTE 2: Ensured by design

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electrical characteristics over recommended operating conditions (unless otherwise noted)

(continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ENABLE

Enable threshold

Disable threshold

Bypass threshold

2.0

0.8

Relative to VIN

−1.4

2.0

−0.5

CBS

Logic high threshold

Logic low threshold

0.8

OVERCURRENT LIMIT

Channel settled after change of voltage code or EN

asserted

OCL trip threshold

OCL hiccup time

250

170

450

0.8

750

360

(th−OCL)

= 552 kHz (see Note 2)

(OCL)

(sync)

PMOS FET SWITCH

ON resistance

TRANSITION TIME

Id = 0.1A

1.4

Ω

DS(on)

7.5 < V < 15, time from EN > V to

Channel status word = 00H

Enable delay time

d(EN)

Command from 7.5 V to bypass,

VIN = 15.0 V

Low−high transition time, V

TLH

Command from bypass to 7.5 V,

175 Ω load with VIN = 15.0 V

High−low transition time, V

THL

THERMAL SHUTDOWN

Over temperature trip point, T

Junction temperature exceeds T

150

°C

(OTP)

Hysteresis temperature

(hys)

SERIAL PORT

Setup time, SDIN, SFS

Hold time, SDIN, SFS

Cycle time, SFS

Inputs valid before SCLK falling edge (see Note 2)

Inputs held after SCLK falling edge (see Note 2)

minimum time between commands (see Note 2)

SCLK

c(SFS)

Output low, SDO

= 0.5 mA (see Note 2)

0.4

OL(SDO)

d(SCLK)

lkg

(sink SDO)

Delay time, SDO

SCLK rising to SDO valid (see Note 2)

SDO = 3.3 V (see Note 2)

See Note 2

Off-state leakage current, SDO

Input low voltage

−1

µA

0.7

Input high voltage

See Note 2

2.3

NOTE 2: Ensured by design

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Terminal Functions

TERMINAL

PIN DESCRIPTION

FUNCTIONAL DESCRIPTION

NAME

LX0

NO.

Channel 0 switch output

Channel 1 switch output

Ground

Output to inductor and catch diode

LX1

GND

SFS

SDI

Power and Analog Ground

Frame sync input

Serial data in

Read/write frame start strobe

8 bit address/16−bit data word command input

EN < V : Disable all channels,

EN > V : Enable activates outputs (see text)

Enable

FB0

FB1

FB2

FB3

Channel 0 feedback input

Channel 1 feedback input

Channel 2 feedback input

Channel 3 feedback input

Feedback from L−C filter output

Assigns internal channels to respond to serial address bit ADR2 = 0 when CBS < V

or to ADR2 = 1 when CBS > V

CBS

Channel bank select

SCLK

SDO

VIN

Serial clock input

Serial clock/synchronization signal

Status data output signal, open drain

Chip supply and channel 0−3 switch input

Serial data out

Input supply voltage

Channel 2 switch output

Channel 3 switch output

LX2

Output to inductor and catch diode

LX3

functional block diagram

ILIM

VIN

LX0

Thermal

Shutdown

Bias

UVLO

Shutdown

FB0

LX1

DACV0

DACV1

DACV2

DACV3

ILIM

PWM Ramp

Reset

GND

Bandgap

Reference

Oscillator,

Clock & Ramp

Generator

FB1

LX2

ILIM

PWM

Control

CBS

Programming

Registers

SFS

SCLK

SDI

Serial

Command

Interface

FB2

LX3

DACs

ILIM

SDO

Output Status

FB3

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detailed description

reference system/voltage divider and multiplexer

The reference system consists of a band-gap circuit, four digital to analog converter outputs (DACs), and

smoothing filters. The reference system provides independent set-point voltages to the PWM control loops of

each channel, and are programmed via the 4-wire serial port. Output control of the regulators is provided in 15

steps with 400-mV resolution over a range of 7.5 V to 13.1 V. The DACs can also be programmed to force the

PMOSFETs into the fully on pass-through or bypass mode to pass the input voltage to any output.

UVLO circuit and power-up state

The undervoltage lockout (UVLO) circuit controls device operation when the input voltage is below the UVLO

threshold such as during power up or power down. Hysteresis built in to the UVLO detection circuit reduces

sensitivity to noise and ripple on the power supply inputs to the TPS54900. Prior to reaching the UVLO threshold,

the ramp oscillator is disabled so that no switching occurs in the TPS54900, the PMOS transistors are forced

into the off-state, and the registers and DACs are reset. Once the UVLO threshold is reached, the soft-start

sequence begins. If the input voltage falls below the UVLO threshold after the device is programmed and

operating, all four outputs are disabled, the DACs are set to zero volts, and the programming registers are reset.

Subsequently returning VIN above the UVLO threshold requires reinitialization of the phase stagger and

channel voltage programming

soft-start sequence and voltage transitioning

When the supply voltage exceeds the UVLO threshold, the TPS54900 is ready to be programmed via the serial

interface. As each channel is programmed and enabled with a voltage code, the channel DACs begin stepping

the output up from zero volts to the target voltage in 200-mV increments. If the target voltage is 15 V (i.e.,

pass-through mode) the DAC continues to increment in 200-mV steps between 13.1 V and the fully on state.

When a channel is commanded to transition from one voltage level to another, the output steps up (or down)

to the new level in 200-mV increments. The period between each DAC increment is approximately 87 µs when

the SCLK frequency equals 4.416 MHz. This results in a maximum ramp-up time of 8 ms when stepping from

0 V to 15 V, and a maximum transition time between max and min regulation voltages (7.5 V, 13.1 V) of 4 ms.

The use of small step increments provides a smooth predictable ramp and prevents inadvertent tripping of the

overcurrent limit.

During this transition period, the channel status may be read via the 4-wire serial port using the read protocol.

The data returned is nonzero while channel is transitioning.

oscillator, divider and sync circuit

The TPS54900 has a free-running internal ramp oscillator that operates at a nominal frequency of 450 kHz.

When the 4.416-MHz SCLK signal is present, a synchronous divide-by-eight circuit provides a 552-kHz clock

to synchronize the PWM ramp. The start of the ramp is coincident with every eighth rising edge of SCLK. If the

TPS54900 SCLK pin is driven at a frequency lower than eight times the free-running frequency of the oscillator

(f ), it may result in chaotic operation. Care should be taken to ensure that the minimum frequency at the SCLK

osc

input is 4.4 MHz.

phase stagger circuit

When two TPS54900 devices are used as a pair to operate as an 8-channel unit, the PWM ramps in the two

devices can be phase staggered to reduce input ripple and bypass requirements. The initialization command

forces the PWM ramp of the device with its CBS pin tied low to be staggered by four SCLK cycles compared

to the device with its CBS pin forced to a logic high. Note that this command clears the voltage programming

in both devices and disables the outputs. Voltage programming instructions can be issued immediately following

the initialization command.

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detailed description (continued)

enable (EN)

If the EN pin is held low when the TPS54900 is powered up, the oscillator starts and free-runs. Serial commands

to initialize the PWM clocks and program the output levels are accepted, but the outputs are held off and do not

begin regulating until the EN pin is pulled above V .

If the TPS54900 is first programmed with outputs enabled and then EN is pulled LOW, all outputs are shut off

and all DACs are reset. The EN pin does not affect the oscillator, which continues to run and maintain PWM

phase stagger. The previously programmed channel voltages are also maintained in the registers. If EN is pulled

above V , the TPS54900 channels start up through the soft-start sequence and reach regulation at the

previously programmed target voltages.

Bypass mode may be forced on all outputs by pulling EN above VIN – 0.5 V. When bypass mode is forced, all

four channels step up to VIN in 200-mV increments.

over current protection

During steady state operation, the overcurrent protection threshold is 250 mA minimum, 750 mA maximum,

sampled approximately 500 ns after the start of the switching cycle. When overcurrent is sensed in the

PMOSFET, the output is disabled for a hiccup time of 170 ms to 360 ms (SCLK = 4.416 MHz). In the

pass-through mode, the overcurrent detection remains active and the hiccup behavior is unchanged.

thermal shutdown

Thermal shutdown disables the controller if the junction temperature exceeds 150°C. The hysteresis is 10°C.

This shuts down off the switching circuitry and resets the soft-start circuitry. If the IC returns to normal

temperature, it restarts and returns to the programmed target voltages.

serial control interface timing diagram

SFS

SCLK

SDI

ADR 2

R/W

ADR 1 ADR 0 S3

High−Z

SDO

(Read: R/W = 1)

High−Z

SDO

(Write: R/W = 0)

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serial command bit assignments

SERIAL BIT

POSITION NAME

DESCRIPTION

Set to logic 1 to read from TPS54900, set to logic 0 to write to TPS54900

R/W

Channel bank select, compared to logic state of CBS pin to select between two TPS54900 devices used in an

8-channel configuration

ADR2

ADR1

ADR0

Internal channel select MSB, used with ADR0 to select one of four output channels

Internal channel select LSB, used with ADR1 to select one of four output channels

Device address MSB (S3 = 1 required to address TPS54900)

Device address bit (S2 = 1 required to address TPS54900)

Device address bit (S1 = 1 required to address TPS54900)

Device address LSB (S0 = 1 required to address TPS54900)

Voltage programming MSB

Voltage programming bit

Voltage programming LSB

Channel enable/disable (D3 = 0 enables channel(s))

Global start

Unassigned

Initialize counters

valid commands

WORD

DESCRIPTION

Initialize PWM clocks with phase stagger and disable all channels

Turn on and regulate all channels to voltage code vvvv (see voltage programming code table)

Turn on and regulate channel aaa to voltage code vvvv (see voltage programming code table)

Disable channel aaa

00001111 00001001

0ddd1111 vvvv0100

0aaa1111 vvvv0000

0aaa1111 dddd1000

1aaa1111 dddddddd

Read channel status from channel aaa

NOTE: aaa:

three bit channel address, 0aa: corresponds to CBS pin < V

1aa:

vvvv:

corresponds to CBS > V

voltage programming code

don’t care state

voltage programming codes

VOLTAGE CODE

(D4−D7)

VOLTAGE CODE

(D4−D7)

Figure 1

OUTPUT VOLTAGE

7.5

7.9

8.3

8.7

9.1

9.5

9.9

10.3

10.7

11.1

11.5

11.9

12.3

12.7

13.1

Pass through mode

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channel status read back codes

STATUS BYTE VALUE

(D0−D7)

OUTPUT MEANING

00H

Channel settled to regulation window

Channel not settled or fault condition (see Note 3)

Non-zero

NOTE 3: Fault conditions detected include over current fault on channel addressed and over temperature fault for device (all channels)

serial interface protocol

The serial interface uses serial clock (SCLK), serial frame sync (SFS), serial data in (SDI), bank select inputs,

and outputs device status on serial data out (SDO). SFS and SDI inputs are sampled on the falling edge of

SCLK. An SFS pulse indicates that the bus master is ready to transmit a word, and the bit and frame counters

in the TPS54900 are reset when SFS is high. The first bit (b15) of the 16-bit word is shifted in on the next falling

edge of SCLK. The first eight bits of the word are denoted as the address or command, and the last eight bits

are data. Refer to the table titled Serial Command Bit Assignments.

The command consists of three fields: the R/W bit, channel select bits ADR2−0, and for device select bits

S3−S0. The R/W bit determines whether the data portion of the word is written to the TPS54900 or read from

the TPS54900. The value in the channel select field determines which output channel is to receive programming

data. Channel select bit ADR2 is compared to the logic level on the channel bank select input. This allows two

distinct TPS54900 devices to be addressed as one logical eight-channel unit. The remaining bits ADR1, ADR0

are decoded to select one of the four on chip channels. The third part of the command is the 4-bit device select,

bits S3−S0. The TPS54900 has been assigned a device ID of F for S3−S0. This value must be used to address

TPS54900 devices.

The data field, D7−D0, is used to program output voltage levels and control TPS54900 operation.

pass through mode

The pass through mode may be used to force a channel’s PMOSFETs to remain in the fully enhanced on state.

Use of the pass through mode is desirable under several conditions. First, transmitting high peak-to-peak

voltages requires maximum headroom on the line driver supply. Second, if the load current is too small, the line

ranger circuit is required to operate in discontinuous mode. The output may ring in response to transient

conditions. Low load current conditions may occur if the line driver is idle and the quiescent current has been

reduced to conserve power. If the line must remain ready to return to normal operation, the pass through mode

is appropriate. If the line is unused or can tolerate start up delays, the channel shutdown mode should be

considered to conserve additional power.

channel shut down

A bit value of 1 in bit 3 is used to shut down the addressed channel. Shutting down an unused channel is

recommended when power savings warrant complete power down of a line driver and start-up delays in

returning to normal operation are not critical.

global program

Data bit 2 in the serial word is the global turn-on and regulate signal. It is used to program all outputs to the same

voltage and start them up at the same time.

PWM clock initialization

Data bit 0 is used to initialize the onboard clocks. The signal to initialize the clocks is ANDed with data bit 5 and

cannot be given without powering down the TPS54900 and going through a complete restart sequence.

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status readback

The TPS54900 is designed to monitor its output state and recognize when it has settled into regulation at its

programmed value. The open drain SDO pin reports a channel in a voltage transition or error condition (Channel

Not Ready) by returning a non-zero data value. When SDO returns a value of 00h, the channel is in regulation.

Any of the following conditions cause a channel not ready status to be reported:

Channel disabled

PWM duty factor outside expected range (i.e. 0% or 100% PW)

Channel in overcurrent

Channel transitioning to new target value

Over-temperature shutdown (affects all four channels)

Noise immunity circuits in the fault detector introduce a delay in the reporting of the channel status. For instance,

if a command to transition to a new target voltage is issued, the output voltage may be stable up to 250 µs before

the detection circuit reports that the channel is ready. The minimum recommended status polling interval per

channel is 500 µs.

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APPLICATION INFORMATION

eight channel application circuit schematic

TPS54900

VIN

15V Input

GND

FB3

LX3

C9 C10

OUTPUT_D

OUTPUT_C

GND

FB2

LX2

CBS

FB1

LX1

SFS

SCLK

SDI

SFS

SCLK

SDI

OUTPUT_B

OUTPUT_A

SDO

FB0

LX0

TPS54900

VIN

FB3

LX3

C11

OUTPUT_H

OUTPUT_G

GND

FB2

LX2

CBS

FB1

LX1

SFS

SCLK

SDI

OUTPUT_F

OUTPUT_E

SDO

FB0

LX0

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APPLICATION INFORMATION

component selection

Components were selected to maximize efficiency while maintaining acceptable area, stability, and output

noise. For instance in choosing the free wheeling diodes, both junctions in the SOT−23 package are used in

parallel to save up to 6 mW per channel. The recommended output filter and internal compensation were

selected with the expectation of a 3.3-µH, 15-µF post filter located at the load (line driver supply input). Use of

one or more ceramic capacitors in place of the 10-µF tantalum for the output filter can reduce board area at the

cost of increased noise and reduced stability margin. Inductors with smaller mechanical dimensions than those

from GCI or Bourns, such as the Coilcraft, reduce required board area and decrease conversion efficiency up

to 4%. Use of nonshielded inductors may increase efficiency, but add risk of EMI. System level testing should

be performed in qualifying component and layout decisions.

layout considerations

Two portions of the layout are critical and deserve close attention. First, the high frequency input bypass

capacitors (C10 and C11 in the eight channel application circuit diagram) must be placed as close as possible

and routed directly to the TPS54900 VIN and GND pins to minimize trace inductance.

Second, the free wheeling diodes (D1−8 in the eight channel application circuit diagram) must also be placed

as close as possible and routed directly to the TPS54900 LX_ and GND pins. Placing the diodes on the opposite

side of the board as the TPS54900, immediately opposite the TPS54900, facilitates low impedance routing of

the diodes to the appropriate TPS54900 pins. The EVM layout uses this approach.

www.ti.com

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

SLVS405 − OCTOBER 2001

APPLICATION INFORMATION

block diagram of eight channel AC5 line card with LineRanger option

220 µH

LX3

LX2

LX1

LX0

CBS

10 µF

220 µH

10 µF

+3.3V

+15V

TPS54900

LineRanger

VIN

10 µF

Power Conv.

PT4801

0.1

GND

220 µH

10 µF

SFS

SCLK

SDI

220 µH

10 µF

SDO

+1.5V

+3.3V

Line

TX+−

Pdown

RX+−

Hybrid

Line I/F

TXdata

TX+−

Pdown

RX+−

Hybrid

Line I/F

RXdata

SFS

SCLK

TNETD

7102

TX+−

Pdown

RX+−

Hybrid

Line I/F

TNETD5800

TNETD

7102

Octal

TNETD5080

Octal

Datapump

TX+−

Pdown

RX+−

Hybrid

Line I/F

Codec

Pdown

Clki

TNETD

7102

Clko

TX+−

Pdown

RX+−

Hybrid

Line I/F

SFS

SCLK

SDI

SFS

SCLK

SDI

TNETD

7102

TX+−

Pdown

RX+−

Hybrid

Line I/F

SDO

TNETD

7102

TX+−

Pdown

RX+−

Hybrid

Line I/F

Reset−

Rst

TX+−

Pdown

RX+−

Hybrid

Line I/F

GPIO1..3

220 µH

10 µF

LX3

LX2

LX1

LX0

CBS

+3.3V

220 µH

10 µF

TPS54900

LineRanger

VIN

0.1

GND

220 µH

10 µF

SFS

SCLK

SDI

220 µH

10 µF

SDO

www.ti.com

ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢆ

SLVS405 − OCTOBER 2001

APPLICATION INFORMATION

evaluation circuit

module pin assignments

PIN NO.

FUNCTION

OUTPUT A

GND

PIN NO.

FUNCTION

15 V Input

GND

SFS

SDI

SCLK

SDO

GND

OUTPUT B

OUTPUT C

GND

15 V Input

Channel Bank Select

Enable

GND

N/C

OUTPUT D

15 V Input

application schematic

TPS54900

15V Input

12, 16,

VIN

FB3

17, 22

C5 C6

OUTPUT_D

LX3

2, 5, 8,

9, 10,

GND

18, 21

FB2

OUTPUT_C

LX2

CBS

SFS

SCLK

SDI

FB1

SFS

SCLK

SDI

OUTPUT_B

LX1

SDO

FB0

SDO

OUTPUT_A

LX0

Contact Texas Instruments for additional information on external components recommendations and EVM

availability.

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

21-Mar-2013

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package Qty

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

(1)

(2)

(3)

(4)

TPS54900PW

OBSOLETE

TSSOP

TBD

Call TI

-40 to 85

54900

TPS54900PWG4

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾Only one of markings shown within the brackets will appear on the physical device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

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TPS54900PWRG4 [TI]

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