TPS54972PWPR [TI]
9A 有源总线终端/DDR 存储器直流/直流转换器 | PWP | 28 | -40 to 85;
| 型号： | TPS54972PWPR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 9A 有源总线终端/DDR 存储器直流/直流转换器 | PWP | 28 | -40 to 85 开关 双倍数据速率 控制器 开关式稳压器 开关式控制器 电源电路 存储 转换器 开关式稳压器或控制器 |
| 文件： | 总16页 (文件大小：355K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
6,4 mm x 9,7 mm
TPS54972
SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002
www.ti.com
9-A OUTPUT, 3-V TO 4-V INPUT TRACKING/TERMINATION
SYNCHRONOUS PWM SWITCHER WITH INTEGRATED FETS (SWIFT™)
FEATURES
DESCRIPTION
Tracks Externally Applied Reference Voltage
As a member of the SWIFT™ family of dc/dc regulators,
the TPS54972 low-input voltage high-output current
synchronous-buck PWM converter integrates all
required active components. Included on the substrate
with the listed features are a true, high performance,
voltage error amplifier that enables maximum
performance under transient conditions and flexibility in
choosing the output filter L and C components; an
under-voltage-lockout circuit to prevent start-up until the
input voltage reaches 3.0 V; an internally set slow-start
circuit to limit in-rush currents; and a status output to
indicate valid operating conditions.
•
15-mΩ MOSFET Switches for High Efficiency at
9-A Continuous Output Source or Sink Current
•
6% to 90% VI Output Tracking Range
•
•
•
•
Wide PWM Frequency: Fixed 350 kHz or
Adjustable 280 kHz to 700 kHz
Load Protected by Peak Current Limit and
Thermal Shutdown
Integrated Solution Reduces Board Area and
Total Cost
APPLICATIONS
The TPS54972 is available in a thermally enhanced
28-pin TSSOP (PWP) PowerPAD™ package, which
eliminates bulky heatsinks. TI provides evaluation
modules and the SWIFT designer software tool to aid in
quickly achieving high-performance power supply
designs to meet aggressive equipment development
cycles.
DDR Memory Termination Voltage
•
Active Termination of GTL and SSTL
High-Speed Logic Families
•
DAC Controlled High Current Output Stage
•
Precision Point of Load Power Supply
•
SIMPLIFIED SCHEMATIC
TRANSIENT RESPONSE
Input
V
(DDQ)
VIN
PH
V
(TTQ)
V = 3.3 V
I
TPS54972
V
= 1.25 V
O
BOOT
PGND
REFIN
VBIAS
COMP
VSENSE
AGND
Compensation
Network
2.25 A to 6.75 A
t – Time – µs/div
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products
conformtospecificationsperthetermsofTexasInstrumentsstandardwarranty.
Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
Copyright © 2002, Texas Instruments Incorporated
TPS54972
SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
-40°C to 85°C
REFIN VOLTAGE
PACKAGE
PART NUMBER
(1)
0.2 V to 1.75 V
Plastic HTSSOP (PWP)
TPS54972PWP
(1)
The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54972PWPR). See the application
section of the data sheet for PowerPAD drawing and layout information.
ABSOLUTE MAXIMUM RATINGS
(2)
over operating free-air temperature range unless otherwise noted
TPS54972
-0.3 V to 7 V
-0.3 V to 4.5 V
-0.3 V to 6 V
-0.3 V to 4 V
-0.3 V to 17 V
-0.3 V to 7 V
-0.6 V to 6 V
Internally Limited
6 mA
ENA
VIN
Input voltage range, VI
RT
VSENSE, REFIN
BOOT
VBIAS, COMP, STATUS
PH
Output voltage range, VO
Source current, IO
PH
COMP, VBIAS
PH
16 A
Sink current, IS
COMP
6 mA
ENA, STATUS
AGND to PGND
10 mA
Voltage differential
±0.3 V
Operating virtual junction temperature range, TJ
Storage temperature, Tstg
-40 to 125 °C
-65 to 150 °C
300 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(2)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
Input voltage, VI
3
4
V
Operating junction temperature, TJ
-40
125
°C
2
TPS54972
SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002
www.ti.com
(3) (4)
DISSIPATION RATINGS
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
TA=25°C POWER TA=70°C POWER TA=85°C POWER
PACKAGE
RATING
RATING
3.81 W
1.97 W
RATING
2.77 W
1.43 W
(5)
28 Pin PWP with solder
14.4°C/W
27.9°C/W
6.94 W
3.58 W
28 Pin PWP without solder
ELECTRICAL CHARACTERISTICS
TJ = –40°C to 125°C, VI = 3 V to 4 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY VOLTAGE, VIN
VIN
Input voltage range
Quiescent current
3.0
4.0
15.8
23.5
1.4
V
fs=350 kHz, RT open, PH pin open
fs=500 kHz, RT=100 kΩ, PH pin open
Shutdown, SS/ENA=0 V
11
16
1
I(Q)
mA
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO
2.95
2.8
3.0
V
V
Stop threshold voltage, UVLO
Hysteresis voltage, UVLO
2.7
0.14
0.16
2.5
V
(6)
Rising and falling edge deglitch, UVLO
µs
BIAS VOLTAGE
Output voltage, VBIAS
Output current, VBIAS
I(VBIAS)=0
2.70
2.80
2.90
100
V
(7)
µA
REGULATION
(6) (8)
Line regulation
(6) (8)
Load regulation
IL=4 A, fs=350 kHz, TJ=85°C
0.04
0.03
%/V
%/A
IL=0 A to 8 A, fs=350 kHz, TJ=85°C
OSCILLATOR
Internally set free running frequency
RT open
280
252
460
663
350
280
500
700
0.75
1
420
308
540
762
kHz
kHz
RT=180 kΩ (1% resistor to AGND)
RT=100 kΩ (1% resistor to AGND)
RT=68 kΩ (1% resistor to AGND)
Externally set free running frequency range
(6)
Ramp valley
Ramp amplitude (peak-to-peak)
(6)
V
V
(6)
Minimum controllable on time
(6)
200
ns
Maximum duty cycle
ERROR AMPLIFIER
90%
(6)
Error amplifier open loop voltage gain
Error amplifier unity gain bandwidth
1 kΩ COMP to AGND
90
3
110
5
dB
(6)
Parallel 10 kΩ, 160 pF COMP to AGND
MHz
Error amplifier common mode input voltage
range
(6)
Powered by internal LDO
VSENSE=Vref
0
VBIAS
250
V
Input bias current, VSENSE
60
nA
(3)
(4)
For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
Test board conditions:
3" x 3", 4 layers, thickness: 0.062"
1.5 oz. copper traces located on the top of the PCB
1.5 oz. copper ground plane on the bottom of the PCB
12 thermal vias (see Recommended Land Pattern in applications section of this data sheet)
•
•
•
•
(5)
(6)
(7)
(8)
Maximum power dissipation may be limited by overcurrent protection.
Specified by design
Static resistive loads only
Specified by the circuit used in Figure 8
3
TPS54972
SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
TJ = –40°C to 125°C, VI = 3 V to 4 V (unless otherwise noted)
PARAMETER
Output voltage slew rate (symmetric), COMP
PWM COMPARATOR
TEST CONDITIONS
MIN
TYP
MAX UNIT
1.0
1.4
V/µs
PWM comparator propagation delay time, PWM
comparator input to PH pin (excluding
deadtime)
(6)
10-mV overdrive
70
85
ns
SLOW-START/ENABLE
Enable threshold voltage, ENA
Enable hysteresis voltage, ENA
0.82
2.6
1.20
0.03
2.5
1.40
V
V
(6)
(6)
Falling edge deglitch, ENA
Internal slow-start time
µs
ms
3.35
4.1
STATUS
Output saturation voltage, PWRGD
Leakage current, PWRGD
Isink=2.5 mA
VI=3.6 V
0.18
0.30
1
V
µA
CURRENT LIMIT
Current limit
VI=3.3 V
11
15
100
200
A
Current limit leading edge blanking time
Current limit total response time
ns
ns
THERMAL SHUTDOWN
Thermal shutdown trip point
(9)
(9)
135
150
10
165
°C
°C
Thermal shutdown hysteresis
OUTPUT POWER MOSFETS
(10)
VI=3.0 V
VI=3.6 V
15
14
30
28
rDS(on)
Power MOSFET switches
mΩ
(10)
(9)
(10)
Specified by design
Matched MOSFETs low-side rDS(on) production tested, high-side rDS(on) production tested.
4
TPS54972
SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002
www.ti.com
TPS54972 Externally Composed Pin-Out
28 Pin HTSSOP PowerPAD
(TOP VIEW)
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AGND
VSENSE
COMP
STATUS
BOOT
PH
RT
ENA
REFIN
VBIAS
VIN
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
PGND
2
3
4
5
6
THERMAL
PAD
7
PH
PH
PH
PH
PH
PH
PH
PH
8
9
10
11
12
13
14
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
NO.
AGND
1
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor,
and SYNC pin. Connect PowerPAD connection to AGND.
BOOT
5
Bootstrap output. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
COMP
ENA
3
Error amplifier output. Connect frequency compensation network from COMP to VSENSE
27
Enable input. Logic high enables oscillator, PWM control, and MOSFET driver circuits. Logic low disables operation
and places device in a low quiescent current state.
PGND
15-19 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper
areas to the input and output supply returns, and negative terminals of the input and output capacitors. A single point
connection to AGND is recommended.
PH
RT
6-14
28
26
4
Phase input/output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs.
External reference input. High impedance input to slow-start and error amplifier circuits.
REFIN
STATUS
Open drain output. Asserted low when VIN < UVLO, VBIAS and internal reference are not settled or the internal
shutdown signal is active. Otherwise STATUS is high.
VBIAS
VIN
25
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a
high quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.
20-24 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
device package with a high-quality, low-ESR 10-µF ceramic capacitor.
VSENSE
2
Error amplifier inverting input. Connect to output voltage compensation network/output divider.
5
TPS54972
SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002
www.ti.com
INTERNAL BLOCK DIAGRAM
BIAS
Vbias
VIN
SHUTDOWN
ENABLE
COMPARATOR
REG
TPS54972
UVLO
UVLO
highdr
highin
ENA
VIN
Falling
Edge
Delay
VIN
SAMPLING
LOGIC
VPHASE
Vilim
Rising
Edge
Delay
BOOT
0.8 V
1–4 µs
/T_SHUT
SHUTDOWN
VIN UVLO
COMPARATOR
ILIM
COMPARATOR
FAULT
BIAS UVLO
BG GOOD
VDDQ
VIN
highdr
highin
Delay
SHUTDOWN
REFIN
Rising
Edge
Delay
SHUTDOWN
Vin_uvlo
Reference/DAC
PWM
COMPARATOR
V
Lout
O
TTQ
PH
ERROR
AMPLIFIER
MUX
VSENSE
DEADTIME
R
S
Q
C
SHUTDOWN
PGND
OSC
Ct
STATUS
Iset
FAULT
AGND
RT
RELATED DC/DC PRODUCTS
TPS54372
TPS54672
TPS54872
•
•
•
6
TPS54972
SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002
www.ti.com
TYPICAL CHARACTERISTICS
DRAIN-SOURCE
ON-STATE RESISTANCE
vs
DRAIN-SOURCE
ON-STATE RESISTANCE
vs
INTERNALLY SET
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
25
25
750
V
= 3.6 V
= 9 A
VIN = 3.0 V
I
I
I
= 9 A
O
O
20
20
650
550
15
15
10
10
5
450
RT = Open
350
250
5
0
0
–40
–40
0
25
85
125
0
25
85
125
–40
0
25
85
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 1
Figure 2
Figure 3
EXTERNALLY SET
OSCILLATOR FREQUENCY
vs
DEVICE POWER LOSSES
vs
INTERNAL SLOW-START TIME
vs
LOAD CURRENT
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
8
3.80
800
700
600
V
= 3.3 V
= 125°C
= 700kHz
R
= 68 kΩ
I
T
7
6
5
4
3
2
1
0
T
J
3.65
3.50
f
S
R
= 100 kΩ
3.35
T
500
400
300
200
3.20
3.05
R
T
= 180 kΩ
2.90
2.75
0
2
4
6
8
10 12 14 16
–40
0
25
85
125
–40
0
25
85
125
T
J
– Junction Temperature – °C
I
– Load Current – A
T – Junction Temperature – °C
J
L
Figure 4
Figure 5
Figure 6
ERROR AMPLIFIER
OPEN LOOP RESPONSE
0
140
120
R
C
T
= 10 kΩ,
= 160 pF,
= 25°C
L
–20
L
–40
–60
–80
A
100
80
60
40
20
Phase
Gain
–100
–120
–140
–160
–180
–200
0
–20
1
10 100 1 k 10 k 100 k 1 M 10 M
f – Frequency – Hz
Figure 7
7
TPS54972
SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002
www.ti.com
APPLICATION INFORMATION
Figure 8 shows the schematic diagram for a typical TPS54972 application. The TPS54972 (U1) can provide up to 9 A of
output current at a nominal output voltage of one half of V(DDQ) (typically 1.25 V). For proper operation, the PowerPAD
underneath the integrated circuit TPS54972 is soldered directly to the printed-circuit board.
COMPONENT SELECTION
The values for the components used in this design example were selected for good transient response and small PCB
area. Ceramic dielectric capacitors are utilized in the output filter circuit. A small size, small value output inductor is
also used. Compensation network components are chosen to maximize closed loop bandwidth and provide good
transient response characteristics. Additional design information is available at www.ti.com.
INPUT VOLTAGE
The input voltage is a nominal 3.3 VDC. The input filter (C4) is a 10-µF ceramic capacitor (Taiyo Yuden). Capacitor C8,
a 10-µF ceramic capacitor (Taiyo Yuden) that provides high frequency decoupling of the TPS54972 from the input
supply, must be located as close as possible to the device. Ripple current is carried in both C4 and C8, and the return
path to PGND should avoid the current circulating in the output capacitors C7, C9, C11, and C12.
FEEDBACK CIRCUIT
The values for these components are selected to provide fast transient response times. Components R1, R2, R3, C1,
C2, and C3 form the loop compensation network for the circuit. For this design, a type 3 topology is used. The transfer
function of the feedback network is chosen to provide maximum closed loop gain available with open loop
characteristics of the internal error amplifier. Closed loop cross-over frequency is typically between 70 kHz and 80 kHz
for input from 3 V to 4 V.
OPERATING FREQUENCY
In the application circuit, RT is grounded through a 71.5 kΩ resistor to select the operating frequency of 700 kHz. To
set a different frequency, place a 68-kΩ to 180-kΩ resistor between RT (pin 28) and analog ground or leave RT floating
to select the default of 350 kHz. The resistance can be approximated using the following equation:
500 kHz
Switching Frequency
R +
100 [kW]
(1)
8
TPS54972
SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002
www.ti.com
V
IN
VDDQ
C4
10 µF
U1
TPS54972PWP
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R 6
AGND
RT
C13
0.1 µF
2
3
10 kΩ
VSENSE
ENA
COMP REFIN
STATUS VBIAS
BOOT
PH
4
5
R2
10 kΩ
C2
470 pF
R 7
10 kΩ
C14
0.1 µF
VIN
VIN
VIN
VIN
VIN
6
7
C10
R 5
71.5 kΩ
1 µF
C6
0.047 µF
PH
C1
12 pF
8
9
PH
PH
PH
10
11
12
13
14
PGND
PGND
C8
10 µF
PH
PH
R 3
301 Ω
PGND
PGND
PH
PH
R1
10 kΩ
PGND
PwrPad
C3
470 pF
VTTQ
R4
2.4 Ω
C12
1 µF
C11
22 µF
C9
22 µF
C7
22 µF
L1
0.65 µH
C5
3300 pF
Figure 8. Application Circuit
OUTPUT FILTER
The output filter is composed of a 0.65-µH inductor and three 22-µF capacitors. The inductor is a low dc resistance
(0.017 Ω) type, Pulse PA0277 0.65-µH. The capacitors used are 22 µF, 6.3-V ceramic types with X5R dielectric. An
additional 1-µF output capacitor (C12) is included to suppress high frequencies.
GROUNDING AND POWERPAD LAYOUT
The TPS54972 has two internal grounds (analog and power). Inside the TPS54972, the analog ground ties to all of the
noise sensitive signals, while the power ground ties to the noisier power signals. The PowerPAD must be tied directly
to AGND. Noise injected between the two grounds can degrade the performance of the TPS54972, particularly at
higher output currents. However, ground noise on an analog ground plane can also cause problems with some of the
control and bias signals. For these reasons, separate analog and power ground areas are recommended. The analog
ground area should be tied to the power ground area directly at the IC to reduce noise between the two grounds. The
only components that should tie directly to the power ground area are the input capacitor, the output capacitor, the
input voltage decoupling capacitor, and the PGND pins of the TPS54972. The power ground areas as well as the
PowerPAD mounting area should be tied to any internal ground planes using multiple vias. The layout of the
TPS54972 evaluation module is representative of a recommended layout for a 4-layer board with the two internal
layers representing the system ground plane. Documentation for the TPS54972 evaluation module can be found on the
Texas Instruments web site under the TPS54972 product folder.
9
TPS54972
SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002
www.ti.com
LAYOUT CONSIDERATIONS FOR THERMAL PERFORMANCE
For operation at full rated load current, the analog ground plane must provide adequate heat dissipating area. A 3 inch
by 3 inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient temperature and
airflow. Most applications have larger areas of internal ground plane available, and the PowerPAD should be
connected to the largest area available. Additional areas on the top or bottom layers also help dissipate heat, and any
area available should be used when 9 A or greater operation is desired. Connection from the exposed area of the
PowerPAD to the analog ground plane layer should be made using 0.013 inch diameter vias to avoid solder wicking
through the vias. Eight vias should be in the PowerPAD area with four additional vias located under the device
package. The size of the vias under the package, but not in the exposed thermal pad area, can be increased to 0.018.
Additional vias beyond the ten recommended that enhance thermal performance should be included in areas not under
the device package.
Minimum recommended thermal vias: 8 x
8 PL
4 PL
0.0130
0.0180
.013 dia. inside powerpad area
4 x .018 dia. under device as shown.
Additional .018 dia. vias may be used if
top side Analog Ground ar ea is
extended.
Connect Pin 1 to Analog Ground plane
in this area for optimum performance
0.0150
0.06
0.0339
0.0650
0.0500
0.3478
0.2090
0.0256
0.0500
0.3820
0.0500
0.0650
0.0339
Minimum recommended exposed
copper area for powerpad. 5 mm
stencils may required 10 percent
larger area.
0.1700
0.1340
Minimum recommended top
side Analog Ground area
0.0603
0.0400
Figure 9. Recommended Land Pattern for 28-Pin PWP PowerPAD
10
TPS54972
SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002
www.ti.com
PERFORMANCE GRAPHS
TA = 25°C (unless otherwise noted)
LINE REGULATION
vs
INPUT VOLTAGE
EFFICIENCY
vs
OUTPUT CURRENT
LOAD REGULATION
vs
OUTPUT CURRENT
1.255
1.254
100
95
90
85
80
75
70
65
60
55
50
1.257
f
V
V
= 700 kHz
= 3.3 V
s
f
V
V
= 700 kHz
= 3.3 V
s
I
I
= 1.25 V
O
1.255
1.253
1.253
1.252
= 1.25 V
O
I
= 0 A
O
1.251
1.25
I
= 4.5 A
O
1.251
1.249
I
= 9 A
O
1.249
1.248
1.247
f
V
V
= 700 kHz
= 3.3 V
s
1.247
1.245
I
1.246
1.245
= 1.25 V
O
0
1
2
3
4
5
6
7
8
9
10
3
3.5
– Input Voltage – V
4
0
2
4
6
8
10
V
I
– Output Current – A
I
– Output Current – A
I
O
O
Figure 10
Figure 11
Figure 12
OUTPUT RIPPLE VOLTAGE
TRANSIENT RESPONSE
f
I
V
V
= 700 kHz,
=9 A,
= 3.3 V,
SLOW-START TIMING
s
O
V
V
= 3.3 V
= 1.25 V
I
V
V
= 3.3 V
I
I
O
= 1.25 V
O
= 1.25 V
O
2.25 A to 6.75 A
t – Time – 1 µs/div
t – Time – 2.5 µs/div
t – Time – µs/div
Figure 13
Figure 14
Figure 15
AMBIENT TEMPERATURE
vs
OUTPUT CURRENT1
125
T
= 125°C,
= 700 kHz,
J
SOURCE-SINK
TRANSIENT RESPONSE
115
105
95
f
s
V = 5 V,
V
I
= 1.25 V
V = 3.3 V
O
I
V
= 1.25 V
O
85
75
65
55
45
35
25
0
2
4
6
8
10 12 14 16
I
– Output Current – A
O
1. Safe operating area is applicable to the test board conditions
listed in the dissipation rating table section of this data sheet.
t – Time – 2.5 µs/div
Figure 16
Figure 17
11
TPS54972
SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002
www.ti.com
DETAILED DESCRIPTION
UNDERVOLTAGE LOCKOUT (UVLO)
The TPS54972 incorporates an undervoltage lockout circuit to keep the device disabled when the input voltage (VIN) is
insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO threshold voltage
of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device operates until VIN falls below
the nominal UVLO stop threshold of 2.80 V. Hysteresis in the UVLO comparator, and a 2.5-µs rising and falling edge
deglitch circuit reduce the likelihood of shutting the device down due to noise on VIN.
ENABLE (ENA)
The enable pin, ENA, provides a digital control to enable or disable (shut down) the TPS54972. An input voltage of
1.4V or greater ensures the TPS54972 is enabled. An input of 0.9 V or less ensures the device operation is disabled.
These are not standard logic thresholds, even though they are compatible with TTL outputs.
When ENA is low, the oscillator, slow-start, PWM control and MOSFET drivers are disabled and held in an initial state
ready for device start-up. On an ENA transition from low to high, device start-up begins with the output starting from
0V.
SLOW-START
The slow-start circuit provides start-up slope control control of the output voltage to limit in-rush currents. The nominal
internal slow-start rate is 0.25 V/ms with the minimum rate being 0.35 V/ms. When the voltage on REFIN rises faster
than the internal slope or is present when device operation is enabled, the output rises at the internal rate. If the
reference voltage on REFIN rises more slowly, then the output rises at approximately the same rate as REFIN.
VBIAS REGULATOR (VBIAS)
The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in junction
temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the VBIAS pin. X7R or
X5R grade dielectrics are recommended because their values are more stable over temperature. The bypass capacitor
should be placed close to the VBIAS pin and returned to AGND. External loading on VBIAS is allowed, with the caution
that internal circuits require a minimum VBIAS of 2.70 V, and external loads on VBIAS with ac or digital switching noise
may degrade performance. The VBIAS pin may be useful as a reference voltage for external circuits.
VOLTAGE REFERENCE
The REFIN pin provides an input for a user supplied tracking voltage. Typically this input is one half of V(DDQ). The input
range for this external reference is 0.2 V to 1.75 V. Above this level, the internal bandgap reference overrides the
externally supplied reference voltage.
OSCILLATOR AND PWM RAMP
The oscillator frequency can be set to an internally fixed value of 350 kHz by leaving the RT pin unconnected (floating).
If a different frequency of operation is required for the application, the oscillator frequency can be externally adjusted
from 280 to 700 kHz by connecting a resistor to the RT pin to ground. The switching frequency is approximated by the
following equation, where R is the resistance from RT to AGND:
100 kW
Switching Frequency +
500 [kHz]
R
The following table summarizes the frequency selection configurations:
SWITCHING FREQUENCY
350 kHz, internally set
RT PIN
Float
Externally set 280 kHz to 700 kHz
R=68 kΩ to 180 kΩ
ERROR AMPLIFIER
The high performance, wide bandwidth, voltage error amplifier sets the TPS54972 apart from most dc/dc converters.
The user has a wide range of output L and C filter components to suit the particular application needs. Type 2 or type 3
compensation can be employed using external compensation components.
12
TPS54972
SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002
www.ti.com
PWM CONTROL
Signals from the error amplifier output, oscillator and current limit circuit are processed by the PWM control logic.
Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM latch, and
portions of the adaptive dead-time and control logic block. During steady-state operation below the current limit
threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch. Once the
PWM latch is set, the low-side FET remains on for a minimum duration set by the oscillator pulse width. During this
period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to charge back up, the low-side
FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the error amplifier output voltage, the
PWM comparator resets the latch, thus turning off the high-side FET and turning on the low-side FET. The low-side
FET remains on until the next oscillator pulse discharges the PWM ramp.
During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the PWM
peak voltage. If the error amplifier is high, the PWM latch is never reset and the high-side FET remains on until the
oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET on. The device operates at
its maximum duty cycle until the output voltage rises to the regulation set-point, setting VSENSE to approximately the
same voltage as VREF. If the error amplifier output is low, the PWM latch is continually reset, and the high-side FET
does not turn on. The low-side FET remains on until the VSENSE voltage decreases to a range that allows the PWM
comparator to change states. The TPS54972 is capable of sinking current continuously until the output reaches the
regulation set-point.
If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds the
error amplifier output. The high-side FET turns off, and the low-side FET turns on to decrease the energy in the output
inductor and consequently the output current. This process is repeated each cycle in which the current limit comparator
is tripped.
DEAD-TIME CONTROL AND MOSFET DRIVERS
Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs during the
switching transitions by actively controlling the turnon times of the MOSFET drivers. The high-side driver does not turn
on until the gate drive voltage to the low-side FET is below 2 V, while the low-side driver does not turn on until the
voltage at the gate of the high-side MOSFET is below 2 V. The high-side and low-side drivers are designed with
300-mA source and sink capability to quickly drive the power MOSFETs gates. The low-side driver is supplied from
VIN, while the high-side drive is supplied from the BOOT pin. A bootstrap circuit uses an external BOOT capacitor and
an internal 2.5-Ω. bootstrap switch connected between the VIN and BOOT pins. The integrated bootstrap switch
improves drive efficiency and reduces external component count.
OVERCURRENT PROTECTION
The cycle by cycle current limiting is achieved by sensing the current flowing through the high-side MOSFET and
comparing this signal to a preset overcurrent threshold. The high side MOSFET is turned off within 200 ns of reaching
the current limit threshold. A 100 ns leading edge blanking circuit prevents false tripping of the current limit when the
high-side switch is turning on. Current limit detection occurs only when current flows from VIN to PH when sourcing
current to the output filter. Load protection during current sink operation is provided by thermal shutdown.
THERMAL SHUTDOWN
The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from shutdown automatically when the junction temperature
decreases to 10°C below the thermal shutdown trip point, and starts up under control of the slow-start circuit.
Thermal shutdown provides protection when an overload condition is sustained for several milliseconds. With a
persistent fault condition, the device cycles continuously; starting up by control of the soft-start circuit, heating up due
to the fault condition, and then shutting down upon reaching the thermal limit trip point. This sequence repeats until the
fault condition is removed.
13
TPS54972
SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002
www.ti.com
STATUS
The status pin is an open drain output that indicates when internal conditions are sufficient for proper operation.
STATUS can be coupled back to a system controller or monitor circuit to indicate that the termination or tracking
regulator is ready for start-up. STATUS is high impedance when the TPS54972 is operating or ready to be enabled.
STATUS is active low if any of the following occur:
VIN < UVLO threshold
•
•
VBIAS or internal reference have not settled.
•
Thermal shutdown is active.
14
TPS54972
SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002
www.ti.com
MECHANICAL DATA
PWR (R-PDSO-G**)
PowerPAD™ PLASTIC SMALL-OUTLINE
20 PINS SHOWN
0,30
0,19
M
0,65
20
0,10
11
Thermal Pad
(See Note D)
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
1
10
0,25
A
0°–ā8°
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
28
DIM
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4073225/F 10/98
(A) All linear dimensions are in millimeters.
(B) This drawing is subject to change without notice.
(C) Body dimensions do not include mold flash or protrusions.
(D) The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is
electrically and thermally connected to the backside of the die and possibly selected leads.
(E) Falls within JEDEC MO-153
15
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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Copyright 2002, Texas Instruments Incorporated
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