TPS5625_技术文档

TPS5615, TPS5618, TPS5625, TPS5633

SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER

SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998

PWP PACKAGE

(TOP VIEW)

±1% Reference Over Full Operating

Temperature Range

Synchronous Rectifier Driver for >90%

Efficiency

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

IOUT

AGND2

OCP

VHYST

VREFB

VSENSE

ANAGND

SLOWST

BIAS

LODRV

LOHIB

DRVGND

LOWDR

DRV

PWRGD

NC

2

3

Fixed Output Voltage Options of 1.5 V,

1.8 V, 2.5 V, and 3.3 V

4

5

User-Selectable Hysteretic-Type Control

Low Supply Current . . . 3 mA Typ

6

NC

7

INHIBIT

IOUTLO

LOSENSE

HISENSE

BOOTLO

HIGHDR

BOOT

8

11.4-V to 13-V Input Voltage Range, V

Power Good Output

CC

9

10

11

12

13

14

Programmable Soft-Start

Overvoltage/Overcurrent Protection

Active Deadtime Control

V

CC

description

NC – No internal connection

The TPS5615 family of synchronous-buck regulator controllers provides an accurate supply voltage to DSPs.

The output voltage is internally set by a resistive divider with an accuracy of 1% over the full operating

temperature range. A hysteretic controller with user-selectable hysteresis is used to dramatically reduce

overshoot and undershoot caused by load transients. Propagation delay from the comparator inputs to the

output drivers is less than 250 ns. Overcurrent shutdown and crossover protection for the output drivers

combine to eliminate destructive faults in the output FETs. PWRGD monitors the output voltage and pulls the

open-collectoroutputlowwhentheoutputdropsbelow93%ofthenominaloutputvoltage. Anovervoltagecircuit

disables the output drivers if the output voltage rises 15% above the nominal value. The inhibit pin can be used

to control power sequencing. Inhibit and undervoltage lockout assures that the 12-V supply voltage and system

supply voltage (5 V or 3.3 V) are within proper operating limits before the controller starts. The output driver

circuits include 2-A drivers with internal 8-V gate-voltage regulators that can easily provide sufficient power for

today’s high-powered DSPs. The high-side driver can be configured either as a ground-referenced driver or as

afloatingbootstrapdriver. TheTPS5615familyisavailableina28-pinTSSOPPowerPad package. Itoperates

over a junction temperature range of 0°C to 125°C.

AVAILABLE OPTIONS

PACKAGE

†

T

J

OUTPUT VOLTAGE

TSSOP

(PWP)

1.5 V

1.8 V

2.5 V

3.3 V

TPS5615PWP

TPS5618PWP

TPS5625PWP

TPS5633PWP

0°C to 125°C

†

The PWP package is availble taped and reeled. Add R suffix to

device type (e.g., TPS5615PWPR).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5615, TPS5618, TPS5625, TPS5633

SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER

SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998

functional block diagram

15

7

28

20

19

21

IOUTLO HISENSE

ANAGND

PWRGD LOSENSE

V

CC

V

CC

2 V

+

2X

22

INHIBIT

1

_

IOUT

UVLO

Shutdown

10 V

Q

S

R

V

CC

Fault

Rising

Edge

Delay

3

OCP

_

Deglitch

+

HIGHDR

100mV

HIGHIN

VPGD

0.93 VREF

V

CC

Analog

Bias

VOVP

1.15 VREF

VSENSE

I

PREREG

Analog

Bias

VREFB

9

BIAS

Slowstart

Comparator

8

14

DRV

DRV REG

SLOWST

5

+

_

Shutdown

16

BOOT

17

HIGHDR

_

Shutdown

CM Filters

18

BOOTLO

+

Bandgap

VREF

_

+

_

Hysteresis

Comparator

13

LOWDR

+

12

DRVGND

Hysteresis

Setting

I

VREFB

2

5

4

6

11

LOHIB

10

LODRV

AGND2

VREFB

VHYST

VSENSE

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5615, TPS5618, TPS5625, TPS5633

SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER

SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998

Terminal Functions

TERMINAL

NAME

AGND2

I/O

DESCRIPTION

NO.

2

Analog ground (must be connected).

ANAGND

BIAS

7

Analog ground

9

Analog bias pin. A 1-µF capacitor should be connected from BIAS to ANAGND.

Bootstrap. A 1-µF capacitor should be connected from BOOT to BOOTLO.

BOOT

16

18

BOOTLO

Bootstrap low. Connect to the junction of the high-side and low-side FETs for floating drive configuration.

Connect to PGND for ground-reference drive configuration.

DRV

14

12

17

19

Drive regulator for the FET drivers. A 1-µF capacitor should be connected from DRV to DRVGND.

Drive ground. Ground for FET drivers. Connect to FET PWRGND.

DRVGND

HIGHDR

HISENSE

High drive. Output drive to high-side power switching FETs.

High current sense. For current sensing across high-side FETs, connect to the drain of the high-side FETs;

for optional current sensing scheme, connect to power supply side of current-sense resistor placed in series

with high-side FET drain.

INHIBIT

IOUT

22

1

Disables the drive signals to the MOSFET drivers. Also serves as UVLO for system logic supply (3.3 V or

5 V). An external pull-up resistor should be connected to system-logic supply.

Current out. Output voltage on this terminal is proportional to the load current as measured across the

R

ofthehighsideFET. Thevoltageonthisterminalequals2×R

×IOUT. Inapplicationswhere

DS(ON)

ds(on)

very accurate current-sensing is required, a sense resistor should be connected between the input supply

and the drain of the high-side FETs.

IOUTLO

21

Current sense low output. This is the voltage on the LOSENSE terminal when the high-side FETs are on.

A ceramic capacitor (between 0.033 µF and 0.1 µF) should be connected from IOUTLO to HISENSE to hold

the sensed voltage.

LODRV

LOHIB

10

11

Low drive enable. Normally tied to 5 V. To configure the low-side FET as a crowbar, pull LODRV low.

Low side inhibit. Connect to the junction of the high- and low-side FETs to control the anti-cross-

conduction and eliminate shoot-through current. Disabled when configured in crowbar mode.

LOSENSE

20

Low current sense. For current sensing across high-side FETs, connect to the source of the high-side FETs;

for optional current sensing scheme, connect to high-side FET drain side of current-sense resistor placed

in series with high-side FET drain.

LOWDR

NC

13

23–27

3

Low drive. Output drive to synchronous rectifier FETs.

No connect

OCP

Over current protection. Current limit trip point is set with a resistor divider between IOUT and ANAGND.

PWRGD

28

Power good. PWRGD signal goes high when output voltage is within 7% of voltage setpoint. Open-drain

output.

SLOWST

VHYST

8

4

Slow Start (soft start). A capacitor form SLOWST to ANAGND sets the slowstart time.

Slowstart current = I

/5

VREFB

Hysteresis set input. The hysteresis is set with a resistor divider from VREFB to ANAGND.

Hysteresis = 2 × (VREFB – VHYST)

V

15

5

12-V supply. A 1-µF capacitor should be connected from V

to DRVGND.

CC

VREFB

Buffered reference voltage

VSENSE

6

VoltagesenseInput. Tobeconnectedfromconverteroutputvoltagebustosenseandcontroloutputvoltage.

It is recommended that a RC low-pass filter be connected at this pin to filter noise.

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5615, TPS5618, TPS5625, TPS5633

SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER

SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998

detailed description

Vref

The reference voltage section consists of a temperature-compensated bandgap reference and a resistive

divider that sets the output voltage option. The output voltage, VREF, is within 1% of the nominal setting over

the full junction temperature range of 0°C to 125°C, and a V

supply voltage range of 11.4 V to 12.6 V. The

CC

output of the reference network is indirectly brought out through a buffer to the VREFB pin. The voltage on this

pin will be within 2% of VREF. It is not recommended to drive loads with VREFB, other than setting the hysteresis

of the hysteretic comparator, because the current drawn from VREFB sets the charging current for the slowstart

capacitor. Refer to the slowstart section for additional information.

hysteretic comparator

The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is

set by 2 external resistors and is centered on VREF. The 2 external resistors form a resistor divider from VREFB

to ANAGND, with the output voltage connecting to the VHYST pin. The hysteresis of the propagation delay from

the comparator inputs to the driver outputs is 250 ns (maximum). The maximum hysteresis setting is 60 mV.

I

= 0.5 µA

O(MAX)

VREFB

R2

V

H

R1

2

VREFB–V

H

VHYST

Where

V

2

H = desired hysteresis voltage

VREFB

TPS56xx

R2

V

H

Figure 1. Setting the Hysteresis Voltage

low-side driver

The low-side driver is designed to drive low-R

n-channel MOSFETs. The current rating of the driver is 2

ds(on)

A, source or sink. The bias to the low-side driver is internally connected to the DRV regulator.

high-side driver

The high-side driver is designed to drive low-R

n-channel MOSFETs. The current rating of the driver is 2

ds(on)

A, source or sink. The high-side driver can be configured either as a ground-referenced driver or as a floating

bootstrap driver. When configured as a floating driver, the bias voltage to the driver is developed from the DRV

regulator. The internal bootstrap diode, connected between the DRV and BOOT pins, is a Schottky for improved

drive efficiency. The maximum voltage that can be applied between BOOT and DRVGND is 30 V. The driver

can be referenced to ground by connecting BOOTLO to DRVGND, and connecting BOOT to eitherDRV or V

.

CC

deadtime control

Deadtime control prevents shoot-through current from flowing through the main power FETs during switching

transitions by actively controlling the turn-on times of the MOSFET drivers. The high-side driver is not allowed

to turn on until the gate-drive voltage to the low-side FET is below 2 V; the low-side driver is not allowed to turn

on until the voltage at the junction of the 2 FETs (Vphase) is below 2 V.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5615, TPS5618, TPS5625, TPS5633

SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER

SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998

detailed description (continued)

current sensing

Current sensing is achieved by sampling and holding the voltage across the high-side power FET while the

high-side FET is on. The sampling network consists of an internal 60-Ω switch and an external ceramic hold

capacitor. Recommended value of the hold capacitor is between 0.033 µF and 0.1 µF. The actual value should

give a time constant (60 Ω × C ) greater than the FET on time. Internal logic controls the turn-on and turn-off

H

of the sample/hold switch such that the switch does not turn on until the Vphase voltage transitions high, and

the switch turns off when the input to the high-side driver goes low. Thus sampling will occur only when the high

side FET is conducting current. The voltage on the IOUT pin equals 2 times the sensed high-side voltage. In

applications where a higher accuracy in current-sensing is required, a sense resistor can be placed in series

with the high-side FET and the voltage across the sense resistor can be sampled by the current sensing circuit.

See Figures 2 and 3.

overcurrent protection

The overcurrent protection (OCP) circuit monitors the current through the high-side FET. The overcurrent

threshold is adjustable with an external resistor divider between IOUT and ANAGND, with the divider voltage

connected to OCP. If the voltage on OCP (V ) exceeds 100 mV, then a fault latch is set and the output drivers

S

are turned off. The latch will remain set until V

goes below the undervoltage lockout value. A 3-µs deglitch

CC

timer is included for noise immunity. The OCP circuit is also designed to protect the high-side power FET against

a short-to-ground fault on the terminal common to both power FETs (Vphase).

R

S

V

CC

V

P

V

CC

V

P

C

H

V

S

V

S

2 * V

S

IOUT

OCP

IOUT

OCP

R1

R2

R1

R2

TPS56xx

R2

V –0.05

S

0.05

R2

V –0.05

S

0.05

R1

Figure 3. Precision OCP Using External Resistor

Figure 2. OCP Using FET ON-Resistance

inhibit

INHIBIT is a TTL-compatible digital input used to enable the controller. When INHIBIT is low, the output drivers

are low and the slowstart capacitor is discharged. When INHIBIT goes high, the short across the slowstart

capacitor is released and normal converter operation begins. When the system-logic supply is connected to

INHIBIT, it also controls power sequencing by locking out controller operation until the system-logic supply

exceeds the input threshold voltage of the inhibit circuit. Thus the 12-V supply and the system-logic supply

(either 5 V or 3.3 V) must be above UVLO thresholds before the controller is allowed to start up. The INHIBIT

comparator start threshold is 2.1 V and the hysteresis is 100 mV.

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5615, TPS5618, TPS5625, TPS5633

SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER

SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998

detailed description (continued)

V

CC

To Power Stage

R1

SHUTDOWN

INHIBIT

R2

TPS56xx

2.1 R1

–2.1

V

TRIP

Where

V

TRIP

=desired V

trip voltage

SUPPLY

Figure 4. Input Undervoltage Lockout Circuit Using INHIBIT

undervoltage lockout (UVLO)

V

CC

The undervoltage lockout circuit disables the controller while the V

supply is below the 10-V start threshold

CC

during power-up. While the controller is disabled, the output drivers will be low and the slowstart capacitor will

be shorted. When V exceeds the start threshold, the short across the slowstart capacitor is released and

CC

normal converter operation begins. There is a 2-V hysteresis in the undervoltage lockout circuit for noise

immunity.

slowstart

The slowstart circuit controls the rate at which V powers up. A capacitor is connected between SLOWSST and

O

ANAGND and is charged by an internal current source. The slowstart charging current is determined by the

following equation:

I(VREFB)

I

SLOWSTART

5

where I(VREFB) is the current flowing out of VREFB. It is recommended that no additional loads be connected

to VREFB, other than the resistor divider for setting the hysteresis voltage. The maximum current that can be

sourced by the VREFB circuit is 500 µA. The slowstart time is set by:

t

5

C

R

SLOWSTART

SLOWST

VREFB

where R

is the total external resistance from VREFB to ANAGND.

VREFB

power good

The power good circuit monitors for an undervoltage condition on V . If V is 7% below V , then PWRGD

REF

O

is pulled low. PWRGD is an open-drain output.

overvoltage protection

The overvoltage protection (OVP) circuit monitors V for an overvoltage condition. If V is 15% above V ,

REF

O

then a fault latch is set and both output drivers are turned off. The latch will remain set until V goes below the

CC

undervoltage lockout value. A 3-µs deglitch timer is included for noise immunity. Refer to the LODRV section

for information on how to protect the load against overvoltages due to a shorted fault across the high-side power

FET.

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5615, TPS5618, TPS5625, TPS5633

SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER

SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998

detailed description (continued)

drive regulator

The drive regulator provides drive voltage to the output drivers. The minimum drive voltage is 7 V. The minimum

short circuit current is 100 mA. Connect a 1-µF ceramic capacitor from DRV to DRVGND.

LODRV

The LODRV circuit is designed to protect the load against overvoltages that occur if the high-side FETs become

shorted. External components to sense an overvoltage condition are required to use this feature. When an

overvoltage fault occurs, LODRV is pulled low and the low-side FET will be turned on, overriding all control

signals inside the TPS56xx controller. The crowbar action will short the system-logic supply to ground through

the faulted high-side FETs and the low-side FETs. A fuse, in series with V , should be added to disconnect the

IN

short circuit.

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 14 V

CC

Input voltage range: BOOT to DRVGND (high-side driver ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 30 V

BOOT to HIGHDRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 15 V

BOOT to BOOTLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 15 V

INHIBIT, LODRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 7.3 V

PWRGD, OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 7 V

LOHIB, LOSENSE, IOUTLO, HISENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 14 V

VSENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 5 V

Voltage difference between ANAGND and DRVGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V

Output current, VREFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 mA

Short circuit duration, DRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous

Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

Operating junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 125°C

J

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: Unless otherwise specified, all voltages are with respect to ANAGND.

DISSIPATION RATING TABLE

T

≤ 25°C

DERATING FACTOR

T

= 70°C

T = 85°C

A

PACKAGE

POWER RATING

ABOVE T = 25°C

POWER RATING POWER RATING

A

PWP

1150 mW

11.5 mW/°C

630 mW 460 mW

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5615, TPS5618, TPS5625, TPS5633

SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER

SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998

recommended operating conditions

MIN

11.4

0

MAX

13

UNIT

Supply voltage, V

V

CC

BOOT to DRVGND

28

BOOT to BOOTLO

0

13

Input voltage

INHIBIT, LODRV, PWRGD, OCP

LOHIB, LOSENSE, IOUTLO, HISENSE

VSENSE

0

6

V

0

13

0

4.5

±0.2

0.4

Voltage difference between ANAGND and DRVGND

0

V

†

Output current, VREFB

0

mA

†

Not recommended to load VREFB other than to set hysteresis since I

VREFB

sets slowstart time.

electrical characteristics over recommended operating virtual junction temperature range,

= 12 V, I = 0 A (unless otherwise noted)

V

CC

DRV

reference

PARAMETER

TPS5615

TEST CONDITIONS

MIN

1.485

1.782

2.475

3.267

TYP

MAX

1.515

1.818

2.525

3.333

UNIT

TPS5618

TPS5625

TPS5633

Reference

voltage

VREF

V

CC

= 11.4 V to 12.6 V

V

VREFB Output voltage

I

= 50 µA

VREF–2% VREF VREF+2%

2

V

REFB

VREFB Output regulation

10 µA ≤ I ≤ 500 µA

mV

O

power good

PARAMETER

Undervoltage trip threshold

TEST CONDITIONS

MIN

TYP

93

0.5

1

MAX

UNIT

90

95 %VREF

Low-level output voltage, PWRGD

High-level input current, PWRGD

Hysteresis

I

O

= 5 mA

0.75

V

= 6 V

µA

mV

PWRGD

10

overvoltage protection

PARAMETER

Overvoltage trip threshold

TEST CONDITIONS

MIN

TYP

115

10

MAX

UNIT

112

120 %VREF

mV

Hysteresis

See Note 2

NOTE 2: Ensured by design, not tested.

slowstart

PARAMETER

TEST CONDITIONS

MIN

TYP

13

3

MAX

UNIT

µA

Charge current

V

= 0.5 V,

I

= 65 µA

10.4

15.6

SLOWST

VREFB

Discharge current

= 1 V

mA

mV

nA

SOFTST

Comparator input offset voltage

Comparator input bias current

Hysteresis

10

100

7.5

See Note 2

10

–7.5

mV

NOTE 2: Ensured by design, not tested.

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5615, TPS5618, TPS5625, TPS5633

SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER

SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998

electrical characteristics over recommended operating virtual junction temperature range,

V

= 12 V, I

= 0 A (unless otherwise noted) (continued)

CC

DRV

inhibit

PARAMETER

TEST CONDITIONS

MIN

1.9

TYP

2.1

MAX

2.35

0.12

UNIT

Startup threshold

Hysteresis

V

0.08

1.85

0.1

Stop threshold

input undervoltage lockout

PARAMETER

MIN

9.25

1.9

TYP

MAX

UNIT

Startup threshold

Hysteresis

10 10.75

V

2

2.2

Stop threshold

7.5

hysteretic comparator

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

2.5

UNIT

mV

nA

Input offset voltage

–2.5

Input bias current

See Note 2

500

3.5

Hysteresis accuracy

V

– V

= 15 mV, (hysteresis window = 30 mV)

= 30 mV

–3.5

mV

REFB

HYST

Maximum hysteresis setting

NOTE 2: Ensured by design, not tested.

V

60

overcurrent protection

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

110

UNIT

mV

OCP trip threshold

Input bias current

90

100

nA

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5615, TPS5618, TPS5625, TPS5633

SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER

SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998

electrical characteristics over recommended operating virtual junction temperature range,

V

= 12 V, I

= 0 A (unless otherwise noted) (continued)

CC

DRV

high-side VDS sensing

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Gain

2

V/V

V

= 12 V,

V

= 11.9 V

HISENSE

Differential input to Vds sensing amp = 100 mV

LOSENSE

Initial accuracy

IOUTLO sink current

IOUT source current

194

206

250

mV

nA

µA

5 V ≤ V

≤ 13 V

IOUTLO

= 0.5 V,

V

= 12 V,

IOUT

IOUTLO

HISENSE

500

50

= 11.5 V

V

= 0.05 V,

IOUT

IOUTLO

HISENSE

IOUT sink current

µA

= 12 V

V

= 11 V

= 4.5 V

= 3 V

0

2

1.5

HISENSE

Output voltage swing

R

= 10 kΩ

V

IOUT

0

0.75

LOSENSE high-level input voltage

LOSENSE low-level input voltage

= 4.5 V,

See Note 2

2.85

V

2.4

80

11.4 V ≤ V

LOSENSE connected to HISENSE,

≤ 12.6 V,

HISENSE

50

62

60

85

V

– V

= 0.15 V

HISENSE

4.5 V ≤ V

IOUTLO

≤ 5.5 V,

HISENSE

LOSENSE connected to HISENSE,

Sample/hold resistance

Ω

123

144

V

– V

= 0.15 V

HISENSE

IOUTLO

3 V ≤ V

≤ 3.6 V,

HISENSE

LOSENSE connected to HISENSE,

67

69

95

75

V

– V

= 0.15 V

HISENSE

IOUTLO

V

= 12.6 V to 3 V,

HISENSE

CMRR

dB

– V

= 100 mV

OUTLO

NOTE 2: Ensured by design, not tested.

deadtime

PARAMETER

TEST CONDITIONS

MIN

2.4

3

TYP

MAX

UNIT

LOHIB

See Note 2

High-level input voltage

LODR

V

LOHIB

1.4

1.7

Low-level input voltage

LODR

V

NOTE 2: Ensured by design, not tested.

LODRV

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

High-level input voltage

LODRV

1.85

Low-level input voltage

0.95

V

drive regulator

PARAMETER

MIN

TYP

MAX

UNIT

V

Output voltage

11.4 V ≤ VCC ≤ 12.6 V,

1 mA ≤ I ≤ 500 mA

I

= 50 mA

7

9

DRV

Output regulation

Short-circuit current

100

mV

mA

DRV

100

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SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER

SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998

electrical characteristics over recommended operating virtual junction temperature range,

V

= 12 V, I

= 0 A (unless otherwise noted) (continued)

CC

DRV

bias regulator

PARAMETER

Output voltage

TEST CONDITIONS

MIN

TYP

MAX

UNIT

11.4 V ≤ VCC ≤ 12.6 V, See Note 3

6

V

NOTE 3: The bias regulator is designed to provide a quiet bias supply for the TPS56xx controller. External loads should not be driven by the bias

regulator.

output drivers

PARAMETER (see Note 4)

TEST CONDITIONS

Duty cycle < 2%, < 100 µs, T = 125°C,

MIN

TYP

MAX

UNIT

t

High-side sink

2

pw

= 6.5 V,

J

V

– V

BOOT

BOOTLO

= 1.5 V (SRC) or 5 V (sink), See Note 2

High-side source

Low-side sink

2

HIGHDR

Peak output current

Output resistance

A

Duty cycle < 2%,

= 6.5 V,

t

< 100 µs, T = 125°C,

pw J

V

= 1.5 V (SRC) or 5 V

LOWDR

DRV

(sink), See Note 2

Low-side source

High-side sink

High-side source

Low-side sink

3

45

T = 125°C, V

– V

= 6.5 V,

BOOTLO

J

BOOT

= 1.5 V (SRC) or 5 V (sink)

V

HIGHDR

Ω

5.7

45

T = 125°C, V

= 6.5 V,

J

DRV

= 1.5 V (SRC) or 5 V (sink)

V

LOWDR

Low-side source

NOTES: 2. Ensured by design, not tested.

4. The pull up/down circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the

combined current from the bipolar and MOSFET transistors. The output resistance is the R of the MOSFET transistor when

DS(ON)

the voltage on the driver output is less than the saturation voltage of the bipolar transistor.

supply current

PARAMETER

supply voltage range

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

11.4

12

13

V

CC

V

= 5 V,

= 0 V,

V

> 10.75 V at startup,

INHIBIT

BOOTLO

CC

See Note 2

3

10

V

quiescent current

mA

V

C

= 5 V,

= 0 V,

= 50 pF,

V

C

> 10.75 V at startup,

INHIBIT

BOOTLO

CC

= 50 pF,

5

HIGHDR

f = 200 kHz

LOWDR

swx

< 9.25 V at startup,

V

= 0 V or V

INHIBIT

BOOT

CC

10

µA

= 13 V,

V

= 0 V

BOOTLO

High-side drive regulator quiescent current

NOTE 2: Ensured by design, not tested.

V

C

= 5 V,

= 13 V,

V

> 10.75 V at startup,

CC

INHIBIT

BOOT

V

f

= 0 V,

2

mA

BOOTLO

= 50 pF,

= 200 kHz

HIGHDR

swx

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SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998

switching characteristics over recommended operating virtual junction temperature range,

V

= 12 V, I

= 0 V (unless otherwise noted)

CC

DRV

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VSENSE to HIGHDR or

LOWDR (excluding deadtime)

Overdrive = 10 mV (see Note 2)

150

250

ns

OCP comparator

See Note 2

1

Propagation delay

OVP comparator

See Note 2

µs

PWRGD comparator

SLOWST comparator

See Note 2

1

Overdrive = 10 mV (see Note 2)

560

900

60

ns

C

= 9 nF,

V

= 6.5 V,

L

BOOT

= 0 V, T = 125°C

HIGHDR output

LOWDR output

HIGHDR output

LOWDR output

V

BOOTLO

= 9 nF,

J

Rise time

Fall time

ns

C

V = 6.5 V,

DRV

L

60

T = 125°C

J

C

= 9 nF,

V

= 6.5 V,

BOOT

L

V

= 0 V, T = 125°C

BOOTLO

= 9 nF,

J

ns

C

V

DRV

= 6.5 V,

L

T = 125°C

J

Deglitch time (includes

comparator propagation

delay)

OCP

OVP

See Note 2

2

5

µs

V

= 12 V,

HISENSE

pulsed from 12 V to 11.9 V,

2

3

IOUTLO

100 ns rise/fall times, See Note 2

V

= 4.5 V,

HISENSE

pulsed from 4.5 V to 4.4 V,

Response time

High-side VDS sensing

µs

IOUTLO

100 ns rise/fall times, See Note 2

V

= 3 V,

HISENSE

pulsed from 3 V to 2.9 V,

3

500

100

IOUTLO

100 ns rise/fall times, See Note 2

Short-circuit protection rising-

edge delay

SCP

LOSENSE = 0 V, (see Note 2)

300

30

ns

3 V ≤ V

V

(see Note 2)

≤ 11 V,

HISENSE

V

sensing sample/hold

DS

Turn-on/turn-off delay

= V

LOSENSE HISENSE

switch

LOWDR to HIGHDRV, and

LOHIB to LOWDR

Crossover delay time

See Note 2

30

Prefilter pole frequency

Propagation delay

Hysteretic comparator

LODRV

See Note 2

5

MHz

ns

400

NOTE 2: Ensured by design, not tested.

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SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998

TYPICAL CHARACTERISTICS

SLOWSTART TIMING

vs

VREFB CURRENT

vs

CAPACITANCE

100

10

1000

100

10

V

= 2 V

= 100µA

REFB

V

= 2 V

I

C

T

REFB

(VREFB)

C

T

= 0.1µF

= 0.1 µF

(SLOWST)

J

(SLOWST)

= 25°C

J

1

0.1

0

1

0.0001

0.001

0.01

0.1

1

10

100

– VREFB Current – µA

1000

Capacitance – µF

I

(VREFB)

Figure 5

Figure 6

OUTPUT DRIVER RISE TIME

vs

OUTPUT DRIVER FALL TIME

vs

LOAD CAPACITANCE

100

1000

100

10

High Side Driver

10

Low Side Driver

1

0.1

1

10

100

0.1

1

10

100

C

– Load Capacitance – nF

C

– Load Capacitance – nF

L

Figure 7

Figure 8

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SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER

SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998

TYPICAL CHARACTERISTICS

OCP THRESHOLD VOLTAGE

OVP THRESHOLD VOLTAGE

vs

JUNCTION TEMPERATURE

vs

JUNCTION TEMPERATURE

105

118

117

116

103

101

115

114

99

97

95

113

112

100

125

0

25

50

75

100

125

0

25

50

75

T

J

– Junction Temperature – °C

T

J

– Junction Temperature – °C

Figure 9

Figure 10

INHIBIT HYSTERESIS VOLTAGE

vs

INHIBIT START THRESHOLD VOLTAGE

vs

JUNCTION TEMPERATURE

150

125

2.1

2.05

100

2

75

50

1.95

1.90

100

125

0

25

50

75

100

125

0

25

50

75

T

J

– Junction Temperature – °C

T

J

– Junction Temperature – °C

Figure 11

Figure 12

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SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998

TYPICAL CHARACTERISTICS

UVLO HYSTERESIS VOLTAGE (V

vs

)

CC

UVLO START THRESHOLD VOLTAGE V

CC

vs

JUNCTION TEMPERATURE

2.5

10.5

2.3

2.1

10

1.9

9.5

1.7

1.5

9

100

125

0

25

50

75

100

125

0

25

50

75

T

J

– Junction Temperature – °C

T

J

– Junction Temperature – °C

Figure 13

Figure 14

PWRGD THRESHOLD VOLTAGE

vs

QUIESCENT CURRENT V

vs

JUNCTION TEMPERATURE

CC

JUNCTION TEMPERATURE

95

6

4

94

93

92

2

0

91

90

100

125

0

25

50

75

100

125

0

25

50

75

T

J

– Junction Temperature – °C

T

J

– Junction Temperature – °C

Figure 15

Figure 16

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SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER

SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998

TYPICAL CHARACTERISTICS

VDS SAMPLE/HOLD RESISTANCE

SLOWSTART CHARGE CURRENT

vs

JUNCTION TEMPERATURE

100

75

15

14

13

50

12

25

0

11

10

100

125

0

25

50

75

100

125

0

25

50

75

T

J

– Junction Temperature – °C

T

J

– Junction Temperature – °C

Figure 17

Figure 18

DRIVE REGULATOR LOAD REGULATION

DRIVE REGULATOR OUTPUT VOLTAGE

vs

JUNCTION TEMPERATURE

175

150

8.5

8.25

8

125

100

7.75

7.5

100

125

0

25

50

75

100

125

0

25

50

75

T

J

– Junction Temperature – °C

T

J

– Junction Temperature – °C

Figure 19

Figure 20

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SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER

SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998

TYPICAL CHARACTERISTICS

HIGH–SIDE DRIVER OUTPUT RESISTANCE

DRIVE REGULATOR LINE REGULATION

vs

JUNCTION TEMPERATURE

5

175

150

4

3

2

125

100

1

0

100

125

0

25

50

75

100

125

0

25

50

75

T

J

– Junction Temperature – °C

T

J

– Junction Temperature – °C

Figure 21

Figure 22

LOW–SIDE DRIVER OUTPUT RESISTANCE

vs

JUNCTION TEMPERATURE

6

5

4

3

2

1

0

100

125

0

25

50

75

T

J

– Junction Temperature – °C

Figure 23

17

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SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER

SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998

APPLICATION INFORMATION

Synchronous rectifier buck regulator circuits are used where high efficiency and low dropout voltages are required.

The TPS56xx controller is useful in applications with very high transient loads and wide dc load ranges, such as

multiple-DSP applications.

The circuit below will meet a wide variety of applications with maximum continuous-rated output currents of up to 8 A.

Design tradeoffs, such as cost, size, or efficiency may need to be addressed for specific applications. Care should

be taken in the proper layout (see last section of this data sheet for specific layout guidelines), especially in the

higher-current configurations, to ensure that noise and ripple are kept to a minimum. Basic layout considerations are

discussed in the 1996 Power Supply Circuits Databook (Literature no. SLVD002). Design guidelines and equations

are discussed in Synchronous Buck Converter Design Using TPS56xx Controllers in SLVP10x EVMs User’s Guide

(Literature no. SLVU007).

18

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SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER

SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998

APPLICATION INFORMATION

R7

11.0 kΩ 1%

R11

750 Ω

R6

1.3 kΩ

C1

22 µF

10 V

C14

0.01 µF

C12 0.1 µF

U1

R9

100 Ω 1%

R12

20.0 kΩ 1%

TPS5625

R1

1.0 kΩ

1

2

3

4

IOUT

PWRGD 28

NC 27

AGND2

OCP

NC 26

C15 1000 pF

VHYST

NC 25

5

6

7

VREFB

NC 24

NC 23

R2

10 kΩ

R13

VSENSE

ANAGND

INHIBIT 22

8

9

SLOWST

BIAS

IOUTLO 21

LOSENSE 20

HISENSE 19

BOOTLO 18

HIGHDR 17

BOOT 16

C3 0.1 µF

C16 0.1 µF

C17 1 µF

10 LODRV

11 LOHIB

12 DRVGND

13 LOWDR

14 DRV

C2

0.1 µF

C4

1 µF

C11

1 µF

VCC 15

R17

1 MΩ

R8

100 Ω

1%

C7 1 µF

R4

10 Ω

R3

10 Ω

L1

2.2 µH

C18

0.1 µF

Q2

Si4410

Q1

Si4410

R16

4.7 Ω

C5 2.2 µF

C6 680 µF 6.3 V

See Note A

C8 0.01 µF

R5

L2

2.7 Ω

2.6 µH

L1 = 10T #22 on T30–18 Core

L2 = 12T #20 on T44–8Core

C9 820 µF 4V

C10 10 µF

Not Used:

R10, R13, R14

C13

R15

4.7 Ω

NOTE A: Theses two traces should be physically close to each other for good noise immunity.

Figure 24. Typical Design Schematic

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SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998

Table 1. Test Results for 2.5-V, 8-A Converter

TEST

Output voltage

Load regulation

Line regulation

Ripple

CONDITIONS

QTY

2.50

UNITS

V

= 5.25 V,

I

= 8 A

V

%

IN

O

= 0.8 to 8 A

0.4

0.2

IN

O

I

O

=6 A,

V

CC

= 4.5 V to 6 V

V

= 5.25 V,

I

= 8 A

50 mVpp

89

IN

O

Efficiency

V

= 8 A

%

O

Table 2. 2.5-V, 8-A Converter Bill of Materials

REF DES

C1

QTY

PART NUMBER

DESCRIPTION

Capacitor, Os-Con, 22 µF, 10 V, 20%

MFG

Sanyo

1

4

10SS22M

C2

GRM39X7R104K016A

Capacitor, Ceramic, 0.1 µF, 16 V, 10%, X7R

muRata

Sanyo

C3

C4

4

1

GRM42-6Y5V105Z016A Capacitor, Ceramic, 1 µF, 16 V, +80%–20%

GRM42-6Y5V225Z016A Capacitor, Os-Con, 2.2 µF, 16 V, Y5U

C5

C6

6SP680M

Capacitor, Os-Con, 680 µF, 6.3 V, 20%

C7

GRM42-6Y5V105Z016A Capacitor, Ceramic, 1 µF, 16 V, +80%–20%

muRata

Sanyo

C8

2

1

GRM39X7R103K025A

4SP820M

Capacitor, Ceramic, 0.01 µF, 25 V, 10%, X7R

Capacitor, Os-Con, 820 µF, 4 V, 20%

C9

C10

C11

C12

C14

C15

C16

C17

C18

J1

GRM235Y5V106Z016A Capacitor, Ceramic, 10 µF, 16 V, Y5V

GRM42-6Y5V105Z016A Capacitor, Ceramic, 1 µF, 16 V, +80%–20%

muRata

Sullins

GRM39X7R104K016A

GRM39X7R103K025A

GRM39X7R102K050A

GRM39X7R104K016A

Capacitor, Ceramic, 0.1 µF, 16 V, 10%, X7R

Capacitor, Ceramic, 0.01 µF, 25 V, 10%, X7R

Capacitor, Ceramic, 1000 pF, 50 V, 10%, X7R

Capacitor, Ceramic, 0.1 µF, 16 V, 10%, X7R

1

GRM42-6Y5V105Z016A Capacitor, Ceramic, 1 µF, 16 V, +80%–20%

GRM39X7R104K016A

S1122-18-ND

Capacitor, Ceramic, 0.1 µF, 16 V, 10%, X7R

Header, RA, 18-pin, 0.23 Posts × 0.20 Tails

Inductor, Filter, 2.2 µH, 8.5 A (10T #22 on T30-18 Core)

Inductor, Filter, 2.6 µH, 8.5 A (12T #20 on T44-8 Core)

FET, N-ch, 30-V, 10-A, 13-mΩ

1

2

L1

L2

Q1

Si4410DY

Std

Siliconix

Q2

FET, N-ch, 30-V, 10-A, 13-mΩ

R1

3

1

2

Resistor, Chip, 1.0 kΩ, 1/16W, 5%

Resistor, Chip, 10 kΩ, 1/16W, 5%

R2

Std

R3

Std

Resistor, Chip, 10 Ω, 1/10W, 5%

R4

Std

Resistor, Chip, 10 Ω, 1/10W, 5%

R5

1

Std

Resistor, Chip, 2.7 Ω, 1/4W, 5%

R6

Std

Resistor, Chip, 1.3 kΩ, 1/16W, 5%

Resistor, Chip, 11.0 kΩ, 1/16W, 1%

Resistor, Chip, 100 Ω, 1/16W, 1%

R7

1

2

Std

R8

Std

R9

Std

Resistor, Chip, 100 Ω, 1/16W, 1%

Resistor, Chip, 750 Ω, 1/16W, 5%

Resistor, Chip, 20.0 kΩ, 1/16W, 1%

Resistor, Chip, 4.7 Ω, 1/16W, 5%

Resistor, Chip, 1 MΩ, 1/16W, 5%

IC, PWM Ripple Controller, FIxed 2.5 V

R11

R12

R15

R16

R17

U1

Std

1

2

Std

1

Std

TPS5625PWP

TI

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APPLICATION INFORMATION

EFFICIENCY

vs

OUTPUT CURRENT

100

95

90

85

80

4

7

8

0

1

2

3

5

6

Output Current – A

Figure 25

Top: Vo 10 mV/div

Bottom: V

2 µs/div

Q2 5 V/div

DS

Figure 26. Output Voltage Ripple at 8 A

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SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998

APPLICATION INFORMATION

20 µs/div

I

O

2.5 A/div

V

O

20 mV/div

Figure 27. Rising Load Transient Response

20 µs/div

I

O

2.5 A/div

V

O

20 mV/div

Figure 28. Falling Load Transient Response

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APPLICATION INFORMATION

layout guidelines

Good power supply results will only occur when care is given to proper design and layout. Layout will affectnoise

pickup and generation and can cause a good design to perform with less than expected results. With a range

of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult

than most general PCB design. The general design should proceed from the switching node to the output, then

back to the driver section and, finally, place the low-level components. Below are several specific points to

consider before layout of a TPS56xx design begins.

1. All sensitive analog components should be referenced to ANAGND. These include components connected

to SLOWST, IOUT, OCP, VSENSE, VREFB, VHYST, BIAS, and LOHIB.

2. Analogground and drive ground should be isolated as much as possible. Ideally, analog ground will connect

to the ground side of the bulk storage capacitors, on V , and drive ground will connect to the main ground

O

plane close to the source of the low-side FET.

3. Connections from the drivers to the gate of the power FETs should be as short and wide as possible to

reduce stray inductance. This becomes more critical if external gate resistors are not being used.

4. The bypass capacitor for the DRV regulator should be placed close to the TPS56xx and be connected to

DRVGND.

5. The bypass capacitor for V

should be placed close to the TPS56xx and be connected to DRVGND.

CC

6. When configuring the high-side driver as a floating driver, the connection from BOOTLO to the power FETs

should be as short and as wide as possible. The other pins that also connect to the power FETs, LOHIB

and LOSENSE, should have a separate connection to the FETs, since BOOTLO will have large peak

currents flowing through it.

7. When configuring the high-side driver as a floating driver, the bootstrap capacitor (connected from BOOT

to BOOTLO) should be placed close to the TPS56xx.

8. When configuring the high-side driver as a ground referenced driver, BOOTLO should be connected to

DRVGND.

9. The bulk storage capacitors across V should be placed close to the power FETs. High-frequency bypass

I

capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the

high-side FET and close to the source of the low-side FET.

10. High-frequency bypass capacitors should be placed across the bulk storage capacitors on V .

O

11. HISENSE and LOSENSE should be connected very close to the drain and source, respectively, of the

high-side FET. HISENSE and LOSENSE should be routed very close to each other to minimize

differential-mode noise coupling to these traces.

23

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5615, TPS5618, TPS5625, TPS5633

SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER

SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998

MECHANICAL DATA

PWP (R-PDSO-G**)

PowerPAD PLASTIC SMALL-OUTLINE PACKAGE

20-PIN SHOWN

0,30

0,19

0,65

20

M

0,10

11

Thermal Pad

(See Note D)

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

1

10

0,25

A

0°–8°

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

14

16

20

24

28

DIM

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

A MAX

A MIN

4073225/E 03/97

NOTES: B. All linear dimensions are in millimeters.

C. This drawing is subject to change without notice.

D. Body dimensions do not include mold flash or protrusions.

E. Thepackagethermalperformancemaybeenhancedbybondingthethermalpadtoanexternalthermalplane.Thispadiselectrically

and thermally connected to the backside of the die and possibly selected leads.

F. Falls within JEDEC MO-153

PowerPAD is a trademark of Texas Instruments Incorporated.

24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.


型号：	TPS5625
厂家：	TEXAS INSTRUMENTS
描述：	SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER 同步降压迟滞DC控制器控制器
文件：	总25页 (文件大小：387K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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