TPS56628DDA [TI]
具有 Eco-Mode 的 4.5V 至 18V、6A 同步降压转换器 | DDA | 8 | -40 to 85;
| 型号： | TPS56628DDA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 Eco-Mode 的 4.5V 至 18V、6A 同步降压转换器 | DDA | 8 | -40 to 85 转换器 |
| 文件： | 总26页 (文件大小：1891K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS56628
www.ti.com.cn
ZHCSBZ7A –OCTOBER 2013–REVISED DECEMBER 2013
具有 Eco-mode™ 的 4.5V 至 18V 输入，6A 同步降压转换器
查询样片: TPS56628
1
特性
说明
23
•
D-CAP2™ 模式支持快速瞬态响应
低输出纹波，支持陶瓷输出电容器
宽 VIN 输入电压范围：4.5V 至 18V
输出电压范围：0.76V 至 5.5V
TPS56628 是一款自适应接通时间 D-CAP2™ 模式同
步降压转换器。 TPS56628 可帮助系统设计人员通过
一个成本有效、低组件数量、低待机电流解决方案来完
成多种终端设备的电源总线调节器集。 TPS56628 的
主控制环路使用 D-CAP2™ 模式控制，此控制方式在
无需外部补偿组件的情况下提供快速瞬态响应。 自适
应接通时间控制支持较高负载状态下的脉宽调制
(PWM) 模式与轻负载下的 Eco-mode™ 工作模式之间
的无缝转换。 Eco-mode™ 使 TPS56628 能够在较轻
负载条件下保持高效率。 TPS56628 的专有电路还使
该器件可采用诸如高分子有机半导体固体电容器
(POSCAP) 或高分子聚合物电容器 (SP-CAP) 等低等
效串联电阻 (ESR) 输出电容器，以及超低 ESR 陶瓷电
容器。 该器件的工作输入电压介于 4.5V 至 18V VIN
之间。 输出电压可在 0.76V 至 5.5V 的范围内设
定。TPS56628 采用 8 引脚 DDA 封装，并且设计运行
温度范围在 -40°C 至 85°C 之间。
•
•
•
•
高效率集成型场效应晶体管 (FET)
针对较低占空比应用进行了优化
- 36mΩ（高侧）与 28mΩ（低侧）
•
•
•
•
•
•
高效率，关断时流耗少于 10μA
高初始带隙基准精度
预偏置软启动
650kHz 开关频率 (fSW
)
逐周期过流限制
在轻负载情况下实现高效率的自动跳跃 Eco-
mode™ 模式
•
•
电源正常输出
固定软启动时间：1.0ms
应用范围
•
低电压系统的广泛应用
–
–
–
–
数字电视电源
高清 Blu-ray Disc™ 播放器
网络家庭终端设备
数字机顶盒 (STB)
VIN
Vout (50mV/div)
TPS56628DDA
EN
1
2
3
4
8
7
6
5
EN
VIN
VBST
SW
VOUT
VFB
VREG5
PG
VOUT
Iout (2A/div)
100 μs/div
GND
PwPd
9
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
D-CAP2, Eco-mode are trademarks of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
English Data Sheet: SLVSC94
TPS56628
ZHCSBZ7A –OCTOBER 2013–REVISED DECEMBER 2013
www.ti.com.cn
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)(2)(3)
TRANSPORT
TA
PACKAGE
ORDERABLE PART NUMBER
PIN
MEDIA
TPS56628DDA
Tube
–40°C to 85°C
DDA
8
TPS56628DDAR
Tape and Reel
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) All package options have Cu NIPDAU lead/ball finish.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–2
MAX
20
VIN, EN
VBST
26
VBST (10 ns transient)
VBST (vs SW)
VFB, PG
28
Input voltage range
Output voltage range
6.5
6.5
20
V
SW
SW (10 ns transient)
VREG5
–3
22
–0.3
–0.2
6.5
0.2
2
V
V
Voltage from GND to thermal pad, Vdiff
Human Body Model (HBM)
Charged Device Model (CDM)
kV
V
Electrostatic discharge
500
150
150
Operating junction temperature, TJ
Storage temperature, Tstg
–40
–55
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
TPS56628
THERMAL METRIC
UNITS
DDA (8 PINS)
θJA
Junction-to-ambient thermal resistance
43.5
49.4
25.6
7.4
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
25.5
5.2
θJCbot
2
Copyright © 2013, Texas Instruments Incorporated
TPS56628
www.ti.com.cn
ZHCSBZ7A –OCTOBER 2013–REVISED DECEMBER 2013
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range, (unless otherwise noted)
MIN
4.5
MAX
18
UNIT
VIN
Supply input voltage range
V
VBST
–0.1
–0.1
–0.1
–0.1
–0.1
–0.1
–1.8
–3
24
VBST (10 ns transient)
27
VBST(vs SW)
6.0
5.7
18
PG
VI
Input voltage range
V
EN
VFB
5.5
18
SW
SW (10 ns transient)
VREG5
22
VO
IO
Output voltage range
–0.1
0
5.7
5
V
Output Current range
IVREG5
mA
°C
TA
Operating free-air temperature
–40
85
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VIN current, TA = 25°C, EN = 5 V,
VFB = 0.8 V
IVIN
Operating - non-switching supply current
Shutdown supply current
950
3
1400
10
μA
μA
IVINSDN
VIN current, TA = 25°C, EN = 0 V
LOGIC THRESHOLD
EN high-level input voltage
EN
1.6
V
V
VEN
EN low-level input voltage
EN pin resistance to GND
EN
0.6
REN
VEN = 12 V
200
400
800
kΩ
VFB VOLTAGE
TA = 25°C, VO = 1.05 V, IO = 10 mA, Eco-
mode™ operation
772
765
mV
mV
TA = 25°C, VO = 1.05 V, continuous mode
operation
VFBTH
VFB threshold voltage
VFB input current
757
751
773
TA = -40 to 85°C, VO = 1.05 V, continuous
mode operation(1)
779
mV
IVFB
VFB = 0.8 V, TA = 25°C
0
±0.15
μA
VREG5 OUTPUT
TA = 25°C, 6 V < VIN < 18 V,
0 < IVREG5 < 5 mA
VVREG5
IVREG5
VREG5 output voltage
Output current
5.2
20
5.5
5.7
V
VIN = 6 V, VREG5 = 4.0 V, TA = 25°C
mA
VFB VOLTAGE AND DISCHARGE RESISTANCE
RDISCHG
VOUT discharge resistance
EN = 0 V, SW = 0.5 V, TA = 25°C
500
800
Ω
MOSFET
High side switch resistance
Low side switch resistance
25°C, VBST - SW = 5.5 V
25°C
36
28
mΩ
mΩ
RDS(on)
CURRENT LIMIT
IOCL
Current limit
L out = 1.5 μH(1)
6.6
7.3
8.9
A
(1) Not production tested.
Copyright © 2013, Texas Instruments Incorporated
3
TPS56628
ZHCSBZ7A –OCTOBER 2013–REVISED DECEMBER 2013
www.ti.com.cn
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
THERMAL SHUTDOWN
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(2)
Shutdown temperature
165
35
TSDN
Thermal shutdown threshold
°C
(2)
Hysteresis
ON-TIME TIMER CONTROL
tON
On time
VIN = 12 V, VO = 1.05 V
TA = 25°C, VFB = 0.7 V
150
260
ns
ns
tOFF(MIN)
Minimum off time
310
1.3
SOFT START
TSS
Soft-start time
Internal soft-start time
0.7
85%
2
1.0
ms
POWER GOOD
VFB rising (Good)
VFB falling (Fault)
PG = 5 V
90%
85%
4
95%
VTHPG
IPG
PG threshold
PG sink current
mA
HICCUP AND OVER-VOLTAGE PROTECTION
VOVP
Output OVP threshold
Output Hiccup threshold
Output Hiccup delay
OVP Detect (L > H)
Hiccup detect (H > L)
To hiccup state
125%
65%
250
VHICCUP
THICCUPDELAY
µs
V
THICCUPENDELAY Output Hiccup Enable delay
Relative to soft-start time
x1.7
UVLO
Wake up VREG5 voltage
Hysteresis VREG5 voltage
3.45
0.13
3.75
0.32
4.05
0.48
UVLO
UVLO threshold
(2) Not production tested.
4
Copyright © 2013, Texas Instruments Incorporated
TPS56628
www.ti.com.cn
ZHCSBZ7A –OCTOBER 2013–REVISED DECEMBER 2013
DEVICE INFORMATION
DDA PACKAGE
(TOP VIEW)
1
2
3
4
8
EN
VIN
EXPOSED
THERMAL PAD
7
VFB
VBST
TPS56628
DDA
HSOP8
6
VREG5
SW
5
PG
GND
PIN FUNCTIONS
PIN
DESCRIPTION
NAME
EN
NO.
1
Enable input control. EN is active high and must be pulled up to enable the device.
Converter feedback input. Connect to output voltage with feedback resistor divider.
VFB
2
5.5 V power supply output. A capacitor (typical 1 µF) should be connected to GND. VREG5 is not active
when EN is low.
VREG5
PG
3
4
Open drain power good output
Ground pin. Power ground return for switching circuit. Connect sensitive VFB returns to GND at a single
point.
GND
SW
5
6
Switch node connection between high-side NFET and low-side NFET.
Supply input for the high-side FET gate drive circuit. Connect 0.1 µF capacitor between VBST and SW
pins. An internal diode is connected between VREG5 and VBST.
VBST
VIN
7
8
Input voltage supply pin.
Exposed Thermal
Pad
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected to
GND.
Back side
Copyright © 2013, Texas Instruments Incorporated
5
TPS56628
ZHCSBZ7A –OCTOBER 2013–REVISED DECEMBER 2013
www.ti.com.cn
FUNCTIONAL BLOCK DIAGRAM
EN
EN
EN
1
Logic
VIN
VIN
OV
8
+25%
VBST
SW
7
Ref
SS
VO
6
2
VFB
Ceramic
Capacitor
-35%
UVP_Hiccup
SGND
5
SW
GND
VREG5
ZC
3
GND
SW
Softstart
Hiccup
PGND
GND
SS
VIN
OV
EN
VREG5
Protection
Logic
UVLO
Ref
4
UVLO
TSD
PG
-10%
Hiccup
REF
Ref
6
Copyright © 2013, Texas Instruments Incorporated
TPS56628
www.ti.com.cn
ZHCSBZ7A –OCTOBER 2013–REVISED DECEMBER 2013
OVERVIEW
The TPS56628 is a 6-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs with
Auto-Skip mode to improve light load efficiency. It operates using D-CAP2™ mode control. The fast transient
response of D-CAP2™ control reduces the output capacitance required to meet a specific level of performance.
Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and special polymer
types. The PG output can be used for sequence operation.
DETAILED DESCRIPTION
PWM Operation
The main control loop of the TPS56628 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines adaptive on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need
for ESR induced output ripple from D-CAP2™ mode control.
PWM Frequency and Adaptive On-Time Control
TPS56628 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS56628 runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage; therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
Auto-Skip Eco-mode™ Control
The TPS56628 is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to a point where
its rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load
current further decreases the converters runs in discontinuous conduction mode. The on-time is kept almost the
same as it was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. The transition point to the light load operation
IOUT(LL) current can be calculated in Equation 1
V
(
-VOUT ×V
)
1
IN
OUT
IOUT (LL)
=
×
2× L× fsw
VIN
(1)
Soft Start and Pre-Biased Soft Start
The TPS56628 has an internal 1.0 ms soft-start. When the EN pin becomes high, internal soft-start function
begins ramping up the reference voltage to the PWM comparator.
The TPS56628 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting
the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-
cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This
scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps
up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal
mode operation.
Copyright © 2013, Texas Instruments Incorporated
7
TPS56628
ZHCSBZ7A –OCTOBER 2013–REVISED DECEMBER 2013
www.ti.com.cn
Power Good
The power-good function is activated after soft start has finished. The power good function becomes active after
1.7 times soft-start time. When the output voltage becomes within -10% of the target value, internal comparators
detect power good state and the power good signal becomes high. The power good output, PG is an open drain
output. If the feedback voltage goes under 15% of the target value, the power good signal becomes low. Rpg
resistor value, which is connected between PG and VREG5, is required from 25kΩ to 150kΩ.
Current Protection
The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. The TPS56628 constantly
monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.
If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented
per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the
voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching
cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in
the same manner. If the over current condition exists for 7 consecutive switching cycles, the internal OCL
threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the
switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the
higher value.
There are some important considerations for this type of over-current protection. The load current one half of the
peak-to-peak inductor current is higher than the over-current threshold also when the current is being limited, the
output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. This may cause the output voltage to fall. When the VFB voltage becomes lower than 65% of the
target voltage, the UVP comparator detects it. After 250 µs detecting the UVP voltage, device will shut down and
re-start after approximately 12ms hiccup time
When the over-current condition is removed, the output voltage returns to the regulated value.
Overvoltage Protection
TPS56628 detects overvoltage conditions by monitoring the feedback voltage (VFB). This function is enabled
after approximately 1.7 x times the soft start time. When the feedback voltage becomes higher than 125% of the
target voltage, the OVP comparator output goes high and both the high-side MOSFET driver and the low-side
MOSFET driver turn off. This function is non-latch operation.
UVLO Protection
Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is
lower than UVLO threshold voltage, the TPS56628 is shut off. This protection is non-latching.
Thermal Shutdown
TPS56628 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C),
the device is shut off. This is non-latch protection.
8
Copyright © 2013, Texas Instruments Incorporated
TPS56628
www.ti.com.cn
ZHCSBZ7A –OCTOBER 2013–REVISED DECEMBER 2013
TYPICAL CHARACTERISTICS
VIN = 12 V, VO = 1.05V, TA = 25°C (unless otherwise noted).
1,400
1,200
1,000
800
10
9
8
7
6
5
4
3
2
1
0
600
400
200
0
±50
0
50
100
150
±50
0
50
100
150
C001
C002
TJ Junction Temperature (C)
TJ Junction Temperature (C)
Figure 1. SUPPLY CURRENT vs JUNCTION TEMPERATURE
Figure 2. VIN SHUTDOWN CURRENT vs
JUNCTION TEMPERATURE
50
1.100
1.075
1.050
1.025
1.000
VIN = 18 V
40
30
20
10
0
V
= 5 V
IN
V
= 12 V
IN
V
= 18 V
IN
0
5
10
15
20
0.0
1.0
2.0
3.0
4.0
5.0
6.0
C003
C004
EN Input Voltage (V)
IOUT - Output Current (A)
Figure 3. EN CURRENT vs EN VOLTAGE
Figure 4. 1.05-V OUTPUT VOLTAGE vs OUTPUT CURRENT
1.080
1.070
1.060
1.050
1.040
1.030
1.020
Vout( 50mV/div )
Iout( 2A/div )
I
= 10 mA
OUT
I
IOUT = 1 A
0
5
10
15
20
100 μs/div )
C005
VIN - Input Voltage (V)
Figure 5. 1.05-V OUTPUT VOLTAGE vs INPUT VOLTAGE
Figure 6. 1.05-V, LOAD TRANSIENT RESPONSE
Copyright © 2013, Texas Instruments Incorporated
9
TPS56628
ZHCSBZ7A –OCTOBER 2013–REVISED DECEMBER 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, VO = 1.05V, TA = 25°C (unless otherwise noted).
100
90
80
70
60
50
40
VIN = 12 V
EN (10V/div)
VREG5 (5V/div)
Vout (0.5V/div)
Vo=1.8V
Vo=3.3V
Vo=5V
PG (5V/div)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
C008
IOUT - Output Current (A)
400 μs/div
Figure 7. START-UP WAVE FORM
Figure 8. EFFICIENCY vs OUTPUT CURRENT
100
900
850
800
750
700
650
600
550
500
450
400
VIN = 12 V
IOUT = 1 A
90
80
70
60
50
40
VO = 1.05 V
VO=1.2V
VO=1.5V
30
Vo=1.8V
V
= 1.8 V
O
20
V
= 2.5 V
O
Vo=3.3V
V
= 3.3 V
O
10
Vo=5V
V
= 5 V
O
0
0.001
0.01
0.1
0
5
10
15
20
C009
C010
IOUT - Output Current (A)
VIN - Input Voltage (V)
Figure 9. LIGHT LOAD EFFICIENCY vs OUTPUT CURRENT
Figure 10. SWITCHING FREQUENCY vs INPUT VOLTAGE
0.780
0.775
0.770
0.765
0.760
900
800
700
600
500
400
300
200
100
0
V
= 1.05 V
O
0.755
0.750
I
= 10 mA
O
V
= 1.8 V
O
I
IO = 1 A
V=3.3V
O
±50
0
50
100
150
0.0
0.1
1.0
10.0
C012
TJ Junction Temperature (C)
C011
IO - Output Current (A)
Figure 11. SWITCHING FREQUENCY vs OUTPUT CURRENT
Figure 12. VFB VOLTAGE vs JUNCTION TEMPERATURE
10
Copyright © 2013, Texas Instruments Incorporated
TPS56628
www.ti.com.cn
ZHCSBZ7A –OCTOBER 2013–REVISED DECEMBER 2013
TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, VO = 1.05V, TA = 25°C (unless otherwise noted).
VO = 50 mV / div
Vo=1.05V
Vo(10mV/div)
SW = 5 V / div
SW( 5V/div)
400ns/div
Time = 1 µsec / div
Figure 13. VOLTAGE RIPPLE AT OUTPUT (IO = 6 A)
Figure 14. DCM VOLTAGE RIPPLE AT
OUTPUT (IO = 30 mA)
7.00
6.00
Vo=1.05V
VIN(50mV/div)
5.00
4.00
3.00
2.00
1.00
0.00
SW( 5V/div)
V
V
= 1.05V
= 1.8V
O
O
O
V
V
= 3.3V
= 5.0V
400ns/div
O
0
20
40
60
80
100
TA - Ambient Temperature (ºC)
Figure 15. VOLTAGE RIPPLE AT INPUT (IO = 6 A)
Figure 16. OUTPUT CURRENT vs AMBIENT TEMPERATURE
Copyright © 2013, Texas Instruments Incorporated
11
TPS56628
ZHCSBZ7A –OCTOBER 2013–REVISED DECEMBER 2013
www.ti.com.cn
DESIGN GUIDE
Step-By-Step Design Procedure
To begin the design process, the user must know a few application parameters:
•
•
•
•
•
Input voltage range
Output voltage
Output current
Output voltage ripple
Input voltage ripple
VIN
4.5 to 18V
VIN
C1
C2
C3
10uF
10uF
0.1uF
1
2
U1
TPS56628 DDA
R3 10.0k
1
2
8
7
6
5
EN
EN
VIN
VBST
SW
C7 0.1uF
VOUT
VOUT
VFB
VREG5
PG
1.05V 6A
L1
R1 8.25k
3
VOUT
R2
22 .1k
R4
1.5uH
4
100 k
C4
C5
1uF
1
C8
C9
GND
PwPd
22uF 22uF
9
Not Installed
1
Figure 17. Shows the Schematic Diagram for This Design Example.
Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 2 to calculate VOUT
.
To improve efficiency at light loads consider using larger value resistors, high resistance is more susceptible to
noise, and the voltage errors from the VFB input current are more noticeable.
æ
ö
÷
÷
R1
ç
= 0.765 x 1 +
V
OUT
ç
÷
÷
ø
ç
è
R2
(2)
(3)
Output Filter Selection
The output filter used with the TPS56628 is an LC circuit. This LC filter has double pole at:
1
F
P
=
2p L
x C
OUT
OUT
12
Copyright © 2013, Texas Instruments Incorporated
TPS56628
www.ti.com.cn
ZHCSBZ7A –OCTOBER 2013–REVISED DECEMBER 2013
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS56628. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor for the output filter must be selected so that the double pole of
Equation 3 is located below the high frequency zero but close enough that the phase boost provided be the high
frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the values
recommended in Table 1
Table 1. Recommended Component Values
Output
Voltage
(V)
C4 (pF)(1)
L1 (µH)
TYP
C8 + C9 (µF)
R1 (kΩ)
R2 (kΩ)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
1
6.81
8.25
12.7
21.5
30.1
49.9
73.2
124
22.1
22.1
22.1
22.1
22.1
22.1
22.1
22.1
5
5
5
5
5
5
2
2
150
150
220
220
100
68
1.0
1.0
1.0
1.0
1.2
1.5
1.8
2.2
1.5
1.5
1.5
1.5
1.5
2.2
2.2
3.3
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
22
22
22
22
22
22
22
22
68
68
68
68
68
68
68
68
1.05
1.2
1.5
1.8
2.5
3.3
5
22
22
22
22
(1) Optional
For higher output voltages, additional phase boost can be achieved by adding a feed forward capacitor (C4) in
parallel with R1
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4,
Equation 5 and Equation 6. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current.
Use 650 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS
current of Equation 6.
V
- V
V
IN(max)
OUT
OUT
I
=
x
IPP
x fSW
V
L
IN(max)
O
(4)
(5)
(6)
I
lpp
I
= I
+
Ipeak
O
2
1
2
2
I
=
I
+
I
Lo(RMS)
O
IPP
12
For this design example, the calculated peak current is 6.51 A and the calculated RMS current is 6.01 A. The
inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating of 11
A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS56628 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 22µF to 68µF. Use Equation 7 to
determine the required RMS current rating for the output capacitor.
V
x (V - V
)
OUT
IN
OUT
I
=
Co(RMS)
12 x V x L
IN
x
fSW
O
(7)
For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.286 A and each output capacitor is rated for 4A.
Copyright © 2013, Texas Instruments Incorporated
13
TPS56628
ZHCSBZ7A –OCTOBER 2013–REVISED DECEMBER 2013
www.ti.com.cn
Input Capacitor Selection
The TPS56628 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1 µF
capacitor (C3) from pin 8 to ground is optional to provide additional high frequency filtering. The capacitor voltage
rating needs to be greater than the maximum input voltage.
Bootstrap Capacitor Selection
A 0.1 µF. ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is
recommended to use a ceramic capacitor.
VREG5 Capacitor Selection
A 1-µF ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is
recommended to use a ceramic capacitor.
THERMAL INFORMATION
This 8-pin DDA package incorporates an exposed thermal pad that is designed to be directly attached to an
external heatsink. The thermal pad must be soldered to the printed circuit board (PCB). After soldering, the PCB
can be used as a heartsick. In addition, through the use of thermal vias, the thermal pad can be attached directly
to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached
to a special heartsick structure designed into the PCB. This design optimizes the heat transfer from the
integrated circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, see the Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No.
SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.
The exposed thermal pad dimensions for this package are shown in the following illustration.
Figure 18. Thermal Pad Dimensions
14
Copyright © 2013, Texas Instruments Incorporated
TPS56628
www.ti.com.cn
ZHCSBZ7A –OCTOBER 2013–REVISED DECEMBER 2013
LAYOUT CONSIDERATIONS
1. The TPS56628 can supply large load currents up to 6 A, so heat dissipation may be a concern. The top side
area of PCB adjacent to the TPS56628 should be filled with ground as much as possible to dissipate heat.
2. The bottom side area directly below the IC should a dedicated ground area. It should be directly connected
to the thermal pad of the device using vias as shown. The ground area should be as large as practical.
Additional internal layers can be dedicated as ground planes and connected to the vias as well.
3. Keep the input switching current loop as small as possible.
4. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin of the device.
5. Keep analog and non-switching components away from switching components.
6. Make a single point connection from the signal ground to power ground.
7. Do not allow switching current to flow under the device.
8. Keep the pattern lines for VIN, SW, and PGND (POWERGROUND) broad.
9. Exposed pad of device must be connected to PGND with solder.
10. VREG5 capacitor should be placed near the device, and connected PGND.
11. Output capacitor should be connected to a broad pattern of the PGND.
12. Voltage feedback loop should be as short as possible, and preferably with ground shield.
13. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to ANALOG
GROUND.
14. Providing sufficient via is preferable for VIN, SW and PGND connection.
15. VFB node should be as short as possible.
16. VIN Capacitor should be placed as near as possible to the device.
Additional
Thermal
Vias
VIN INPUT
BYPASS
CAPACITOR
TO ENABLE
CONTROL
VIN INPUT
BYPASS
CAPACITOR
VIN
FEEDBACK
RESISTORS
EN
VIN
BOOST
CAPACITOR
VFB
VBST
VOUT
VREG5
PG
SW
OUTPUT
INDUCTOR
EXPOSED
POWERPAD
AREA
BIAS
CAP
GND
Connection to
POWER GROUND
on internal or
OUTPUT
FILTER
CAPACITOR
bottom layer
Additional
Thermal
Vias
POWER GROUND
ANALOG
GROUND
TRACE
Figure 19. PCB Layout
Copyright © 2013, Texas Instruments Incorporated
15
TPS56628
ZHCSBZ7A –OCTOBER 2013–REVISED DECEMBER 2013
www.ti.com.cn
修订历史记录
谨记：当前版本的页码也许与之前的版本不同。
Changes from Original (October 2013) to Revision A
Page
•
•
•
•
•
•
•
Deleted 说明中的“此器件还特有一个可调软启动时间。”。 ................................................................................................... 1
Deleted "GND" spec from Output Voltage Range in the Absolute Maximum Ratings table. ............................................... 2
Deleted "GND" spec from Input Voltage Range in the Recommended Operating Conditions table.. .................................. 3
Deleted "TJ" spec from the Recommended Operating Conditions table. ............................................................................. 3
Changed VTHPG spec for VFB falling (Fault) condition from "65%" to "85%" in Electrical Characteristics table ................... 4
Changed GND pin description from "SS and VFB" to "VFB" in the Pin Functions table. ..................................................... 5
Changed input names from "PGND" to "GND" at the ZC and OCP comparators in the Functional Block Diagram
graphic .................................................................................................................................................................................. 6
•
•
Changed text string from "constant on-time" to "adaptive on-time" in the 1st paragraph of PWM Operation. ..................... 7
Changed text string from "detects over and under voltage" to "detects overvoltage" in the Overvoltage Protection
section. .................................................................................................................................................................................. 8
•
•
•
•
•
Added VO = 1.05V to Conditions statement for the Typical Characteristics graphs. ............................................................ 9
Changed time scale callout from "100 µs/div" to "400 µs/div" on Figure 7 ........................................................................ 10
Added VO = 1.05V to Conditions statement for the Typical Characteristics graphs. .......................................................... 10
Added VO = 1.05V to Conditions statement for the Typical Characteristics graphs. .......................................................... 11
Deleted "-950 mv dc offset" text string from signal trace label; and changed SW label from "10 V/div" to "5 V/div" on
Figure 14 ............................................................................................................................................................................. 11
•
Changed some itemized notes in the Layout Considerations section for clarification. ...................................................... 15
16
Copyright © 2013, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS56628DDA
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
8
8
75
RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
-40 to 85
-40 to 85
56628
56628
TPS56628DDAR
2500 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS56628DDAR
SO
Power
PAD
DDA
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SO PowerPAD DDA
SPQ
Length (mm) Width (mm) Height (mm)
366.0 364.0 50.0
TPS56628DDAR
8
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
TPS56628DDA
TPS56628DDA
DDA
DDA
HSOIC
HSOIC
8
8
75
75
517
508
7.87
7.77
635
4.25
NA
2540
Pack Materials-Page 3
GENERIC PACKAGE VIEW
DDA 8
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
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Copyright © 2022，德州仪器 (TI) 公司
相关型号：
TPS568215OARNNR
具有 D-CAP3 控制功能和 Out-of-Audio™ 模式的 4.5V 至 17V、8A 同步 SWIFT™ 降压转换器 | RNN | 18 | -40 to 125
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TPS568215OARNNT
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