TPS568230RJET [TI]
针对解决方案成本进行了优化的 4.5V 至 18V、8A 同步 SWIFT™ 降压转换器 | RJE | 20 | -40 to 125;
| 型号： | TPS568230RJET |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 针对解决方案成本进行了优化的 4.5V 至 18V、8A 同步 SWIFT™ 降压转换器 | RJE | 20 | -40 to 125 开关 输出元件 转换器 |
| 文件： | 总32页 (文件大小：2510K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS568230
ZHCSIY3C –MARCH 2019–REVISED AUGUST 2019
TPS568230 4.5V 至 18V 输入、8A 同步降压稳压器
1 特性
3 说明
1
•
•
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输入电压范围：4.5V 至 18V
TPS568230 是一款配备了集成 MOSFET 且具有成本
效益、高电压输入、高效的同步降压转换器。
D-CAP3™架构控制，可实现快速瞬态响应
输出电压范围：0.6V 至 7V
TPS568230 具有 ULQ™（超低静态电流）功能，可实
现低偏置电流。其工作电源输入电压范围为 4.5V 至
18V。该器件使用 DCAP3™ 控制模式提供快速瞬态响
应、良好的线路和负载调节，无需外部补偿，并支持低
等效串联电阻 (ESR) 输出电容器，如专用聚合物和超
低 ESR 陶瓷电容器。
0.6V ±1% 基准电压 (25°C)
支持 8A 的连续输出电流
集成 19.5mΩ 和 9.5mΩ RDS(on) 内部功率 MOSFET
ULQ™（超低静态电流）功能，可实现较长的电池
寿命
•
可选择运行模式：
TPS568230 具有完整的过压、欠压、过流、过热以及
欠压锁定保护功能。它结合了电源正常信号、输出放电
功能和大负荷运行功能。
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–
–
强制连续导通模式 (FCCM)
Out-of-Audio™(OOA) 模式
高级 Eco-Mode™
•
•
•
•
•
•
•
•
可选 600kHz、800kHz 和 1MHz 开关频率
支持高达 90% 的负荷运行
TPS568230 配备了 MODE 引脚，用于选择所需的运
行模式。为了在轻负载条件下实现高效率，可选择
OOA 模式和高级 Eco-mode™。OOA 模式不允许器件
低于可闻频率（低于 25kHz 开关频率）。FCCM 还符
合严格的输出电压纹波要求。
可调节软启动时间（通过 SS 引脚调节）
电源正常状态输出
内置输出放电功能
逐周期过流保护
TPS568230 同时支持内部和外部软启动时间选项。内
部固定软启动时间为 1.3ms。更长的软启动时间可通
过在 SS 引脚上连接外部电容器来实现。
可提供故障保护的非锁存保护
小型 3.0mm × 3.0mm HotRod™QFN 封装
2 应用
TPS568230 采用 20 引脚 3.0mm x 3.0mm HotRod™
封装，额定结温范围为 -40oC 至 125oC。
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数字电视、机顶盒、游戏机
服务器、存储和网络负载点
器件信息(1)
工业计算机和工厂自动化 应用
器件型号
TPS568230
封装
VQFN (20)
封装尺寸（标称值）
具有典型 5V、12V、15V 输入的分布式电源系统
3.00mm × 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
典型应用
效率与输出电流 ECO 模式
L
100
TPS568230
VIN
VOUT
SW
VIN
95
90
85
80
75
VCC
CIN
CBST
R1
R2
COUT
RM_H
VBST
FB
EN
RM_L
MODE
PGOOD
R5
PGOOD
VCC
SS
70
AGND
GND
Could be floating
Css
C1
VVIN=6V, VOUT=5V,FSW=600kHz
VVIN=8.4V,VOUT=5V,FSW=600kHz
VVIN=12V, VOUT=5V,FSW=600kHz
65
60
0.001
0.01
0.1
I-Load (A)
1
10
D034
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEY5
TPS568230
ZHCSIY3C –MARCH 2019–REVISED AUGUST 2019
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 16
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application ................................................. 18
Power Supply Recommendations...................... 24
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 14
8
9
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 24
11 器件和文档支持 ..................................................... 25
11.1 器件支持 ............................................................... 25
11.2 接收文档更新通知 ................................................. 25
11.3 社区资源................................................................ 25
11.4 商标....................................................................... 25
11.5 静电放电警告......................................................... 25
11.6 Glossary................................................................ 25
12 机械、封装和可订购信息....................................... 25
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (March 2019) to Revision C
Page
•
•
•
•
•
Added VENH min value 1.21V.................................................................................................................................................. 6
Changed VENH typical value from 1.2V to 1.31V .................................................................................................................... 6
Changed VENL min value from 0.8V to 0.95V ......................................................................................................................... 6
Changed VENLtypical value from 1.05V to 1.11V.................................................................................................................... 6
Added VENL max value 1.19V ................................................................................................................................................ 6
Changes from Revision A (February 2019) to Revision B
Page
•
Changed SW negative voltage for DC change from -2V to -1V............................................................................................. 4
Changes from Original (October 2018) to Revision A
Page
•
已更改 将销售状态从“预告信息”更改为“生产数据”。 .............................................................................................................. 1
2
Copyright © 2019, Texas Instruments Incorporated
TPS568230
www.ti.com.cn
ZHCSIY3C –MARCH 2019–REVISED AUGUST 2019
5 Pin Configuration and Functions
RJE Package
20-Pin VQFN
Top View
SW
SW
GND
VCC
NC
18
20
16
19
17
1
15
BST
MODE
3
3
2
14 FB
VIN
4
3
4
13
GND
VIN
AGND
VIN
4
12
11
EN
SS
VIN
5
8
9
6
10
7
NC
PGOOD
GND
GND
SW
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Supply input for the gate drive voltage of the high-side MOSFET. Connect the bootstrap capacitor between
BST and SW, 0.1uF is recommended.
BST
1
I
Input voltage supply pin for the control circuitry. Connect the input decoupling capacitors between VIN and
GND.
VIN
2,3,4,5
P
SW
6,19,20
O
G
Switch node terminal. Connect the output inductor to this pin.
GND
7,8,18,Pad
Power GND terminal for the controller circuit and the internal circuitry.
Open drain power good indicator. It is asserted low if output voltage is out of PGOOD threshold, over
voltage or if the device is under thermal shutdown, EN shutdown or during soft start.
PGOOD
9
O
I
Soft-start time selection pin. Connecting an external capacitor sets the soft-start time and if no external
capacitor is connected, the soft-start time is about 1.3ms.
SS
11
10,16
12
NC
Not connect. Can be connected to GND plane for better thermal achieved.
Enable pin of buck converter. EN pin is a digital input pin, decides turn on or off buck converter. Internal
pull down current to disable converter if leave this pin open.
EN
I
G
I
AGND
FB
13
Ground of internal analog circuitry. Connect AGND to GND plane with a short trace.
Converter feedback input. Connect to the center tap of the resistor divider between output voltage and
AGND.
14
Switching frequency and light load operation mode selection pin. Connect this pin to a resistor divider from
VCC and AGND, the different MODE options are shown in 表 1
MODE
VCC
15
17
I
5.0-V internal VCC LDO output. This pin supplies voltage to the internal circuitry and gate driver. Bypass
this pin with a 1-μF capacitor.
O
Copyright © 2019, Texas Instruments Incorporated
3
TPS568230
ZHCSIY3C –MARCH 2019–REVISED AUGUST 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–1
MAX
22
27
6
UNIT
V
VIN
VBST
V
VBST-SW
V
Input voltage
MODE, FB, SS
6
V
EN
4
V
GND, AGND
SW
0.3
22
23
6
V
V
Output voltage
SW (10-ns transient)
PGOOD
–3
V
–0.3
–40
–55
V
TJ
Operating junction temperature
Storage temperature
150
150
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
V
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22- V C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
18
UNIT
V
VIN
4.5
–0.3
–0.3
–0.3
–0.3
–0.3
–1
VBST
23
V
VBST-SW
MODE, FB, SS
EN
5.5
5.5
3.6
0.3
18
V
Input voltage
V
V
GND, AGND
SW
V
V
Output voltage
SW (10-ns transient)
PGOOD
–3
19
V
–0.3
5.5
8
V
IOUT
TJ
Output current
A
Operating junction temperature
–40
125
°C
4
Copyright © 2019, Texas Instruments Incorporated
TPS568230
www.ti.com.cn
ZHCSIY3C –MARCH 2019–REVISED AUGUST 2019
6.4 Thermal Information
TPS568230
THERMAL METRIC(1)
RJE (VQFN)
20 PINS
44.9
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
32.3
13.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.3
ψJB
13.5
RθJC(bot)
16.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
6.5 Electrical Characteristics
TJ =-40°C to 125°C, VVIN = 12 V, unless otherwise noted
PARAMETER
SUPPLY CURRENT
TEST CONDITION
MIN
TYP
MAX
UNIT
VIN
Input voltage range
VIN supply current
VIN
4.5
18
V
IVIN
No load, VEN=3.3V, non-switching
No load, VEN=0V
105
2
uA
uA
IVINSDN
VCC OUTPUT
Shutdown supply current
VVIN>5.0V
VVIN=4.5V
4.85
20
5
5.15
V
V
VCC
VCC output voltage
VCC current limit
4.5
ICC
mA
FEEDBACK VOLTAGE
TJ = 25°C
594
592
600
600
606
611
mV
mV
VFB
FB voltage
TJ = -40°C to 125°C
DUTY CYCLE and FREQUENCY CONTROL
FSW
Switching frequency
SW minumum on time
SW minimum off time
TJ = 25°C , FSW=600kHz,Vo=1V
TJ = 25°C
600
60
kHz
ns
TON(MIN)
TOFF(MIN)
VFB = 0.5 V
190
ns
MOSFET and DRIVERS
RDS(ON)H
High side switch resistance
TJ = 25°C
TJ = 25°C
19.5
9.5
mΩ
mΩ
RDS(ON)L
Low side switch resistance
OOA FUNCTION
TOOA
OOA mode operation period
28
us
OUTPUT DISCHARGE and SOFT START
RDIS
Discharge resistance
Soft start time
TJ=25°C, VEN=0V
420
1.3
5
Ω
TSS
Internal soft-start time,SS floating
ms
uA
ISS
Soft start charge current
POWER GOOD
TPGDLY
PG start-up delay
PG threshold
PG from low to high
VFB falling (fault)
VFB rising (good)
VFB rising (fault)
VFB falling (good)
IOL =4mA
1
85
ms
%
%
%
%
V
90
VPGTH
115
110
VPG_L
PG sink current capability
PG leak current
0.4
1
IPGLK
VPGOOD =5.5V
uA
CURRENT LIMIT
IOCL
Over current threshold
Valley current set point
8.1
9.8
12
A
Copyright © 2019, Texas Instruments Incorporated
5
TPS568230
ZHCSIY3C –MARCH 2019–REVISED AUGUST 2019
www.ti.com.cn
Electrical Characteristics (continued)
TJ =-40°C to 125°C, VVIN = 12 V, unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
INOCL
Negative over current threshold
3.9
A
LOGIC THRESHOLD
VENH
VENL
IEN
EN high-level input voltage
1.21
0.95
1.31
1.11
2
1.4
V
V
EN low-level input voltage
1.19
Enable internal pull down current VEN=0.8V
µA
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
OVP trip threshold
OVP prop deglitch
UVP trip threshold
UVP prop deglitch
125
20
%
us
%
tOVPDLY
VUVP
TJ=25°C
60
tUVPDLY
256
us
Output hiccup delay relative to
SS time
TUVPDEL
256
7
us
Output hiccup enable delay
relative to SS time
TUVPEN
cycle
UVLO
Wake up
Shutdown
Hysteresis
4.2
3.8
0.4
4.4
V
V
V
VUVLOVIN
VIN UVLO threshold
3.6
OVER TEMPERATURE PROTECTION
TOTP
OTP trip threshold(1)
OTP hysteresis(1)
Shutdown temperature
Hysteresis
150
20
°C
°C
TOTPHSY
(1) Not production tested
6
版权 © 2019, Texas Instruments Incorporated
TPS568230
www.ti.com.cn
ZHCSIY3C –MARCH 2019–REVISED AUGUST 2019
6.6 Typical Characteristics
TJ=-40oC to 125oC, VVIN=12V(unless otherwise noted)
120
118
116
114
112
110
108
106
104
3
2.75
2.5
2.25
2
1.75
1.5
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (OC)
Junction Temperature (OC)
D001
D002
VEN = 3.3 V
图 1. Supply Current vs Junction Temperature
VEN = 0 V
图 2. Shutdown Current vs Temperature
615
610
605
600
595
590
1.36
1.34
1.32
1.3
1.28
1.26
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (OC)
Junction Temperature (OC)
D003
D004
图 3. Feedback Voltage vs Junction Temperature
图 4. Enable On Voltage vs Junction Temperature
1.12
1.11
1.1
27.5
25
22.5
20
1.09
1.08
1.07
1.06
17.5
15
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (OC)
Junction Temperature (OC)
D005
D011
图 5. Enable Off Voltage vs Junction Temperature
图 6. High-Side RDS(on) vs Junction Temperature
版权 © 2019, Texas Instruments Incorporated
7
TPS568230
ZHCSIY3C –MARCH 2019–REVISED AUGUST 2019
www.ti.com.cn
Typical Characteristics (接下页)
TJ=-40oC to 125oC, VVIN=12V(unless otherwise noted)
16
130
128
126
124
122
120
14
12
10
8
6
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (OC)
Juncition Temperature (OC)
D012
D006
图 7. Low-Side RDS(on) vs Junction Temperature
图 8. OVP Threshold vs Junction Temperature
64
440
435
430
425
420
415
63
62
61
60
59
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (OC)
Junction Temperature (OC)
D007
D008
图 9. UVP Threshold vs Junction Temperature
图 10. Discharge Resistor vs Junction Temperature
11
1.35
10.6
10.2
9.8
9.4
9
1.33
1.31
1.29
1.27
1.25
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (OC)
Junction Temperature (OC)
D009
D010
图 11. Valley Current Limit vs Junction Temperature
图 12. Soft-Start Time vs Junction Temperature
8
版权 © 2019, Texas Instruments Incorporated
TPS568230
www.ti.com.cn
ZHCSIY3C –MARCH 2019–REVISED AUGUST 2019
Typical Characteristics (接下页)
TJ=-40oC to 125oC, VVIN=12V(unless otherwise noted)
100
95
90
85
80
75
70
65
60
55
100
90
80
70
60
50
40
30
20
10
0
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
50
45
40
0.001
0.01
0.1
I-Load (A)
1
10
0.001
0.01
0.1
I-Load (A)
1
10
D027
D028
图 13. Efficiency, Eco-mode, FSW = 600 kHz
图 14. Efficiency, OOA-mode, FSW = 600 kHz
100
90
80
70
60
50
40
30
20
10
0
100
95
90
85
80
75
70
65
60
55
50
45
40
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
0.001
0.01
0.1
I-Load (A)
1
10
0.001
0.01
0.1
I-Load (A)
1
10
D029
D030
图 15. Efficiency, FCCM, FSW = 600 kHz
图 16. Efficiency, Eco-mode, FSW = 1 MHz
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
0.001
0.01
0.1
I-Load (A)
1
10
0.001
0.01
0.1
I-Load (A)
1
10
D031
D032
图 17. Efficiency, OOA-mode, FSW = 1 MHz
图 18. Efficiency, FCCM, FSW = 1 MHz
版权 © 2019, Texas Instruments Incorporated
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TPS568230
ZHCSIY3C –MARCH 2019–REVISED AUGUST 2019
www.ti.com.cn
Typical Characteristics (接下页)
TJ=-40oC to 125oC, VVIN=12V(unless otherwise noted)
1
700
600
500
400
300
200
100
0
VVIN=6V, VOUT=5V
VVIN=8.4V,VOUT=5V
VVIN=12V, VOUT=5V
VVIN=5V, VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V, VOUT=1V
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0.001
0.01
0.1
I-Load (A)
1
10
0.001
0.01
0.1
I-Load (A)
1
10
D035
D023
图 19. Load Regulation, Eco-mode, FSW = 600 kHz
图 20. FSW Load Regulation, Eco-mode, FSW = 600 kHz
700
600
500
400
300
200
100
0
800
VVIN=5V, VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V, VOUT=1V
700
600
500
400
VVIN=5V, VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V, VOUT=1V
0.001
0.01
0.1
I-Load (A)
1
10
0.001
0.01
0.1
I-Load (A)
1
10
D036
D037
图 21. FSW Load Regulation, OOA-mode, FSW = 600 kHz
图 22. FSW Load Regulation, FCCM, FSW = 600 kHz
900
900
800
700
600
500
400
300
200
100
0
VVIN=5V, VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V, VOUT=1V
VVIN=5V, VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V, VOUT=1V
800
700
600
500
400
300
200
100
0
0.001
0.01
0.1
I-Load (A)
1
10
0.001
0.01
0.1
I-Load (A)
1
10
D038
D039
图 23. FSW Load Regulation, Eco-mode, FSW = 800 kHz
图 24. FSW Load Regulation, OOA-mode, FSW = 800 kHz
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Typical Characteristics (接下页)
TJ=-40oC to 125oC, VVIN=12V(unless otherwise noted)
1000
800
700
600
500
400
900
800
700
600
VVIN=5V, VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V, VOUT=1V
VVIN=12V,VOUT=1V
VVIN=12V,VOUT=3.3V
VVIN=12V,VOUT=5V
500
0.001
0.01
0.1
I-Load (A)
1
10
0.001
0.01
0.1
I-Load (A)
1
10
D040
D044
图 25. FSW Load Regulation, FCCM, FSW = 800 kHz
图 26. FSW Load Regulation, FCCM, FSW = 600 kHz
1100
1000
900
800
700
600
500
1300
1200
1100
1000
900
VVIN=12V,VOUT=1V
VVIN=12V,VOUT=3.3V
VVIN=12V,VOUT=5V
VVIN=12V,VOUT=1V
VVIN=12V,VOUT=3.3V
VVIN=12V,VOUT=5V
800
700
0.001
0.01
0.1
I-Load (A)
1
10
0.001
0.01
0.1
I-Load (A)
1
10
D045
D046
图 27. FSW Load Regulation, FCCM, FSW = 800 kHz
图 28. FSW Load Regulation, FCCM, FSW = 1 MHz
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7 Detailed Description
7.1 Overview
The TPS568230 is 8-A integrated FET synchronous buck converter which operates from 4.5V to 18V input
voltage (VIN), and the output is from 0.6V to 7V. The proprietary D-CAP3™ mode enables low external
component count, ease of design, optimization of the power design for cost, size and efficiency. The key feature
of the TPS568230 is ultra-low quiescent current (ULQ™) mode. This feature is beneficial for long battery life in
system standby mode. The device employs D-CAP3™ mode control that provides fast transient response with no
external compensation components and an accurate feedback voltage. The control topology provides seamless
transition between CCM operating mode at higher load condition and DCM operation at lighter load condition.
Eco-mode™ allows the TPS568230 to maintain high efficiency at light load. OOA (out of audio) mode makes
switching frequency above audible frequency larger than 25 kHz, even there is no loading at output side. FCCM
mode has the constant switching frequency at both light and heavy load. The TPS568230 is able to adapt to both
low equivalent series resistance (ESR) output capacitors such as POSCAP or SP-CAP, and ultra-low ESR
ceramic capacitors.
12
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7.2 Functional Block Diagram
PG high
threshold
PGOOD
+
+
UV threshold
+
UV
Delay
PG low
threshold
+
OV
VIN
OV threshold
FB
+
LDO
VCC
0.6 V
VREGOK
4.2 V /
3.8 V
+
+
PWM
+
+
Control Logic
VBST
VIN
SS
ñ
ñ
ñ
ñ
ñ
ñ
ñ
On/Off time
Minimum On/Off
TON Extension
OVP/UVP/TSD
OOA/SKIP/FCCM
Soft-Start
Ripple injection
SW
SW
XCON
Internal SS
PGOOD
SS
GND
One shot
+
OCL
ZC
EN threshold
+
+
+
EN
NOCL
THOK
+
150°C /20°C
AGND
Light load operation
/Switching frequency set
Discharge control
MODE
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7.3 Feature Description
7.3.1 PWM Operation and D-CAP3™ Control
The main control loop of the buck is adaptive on-time pulse width modulation (PWM) controller that supports a
proprietary DCAP3™ mode control. The DCAP3™ mode control combines adaptive on-time control with an
internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. The
TPS568230 also includes an error amplifier that makes the output voltage very accurate.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one-shot duration is set proportional to the output voltage, VOUT, and is inversely
proportional to the converter input voltage, VIN, to maintain a pseudo-fixed frequency over the input voltage
range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is
turned on again when the feedback voltage falls below the reference voltage. An internal ripple generation circuit
is added to reference voltage for emulating the output ripple, this enables the use of very low-ESR output
capacitors such as multi-layered ceramic caps (MLCC). No external current sense network or loop compensation
is required for DCAP3™ control topology.
For any control topology that is compensated internally, there is a range of the output filter it can support. The
output filter used with the TPS568230 is a low-pass L-C circuit. This L-C filter has a double-pole frequency
described in 公式 1.
1
fp =
2ìpì LOUTìCOUT
(1)
At low frequency, the overall loop gain is set by the output set-point resistor divider network and the internal gain
of the TPS568230. The low-frequency L-C double pole has a 180 degree drop in phase. At the output filter
frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. The internal ripple
generation network introduces a high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per
decade and leads the 90 degree phase boost. The internal ripple injection high-frequency zero is related to the
switching frequency. The crossover frequency of the overall system should usually be targeted to be less than
one-third of the switching frequency (FSW).
7.3.2 Soft Start
The TPS568230 has an internal 1.3-ms soft start, and also an external SS pin is provided for setting higher soft-
start time if needed. When the EN pin becomes high, the soft-start function begins ramping up the reference
voltage to the PWM comparator.
If the application needs a larger soft start time, it can be set by connecting a capacitor on SS pin. When the EN
pin becomes high, the soft-start charge current (ISS) begins charging the external capacitor (CSS) connected
between SS and AGND. The devices tracks the lower of the internal soft-start voltage or the external soft-start
voltage as the reference. The equation for the soft-start time (TSS) is shown in 公式 2:
Css(nF)ìVREF(V)
T =
ss
Iss(mA)
(2)
where
•
VREF is 0.6 V and ISS is 5 μA
7.3.3 Large Duty Operation
The TPS568230 can support large duty operations by its internal TON extension function. When the VIN/VOUT
<1.6, and the VFB is lower than internal VREF, the TON will be extended to implement the large duty operation and
also improve the performance of the load transient performance.
7.3.4 Power Good
The Power Good (PGOOD) pin is an open-drain output. Once the VFB is between 90% and 110% of the target
output voltage, the PGOOD is de-asserted and floats after a 1-ms de-glitch time. A 100 kΩ pullup resistor is
recommended to pull the voltage up to VCC. The PGOOD pin is pulled low when:
14
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Feature Description (接下页)
•
•
•
the FB pin voltage is lower than 85% or greater than 115% of the target output voltage
in an OVP, UVP, or thermal shutdown event
during the soft-start period.
7.3.5 Over Current Protection and Undervoltage Protection
The TPS568230 has the over current protection and undervoltage protection. The output over current limit (OCL)
is implemented using a cycle-by-cycle valley detect circuit. The switch current is monitored during the OFF state
by measuring the low-side FET drain to source voltage. This voltage is proportional to the switch current. To
improve accuracy, the voltage sensing is temperature compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. If the monitored current is
above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even
the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of over current protection. When the load current is higher
than the over current threshold by one half of the peak-to-peak inductor ripple current, the OCL is triggered and
the current is being limited, the output voltage tends to drop because the load demand is higher than what the
converter can support. When the output voltage falls below 60% of the target voltage, the UVP comparator
detects it, the device will shut off after a wait time of 256us and then re-start after the hiccup time (typically
7*Tss). When the over current condition is removed, the output will be recovered.
7.3.6 Over Voltage Protection
The TPS568230 has the over voltage protection feature. When the output voltage becomes higher than 125% of
the target voltage, the OVP comparator output goes high, the output will be discharged after a wait time of 20 µs.
When the over voltage condition is removed, the output voltage will be recovered.
7.3.7 UVLO Protection
Undervoltage Lockout protection (UVLO) monitors the VIN power input. When the voltage is lower than UVLO
threshold voltage, the device is shut off and output is discharged. This is a non-latch protection.
7.3.8 Output Voltage Discharge
The TPS568230 has the discharge function by using internal MOSFET about 420Ω RDS(on), which is connected
to the output terminal SW. The discharge is slow due to the lower current capability of the MOSFET.
7.3.9 Thermal Shutdown
The TPS568230 monitors the internal die temperature. If the temperature exceeds the threshold value (typically
150°C), the device is shut off and the output will be discharged. This is a non-latched protection, the device
restarts switching when the temperature goes below the thermal shutdown threshold.
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7.4 Device Functional Modes
7.4.1 Light Load Operation
TPS568230 has a MODE pin which can setup three different modes of operation for light load running and 600
kHz/800 kHz/1 MHz switching frequency at heavy load .The light load running includes Out-of-Audio mode ,
Advanced Eco-mode and Force CCM mode.
7.4.2 Advanced Eco-mode™ Control
The advanced Eco-mode™ control scheme to maintain high light load efficiency. As the output current decreases
from heavy load conditions, the inductor current is also reduced and eventually comes to a point where the
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when the zero inductor current is detected. As the load
current further decreases, the converter runs into discontinuous conduction mode. The on-time is kept almost the
same as it was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. This makes the switching frequency lower,
proportional to the load current, and keeps the light load efficiency high. The light load current where the
transition to Eco-mode™ operation happens ( IOUT(LL) ) can be calculated from 公式 3.
(V -VOUT ) × VOUT
1
IN
IOUT(LL)
=
×
2 × LOUT × FSW
V
IN
(3)
After identifying the application requirements, design the output inductance (LOUT) so that the inductor peak-to-
peak ripple current is approximately between 20% and 30% of the IOUT(max) (peak current in the application). It is
also important to size the inductor properly so that the valley current does not hit the negative low-side current
limit.
7.4.3 Out of Audio Mode
Out-of-Audio (OOA) light-load mode is a unique control feature that keeps the switching frequency above audible
frequency towards a virtual no-load condition. During Out-of-Audio operation, the OOA control circuit monitors
the states of both high-side and low-side MOSFETs and forces them switching if both MOSFETs are off for more
than 28 μs. When both high-side and low-side MOSFETs are off for more than 28 μs during a light-load
condition, the lowside FET will be on for discharge till reverse OC happens or output voltage drops to trigger the
high-side FET on. This mode initiates one cycle of the low-side MOSFET and the high-side MOSFET turning on.
Then, both MOSFETs stay turned off waiting for another 28 μs.
If the MODE pin is selected to operate in OOA mode, when the device works at light load, the minimum
switching frequency is above 25 kHz which avoids the audible noise in the system.
7.4.4 Force CCM Mode
Force CCM(FCCM) mode keeps the converter to operate in continuous conduction mode during light-load
conditions and allows the inductor current to become negative. During FCCM mode, the switching frequency
(FSW) is maintained at an almost constant level over the entire load range, which is suitable for applications
requiring tight control of the switching frequency and output voltage ripple at the cost of lower efficiency under
light load.
7.4.5 Mode Selection
The device reads the voltage on the MODE pin during start-up and latches onto one of the MODE options listed
below in 表 1 . The voltage on the MODE pin can be set by connecting this pin to the center tap of a resistor
divider connected between VCC and AGND. A guideline for the top resistor (RM_H) and the bottom resistor (RM_L
)
is shown in 表 1, and 1% resistors are recommended. It is important that the voltage for the MODE pin is derived
from the VCC rail only since internally this voltage is referenced to detect the MODE option. The MODE pin
setting can be reset only by a VIN power cycling or EN toggle.
16
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Device Functional Modes (接下页)
表 1. MODE Pin Resistor Settings
RM_H(kΩ)
330
330
330
300
150
160
110
75
RM_L (kΩ)
LIGHT LOAD OPERATION
Eco-mode
Eco-mode
Eco-mode
OOA mode
OOA mode
OOA mode
FCCM
SWITCHING FREQUENCY (kHz)
5.1
15
27
43
33
51
51
51
51
600
800
1000
600
800
1000
600
FCCM
800
51
FCCM
1000
图 29 below shows the typical start-up sequence of the device once the enable signal crosses the EN turn on
threshold. After the voltage on VCC crosses the rising UVLO threshold it takes about 500us to read the first
mode setting and approximately 100us from there to finish the last mode setting. The output voltage starts
ramping after the mode reading is done.
EN threshold
1.2V
EN
VCC UVLO
4.2V
VCC
MODE9
MODE1
MODE
500us
100us
Tss
90% VOUT
1ms
VOUT
PGOOD
图 29. Power-Up Sequence
7.4.6 Standby Operation
The TPS568230 can be placed in standby mode by pulling the EN pin low. The device operates with a shutdown
current of 2 µA when in standby condition. EN pin is pulled low internally, when float, the part is disabled by
default.
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The schematic of 图 30 shows a typical application for TPS568230 with 1-V output. This design converts an input
voltage range of 4.5 V to 18 V down to 1 V with a maximum output current of 8 A.
8.2 Typical Application
图 30. 1-V, 8-A Reference Design with Eco-mode, FSW = 600 kHz
8.2.1 Design Requirements
表 2 lists the design parameters for this example.
表 2. Design Parameters
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
VOUT
Output voltage
1
V
A
IOUT
Output current
8
ΔVOUT
VIN
Transient response
Input voltage
0 A - 8 A load step,2.5A/us
±40
mV
V
4.5
12
18
18
VOUT(ripple)
FSW
Output voltage ripple
Switching frequency
Light load operating mode
Ambient temperature
mV(P-P)
kHz
600
Eco-mode
25
TA
°C
18
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8.2.2 Detailed Design Procedure
8.2.2.1 External Component Selection
8.2.2.1.1 Output Voltage Set Point
To change the output voltage of the application, it is necessary to change the value of the upper feedback
resistor. By changing this resistor the user can change the output voltage above 0.6 V. See 公式 4
RUPPER
VOUT = 0.6 ì (1+
)
RLOWER
(4)
8.2.2.1.2 Inductor Selection
The inductor ripple current is filtered by the output capacitor. A higher inductor ripple current means the output
capacitor should have a ripple current rating higher than the inductor ripple current. See 表 3 for recommended
inductor values.
The RMS and peak currents through the inductor can be calculated using 公式 5 and 公式 6. It is important that
the inductor is rated to handle these currents.
2
≈
∆
’
÷
≈
∆
∆
«
’
÷
÷
◊
VOUT ì(V
- VOUT )
1
IN(max)
IL
=
I2
+
ì
OUT
(
RMS
)
∆
∆
«
÷
÷
◊
12
V
ìLOUT ìFSW
IN(max)
(5)
(6)
IL(ripple)
IL(peak) = IOUT
+
2
During transient and short-circuit conditions, the inductor current can increase up to the current limit of the device
so it is safe to choose an inductor with a saturation current higher than the peak current under current limit
condition.
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8.2.2.1.3 Output Capacitor Selection
After selecting the inductor the output capacitor needs to be optimized. In DCAP3™, the regulator reacts within
one cycle to the change in the duty cycle so the good transient performance can be achieved without needing
large amounts of output capacitance. The recommended output capacitance range is given in 表 3.
Ceramic capacitors have very low ESR, otherwise the maximum ESR of the capacitor should be less than
VOUT(ripple)/IOUT(ripple)
.
表 3. Recommended Component Values
RUPPER
(kΩ)
VOUT (V)
RLOWER (kΩ)
Fsw (kHz)
LOUT (µH)
COUT(min) (µF)
COUT(max) (µF)
CFF (PF)
600
800
0.47
0.33
0.27
0.68
0.47
0.33
1.5
66
66
66
66
66
66
66
66
66
66
66
66
500
500
500
500
500
500
500
500
500
500
500
500
-
0.6
10
0
-
1000
600
-
-
1
30
20
30
20
800
-
1000
600
-
47-330
47-330
47-330
47-330
47-330
47-330
3.3
5.0
90
800
1.2
1000
600
1
2.2
220
800
1.5
1000
1.2
8.2.2.1.4 Input Capacitor Selection
The TPS568230 requires input decoupling capacitors on power supply input VIN, and the bulk capacitors are
needed depending on the application. The minimum input capacitance required is given in 公式 7.
IOUT×VOUT
CIN(min)
=
V
INripple×V ×FSW
IN
(7)
TI recommends using a high-quality X5R or X7R input decoupling capacitors of 40 µF on the input voltage pin
VIN. The voltage rating on the input capacitor must be greater than the maximum input voltage. The capacitor
must also have a ripple current rating greater than the maximum input current ripple of the application. The input
ripple current is calculated by 公式 8:
VIN(min)-VOUT
(
)
VOUT
ICIN(rms) = IOUT ×
×
VIN(min)
VIN(min)
(8)
A 1-µF ceramic capacitor is needed for the decoupling capacitor on VCC pin.
20
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8.2.3 Application Curves
图 31 through 图 44 apply to the circuit of 图 30. VIN = 12 V. TJ = 25°C unless otherwise specified.
95
90
85
80
75
70
65
60
55
50
45
40
1
0.8
0.6
0.4
0.2
0
VVIN=5V, VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V, VOUT=1V
-0.2
-0.4
-0.6
-0.8
-1
VVIN=5V, VOUT=1V,FSW=600kHz
VVIN=8.4V,VOUT=1V,FSW=600kHz
VVIN=12V, VOUT=1V,FSW=600kHz
0.001
0.01
0.1
I-Load (A)
1
10
0.001
0.01
0.1
I-Load (A)
1
10
D033
D019
图 31. Efficiency Curve
图 32. Load Regulation
800
700
600
500
400
300
200
700
600
500
400
300
200
100
0
VVIN=5V, VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V, VOUT=1V
4
6
8
10
VIN (V)
12
14
16
18
0
1
2
3
4
I-Load (A)
5
6
7
8
D025
D047
IOUT = 8 A
图 33. Switching Frequency vs Input Voltage
图 34. Switching Frequency vs Output Load
0.1
0.08
0.06
0.04
0.02
0
1
0.8
0.6
0.4
0.2
0
-0.02
-0.04
-0.06
-0.08
-0.1
-0.2
-0.4
-0.6
-0.8
-1
4
6
8
10
12
14
16
18
4
6
8
10
12
14
16
18
VIN (V)
VIN (V)
D021
D021
图 35. Line Regulation,IOUT = 0.01 A
图 36. Line Regulation,IOUT = 8 A
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Vout=20mV/div (AC coupled)
Vout=20mV/div (AC coupled)
SW=5V/div
SW=5V/div
200us/div
2us/div
图 37. Output Voltage Ripple, IOUT = 0.01 A
图 38. Output Voltage Ripple, IOUT = 8 A
EN=2V/div
EN=2V/div
Vout=1V/div
Vout=1V/div
IL=5A/div
IL=5A/div
2ms/div
400us/div
图 39. Start-Up Through EN, IOUT = 4A
图 40. Shut-down Through EN, IOUT = 4A
Vin=10V/div
Vout=1V/div
Vin=10V/div
Vout=1V/div
IL=5A/div
IL=5A/div
4ms/div
4ms/div
图 42. Start Up Relative to VIN Falling, IOUT = 4 A
图 41. Start Up Relative to VIN Rising, IOUT = 4 A
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Vout=50mV/div (AC coupled)
Vout=50mV/div (AC coupled)
Iout=5A/div
Iout=5A/div
200us/div
200us/div
Slew Rate=2.5A/us
Slew Rate=2.5A/us
图 43. Transient Response, 0.8 A to 7.2 A
图 44. Transient Response, 0 A to 8 A
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9 Power Supply Recommendations
The TPS568230 is intended to be powered by a well regulated dc voltage. The input voltage range is 4.5 to 23 V.
TPS568230 is a buck converter. The input supply voltage must be greater than the desired output voltage for
proper operation. Input supply current must be appropriate for the desired output current. If the input voltage
supply is located far from the TPS568230 circuit, additional input bulk capacitance is recommended, typical
values are 100 μF to 470 μF.
10 Layout
10.1 Layout Guidelines
•
Recommend a four-layer PCB for good thermal performance and with maximum ground plane. 3-inch × 3-
inch, four-layer PCB with 2-oz copper is used as example.
•
•
Place the decoupling capacitors right across VIN and VCC as close as possible.
Place output inductor and capacitors with IC at the same layer, SW routing should be as short as possible to
minimize EMI, and should be a width plane to carry big current, enough vias should be added to the GND
connection of output capacitor and also as close to the output pin as possible.
•
•
Place BST resistor and capacitor with IC at the same layer, close to BST and SW plane, >15 mil width trace
is recommended to reduce line parasitic inductance.
Feedback could be 20mil and must be routed away from the switching node, BST node or other high
efficiency signal.
•
•
VIN trace must be wide to reduce the trace impedance and provide enough current capability.
Place multiple vias under the device near VIN and GND and near input capacitors to reduce parasitic
inductance and improve thermal performance
10.2 Layout Example
图 45 shows the recommended top-side layout. Component reference designators are the same as the circuit
shown in 图 30. Resistor divider for EN is not used in the circuit of 图 30, but are shown in the layout for
reference.
VIN
VOUT
SW
GND
GND
AGND
图 45. Top-Layer Layout
24
版权 © 2019, Texas Instruments Incorporated
TPS568230
www.ti.com.cn
ZHCSIY3C –MARCH 2019–REVISED AUGUST 2019
11 器件和文档支持
11.1 器件支持
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
D-CAP3, ULQ, Out-of-Audio, Eco-Mode, HotRod, DCAP3, Eco-mode, E2E are trademarks of Texas Instruments.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2019, Texas Instruments Incorporated
25
PACKAGE OPTION ADDENDUM
www.ti.com
24-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS568230RJER
TPS568230RJET
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
RJE
RJE
20
20
3000 RoHS & Green Call TI | SN | NIPDAU Level-2-260C-1 YEAR
250 RoHS & Green Call TI | SN | NIPDAU Level-2-260C-1 YEAR
-40 to 125
-40 to 125
568230
568230
Samples
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Mar-2023
Addendum-Page 2
GENERIC PACKAGE VIEW
RJE 20
3 x 3, 0.45 mm pitch
VQFN-HR - 1 mm max height
QUAD FLATPACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224683/A
www.ti.com
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RJE0020A
3.1
2.9
A
B
ꢆꢇꢄ;ꢀꢁꢀꢈꢉꢊ7<3
(0.25)
DETAIL A
CHAMFERS ARE OPTIONAL
TYPICAL
3.1
2.9
PIN 1 INDEX AREA
0.5
0.3
0.25
0.15
DETAIL B
OPTIONAL PIN 1
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 1.8
PKG
(0.1) TYP
SEE TERMINAL
DETAIL A
10
6
16X 0.45
11
5
(0.018)
PKG
2X
1.8
ꢀꢁꢃꢂꢀꢁꢅ
21
0.25
20X
0.15
0.1
C B A
C
1
15
0.05
16
20
(0.06)
PIN 1 ID
DETAIL B
0.5
0.3
20X
ꢀꢁꢂꢃꢄꢀꢁꢅ
4223546 / B 08/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RJE0020A
(0.675)
(0.06)
20
16
20X (0.6)
20X (0.2)
1
15
(0.018)
16X (0.45)
21
PKG
(2.8)
(0.76)
11
5
(R0.05) TYP
6
10
PKG
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
SOLDER MASK
OPENING
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
DEFINED
NON- SOLDER MASK
DEFINED
(PAD 21)
SOLDER MASK DETAILS
4223546 / B 08/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RJE0020A
(0.64)
(0.06)
20
16
20X (0.6)
20X (0.2)
1
15
(0.018)
(0.72)
16X (0.45)
21
PKG
(2.8)
5
11
(R0.05) TYP
10
6
PKG
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PAD 21: 90%
SCALE: 20X
4223546 / B 08/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
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Copyright © 2023，德州仪器 (TI) 公司
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