TPS568215RNNR [TI]
具有 D-CAP3 控制功能的 4.5V 至 17V、8A 同步 SWIFT™ 降压转换器 | RNN | 18 | -40 to 125;
| 型号： | TPS568215RNNR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 D-CAP3 控制功能的 4.5V 至 17V、8A 同步 SWIFT™ 降压转换器 | RNN | 18 | -40 to 125 开关 输出元件 转换器 |
| 文件： | 总36页 (文件大小：1408K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS568215
ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
TPS568215 4.5V 至 17V 输入、8A 同步降压 SWIFT™ 转换器
1 特性
•
IPC 和工厂自动化
1
•
集成 19mΩ 和 9.4mΩ 金属氧化物半导体场效应晶
3 说明
体管 (MOSFET)
TPS568215 是 TI 旗下最小的一款单片 8A 同步降压转
换器，具有自适应导通时间 D-CAP3™ 控制模式。该
器件集成了 RDS(on) 较低的功率 MOSFET，简单易用
并且高效运行，所需外部组件最少，适用于空间受限的
电源系统。主要 特性 包括非常精确的基准电压、快速
负载瞬时响应、提升轻载效率的自动跳跃工作模式、可
调节电流限值并且无需外部补偿。强制持续传导模式有
助于满足高性能 DSP 和 FPGA 应用的严格电压调节精
度要求。TPS568215 采用耐热增强型 18 引脚
•
•
•
•
•
•
可选 FSW：400kHz、800kHz 和 1.2MHz
可调节电流限制设置，具有断续重启功能
整个温度范围内的基准电压为 0.6V ±1%
支持 5V 外部可选偏置功能，以提升效率
D-CAP3™针对快速瞬态响应的控制模式
实现精密输出电压纹波的可选强制连续导通模式
(FCCM) 或实现高轻载效率的自动跳跃 Eco-
mode™
•
•
•
•
•
•
0.6V 至 5.5V 输出电压范围
支持陶瓷输出电容
HotRod™ 四方扁平无引线 (QFN) 封装，经设计在 -
40°C 至 150°C 的结温范围内额定运行。TPS568215
与 TPS56C215 引脚兼容，因此用户可以在 6A 至 12A
范围内灵活选择采用同一封装的解决方案。
针对预偏置输出的单调性启动
可调节软启动，默认软启动时间为 1ms
-40°C 至 150°C 运行结温
小型 3.5mm x 3.5mm HotRod™四方扁平无引线
(QFN) 封装
由 WEBENCH®设计中心提供支持
器件信息(1)
器件型号
TPS568215
封装
VQFN (18)
封装尺寸（标称值）
•
3.5mm x 3.5mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
2 应用
•
•
•
服务器和存储
空白
空白
机顶盒和高端数字电视 (DTV)
网络互联和电信、负载点 (POL)
典型应用电路原理图
效率与输出电流间的关系
100
95
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VLb=12V, VhÜÇ=1.2V, F{í= 400kHz
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4
5
6
7
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Output Current (A)
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1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSDI8
TPS568215
ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 18
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application ................................................. 19
Power Supply Recommendations...................... 24
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Timing Requirements................................................ 7
6.7 Typical Characteristics.............................................. 8
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 14
8
9
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 25
11 器件和文档支持 ..................................................... 28
11.1 器件支持 ............................................................... 28
11.2 接收文档更新通知 ................................................. 28
11.3 社区资源................................................................ 28
11.4 商标....................................................................... 28
11.5 静电放电警告......................................................... 28
11.6 Glossary................................................................ 28
12 机械、封装和可订购信息....................................... 28
7
4 修订历史记录
Changes from Original (October 2016) to Revision A
Page
•
•
已更改 产品预览至量产数据发布 ............................................................................................................................................ 1
Added Specifications ............................................................................................................................................................. 4
2
Copyright © 2016, Texas Instruments Incorporated
TPS568215
www.ti.com.cn
ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
5 Pin Configuration and Functions
RNN Package
18-Pin VQFN
BOTTOM VIEW
TOP VIEW
AGND 12
VIN 11
1 BOOT
BOOT 1
VIN 2
12 AGND
11 VIN
2 VIN
PGND 10
PGND 9
PGND 8
3 PGND
4 PGND
5 PGND
PGND 3
PGND 4
PGND 5
10 PGND
9 PGND
8 PGND
7
6
6
7
SW
SW
Pin Functions
PIN
NAME
I/O DESCRIPTION
NO.
Supply input for the gate drive voltage of the high-side MOSFET. Connect a 0.1uF bootstrap capacitor
between BOOT and SW.
1
BOOT
VIN
I
Input voltage supply pin for the control circuitry. Connect the input decoupling capacitors between VIN and
PGND.
2,11
P
G
3, 4, 5,
8, 9, 10
PGND
Power GND terminal for the controller circuit and the internal circuitry.
6, 7
12
SW
O
G
I
Switch node terminal. Connect the output inductor to this pin.
AGND
FB
Ground of internal analog circuitry. Connect AGND to PGND plane.
Converter feedback input. Connect to the resistor divider between output voltage and AGND.
13
Soft-Start time selection pin. Connecting an external capacitor sets the soft-start time and if no external
capacitor is connected, the soft-start time in 1ms.
14
SS
O
Enable input control, leaving this pin floating enables the converter. It can also be used to adjust the input
UVLO by connecting to the resistor divider between VIN and EN.
15
16
17
18
EN
I
O
I/O
I
Open Drain Power Good Indicator, it is asserted low if output voltage is out of PGOOD threshold,
Overvoltage or if the device is under thermal shutdown, EN shutdown or during soft start.
PGOOD
VREG5
MODE
4.7-V internal LDO output which can also be driven externally with a 5V input. This pin supplies voltage to
the internal circuitry and gate driver. Bypass this pin with a 4.7-μF capacitor.
Switching Frequency, Current Limit selection and Light load operation mode selection pin. Connect this pin
to a resistor divider from VREG5 and AGND for different MODE options shown in table 4.
Copyright © 2016, Texas Instruments Incorporated
3
TPS568215
ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–2
MAX
20
UNIT
VIN
SW
19
SW(10 ns transient)
–3
20
EN
Input Voltage
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
6.5
6.5
25.5
6.5
6
V
BOOT –SW
BOOT
SS, MODE, FB
VREG5
Output Voltage PGOOD
6.5
V
A
Output
IOUT
10
Current(2)
TJ
Operating junction temperature
Storage temperature
–40
–55
150
150
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) In order to be consistent with the TI reliability requirement of 100k Power-On-Hours at 105°C junction temperature, the output current
should not exceed 10A continuously under 100% duty operation as to prevent electromigration failure in the solder. Higher junction
temperature or longer power-on hours are achievable at lower than 10A continuos output current.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
17
UNIT
VIN
SW
–1.8
–0.1
–0.1
17
Input Voltage
V
BOOT
VREG5
23.5
5.2
Output
Current
ILOAD
0
8
A
Operating
junction
TJ
-40
150
°C
temperature
4
Copyright © 2016, Texas Instruments Incorporated
TPS568215
www.ti.com.cn
ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
6.4 Thermal Information
RNN PACKAGE
UNIT
THERMAL METRIC(1)
18 PINS
RθJA
Junction-to-ambient thermal resistance
42.3
23.9
10.0
0.5
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
10.0
0.5
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2016, Texas Instruments Incorporated
5
TPS568215
ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
www.ti.com.cn
MAX UNIT
6.5 Electrical Characteristics
TJ = –40°C to 150°C, VIN=12V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
SUPPLY CURRENT
IIN
VIN supply current
TJ = 25°C, VEN=5 V, non switching
TJ = 25°C, VEN=0 V
600
7
700
µA
µA
IVINSDN
VIN shutdown current
LOGIC THRESHOLD
VENH
VENL
EN H-level threshold voltage
1.175
1.025
1.225
1.104
0.121
1.91
1.3
V
V
EN L-level threshold voltage
1.15
VENHYS
IENp1
V
VEN = 1.0 V
VEN = 1.3 V
0.35
3
2.95
5.5
µA
µA
EN pull-up current
IENp2
4.197
FEEDBACK VOLTAGE
TJ = 25°C
598
597.5
594
600
600
600
600
602
602.5
602.5
606
mV
mV
mV
mV
TJ = 0°C to 85°C
TJ = –40°C to 85°C
TJ = –40°C to 150°C
VFB
FB voltage
594
LDO VOLTAGE
VREG5
LDO Output voltage
TJ = –40°C to 150°C
TJ = –40°C to 150°C
4.58
100
4.7
4.83
200
V
ILIM5
LDO Output Current limit
150
mA
MOSFET
RDS(on)H
RDS(on)L
High side switch resistance
Low side switch resistance
TJ = 25°C, VVREG5 = 4.7 V
TJ = 25°C, VVREG5 = 4.7 V
19
mΩ
mΩ
9.4
SOFT START
Iss
Soft start charge current
TJ = -40°C to 150°C
4.9
6
7.1
µA
CURRENT LIMIT
ILIM-1 option, Valley Current
ILIM option, Valley Current
Valley Current
6
8
7.1
9.4
3
8.15
10.8
A
A
A
Current Limit (Low side sourcing)
IOCL
Current Limit (Low side negative)
PGOOD threshold
POWER GOOD
VFB falling (fault)
VFB rising (good)
VFB rising (fault)
VFB falling (good)
84%
93%
VPGOODTH
116%
107%
OUTPUT UNDERVOLTAGE PROTECTION
VUVP Output UVP threshold
THERMAL SHUTDOWN
68% x
VFB
Hiccup detect
Shutdown temperature
Hysteresis
160
15
°C
°C
°C
°C
TSDN
Thermal shutdown threshold
Shutdown temperature
Hysteresis
171
18
TSDN VREG5
VREG5 thermal shutdown threshold
UVLO
VREG5 rising voltage
VREG5 falling voltage
VREG5 hysteresis
4.1
4.3
3.57
730
4.5
V
V
UVLO
UVLO threshold
3.34
mV
6
Copyright © 2016, Texas Instruments Incorporated
TPS568215
www.ti.com.cn
ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
6.6 Timing Requirements
PARAMETER
CONDITIONS
MIN
TYP
MAX UNIT
ON-TIME TIMER CONTROL
tON
SW On Time
VIN = 12 V, VOUT=3.3 V, FSW = 800 kHz
VIN = 17 V, VOUT=0.6 V, FSW= 1200 kHz
25°C, VFB=0.5 V
310
340
54
380
310
ns
ns
ns
tON min
tOFF
SW Minimum on time
SW Minimum off time
SOFT START
tSS Soft start time
Internal soft start time
1.045
ms
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
tUVPDEL
Output Hiccup delay relative to SS time
UVP detect
1
7
cycle
cycle
Output Hiccup enable delay relative to
SS time
tUVPEN
UVP detect
版权 © 2016, Texas Instruments Incorporated
7
TPS568215
ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
www.ti.com.cn
6.7 Typical Characteristics
1000
900
800
700
600
500
400
300
200
20
18
16
14
12
10
8
6
4
2
VLb = 12V
150
V
Lb =12V
0
0
50
100
0
50
100
150
œ50
œ50
œ50
œ50
œ50
œ50
TJ - Junction Temperature (°C)
TJ - Junction Temperature (°C)
C001
C002
图 1. Quiescent Current vs Temperature
图 2. Shutdown Current vs Temperature
0.603
0.602
0.601
0.6
30
25
20
15
10
0.599
0.598
0.597
VLb =12V
VLb =12V
0
50
100
150
0
50
100
150
TJ - Junction Temperature (°C)
TJ - Junction Temperature (°C)
C003
C004
图 3. Feedback Voltage vs Temperature
图 4. High-side Rdson vs Temperature
15
14
13
12
11
10
9
8
7
6
5
4
8
7
6
VLb =12V
V
Lb =12V
5
0
50
100
150
0
50
100
150
TJ - Junction Temperature (°C)
TJ - Junction Temperature (°C)
C005
C006
图 5. Low-side Rdson vs Temperature
图 6. Soft-Start Charge Current vs Temperature
8
版权 © 2016, Texas Instruments Incorporated
TPS568215
www.ti.com.cn
ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
Typical Characteristics (接下页)
3
6
5.5
5
2.5
2
4.5
4
1.5
1
3.5
3
VLb =12V
V =12V
Lb
0
50
100
150
0
50
100
150
œ50
œ50
TJ - Junction Temperature (°C)
TJ - Junction Temperature (°C)
C007
C008
图 7. Enable Pull-Up Current, VEN =1.0V
图 8. Enable Pull-Up Current, VEN =1.3V
120
115
110
105
100
95
12
11
10
9
ILIM option
ILIM-1 Option
VC. rising
VC. falling
VC. rising
VC. falling
8
90
7
85
80
6
1
2
3
4
5
6
7
8
9
10
0
50
100
150
œ50
TJ - Junction Temperature (°C)
TJ - Junction Temperature (°C)
C009
C010
图 9. PGOOD Threshold vs Temperature
图 10. Valley Current Limit vs Temperature
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
hÜÇ= 1.2V, F{í = 400kHz
hÜÇ= 1.2V, F{í= 800kHz
hÜÇ= 1.2V, F{í = 1200kHz
V
Lb = 12V, VhÜÇ= 1.2V
= 12V, VhÜÇ= 3.3V
V
V
Lb
VLb = 12V, VhÜÇ= 5.5V
V
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
Output Current (A)
Ouput Current(A)
C013
C022
图 12. Efficiency, Mode = DCM, FSW = 400kHz
图 11. Efficiency with Internal VREG5 = 4.7 V, VIN = 12 V
版权 © 2016, Texas Instruments Incorporated
9
TPS568215
ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
www.ti.com.cn
Typical Characteristics (接下页)
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
10
0
V
= 12V, VhÜÇ= 1.2V
V
V
V
Lb = 12V, VhÜÇ= 1.2V
Lb = 12V, VhÜÇ= 3.3V
Lb = 12V, VhÜÇ= 5.5V
Lb
VLb = 12V, VhÜÇ= 3.3V
10
0
VLb = 12V, VhÜÇ= 5.5V
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
Output Current (A)
Output Current (A)
C014
C015
图 13. Efficiency, Mode = FCCM, FSW = 400kHz
图 14. Efficiency, Mode = DCM, FSW = 1200kHz
100
90
80
70
60
50
40
30
20
10
0
1.198
1.197
1.196
1.195
1.194
VLb = 4.5V, VhÜÇ= 1.2V
VLb = 12V, VhÜÇ= 1.2V
VLb = 12V, VhÜÇ= 1.2V
VLb = 12V, VhÜÇ= 3.3V
VLb = 17V,VhÜÇ= 1.2V
VLb = 12V, VhÜÇ= 5.5V
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
Output Current (A)
Output Current (A)
C016
C017
图 15. Efficiency, Mode = FCCM, FSW = 1200kHz
图 16. Load Regulation, FSW = 400kHz
600
500
400
300
200
1000
900
800
700
600
V
= 12V, VhÜÇ= 1.2V
= 12V, VhÜÇ= 3.3V
Lb
V
Lb
VLb = 12V, VhÜÇ= 5.5V
V
= 12V,VhÜÇ= 1.2V
Lb
VLb = 12V,VhÜÇ= 3.3V
VLb = 12V,VhÜÇ= 5.5V
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
Output Current (A)
Output Current (A)
C018
C019
图 17. FSW Load Regulation, Mode = FCCM, FSW = 400kHz
图 18. FSW Load Regulation, Mode = FCCM, FSW = 800kHz
10
版权 © 2016, Texas Instruments Incorporated
TPS568215
www.ti.com.cn
ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
Typical Characteristics (接下页)
1400
1400
1200
1000
800
600
400
200
0
V
= 12V, VhÜÇ= 1.2V
Lb
VLb = 12V, VhÜÇ= 3.3V
VLb = 12V, VhÜÇ= 5.5V
1300
1200
1100
1000
F{í= 400kHz
F{í= 800kHz
F{í= 1200kHz
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
Output Current (A)
Load Current (A)
C020
C021
图 19. FSW Load Regulation, Mode = FCCM, FSW = 1200kHz
图 20. FSW Load Regulation, Mode = DCM, VIN = 12V,
VOUT=1.2V
版权 © 2016, Texas Instruments Incorporated
11
TPS568215
ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TPS568215 is a high density synchronous step down buck converter which can operate from 4.5-V to 17-V
input voltage (VIN). It has 19-mΩ and 9-mΩ integrated MOSFETs that enable high efficiency up to 8 A. The
device employs D-CAP3™ mode control that provides fast transient response with no external compensation
components and an accurate feedback voltage. The control topology provides seamless transition between
FCCM operating mode at higher load condition and DCM/Eco-mode™ operation at lighter load condition.
DCM/Eco-mode™ allows the TPS568215 to maintain high efficiency at light load. The TPS568215 is able to
adapt to both low equivalent series resistance (ESR) output capacitors such as POSCAP or SP-CAP, and
ultralow ESR ceramic capacitors.
The TPS568215 has three selectable switching frequencies (FSW) 400kHz, 800kHz and 1200kHz which gives the
flexibility to optimize the design for higher efficiency or smaller size. There are two selectable current limits. All
these options are configured by choosing the right voltage on the MODE pin.
The TPS568215 has a 4.7 V internal LDO that creates bias for all internal circuitry. There is a feature to
overdrive this internal LDO with an external voltage on the VREG5 pin which improves the converter’s efficiency.
The undervoltage lockout (UVLO) circuit monitors the VREG5 pin voltage to protect the internal circuitry from low
input voltages. The device has an internal pull-up current source on the EN pin which can enable the device
even with the pin floating.
Soft-start time can be selected by connecting a capacitor to the SS pin. The device is protected from output
short, undervoltage and over temperature conditions.
12
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TPS568215
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ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
7.2 Functional Block Diagram
PG rising threshold
TPS568215
+
PGOOD
PGOOD Logic
UV
UV threshold
+
+
Delay
UVP / OVP
Logic
VREG5
PG falling threshold
+
OV threshold
LDO
OV
VIN
UVLO
Internal Ramp
+
BOOT
BOOT
-
VREF
-
+
+
Error Amp
Control Logic
+
FB
-
ñ
ñ
ñ
ñ
ñ
ñ
ñ
On Time
Min On Time/Off Time
FCCM/SKIP
Soft-Start
Power Good
SW
SW
ó/hb
Internal SS
One shot
VREG5
Internal/External VREG5
UVP/TSD
SS
PGND
Light Load Operation/
Current Limit/
Switching Frequency
MODE
TSD 160C/171C
SW
OCL
+
Ip1 Ip2
EN
+
ZC
+
Enable Threshold
NOCL
+
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13
TPS568215
ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
www.ti.com.cn
7.3 Feature Description
7.3.1 PWM Operation and D-CAP3™ Control
The TPS568215 operates using the adaptive on-time PWM control with a proprietary D-CAP3™ control which
enables low external component count with a fast load transient response while maintaining a good output
voltage accuracy. At the beginning of each switching cycle the high side MOSFET is turned on for an on-time set
by an internal one shot timer. This on-time is set based on the converter’s input voltage, output voltage and the
pseudo-fixed frequency hence this type of control topology is called an adaptive on-time control. The one shot
timer resets and turns on again once the feedback voltage (VFB) falls below the internal reference voltage (VREF).
An internal ramp is generated which is fed to the FB pin to simulate the output voltage ripple. This enables the
use of very low-ESR output capacitors such as multi-layered ceramic caps (MLCC). No external current sense
network or loop compensation is required for DCAP3™ control topology.
The TPS568215 includes an error amplifier that makes the output voltage very accurate. This error amplifier is
absent in other flavors of DCAP3™. For any control topology that is compensated internally, there is a range of
the output filter it can support. The output filter used with the TPS568215 is a low pass L-C circuit. This L-C filter
has double pole that is described in
1
¦
=
P
2´ p´ LOUT ´ COUT
(1)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS568215. The low frequency L-C double pole has a 180 degree in phase. At the output filter
frequency, the gain rolls off at a –40dB per decade rate and the phase drops rapidly. The internal ripple
generation network introduces a high-frequency zero that reduces the gain roll off from –40dB to –20dB per
decade and increases the phase to 90 degree one decade above the zero frequency. The internal ripple injection
high frequency zero is changed according to the switching frequency selected as shown in table below. The
inductor and capacitor selected for the output filter must be such that the double pole is located close enough to
the high-frequency zero so that the phase boost provided by this high-frequency zero provides adequate phase
margin for the stability requirement. The crossover frequency of the overall system should usually be targeted to
be less than one-fifth of the switching frequency (FSW).
表 1. Ripple Injection Zero
Switching Frequency (kHz)
Zero Location (kHz)
400
800
7.1
14.3
21.4
1200
表 2 lists the inductor values and part numbers that are used to plot the efficiency curves in the Typical
Characteristics section.
表 2. Inductor Values
Würth Part
VOUT(V)
FSW(kHz)
LOUT(uH)
Number(1)
744325120
744311068
744314047
744325240
744314150
744314110
744325330
744325240
744325120
400
800
1.2
0.68
0.47
2.4
1.2
1200
400
3.3
5.5
800
1.5
1200
400
1.1
3.3
800
2.4
1200
1.2
(1) See Third-Party Products disclaimer
14
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TPS568215
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ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
7.3.2 Eco-mode™ Control
The TPS568215 is designed with Eco-mode™ control to increase efficiency at light loads. This option can be
chosen using the MODE pin as shown in table 3. As the output current decreases from heavy load condition, the
inductor current is also reduced. If the output current is reduced enough, the valley of the inductor current
reaches the zero level, which is the boundary between continuous conduction and discontinuous conduction
modes. The low-side MOSFET is turned off when a zero inductor current is detected. As the load current further
decreases the converter runs into discontinuous conduction mode. The on-time is kept approximately the same
as it is in continuous conduction mode. The off-time increases as it takes more time to discharge the output with
a smaller load current. The light load current where the transition to Eco-mode™ operation happens ( IOUT(LL)
)
can be calculated from 公式 2.
(V -VOUT ) × VOUT
1
IN
IOUT(LL)
=
×
2 × LOUT × FSW
V
IN
(2)
After identifying the application requirements, design the output inductance so that the inductor peak-to-peak
ripple current is approximately between 20% and 30% of the ICC(ma×) (peak current in the application). it is also
important to size the inductor properly so that the valley current doesn't hit the negative low side current limit.
7.3.3 4.7 V LDO and External Bias
The VREG5 pin is the output of the internal 4.7-V linear regulator that creates the bias for all the internal circuitry
and MOSFET gate drivers. The VREG5 pin needs to be bypassed with a 4.7-µF capacitor. An external voltage
that is above the LDO's internal output voltage can override the internal LDO, switching it to the external rail once
a higher voltage is detected. This enhances the efficiency of the converter because the quiescent current now
runs off this external rail instead of the input power supply. The UVLO circuit monitors the VREG5 pin voltage
and disables the output when VREG5 falls below the UVLO threshold. When using an external bias on the
VREG5 rail, any power-up and power-down sequencing can be applied but it is important to understand that if
there is a discharge path on the VREG5 rail that can pull a current higher than the internal LDO's current limit
(ILIM5) from the VREG5, then the VREG5 LDO turns off thereby shutting down the output of TPS568215. If such
condition does not exist and if the external VREG5 rail is turned off, the VREG5 voltage switches over to the
internal LDO voltage which is 4.7 V typically in a few nanoseconds. Figure 26 below shows this transition of the
VREG5 voltage from an external bias of 5.5 V to the internal LDO output of 4.7 V when the external bias to
VREG5 is disabled while the output of TPS568215 remains unchanged.
7.3.4 MODE Selection
TPS568215 has a MODE pin that can offer 12 different states of operation as a combination of Current Limit,
Switching Frequency and Light Load operation. The device can operate at two different current limits ILIM-1 and
ILIM to support an output continuous current of 6 A, 8 A respectively. The TPS568215 is designed to compare
the valley current of the inductor against the current limit thresholds so it is important to understand that the
output current will be half the ripple current above the valley current. TPS568215 can operate at three different
frequencies of 400 kHz, 800 kHz and 1200 kHz and also can choose between Eco-mode™ and FCCM mode.
The device reads the voltage on the MODE pin during start-up and latches onto one of the MODE options listed
below in table 3. The voltage on the MODE pin can be set by connecting this pin to the center tap of a resistor
divider connected between VREG5 and AGND. A guideline for the top resistor (RM_H) and the bottom resistor
(RM_L) as 5% resistors is shown in Table 3. It is important that the voltage for the MODE pin is derived from the
VREG5 rail only since internally this voltage is referenced to detect the MODE option. The MODE pin setting can
be reset only by a VIN power cycling.
表 3. Mode Pin Resistor Settings
RM_L (kΩ)
RM_H (kΩ)
Light Load
Operation
Current Limit
Frequency (kHz)
5.1
10
20
20
51
51
51
300
200
160
120
200
180
150
FCCM
FCCM
FCCM
FCCM
FCCM
FCCM
DCM
ILIM-1
ILIM
400
400
ILIM-1
ILIM
800
800
ILIM-1
ILIM
1200
1200
400
ILIM-1
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www.ti.com.cn
表 3. Mode Pin Resistor Settings (接下页)
51
51
51
51
51
120
91
82
62
51
DCM
DCM
DCM
DCM
DCM
ILIM
ILIM-1
ILIM
400
800
800
ILIM-1
ILIM
1200
1200
图 21 below shows the typical start-up sequence of the device once the enable signal crosses the EN turn-on
threshold. After the voltage on VREG5 crosses the rising UVLO threshold it takes about 500us to read the first
mode setting and approximately 100us from there to finish the last mode setting. The output voltage starts
ramping after the mode reading is done.
9b tꢁresꢁold
1.2ë
9b
ëw9D5 Üë[h
4.3ë
ëw9D5
ahꢀ916
ahꢀ91
ahꢀ9
500us
100us
tss(1ms)
ëhÜÇ
图 21. Power-Up Sequence
7.3.5 Soft Start and Pre-biased Soft Start
The TPS568215 has an adjustable soft-start time that can be set by connecting a capacitor on SS pin. When the
EN pin becomes high, the soft-start charge current (ISS) begins charging the external capacitor (CSS) connected
between SS and AGND. The devices tracks the lower of the internal soft-start voltage or the external soft-start
voltage as the reference. The equation for the soft-start time (TSS) is shown in 公式 3:
CSS × VREF
TSS(S)
=
ISS
where
•
VREF is 0.6 V and ISS is 6 µA
(3)
If the output capacitor is pre-biased at startup, the device initiates switching and starts ramping up only after the
internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the
converters ramp up smoothly into regulation point.
16
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TPS568215
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ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
7.3.6 Enable and Adjustable UVLO
The EN pin controls the turn-on and turn-off of the device. When EN pin voltage is above the turn-on threshold
which is around 1.2 V, the device starts switching and when the EN pin voltage falls below the turn-off threshold
which is around 1.1V it stops switching. If the user application requires a different turn-on (VSTART) and turn-off
thresholds (VSTOP) respectively, the EN pin can be configured as shown in 图 22 by connecting a resistor divider
between VIN and EN. The EN pin has a pull-up current Ip1 that sets the default state of the pin when it is floating.
This current increases to Ip2 when the EN pin voltage crosses the turn-on threshold. The UVLO thresholds can
be set by using 公式 4 and 公式 5.
TPS568215
VIN
Ip1
Ih
R 1
R 2
EN
Copyright © 2016, Texas Instruments Incorporated
图 22. Adjustable VIN Under Voltage Lock Out
æ
ç
è
ö
VENFALLING
VSTART
- VSTOP
÷
VENRISING
ø
R1 =
æ
ö
÷
ø
VENFALLING
I
1-
+ I
p1 ç
h
VENRISING
è
(4)
R1´ VENFALLING
R2 =
V
STOP - VENFALLING +R1 Ip2
where
•
•
•
•
•
Ip2 = 4.197 μA
Ip1 = 1.91 μA
Ih = 2.287 μA
VENRISING = 1.225 V
VENFALLING = 1.104 V
(5)
7.3.7 Power Good
The Power Good (PGOOD) pin is an open drain output. Once the FB pin voltage is between 93% and 107% of
the internal reference voltage (VREF) the PGOOD is de-asserted and floats after a 200 μs de-glitch time. A pull-up
resistor of 10 kΩ is recommended to pull it up to VREG5. The PGOOD pin is pulled low when the FB pin voltage
is lower than VUVP or greater than VOVP threshold; or, in an event of thermal shutdown or during the soft-start
period.
7.3.8 Over Current Protection and Under Voltage Protection
The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch
current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is
proportional to the switch current. During the on time of the high-side FET switch, the switch current increases at
a linear rate determined by input voltage , output voltage, the on-time and the output inductor value. During the
on time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the
load current IOUT. If the measured drain to source voltage of the low-side FET is above the voltage proportional to
current limit, the low side FET stays on until the current level becomes lower than the OCL level which reduces
the output current available. When the current is limited the output voltage tends to drop because the load
demand is higher than what the converter can support. When the output voltage falls below 68% of the target
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ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
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voltage, the UVP comparator detects it and shuts down the device after a wait time of 1ms, the device re-starts
after a hiccup time of 7ms. In this type of valley detect control the load current is higher than the OCL threshold
by one half of the peak to peak inductor ripple current. When the overcurrent condition is removed, the output
voltage returns to the regulated value. If an OCL condition happens during start-up then the device enters
hiccup-mode immediately without a wait time of 1ms.
7.3.9 Out-of-Bounds Operation
The device has an out-of-bounds (OOB) overvoltage protection that protects the output load at a much lower
overvoltage threshold of 8% above the target voltage. OOB protection does not trigger an overvoltage fault, OOB
protection operates as an early no-fault overvoltage protection mechanism. During the OOB operation, the
controller operates in forced PWM mode only by turning on the low-side FET. Turning on the low-side FET
beyond the zero inductor current quickly discharges the output capacitor thus causing the output voltage to fall
quickly toward the setpoint. During the operation, the cycle-by cycle negative current limit is also activated to
ensure the safe operation of the internal FETs.
7.3.10 UVLO Protection
Under voltage lock out protection (UVLO) monitors the internal VREG5 regulator voltage. When the VREG5
voltage is lower than UVLO threshold voltage, the device is shut off. This protection is non-latching.
7.3.11 Thermal Shutdown
The device monitors the internal die temperature. If this temperature exceeds the thermal shutdown threshold
value (TSDN typically 160°C) the device shuts off. This is a non-latch protection. During start up, if the device
temperature is higher than 160°C the device does not start switching and does not load the MODE settings. If the
device temp goes higher than TSDN threshold after startup, it stops switching with SS reset to ground and an
internal discharge switch turns on to quickly discharge the output voltage. The device re-starts switching when
the temperature goes below the thermal shutdown threshold but the MODE settings are not re-loaded again.
There is a second higher thermal protection on the device TSDN VREG5 which protects it from over temperature
conditions not caused by the switching of the device itself. This threshold is at typically 170°C. Even under
nonswitching condition of the device after exceeding TSDN threshold, if it still continues to heat up the VREG5
output shuts off once temperature goes beyond TSDN VREG5, thereby shutting down the device completely.
7.3.12 Output Voltage Discharge
The device has a 500ohm discharge switch that discharges the output VOUT through SW node during any event
of fault like output overvoltage, output undervoltage , TSD , if VREG5 voltage below the UVLO and when the EN
pin voltage (VEN) is below the turn-on threshold.
7.4 Device Functional Modes
7.4.1 Light Load Operation
When the MODE pin is selected to operate in FCCM mode, the converter operates in continuous conduction
mode (FCCM) during light-load conditions. During FCCM, the switching frequency (FSW) is maintained at an
almost constant level over the entire load range which is suitable for applications requiring tight control of the
switching frequency and output voltage ripple at the cost of lower efficiency under light load. If the MODE pin is
selected to operate in DCM/Eco-mode™, the device enters pulse skip mode after the valley of the inductor ripple
current crosses zero. The Eco-mode™ maintains higher efficiency at light load with a lower switching frequency.
7.4.2 Standby Operation
The TPS568215 can be placed in standby mode by pulling the EN pin low. The device operates with a shutdown
current of 7uA when in standby condition.
18
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TPS568215
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ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The schematic of 图 23 shows a typical application for TPS568215. This design converts an input voltage range
of 4.5 V to 17 V down to 1.2 V with a maximum output current of 8 A.
8.2 Typical Application
VIN = 4.5 V - 17 V
VIN
U1
TPS568215RNNR
BOOT
C1
0.1µF
C2
0.1µF
C3
22µF
C4
22µF
C5
22µF
C6
22µF
L1
C9
VOUT = 1.2 V, 8 A
2
1
VIN
VOUT
11
470nH
R4
VIN
0.1µF
6
SW
SW
FB
C11
47µF
C12
47µF
C13
47µF
C14
47µF
7
14
15
16
18
17
13
SS
10.0k
C7
0.047µF
V5
3
EN
PGND
PGND
PGND
PGND
PGND
PGND
PGOOD
EN
4
5
PGOOD
MODE
VREG5
C10 56pF
8
R1 10.0k
9
R5
10.0k
10
R2
52.3k
V5
12
AGND
R3
49.9k
C8
4.7µF
Copyright © 2016, Texas Instruments Incorporated
图 23. Application Schematic
8.2.1 Design Requirements
表 4. Design Parameters
PARAMETER
CONDITIONS
MIN
TYP
1.2
8
MAX
UNIT
VOUT
Output voltage
V
A
IOUT
Output current
ΔVOUT
VIN
Transient response
Input voltage
4-A load step
±30
12
mV
V
4.5
17
VOUT(ripple)
Output voltage ripple
<10
mV(P-P)
Internal
UVLO
Start input voltage
Input voltage rising
Input voltage falling
V
Internal
UVLO
Stop input voltage
V
fSW
Switching frequency
1.2
DCM
25
MHz
Operating Mode
TA
Ambient temperature
°C
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www.ti.com.cn
8.2.2 Detailed Design Procedure
8.2.2.1 External Component Selection
8.2.2.1.1 Output Voltage Set Point
To change the output voltage of the application, it is necessary to change the value of the upper feedback
resistor. By changing this resistor the user can change the output voltage above 0.6 V. See 公式 6
æ
ö
RUPPER
VOUT = 0.6´ 1+
ç
÷
RLOWER ø
è
(6)
8.2.2.1.2 Switching Frequency and Mode Selection
Switching Frequency, current limit and switching mode (DCM or FCCM) are set by a voltage divider from VREG5
to GND connected to the MODE pin. See 表 3 for possible MODE pin configurations. Switching frequency
selection is a tradeoff between higher efficiency and smaller system solution size. Lower switching frequency
yields higher overall efficiency but relatively bigger external components. Higher switching frequencies cause
additional switching losses which impact efficiency and thermal performance. For this design 1.2 MHz is chosen
as the switching frequency, the switching mode is DCM and the output current is 8 A.
8.2.2.1.3 Inductor Selection
The inductor ripple current is filtered by the output capacitor. A higher inductor ripple current means the output
capacitor should have a ripple current rating higher than the inductor ripple current. See 表 5 for recommended
inductor values.
The RMS and peak currents through the inductor can be calculated using 公式 7 and 公式 8. It is important that
the inductor is rated to handle these currents.
æ
2 ö
÷
÷
÷
ø
æ
ç
ö
÷
VOUT × V
- VOUT
(
× LOUT × FSW
IN(max)
)
1
IN(max)
ç 2
I
IL(rms)=
+
×
OUT
ç
ç
è
÷
ø
12
V
ç
è
(7)
(8)
IOUT(ripple)
I
= IOUT
+
L(peak)
2
During transient/short circuit conditions the inductor current can increase up to the current limit of the device so it
is safe to choose an inductor with a saturation current higher than the peak current under current limit condition.
8.2.2.1.4 Output Capacitor Selection
After selecting the inductor the output capacitor needs to be optimized. In DCAP3, the regulator reacts within one
cycle to the change in the duty cycle so the good transient performance can be achieved without needing large
amounts of output capacitance. The recommended output capacitance range is given in 表 5
Ceramic capacitors have very low ESR, otherwise the maximum ESR of the capacitor should be less than
VOUT(ripple)/IOUT(ripple)
表 5. Recommended Component Values
VOUT (V)
RLOWER (kΩ)
RUPPER (kΩ)
FSW (kHz)
400
LOUT (µH)
0.68
0.47
0.33
1.2
COUT(min) (µF)
COUT(max) (µF)
CFF (pF)
300
100
88
500
500
500
500
500
500
500
500
500
–
0.6
10
0
800
–
1200
400
–
100
88
–
1.2
3.3
10
800
0.68
0.47
2.4
–
1200
400
88
–
88
100–220
100–220
100–220
45.3
800
1.5
88
1200
1.1
88
20
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TPS568215
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ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
表 5. Recommended Component Values (接下页)
VOUT (V)
RLOWER (kΩ)
RUPPER (kΩ)
FSW (kHz)
400
LOUT (µH)
3.3
COUT(min) (µF)
COUT(max) (µF)
CFF (pF)
100–220
100–220
100–220
88
88
88
500
500
700
5.5
82.5
800
2.4
1200
1.2
8.2.2.1.5 Input Capacitor Selection
The minimum input capacitance required is given in 公式 9.
IOUT×VOUT
CIN(min)
=
V
INripple×V ×FSW
IN
(9)
TI recommends using a high quality X5R or X7R input decoupling capacitors of 40 µF on the input voltage pin.
The voltage rating on the input capacitor must be greater than the maximum input voltage. The capacitor must
also have a ripple current rating greater than the maximum input current ripple of the application. The input ripple
current is calculated by 公式 10 below:
VIN(min)-VOUT
(
)
VOUT
ICIN(rms) = IOUT ×
×
VIN(min)
VIN(min)
(10)
8.2.3 Application Curves
图 24 through 图 40 apply to the circuit of 图 23. VIN = 12 V. Ta = 25 °C unless otherwise specified.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 5V
VIN = 12V
VIN = 5V
VIN = 12V
0
1
2
3
4
5
6
7
8
0.001
0.010.02 0.05 0.1 0.2 0.5
Output Current (A)
1
2 3 45 7 10
Output Current (A)
D101
D102
图 24. Efficiency
图 25. Light Load Efficiency
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21
TPS568215
ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
www.ti.com.cn
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
Output Current (A)
Output Current (A)
D103
D104
图 26. Load Regulation, VIN = 5 V
图 27. Load Regulation, VIN = 12 V
0.25
60
180
50
40
150
120
90
0.20
0.15
30
0.10
20
60
0.05
10
30
0.00
0
0
-10
-20
-30
-40
-50
-60
-30
-60
-90
-120
-150
-180
-0.05
-0.10
-0.15
-0.20
-0.25
Gain (dB)
Phase (Deg)
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
100 200 500 1000
10000
100000
500000
Input Voltage (V)
Frequency (Hz)
D105
D106
图 28. Line Regulation, IOUT = 6 A
图 29. Loop Response, IOUT = 6 A
VIN = 20 mV / div (ac coupled)
VIN = 20 mV / div (ac coupled)
SW = 5 V / div
SW = 5 V / div
Time = 10 µsec / div
Time = 500 nsec / div
图 31. Input Voltage Ripple, IOUT = 700 mA
图 30. Input Voltage Ripple, IOUT = 10 mA
22
版权 © 2016, Texas Instruments Incorporated
TPS568215
www.ti.com.cn
ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
VIN = 50 mV / div (ac coupled)
VOUT = 20 mV / div (ac coupled)
SW = 5 V / div
SW = 5 V / div
Time = 50 µsec / div
Time = 500 nsec / div
图 32. Input Voltage Ripple, IOUT = 8 A
图 33. Output Voltage Ripple, IOUT = 10 mA
VOUT = 20 mV / div (ac coupled)
VOUT = 20 mV / div (ac coupled)
SW = 5 V / div
SW = 5 V / div
Time = 500 nsec / div
Time = 500 nsec / div
图 34. Output Voltage Ripple, IOUT = 700 mA
图 35. Output Voltage Ripple, IOUT = 8 A
VIN = 10 V / div
VIN = 10 V / div
EN = 5 V / div
EN = 5 V / div
VO = 500 mV / div
PG = 5 V / div
VO = 500 mV / div
PG = 5 V / div
Time = 2 msec / div
Time = 2 msec / div
图 36. Start Up Relative to VIN Rising
图 37. Start Up Relative to EN Rising
版权 © 2016, Texas Instruments Incorporated
23
TPS568215
ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
www.ti.com.cn
VIN = 10 V / div
VIN = 10 V / div
EN = 5 V / div
VO = 500 mV / div
EN = 5 V / div
VO = 500 mV / div
PG = 5 V / div
PG = 5 V / div
Time = 2 msec / div
Time = 2 msec / div
图 38. Shut Down Relative to VIN Falling
图 39. Shut Down Relative to EN Falling
VO = 50 mV / div (ac coupled)
IO = 2 A / div
Load step = 2 A - 6 A, slew rate = 500 mA / µsec
Time = 200 µsec / div
图 40. Transient Response
9 Power Supply Recommendations
The TPS568215 is intended to be powered by a well regulated dc voltage. The input voltage range is 4.5 to 17 V.
TPS568215 is a buck converter. The input supply voltage must be greater than the desired output voltage for
proper operation. Input supply current must be appropriate for the desired output current. If the input voltage
supply is located far from the TPS568215 circuit, some additional input bulk capacitance is recommended.
Typical values are 100 µF to 470 µF.
24
版权 © 2016, Texas Instruments Incorporated
TPS568215
www.ti.com.cn
ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
10 Layout
10.1 Layout Guidelines
•
Recommend a four-layer or six-layer PCB for good thermal performance and with maximum ground plane. 3"
x 3", four-layer PCB with 2-oz. copper used as example.
•
•
•
Recommend having equal caps on each side of the IC. Place them right across VIN as close as possible.
Inner layer 1 will be ground with the PGND to AGND net tie
Inner layer2 has VIN copper pour that has vias to the top layer VIN. Place multiple vias under the device
near VIN and GND and near input capacitors to reduce parasitic inductance and improve thermal
performance
•
•
•
Bottom later is GND with the BOOT trace routing.
Feedback should be referenced to the quite AGND and routed away from the switch node.
VIN trace must be wide to reduce the trace impedance.
10.2 Layout Example
图 41 shows the recommended top side layout. Component reference designators are the same as the circuit
shown in 图 23. Resistor divider for EN is not used in the circuit of 图 23, but are shown in the layout for
reference.
PGOOD
OUTPUT
R1
BOOT
VIN
AGND
VIN
PGND
PGND
PGND
PGND
PGND
PGND
C1
C2
C3
C4
C5
C6
L1
C11
C12
C13
C14
图 41. Top Side Layout
版权 © 2016, Texas Instruments Incorporated
25
TPS568215
ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
www.ti.com.cn
Layout Example (接下页)
图 42 shows the recommended layout for the first internal layer. It is comprised of a large PGND plane and a
smaller ANGD island. AGND and PGND are connected at a single point to reduce circulating currents.
AGND
SINGLE POINT
AGND TO PGND
CONNECTION
PGND PLANE
图 42. Mid Layer 1 Layout
图 43 shows the recommended layout for the second internal layer. It is comprised of a large PGND plane, a
smaller copper fill area to connect the two top side VIN copper areas and a second VOUT copper fill area.
VIN
PGND PLANE
VOUT
图 43. Mid Layer 2 Layout
26
版权 © 2016, Texas Instruments Incorporated
TPS568215
www.ti.com.cn
ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
Layout Example (接下页)
图 44 shows the recommended layout for the bottom layer. It is comprised of a large PGND plane and a trace to
connect the BOOT capacitor to the SW node.
PGND PLANE
图 44. Bottom Layer Layout
版权 © 2016, Texas Instruments Incorporated
27
TPS568215
ZHCSFM7A –OCTOBER 2016–REVISED OCTOBER 2016
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 开发支持
•
《TPS568215EVM-762 8A SWIFT™ 稳压器评估模块用户指南》
11.2 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
D-CAP3, HotRod, Eco-mode, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏
28
版权 © 2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS568215RNNR
TPS568215RNNT
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
RNN
RNN
18
18
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
568215
568215
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS568215RNNR
TPS568215RNNT
VQFN-
HR
RNN
RNN
18
18
3000
250
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q2
VQFN-
HR
180.0
12.4
3.75
3.75
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS568215RNNR
TPS568215RNNT
VQFN-HR
VQFN-HR
RNN
RNN
18
18
3000
250
346.0
210.0
346.0
185.0
33.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RNN0018A
VQFN-HR - 1 mm max height
SCALE 3.200
PLASTIC QUAD FLATPACK - NO LEAD
3.6
3.4
B
A
PIN 1 INDEX AREA
3.6
3.4
30.000
ALTERNATE PIN 1 ID SHAPE
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
0.6
1.0
0.9
8X
0.35
0.25
2X
(0.2) TYP
7
6
8
5
4X 0.55
0.3
0.2
6X
2.5
2X
2X 0.65
2.3
PKG
2X
0.925
0.45
0.35
12
8X
2X
1
2X 0.575
SEE ALTERNATE
PIN 1 ID DETAIL
18
13
0.3
0.2
SYMM
0.45
0.35
7X
0.1
0.05
C B A
5X 0.5
2.5
0.45
0.35
C
ALL PADS
4222688/E 03/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RNN0018A
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.5)
2X (1.65)
5X (0.5)
SYMM
18
13
8X (0.6)
(1.65)
8X (0.25)
(R0.05) TYP
1
EXPOSED METAL
TYP
12
2X (0.925)
2X (0.4)
11
2X (0.35)
2
PKG
0.000
2X
(2.6)
2X (0.3)
(0.65)
2X (0.85)
8
2X (1.4)
5
6X (0.25)
8X (1.15)
6
7
2X (0.3)
2X (0.3)
8X (1.375)
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
EXPOSED METAL SHOWN
SCALE:25X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
SOLDER MASK
OPENING
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
SOLDER MASK DETAILS
(PREFERRED)
4222688/E 03/2021
NOTES: (continued)
3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
RNN0018A
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.5)
(1.65)
5X (0.5)
SYMM
13
18
8X (0.6)
(1.65)
8X (0.25)
1
EXPOSED
METAL, TYP
2X (0.925)
2X (0.36)
12
6X (0.3)
2
11
2X (0.35)
(0.2825)
PKG
0.000
6X
(0.733)
2X (0.3)
(0.651)
2X (0.85)
2X (1.4)
8
5
(1.585)
6X (0.25)
8X (1.15)
EXPOSED METAL
TYP
EXPOSED METAL
TYP
7
6
8X (1.375)
(R0.05) TYP
(0.3) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PADS 6 & 7: 83% - PADS 2 & 11: 90%
SCALE:30X
4222688/E 03/2021
NOTES: (continued)
5. For alternate stencil design recommendations, see IPC-7525 or board assembly site preference.
www.ti.com
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