TPS61089RNRT [TI]
采用 2.0mm x 2.5mm VQFN 封装的 12.6V、7A 全集成同步升压转换器 | RNR | 11 | -40 to 125;
| 型号： | TPS61089RNRT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 2.0mm x 2.5mm VQFN 封装的 12.6V、7A 全集成同步升压转换器 | RNR | 11 | -40 to 125 升压转换器 |
| 文件： | 总34页 (文件大小：2507K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS61089, TPS610891
ZHCSF69C –NOVEMBER 2015 –REVISED AUGUST 2021
采用2.0mm x 2.5mm VQFN 封装的TPS61089x 12.6V、7A 完全集成的同步升压转
换器
19mΩ 主电源开关和 27mΩ 整流器开关。该器件可以
为便携式设备提供高效率小型电源解决方案。
1 特性
TPS61089x 具有 2.7V 至 12V 的宽输入电压范围，可
支持由单节或两节锂离子/锂聚合物电池供电的应用。
TPS61089x 具备 7A 持续开关电流能力，能够提供高
达12.6V 的输出电压。
• 输入电压范围：2.7 V 至12 V
• 输出电压范围：4.5 V 至12.6 V
• 效率高达90%（VIN = 3.3V、VOUT = 9V 且IOUT
2A 时）
=
• 针对高脉冲电流的电阻可编程峰值电流限值高达
TPS61089x 采用自适应恒定关断时间峰值电流控制拓
扑结构调节输出电压。在中等到重负载条件下，
TPS61089x 以 PWM 模式工作。在轻载条件下，
TPS61089 以可提升效率的脉频调制 (PFM) 模式工
作，而 TPS610891 仍以可避免因开关频率较低而引发
应用问题的 PWM 模式工作。PWM 模式下的开关频率
可在 200kHz 至 2.2MHz 之间调节。TPS61089x 还内
置 4ms 软启动功能和可调节开关电流峰值限制功能。
此外，该器件还提供 13.2V 输出过压保护、逐周期过
流保护和热关断保护。
10A
• 可调开关频率：200kHz 至2.2MHz
• 4ms 内置软启动时间
• 轻负载下采用PFM 运行模式(TPS61089)
• 轻负载下采用强制PWM 运行模式(TPS610891)
• 在13.2V 时提供内部输出过压保护
• 逐周期过流保护
• 热关断
• 2.00mm × 2.50mm VQFN HotRod™ 封装
• 使用TPS61089x 并借助WEBENCH® Power
Designer 创建定制设计方案
TPS61089x 采用极其紧凑的 2.0mm × 2.5mm、11 引
脚VQFN 封装。
2 应用
器件信息表
封装(1)
• Bluetooth™ 扬声器
• 快充移动电源
• 便携式刷卡机(POS) 终端
封装尺寸（标称值）
器件型号
TPS61089x
VQFN (11)
2.00mm x 2.50mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
3 说明
TPS61089x 代表 TPS61089 和 TPS610891 。
TPS61089x 是一款全集成同步升压转换器，带有
L1
VIN
VOUT
SW
VOUT
C4
C1
R3
C2
BOOT
GND
R1
R2
FSW
VIN
FB
COMP
ILIM
ON
EN
OFF
C6
R5
C5
VCC
C3
R4
典型应用电路
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSD38
TPS61089, TPS610891
ZHCSF69C –NOVEMBER 2015 –REVISED AUGUST 2021
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes..........................................11
9 Application and Implementation..................................13
9.1 Application Information............................................. 13
9.2 Typical Application.................................................... 13
10 Power Supply Recommendations..............................21
11 Layout...........................................................................22
11.1 Layout Guidelines................................................... 22
11.2 Layout Example...................................................... 22
12 Device and Documentation Support..........................24
12.1 Device Support....................................................... 24
12.2 接收文档更新通知................................................... 24
12.3 支持资源..................................................................24
12.4 Trademarks.............................................................24
12.5 Electrostatic Discharge Caution..............................24
12.6 术语表..................................................................... 24
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................6
7.6 Typical Characteristics................................................7
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
8.2 Functional Block Diagram...........................................9
8.3 Feature Description...................................................10
Information.................................................................... 25
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (July 2016) to Revision C (August 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式。..................................................................................... 1
• 更正了整个文档中的语法和数值格式.................................................................................................................. 1
• 添加了WEBENCH 链接..................................................................................................................................... 1
Changes from Revision A (April 2016) to Revision B (July 2016)
Page
• Changed x axis in .............................................................................................................................................. 7
• Changed x axis in .............................................................................................................................................. 7
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5 Device Comparison Table
PART NUMBER
OPERATION MODE AT LIGHT LOAD
TPS61089RNR
PFM
TPS610891RNR(1)
Forced PWM
(1) Product Preview. Contact TI factory for more information.
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6 Pin Configuration and Functions
FSW
VCC
BOOT
VIN
FB
ILIM
EN
COMP
图6-1. 11-Pin VQFN With Thermal Pad RNR Package (Top View)
表6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NUMBER
FSW
VCC
FB
1
I
The switching frequency is programmed by a resister between this pin and the SW pin.
Output of the internal regulator. A ceramic capacitor of more than 1.0 µF is required between
this pin and ground.
2
3
4
O
I
Output voltage feedback
Output of the internal error amplifier. The loop compensation network should be connected
between this pin and the GND pin.
COMP
O
GND
5
6
PWR
PWR
Ground
VOUT
Boost converter output
Enable logic input. Logic high level enables the device. Logic low level disables the device
and turns it into shutdown mode.
EN
7
I
Adjustable switching peak current limit. An external resister should be connected between
this pin and the GND pin.
ILIM
8
9
O
I
VIN
IC power supply input
Power supply for high-side MOSFET gate driver. A capacitor must be connected between
this pin and the SW pin
BOOT
10
O
The switching node pin of the converter. It is connected to the drain of the internal low-side
power MOSFET and the source of the internal high-side power MOSFET.
SW
11
PWR
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–40
–65
MAX
SW + 7
14.5
7
UNIT
BOOT
VIN, SW, FSW, VOUT
Voltage at terminals(2)
V
EN, VCC, COMP
ILIM, FB
Operating junction temperature, TJ
3.6
150
°C
°C
Storage temperature, Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
MAX
12
UNIT
VIN
VOUT
L
Input voltage range
V
V
Output voltage range
4.5
12.6
10
Inductance, effective value
Input capacitance, effective value
Output capacitance, effective value
Operating junction temperature
0.47
10
2.2
47
µH
µF
µF
°C
CIN
CO
TJ
10
1000
125
–40
7.4 Thermal Information
TPS61089x
RNR (VQFN)
11 PINS
53.4
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
59.2
9.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
Junction-to-ambient thermal resistance on EVM
0.5
ψJT
9.5
ψJB
RθJC(bot)
0.7
(2)
RθJA(EVM)
39.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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(2) The EVM board is a 4-layer PCB of 76-mm x 52-mm size. The copper thickness of top layer and bottom layer is 2 oz. The copper
thickness of inner layers is 1 oz.
7.5 Electrical Characteristics
VIN = 2.7 V to 5.5 V, VOUT = 9 V, TJ = –40°C to 125°C. Typical values are at TJ = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VIN
Input voltage range
2.7
12
2.7
2.5
V
V
VIN rising
VIN falling
Input voltage undervoltage lockout
(UVLO) threshold
VIN_UVLO
2.4
200
5.8
V
VIN_HYS
VCC
VIN UVLO hysteresis
VCC regulation voltage
VCC UVLO threshold
mV
V
ICC = 2 mA, VIN = 8 V
VCC falling
VCC_UVLO
2.1
V
IC enabled, No load, VIN = 2.7 V to 5.5 V, VFB = 1.3
V, VOUT = 12 V, TJ ≤85°C
Quiescent current into VIN pin
1
3
µA
IQ
IC enabled, No load, VIN = 2.7 V to 5.5 V, VFB = 1.3
V, VOUT = 12 V, TJ ≤85°C
Quiescent current into VOUT pin
Shutdown current into VIN pin
100
1
180
3
µA
µA
ISD
IC disabled, VIN = 2.7 V to 5.5 V, TJ ≤85°C
OUTPUT
VOUT
Output voltage range
4.5
12.6
V
V
PWM mode
PFM mode
VFB = 1.2 V
1.188
1.212
1.224
1.236
VREF
Reference voltage at FB pin
V
IFB_LKG
VOVP
VOVP_HYS
tSS
Leakage current into FB pin
100
nA
Output overvoltage protection
threshold
VOUT rising
12.7
2
13.2
13.6
V
Output overvoltage protection
hysteresis
VOUT falling below VOVP
0.25
4
V
Soft startup time
COUT(effective) = 47 µF, IOUT = 0 A
6
ms
ERROR AMPLIFIER
ISINK
COMP pin sink current
VFB = VREF + 200 mV, VCOMP = 1.9 V
VFB = VREF –200 mV, VCOMP = 1.9 V
VFB = 1 V, RILIM = 127 kΩ
20
20
µA
µA
V
ISOURCE
VCCLP_H
VCCLP_L
GEA
COMP pin source current
High clamp voltage at the COMP pin
Low clamp voltage at the COMP pin
Error amplifier transconductance
2.3
1.4
190
V
VFB = 1.4 V, RILIM = 127 kΩ
VCOMP = 1.9 V
µS
POWER SWITCH
High-side MOSFET on-resistance
Low-side MOSFET on-resistance
SWITCHING FREQUENCY
VCC = 6 V
VCC = 6 V
27
19
44
31
mΩ
mΩ
RDS(on)
500
2000
90
kHz
kHz
ns
RFSW = 301 kΩ
RFSW = 46.4 kΩ
VCC = 6 V
fSW
Switching frequency
Minimum on time
tON_min
180
CURRENT LIMIT
7.3
9.0
8.1
10
8.9
11
A
A
V
RILIM = 127 kΩ
RILIM = 100 kΩ
ILIM
Peak switch current limit, TPS61089
Internal reference voltage at ILIM pin
VILIM
1.212
EN LOGIC INPUT
VEN_H
EN Logic high threshold
1.2
V
V
VEN_L
EN Logic Low threshold
EN pulldown resistor
0.4
REN
800
kΩ
PROTECTION
TSD
Thermal shutdown threshold
Thermal shutdown hysteresis
TJ rising
150
20
°C
°C
TSD_HYS
TJ falling below TSD
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7.6 Typical Characteristics
VIN = 3.6 V, VOUT = 9 V, TJ = 25°C, unless otherwise noted
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
20
10
0
20
VIN = 3 V
VIN = 3.6 V
VIN = 4.2 V
VOUT = 5 V
VOUT = 9 V
VOUT = 12 V
10
0
0.0001
0.001
0.01 0.1
Output Current (A)
1
10
0.0001
0.001
0.01 0.1
Output Current (A)
1
10
D001
D001
TPS61089
VOUT = 9 V
TPS61089
VIN = 3.6 V
图7-1. Load Efficiency with Different Input Voltage
图7-2. Load Efficiency with Different Output
Voltage
12
10
8
2500
2000
1500
1000
500
6
4
2
0
0
0
100 200 300 400 500 600 700 800 900
Resistance (kW)
100
150
200
250
Resistance (kW)
300
350
400
D004
D003
TPS61089
图7-4. Switching Frequency Setting
图7-3. Switching Peak Current Limit Setting
1.22
160
140
120
100
80
1.216
1.212
1.208
1.204
1.2
60
40
20
-40
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-20
0
20 40
Temperature (°C)
60
80
100
D005
D006
图7-5. Reference Voltage vs Temperature
图7-6. Quiescent Current vs Temperature
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2
1.6
1.2
0.8
0.4
0
-40
-20
0
20 40
Temperature (°C)
60
80
100
D007
图7-7. Shutdown Current vs Temperature
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8 Detailed Description
8.1 Overview
The TPS61089x is a synchronous boost converter, integrating a 19-mΩ main power switch and a 27-mΩ
rectifier switch with adjustable switch current up to 10 A. It is capable to output continuous power more than 18
W from input of a single cell Lithium-ion battery or two-cell Lithium-ion batteries in series. The TPS61089x
operates at a quasi-constant frequency pulse-width modulation (PWM) at moderate to heavy load currents. At
light load current, the TPS61089 operates in PFM mode and the TPS610891 operates in forced PWM (FPWM)
mode. The PFM mode brings high efficiency over the entire load range, and the FPWM mode can avoid the
acoustic noise and switching frequency interference at light load. The converter uses the constant off-time peak
current mode control scheme, which provides excellent line and load transient response with minimal output
capacitance. The external loop compensation brings flexibility to use different inductors and output capacitors.
The TPS61089x supports adjustable switching frequency ranging from 200 kHz to 2.2 MHz. The device
implements cycle-by-cycle current limit to protect the device from overload conditions during boost switching.
The current limit is set by an external resistor.
8.2 Functional Block Diagram
L1
VIN
C4
C1
SW
BOOT
VIN
VOUT
VOUT
dead me
control logic
C2
LDO
VCC
R1
GND
C3
Comp
Comp
CLIMIT
FB
FSW
Gm
R2
R3
Vref
1/K
VIN
SW
COMP
EN
R5
Shutdown
ON/
OFF
Shutdown
Control
Vref
C5
OVP
VOUT
VIN
CLIMIT
ILIM
UVLO
Thermal
shutdown
R4
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8.3 Feature Description
8.3.1 Undervoltage Lockout (UVLO)
An undervoltage lockout (UVLO) circuit stops the operation of the converter when the input voltage drops below
the typical UVLO threshold of 2.5 V. A hysteresis of 200 mV is added so that the device cannot be enabled again
until the input voltage goes up to 2.7 V. This function is implemented to prevent the device from malfunctioning
when the input voltage is between 2.5 V and 2.7 V.
8.3.2 Enable and Disable
When the input voltage is above maximal UVLO rising threshold of 2.7 V and the EN pin is pulled above the high
threshold, the TPS61089x is enabled. When the EN pin is pulled below the low threshold, the TPS61089x goes
into shutdown mode. The device stops switching in shutdown mode and consumes less than 3-µA current.
Because of the body diode of the high-side rectifier FET, the input voltage goes through the body diode and
appears at the VOUT pin at shutdown mode.
8.3.3 Soft Start
The TPS61089x implements the soft start function to reduce the inrush current during start-up. The TPS61089x
begins soft start when the EN pin is pulled to logic high voltage. The soft start time is typically 4 ms.
8.3.4 Adjustable Switching Frequency
The TPS61089x features a wide adjustable switching frequency ranging from 200 kHz to 2.2 MHz. The switching
frequency is set by a resistor connected between the FSW pin and the SW pin of the TPS61089x. Do not leave
the FSW pin open. Use 方程式1 to calculate the resistor value required for a desired frequency.
VOUT
1
4ì(
- tDELAY
ì
)
ƒSW
V
IN
RFREQ
=
CFREQ
(1)
where
• RFREQ is the resistance connected between the FSW pin and the SW pin
• CFREQ = 24 pF
• ƒSW is the desired switching frequency
• tDELAY = 86 ns
• VIN is the input voltage
• VOUT is the output voltage
8.3.5 Adjustable Peak Current Limit
To avoid an accidental large peak current, an internal cycle-by-cycle current limit is adopted. The low-side switch
turns off immediately as long as the peak switch current touches the limit. The peak inductor current can be set
by selecting the correct external resistor value correlating with the required current limit. Use 方程式 2 to
calculate the correct resistor value for the TPS61089.
1030000
I
=
LIM
R
ILIM
(2)
where
• RILIM is the resistance connected between the ILIM pin and ground
• ILIM is the switch peak current limit
For a typical current limit of 8 A, the resistor value is 127 kΩfor the TPS61089.
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8.3.6 Overvoltage Protection
If the output voltage at the VOUT pin is detected above the overvoltage protection threshold of 13.2 V (typical
value), the TPS61089x stops switching immediately until the voltage at the VOUT pin drops the hysteresis
voltage lower than the output overvoltage protection threshold. This function prevents overvoltage on the output
and secures the circuits connected to the output from excessive overvoltage.
8.3.7 Thermal Shutdown
A thermal shutdown is implemented to prevent damage due to excessive heat and power dissipation. Typically,
the thermal shutdown happens at the junction temperature of 150°C. When the thermal shutdown is triggered,
the device stops switching until the junction temperature falls below typically 130°C, then the device starts
switching again.
8.4 Device Functional Modes
8.4.1 Operation
The TPS61089x synchronous boost converter operates at a quasi-constant frequency pulse width modulation
(PWM) in moderate to heavy load condition. Based on the VIN to VOUT ratio, a circuit predicts the required off-
time of the switching cycle. At the beginning of each switching cycle, the low-side N-MOSFET switch, shown in
节 8.2, is turned on, and the inductor current ramps up to a peak current that is determined by the output of the
internal error amplifier. After the peak current is reached, the current comparator trips, and turns off the low-side
N-MOSFET switch and the inductor current goes through the body diode of the high-side N-MOSFET in a dead-
time duration. After the dead-time duration, the high-side N-MOSFET switch is turned on. Since the output
voltage is higher than the input voltage, the inductor current decreases. The high-side switch is not turned off
until the fixed off-time is reached. After a short dead-time duration, the low-side switch is turned on again and the
switching cycle is repeated.
In light load condition, the TPS61089 implements PFM mode for applications requiring high efficiency at light
load. And the TPS610891 implements forced PWM mode for applications requiring fixed switching frequency to
avoid unexpected switching noise interference.
8.4.1.1 Forced PWM Mode
In forced PWM mode, the TPS610891 keeps the switching frequency unchanged in light load condition. When
the load current decreases, the output of the internal error amplifier decreases as well to keep the inductor peak
current down, delivering less power from input to output. When the output current further reduces, the current
through the inductor will decrease to zero during the off-time. The high-side N-MOSFET is not turned off even if
the current through the MOSFET is zero. Thus, the inductor current changes its direction after it runs to zero.
The power flow is from output side to input side. The efficiency will be low in this mode. But with the fixed
switching frequency, there is no audible noise and other problems which might be caused by low switching
frequency in light load condition.
8.4.1.2 PFM Mode
The TPS61089 improves the efficiency at light load with PFM mode. When the converter operates in light load
condition, the output of the internal error amplifier decreases to make the inductor peak current down, delivering
less power to the load. When the output current further reduces, the current through the inductor will decrease to
zero during the off-time. Once the current through the high-side N-MOSFET is zero, the high-side MOSFET is
turned off until the beginning of the next switching cycle. When the output of the error amplifier continuously
goes down and reaches a threshold with respect to the peak current of ILIM / 10, the output of the error amplifier
is clamped at this value and does not decrease any more. If the load current is smaller than what the TPS61089
delivers, the output voltage increases above the nominal setting output voltage. The TPS61089 extends its off
time of the switching period to deliver less energy to the output and regulate the output voltage to 1.0% higher
than the nominal setting voltage. With the PFM operation mode, the TPS61089 keeps the efficiency above 70%
even when the load current decreases to 1 mA. At light load, the output voltage ripple is much smaller due to low
peak inductor current. Refer to 图8-1.
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Output
Voltage
PFM mode at light load
1.01 x VOUT_NOM
VOUT_NOM
PWM mode at heavy load
图8-1. Output Voltage in PWM Mode and PFM Mode
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9 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The TPS61089x is designed for outputting voltage up to 12.6 V with 7-A continuous switch current capability to
deliver more than 18-W power. The TPS61089x operates at a quasi-constant frequency pulse-width modulation
(PWM) in moderate to heavy load condition. In light load condition, the TPS61089 operates in PFM mode and
the TPS610891 operates in forced PWM mode. The PFM mode brings high efficiency over entire load range,
while PWM mode can avoid the acoustic noise as the switching frequency is fixed. In PWM mode, the
TPS61089x converter uses the adaptive constant off-time peak current control scheme, which provides excellent
transient line and load response with minimal output capacitance. The TPS61089x can work with a different
inductor and output capacitor combination by external loop compensation. It also supports adjustable switching
frequency ranging from 200 kHz to 2.2 MHz.
9.2 Typical Application
L1
1.8µH
VIN = 3.0V to 4.35V
VOUT = 9V
SW
VOUT
GND
C1
22µF
C4
0.1µF
R3
301k
C2
BOOT
3 x 22µF
R1
681k
FSW
VIN
FB
COMP
ILIM
ON
R2
EN
OFF
107k
R5
C6
VCC
17.4k
C3
2.2µF
R4
127k
C5
4.7nF
图9-1. TPS61089x Single Cell Li-ion Battery to 9-V/2-A Output Converter
9.2.1 Design Requirements
表9-1. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUES
Input voltage range
Output voltage
3.0 to 4.35 V
9 V
Output voltage ripple
Output current rating
Operating frequency
Operation mode at light load
100 mV peak to peak
2 A
500 kHz
PFM
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9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS61089x device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Setting Switching Frequency
The switching frequency is set by a resistor connected between the FSW pin and the SW pin of the TPS61089x.
The resistor value required for a desired frequency can be calculated using 方程式3.
VOUT
1
4ì(
- tDELAY
ì
)
ƒSW
V
IN
RFREQ
=
CFREQ
(3)
where
• RFREQ is the resistance connected between the FSW pin and the SW pin
• CFREQ = 24 pF
• ƒSW is the desired switching frequency
• tDELAY = 86 ns
• VIN is the input voltage
• VOUT is the output voltage
9.2.2.3 Setting Peak Current Limit
The peak input current is set by selecting the correct external resistor value correlating to the required current
limit. Use 方程式4 to calculate the correct resistor value:
1030000
I
=
LIM
R
ILIM
(4)
where
• RILIM is the resistance connected between the ILIM pin and ground
• ILIM is the switching peak current limit
For a typical current limit of 8 A, the resistor value is 127 kΩ. Considering the device variation and the tolerance
over temperature, the minimum current limit at the worst case can be 0.8 A lower than the value calculated by 方
程式 4. The minimum current limit must be higher than the required peak switch current at the lowest input
voltage and the highest output power to make sure the TPS61089x does not hit the current limit and still can
regulate the output voltage in these conditions.
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9.2.2.4 Setting Output Voltage
The output voltage is set by an external resistor divider (R1, R2 in TPS61089x Single Cell Li-ion Battery to 9-V/2-
A Output Converter). Typically, a minimum current of 10 μA flowing through the feedback divider gives good
accuracy and noise covering. A resistor of less than 120 kΩis typically selected for low-side resistor R2.
When the output voltage is regulated, the typical voltage at the FB pin is VREF. Thus, the value of R1 is
calculated as:
(VOUT - VREF )ìR2
R1 =
VREF
(5)
9.2.2.5 Inductor Selection
Because the selection of the inductor affects the steady state operation of the power supply, transient behavior,
loop stability, and boost converter efficiency, the inductor is the most important component in switching power
regulator design. Three most important specifications to the performance of the inductor are the inductor value,
DC resistance, and saturation current.
The TPS61089x is designed to work with inductor values between 0.47 µH and 10 µH. A 0.47-µH inductor is
typically available in a smaller or lower-profile package, while a 10-µH inductor produces lower inductor current
ripple. If the boost output current is limited by the peak current protection of the IC, using a 10-µH inductor can
maximize the controller’s output current capability.
Inductor values can have ±20% or even ±30% tolerance with no current bias. When the inductor current
approaches saturation level, its inductance can decrease 20% to 35% from the value at 0-A current depending
on how the inductor vendor defines saturation. When selecting an inductor, make sure its rated current,
especially the saturation current, is larger than its peak current during the operation.
Follow 方程式 6 to 方程式 7 to calculate the peak current of the inductor. To calculate the current in the worst
case, use the minimum input voltage, maximum output voltage, and maximum load current of the application. To
leave enough design margin, TI recommends using the minimum switching frequency, the inductor value with –
30% tolerance, and a low-power conversion efficiency for the calculation.
In a boost regulator, calculate the inductor DC current as in 方程式6.
VOUT ìIOUT
IDC
=
V ì h
IN
(6)
where
• VOUT is the output voltage of the boost regulator
• IOUT is the output current of the boost regulator
• VIN is the input voltage of the boost regulator
• ηis the power conversion efficiency
Calculate the inductor current peak-to-peak ripple as in 方程式7.
1
IPP
=
1
1
L ì(
+
)ì ƒSW
VOUT - V
V
IN
IN
(7)
where
• IPP is the inductor peak-to-peak ripple
• L is the inductor value
• ƒSW is the switching frequency
• VOUT is the output voltage
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• VIN is the input voltage
Therefore, the peak current, ILpeak, seen by the inductor is calculated with 方程式8.
IPP
ILpeak = IDC
+
2
(8)
Set the current limit of the TPS61089x higher than the peak current ILpeak. Then select the inductor with
saturation current higher than the setting current limit.
Boost converter efficiency is dependent on the resistance of its current path, the switching loss associated with
the switching MOSFETs, and the core loss of the inductor. The TPS61089x has optimized the internal switch
resistance. However, the overall efficiency is affected significantly by the DC resistance (DCR) of the inductor,
equivalent series resistance (ESR) at the switching frequency, and the core loss. Core loss is related to the core
material and different inductors have different core loss. For a certain inductor, larger current ripple generates
higher DCR and ESR conduction losses and higher core loss. Usually, a data sheet of an inductor does not
provide the ESR and core loss information. If needed, consult the inductor vendor for detailed information.
Generally, TI would recommend an inductor with lower DCR and ESR. However, there is a tradeoff among the
inductance of the inductor, DCR and ESR resistance, and its footprint. Furthermore, shielded inductors typically
have higher DCR than unshielded inductors. 表 9-2 lists recommended inductors for the TPS61089x. Verify
whether the recommended inductor can support the user's target application with the previous calculations and
bench evaluation. In this application, the Sumida inductor CDMC8D28NP-1R8MC is selected for its small size
and low DCR.
表9-2. Recommended Inductors
DCR MAX
(mΩ)
SATURATION CURRENT /
HEAT RATING CURRENT (A)
SIZE MAX
(L × W × H mm)
PART NUMBER
L (µH)
VENDOR
CDMC8D28NP-1R8MC
744311150
1.8
1.5
12.6
7.2
9.4 / 9.3
9.5 x 8.7 x 3.0
7.3 x 7.2 x 4.0
Sumida
14.0 / 11.0
Wurth-
Elektronik
744311220
2.2
12.5
13.0 / 9.0
7.3 × 7.2 × 4.0
Wurth-
Elektronik
PIMB103T-2R2MS
PIMB065T-2R2MS
2.2
2.2
9.0
16 / 13
11.2 × 10.3 × 3.0
7.4 × 6.8 × 5.0
Cyntec
Cyntec
12.5
12 / 10.5
9.2.2.6 Input Capacitor Selection
For good input voltage filtering, TI recommends low-ESR ceramic capacitors. The VIN pin is the power supply for
the TPS61089x. A 0.1-μF ceramic bypass capacitor is recommended as close as possible to the VIN pin of the
TPS61089x. The VCC pin is the output of the internal LDO. A ceramic capacitor of more than 1.0 μF is required
at the VCC pin to get a stable operation of the LDO.
For the power stage, because of the inductor current ripple, the input voltage changes if there is parasitic
inductance and resistance between the power supply and the inductor. It is recommended to have enough input
capacitance to make the input voltage ripple less than 100 mV. Generally, 10-μF input capacitance is sufficient
for most applications.
Note
DC bias effect: High-capacitance ceramic capacitors have a DC bias effect, which has a strong
influence on the final effective capacitance. Therefore, the right capacitor value must be chosen
carefully. The differences between the rated capacitor value and the effective capacitance result from
package size and voltage rating in combination with material. A 10-V rated 0805 capacitor with 10 μF
can have an effective capacitance of less 5 μF at an output voltage of 5 V.
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9.2.2.7 Output Capacitor Selection
For small output voltage ripple, TI recommends a low-ESR output capacitor like a ceramic capacitor. Typically,
three 22-μF ceramic output capacitors work for most applications. Higher capacitor values can be used to
improve the load transient response. Take care when evaluating a capacitor’s derating under DC bias. The
bias can significantly reduce capacitance. Ceramic capacitors can lose most of their capacitance at rated
voltage. Therefore, leave margin on the voltage rating to ensure adequate effective capacitance. From the
required output voltage ripple, use the following equations to calculate the minimum required effective
capacitance CO:
(VOUT - VIN_MIN)ìIOUT
V
=
ripple _ dis
VOUT ì ƒSW ì CO
(9)
V
= ILpeak ìRESR
ripple _ESR
(10)
where
• Vripple_dis is output voltage ripple caused by charging and discharging of the output capacitor.
• Vripple_ESR is output voltage ripple caused by ESR of the output capacitor.
• VIN_MIN is the minimum input voltage of boost converter.
• VOUT is the output voltage.
• IOUT is the output current.
• ILpeak is the peak current of the inductor.
• ƒSW is the converter's switching frequency.
• RESR is the ESR of the output capacitors.
9.2.2.8 Loop Stability
The TPS61089x requires external compensation, which allows the loop response to be optimized for each
application. The COMP pin is the output of the internal error amplifier. An external compensation network
comprised of resistor R5, ceramic capacitors C5 and C6 is connected to the COMP pin.
The power stage small signal loop response of constant off time (COT) with peak current control can be modeled
by 方程式11.
≈
∆
«
’≈
÷∆
’
÷
S
S
1 +
1 -
RO ì 1 - D
2 ì p ì ƒESRZ ◊«
2 ì p ì ƒRHPZ ◊
(
)
ì
GPS (S) =
S
2 ì Rsense
1 +
2 ì p ì ƒP
(11)
where
• D is the switching duty cycle
• RO is the output load resistance
• Rsense is the equivalent internal current sense resistor, which is 0.08 Ω
• ƒP is the pole's frequency
• ƒESRZ is the zero's frequency
• ƒRHPZ is the right-half-plane-zero's frequency
The D, ƒP, ƒESRZ, and ƒRHPZ can be calculated by following equations:
V
IN ì h
D = 1-
VOUT
(12)
where
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• ηis the power conversion efficiency
2
ƒP
=
2p ì RO ì CO
(13)
where
• CO is effective capacitance of the output capacitor
1
ƒESRZ
=
2p ì RESR ì CO
(14)
where
• RESR is the equivalent series resistance of the output capacitor
2
RO ì 1 - D
(
)
ƒRHPZ
=
2p ì L
(15)
The COMP pin is the output of the internal transconductance amplifier. 方程式16 shows the small signal transfer
function of compensation network.
≈
∆
«
’
÷
S
1 +
2 ì p ì ƒCOMZ ◊
GEA ì REA ì VREF
VOUT
Gc(S) =
ì
≈
∆
«
’≈
’
÷
S
S
1 +
1 +
÷∆
2 ì p ì ƒCOMP1 ◊«
2 ì p ì ƒCOMP2 ◊
(16)
where
• GEA is the amplifier’s transconductance
• REA is the amplifier’s output resistance
• VREF is the refernce voltage at the FB pin
• VOUT is the output voltage
• ƒCOMP1, ƒCOMP2 are the poles' frequency of the compensation network
• ƒCOMZ is the zero's frequency of the compensation network
The next step is to choose the loop crossover frequency, ƒC. The higher in frequency that the loop gain stays
above zero before crossing over, the faster the loop response is. It is generally accepted that the loop gain cross
over no higher than the lower of either 1/10 of the switching frequency, ƒSW, or 1/5 of the RHPZ frequency,
ƒRHPZ
.
At the crossover frequency, the loop gain is 1. Thus the value of R5 can be calculated by 方程式 17, then set the
values of C5 and C6 (in TPS61089x Single Cell Li-ion Battery to 9-V/2-A Output Converter) by 方程式 18 and 方
程式19.
2pì VOUT ìRsense ì ƒC ìCO
R5 =
(1 œ D)ì VREF ìGEA
(17)
where
• ƒC is the selected crossover frequency
The value of C5 can be set by 方程式18.
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RO ìCO
2R5
C5 =
(18)
(19)
The value of C6 can be set by 方程式19.
RESR ì CO
R5
C6 =
If the calculated value of C6 is less than 10 pF, it can be left open.
Designing the loop for greater than 45° of phase margin and greater than 10-dB gain margin eliminates output
votlage ringing during the line and load transient.
9.2.3 Application Curves
Vout (AC)
20 mV/div
Vout (AC)
100 mV/div
Inductor
Current
2 A/div
Inductor
Current
1 A/div
SW
3 V/div
SW
3 V/div
VIN = 3.6 V
VOUT = 9 V
IOUT = 2 A
VIN = 3.6 V
VOUT = 9 V
IOUT = 200 mA
图9-2. Switching Waveforms in CCM
图9-3. Switching Waveforms in DCM
Vout (AC)
10 mV/div
EN
1 V/div
Inductor
Current
600 mA/div
Vout
2 V/div
SW
3 V/div
Inductor
Current
2 A/div
VIN = 3.6 V
VOUT = 9 V
IOUT = 20 mA
图9-4. Switching Waveforms in PFM Mode
图9-5. Start-up Waveforms
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EN
1 V/div
Output
Current
500 mA/div
Vout
2 V/div
Vout (AC)
500 mV/div
Inductor
Current
2 A/div
VIN = 3.6 V
VOUT = 9V
IOUT = 1 A to 2 A
图9-7. Load Transient
图9-6. Shutdown Waveforms
Input
Voltage
500 mV/div
Vout (AC)
200 mV/div
VIN = 3.3 V to 4.0
VOUT = 9 V
IOUT = 2 A
V
图9-8. Line Transient
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10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.7 V to 12 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the converter, additional bulk
capacitance can be required in addition to the ceramic bypass capacitors. A typical choice is an electrolytic or
tantalum capacitor with a value of 47 μF.
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11 Layout
11.1 Layout Guidelines
As for all switching power supplies, especially those running at high switching frequency and high currents,
layout is an important design step. If layout is not carefully done, the regulator could suffer from instability and
noise problems. To maximize efficiency, switching rise time and fall time are very fast. To prevent radiation of
high-frequency noise (for example, EMI), proper layout of the high-frequency switching path is essential.
Minimize the length and area of all traces connected to the SW pin, and always use a ground plane under the
switching regulator to minimize interplane coupling. The input capacitor needs to be close to the VIN pin and
GND pin to reduce the input supply current ripple.
The most critical current path for all boost converters is from the switching FET, through the rectifier FET, then
the output capacitors, and back to ground of the switching FET. This high current path contains nanosecond rise
time and fall time, and should be kept as short as possible. Therefore, the output capacitor needs not only to be
close to the VOUT pin, but also to the GND pin to reduce the overshoot at the SW pin and VOUT pin.
11.2 Layout Example
trace on bottom layer
GND
VOUT
EN
VOUT
GND
SW
SW
COMP
COUT
GND
L
CIN
VIN
图11-1. Layout Example
11.2.1 Thermal Considerations
The maximum IC junction temperature should be restricted to 125°C under normal operating conditions.
Calculate the maximum allowable dissipation, PD(max), and keep the actual power dissipation less than or equal
to PD(max). The maximum-power-dissipation limit is determined using 方程式20.
125 - TA
RqJA
PD(max)
=
(20)
where
• TA is the maximum ambient temperature for the application
• RθJA is the junction-to-ambient thermal resistance given in the Thermal Information table
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The TPS61089x comes in a thermally-enhanced VQFN package. The pads underneath the package improve the
thermal capabilities of the package. The real junction-to-ambient thermal resistance of the package greatly
depends on the PCB type, layout, and pad connection. Using thick PCB copper and soldering the SW pin, VOUT
pin, and GND pin to large copper plate enhances the thermal performance. Using more vias connects the
ground plate on the top layer and bottom layer around the IC without solder mask also improves the thermal
capability.
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12 Device and Documentation Support
12.1 Device Support
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
12.1.2 Development Support
12.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS61089x device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
HotRod™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
15-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS61089RNRR
TPS61089RNRT
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
RNR
RNR
11
11
3000 RoHS & Green
250 RoHS & Green
Call TI | NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
ZGOI
ZGOI
Samples
Samples
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Jul-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS61089RNRR
TPS61089RNRT
VQFN-
HR
RNR
RNR
11
11
3000
250
180.0
8.4
2.25
2.8
1.1
4.0
8.0
Q2
VQFN-
HR
180.0
8.4
2.25
2.8
1.1
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS61089RNRR
TPS61089RNRT
VQFN-HR
VQFN-HR
RNR
RNR
11
11
3000
250
182.0
182.0
182.0
182.0
20.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
RNR0011A
VQFN - 1 mm max height
SCALE 4.500
PLASTIC QUAD FLATPACK - NO LEAD
2.6
2.4
B
A
PIN 1 INDEX AREA
2.1
1.9
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
0.7
0.4
0.3
0.45
0.25
2X
7X
2X
(0.2) TYP
5
6
4
7
0.9
0.7
2X
1.5
PKG
6X 0.5
0.9
0.7
11
10
1
0.3
SYMM
0.45
0.25
8X
(0.18)
0.2
0.1
0.05
C B
A
2X (0.25)
ALL PADS
C
1.1
0.9
4222143/A 08/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RNR0011A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1)
SYMM
(
0.2) VIA
(0.25)
(0.38)
11
8X (0.55)
8X (0.25)
1
(1)
10
(1)
(0.7)
PKG
(0.7)
6X (0.5)
2X (1)
7
4
(R0.05) TYP
5
6
2X
(0.35)
(0.7)
(2.35)
LAND PATTERN EXAMPLE
SCALE:25X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
PADS 5,6 & 11
NON SOLDER MASK
DEFINED
PADS 1-4 & 7-10
SOLDER MASK DETAILS
4222143/A 08/2015
NOTES: (continued)
3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
RNR0011A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1)
(0.75)
SYMM
2X (0.25)
2X (0.28)
SOLDER MASK
EDGE, TYP
11
8X (0.55)
1
10
2X
(1.06)
8X (0.25)
(0.52)
PKG
(0.46)
2X
(0.74)
6X (0.5)
2X (0.92)
7
4
(R0.05) TYP
6
5
METAL UNDER
SOLDER MASK
TYP
2X (0.35)
(0.7)
(2.35)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PADS 5 & 6: 90% - PAD 11: 79%
SCALE:30X
4222143/A 08/2015
NOTES: (continued)
5. For alternate stencil design recommendations, see IPC-7525 or board assembly site preference.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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