TPS61281DYFFT [TI]
具有直通模式的 2.3MHz、3A 同步升压转换器 | YFF | 16 | -40 to 85;型号: | TPS61281DYFFT |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有直通模式的 2.3MHz、3A 同步升压转换器 | YFF | 16 | -40 to 85 升压转换器 |
文件: | 总63页 (文件大小:4105K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS61280D, TPS61281D, TPS61282D,, TPS61280E
ZHCSHC3B –JANUARY 2018 –REVISED JUNE 2023
TPS6128xD/E 适用于单节锂离子、富镍、硅阳极电池应用的
低IQ、宽电压电池前端直流/直流转换器
1 特性
3 说明
• 频率为2.3MHz 时,工作效率达95%
• 低IQ 直通模式下具有3µA 静态电流
• 2.3V 至4.8V 的宽VIN 范围
• VOUT = 3.35V 且VIN ≥2.65V 时,IOUT ≥4A(峰
值)
TPS6128xD/E 器件可以为由锂离子、富镍、硅阳极或
磷酸铁锂电池供电的产品提供电源解决方案。电压范围
针对诸如智能手机或平板电脑内单节电池便携式应用进
行了优化。
TPS6128xD/E 可用作高功率预稳压器,延长电池运行
时间并克服受电系统的输入电流和电压限制。
• 集成直通模式(35mΩ)
• 可编程谷值电感器电流限值和输出电压
• 关断期间进入真正的直通模式
• 出色的线路和负载瞬态
在关断情况下,TPS6128xD/E 运行在真正的直通模式
下,静态耗电仅为3µA,可充分延长电池寿命。
• 低纹波轻负载PFM 模式
运行期间,当电池处于良好的充电状态中时,一个低欧
姆、高效集成直通路径将电池连接至受电系统。
• 具有片上E2PROM(写保护)的原样定制
• 两个接口选项:
如果电池进入较低的充电状态,并且其电压变为低于所
需的最小系统电压时,此器件无缝转换至升压模式以利
用整个电池容量。
– 与I2C 兼容的I/F:高达3.4Mbps
(TPS61280D/E)
– 简单的I/O 逻辑控制接口
• 热关断和过载保护
• 总解决方案尺寸< 20mm2,规格:小于1mm
器件信息(1)
封装尺寸(标称值)
器件型号
TPS61280D
封装
2 应用
TPS61281D
TPS61282D
TPS61280E
DSBGA (16)
1.66mm x 1.66mm
• 单节富镍、硅阳极、锂离子、磷酸铁锂电池的智能
手机或平板电脑
• 2.5G、3G、4G 小型模块数据卡
• 具有高峰值功率负载的电流受限应用
(1) 要了解所有可用封装,请参见数据表末尾的可订购产品附录。
TPS61280D
SW
SW
VIN
VIN
VOUT
VBAT’
L
VOUT
0.47μH
CO (x2)
10µF X5R 6.3V (0603)
Battery
2.5V .. 4.35V
CI
1.5µF X5R 6.3V (0402)
Voltage Select
Enable
VSEL
EN
1.8V
Forced Bypass / Auto
BYP
SCL
I2 C Bus
Interrupt
SDA
GPIO
PGND
PGND
PGND
AGND
Copyright © 2016, Texas Instruments Incorporated
简化版原理图
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLVSEA0
TPS61280D, TPS61281D, TPS61282D,, TPS61280E
ZHCSHC3B –JANUARY 2018 –REVISED JUNE 2023
www.ti.com.cn
Table of Contents
9.5 Programming............................................................ 25
9.6 Register Maps...........................................................28
10 Application and Implementation................................37
10.1 Application Information........................................... 37
10.2 Typical Application.................................................. 38
11 Power Supply Recommendations..............................51
12 Layout...........................................................................52
12.1 Layout Guidelines................................................... 52
12.2 Layout Example...................................................... 52
12.3 Thermal Information................................................53
13 Device and Documentation Support..........................54
13.1 Device Support....................................................... 54
13.2 接收文档更新通知................................................... 54
13.3 支持资源..................................................................54
13.4 Trademarks.............................................................54
13.5 静电放电警告.......................................................... 54
13.6 术语表..................................................................... 54
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明(续).........................................................................3
6 Device Comparison Table...............................................3
7 Pin Configuration and Functions...................................4
8 Specifications.................................................................. 6
8.1 Absolute Maximum Ratings........................................ 6
8.2 ESD Ratings............................................................... 6
8.3 Recommended Operating Conditions.........................6
8.4 Thermal Information....................................................7
8.5 Electrical Characteristics.............................................7
8.6 I2C Interface Timing Characteristics(1) ....................... 9
8.7 I2C Timing Diagrams................................................. 11
8.8 Typical Characteristics..............................................12
9 Detailed Description......................................................14
9.1 Overview...................................................................14
9.2 Functional Block Diagram.........................................16
9.3 Feature Description...................................................17
9.4 Device Functional Modes..........................................18
Information.................................................................... 55
14.1 Package Summary..................................................55
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision A (August 2018) to Revision B (June 2023)
Page
• TPS61280E 初始发行版..................................................................................................................................... 1
Changes from Revision * (January 2018) to Revision A (August 2018)
Page
• 将产品预发布 添加到量产 数据...........................................................................................................................1
• 将器件TPS61281D 和TPS61282D 从产品预发布 更改为量产数据.................................................................1
• Changed the TPS61280D pin configuration....................................................................................................... 4
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Product Folder Links: TPS61280D TPS61281D TPS61282D, TPS61280E
English Data Sheet: SLVSEA0
TPS61280D, TPS61281D, TPS61282D,, TPS61280E
www.ti.com.cn
ZHCSHC3B –JANUARY 2018 –REVISED JUNE 2023
5 说明(续)
TPS6128xD/E 器件支持超过 4A 的脉冲负载电流,即使是深度放电的电池亦可。在这种运行模式下,
TPS6128xD/E 可充分使用全部电池容量:克服了具有最小高电平输入电压的受电元件的电池切断电压过高的问
题;新的电池化学物质可完全放电;该器件可对强制系统关断的高电流脉冲进行缓冲,从而实现在升压和旁路模
式之间的无缝转换。
这会对电池导通时间产生很大影响,从而在相同的电池容量前提下提供更长的使用时间和更佳的用户体验,或者
在相同的使用时间前提下降低电池成本。
TPS6128xD/E 采用 16 引脚 Chip-Scale Package (CSP),最大限度地减少了外部元件的数量,因此拥有非常小巧
的解决方案尺寸(< 20mm2),支持使用小型电感器和输入电容器。
TPS6128xD/E 在2.3MHz 的同步升压模式下运行,在轻负载电流情况下会进入省电模式运行(PFM),以便在整个
负载电流范围内保持高效率。
6 Device Comparison Table
DEVICE
SPECIFIC FEATURES
PART NUMBER
DC/DC boost / bypass threshold = 3.15 V (VSEL = L)
I2C Control Interface
DC/DC boost / bypass threshold = 3.35 V (VSEL = H)
Valley inductor current limit = 3 A
TPS61280D
TPS61281D
TPS61282D
User Prog. E2PROM Settings
GPIO pin default configuration is RST/FAULT input/output
DC/DC boost / bypass threshold = 3.15 V (VSEL = L)
DC/DC boost / bypass threshold = 3.35 V (VSEL = H)
Valley inductor current limit = 3 A
Simple Logic Control Interface
Simple Logic Control Interface
GPIO pin default configuration is RST/FAULT input/output
DC/DC boost / bypass threshold = 3.3 V (VSEL = L)
DC/DC boost / bypass threshold = 3.5 V (VSEL = H)
Valley inductor current limit = 4 A
GPIO pin default configuration is RST/FAULT input/output
DC/DC boost / bypass threshold = 3.4 V (VSEL = L)
DC/DC boost / bypass threshold = 3.45 V (VSEL = H)
Valley inductor current limit = 5 A
I2C Control Interface
Support 1.2 V I/O
TPS61280E
I/O logic Low/High: 0.36V / 0.84V
GPIO pin default configuration is mode selection input
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Product Folder Links: TPS61280D TPS61281D TPS61282D, TPS61280E
English Data Sheet: SLVSEA0
TPS61280D, TPS61281D, TPS61282D,, TPS61280E
ZHCSHC3B –JANUARY 2018 –REVISED JUNE 2023
www.ti.com.cn
7 Pin Configuration and Functions
1
2
3
4
1
2
3
4
A
B
C
D
EN
GPIO
VIN
VIN
D
C
B
A
AGND
PGND
PGND
PGND
VSEL
nBYP
AGND
SCL
VOUT
VOUT
nBYP
VSEL
EN
SDA
SW
VOUT
VIN
SW
SDA
SW
SW
SCL
VOUT
PGND
PGND
PGND
GPIO
VIN
Not to scale
Not to scale
图7-1. TPS61280D/E YFF Package 16-Bump
图7-2. TPS61280D/E YFF Package 16-Bump
DSBGA Top View
DSBGA Bottom View
表7-1. Pin Functions, TPS61280D/E
PIN
I/O
DESCRIPTION
NAME
VIN
NO.
A3, A4
B3, B4
I
Power supply input.
VOUT
O
Boost converter output.
This is the enable pin of the device. On the rising edge of the enable pin, all the registers are reset with their default
values. This input must not be left floating and must be terminated.
EN = Low: The device is forced into shutdown mode and the I2C control interface is disabled. Depending on the logic
level applied to the nBYP input, the converter can either be forced in pass-through mode or it's output can be
regulated to a minimum level so as to limit the input-to-output voltage difference to less than 3.6V (typ). The current
consumption is reduced to a few µA. For more details, refer to 表9-2.
EN
A1
I
EN = High: The device is operating normally featuring automatic dc/dc boost, pass-through mode transition. For more
details, refer to 表9-2.
This pin can either be configured as a input (mode selection) or as dual role input/open-drain output RST/ FAULT )
pin. For TPS61280D, default configuration is RST/ FAULT input/output. For TPS61280E, default configuration is
mode selection input. The input must not be left floating and must be terminated.
Manual Reset Input: Drive RST/ FAULT low to initiate a reset of the converter's output. nRST/nFAULT controls a
falling edge-triggered sequence consisting of a discharge phase of the capacitance located at the converter's output
followed by a start-up phase.
GPIO
A2
I/O
Fault Output (open-drain interrupt signal to host): Indicates that a fault has occurred (e.g. thermal shutdown, output
voltage out of limits, current limit triggered, and so on). To signal such an event, the device generates a falling edge-
triggered interrupt by driving a negative pulse onto the GPIO line and then releases the line to its inactive state.
Mode selection input = Low: The device is operating in regulated frequency pulse width modulation mode (PWM) at
high-load currents and in pulse frequency modulation mode (PFM) at light load currents.
Mode selection input = High: Low-noise mode enabled, regulated frequency PWM operation forced.
VSEL signal is primarily used to set the output voltage dc/dc boost, pass-through threshold. This pin must not be left
floating and must be terminated.
VSEL
nBYP
B1
C1
I
I
A logic low level on the BYP input forces the device in pass-through mode. This pin must not be left floating and must
be terminated.
SCL
B2
C2
I
Serial interface clock line. This pin must not be left floating and must be terminated.
Serial interface address/data line. This pin must not be left floating and must be terminated.
Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor.
Power ground pin.
SDA
I/O
I/O
SW
C3, C4
D2, D3, D4
D1
PGND
AGND
Analog ground pin. This is the signal ground reference for the IC.
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Product Folder Links: TPS61280D TPS61281D TPS61282D, TPS61280E
English Data Sheet: SLVSEA0
TPS61280D, TPS61281D, TPS61282D,, TPS61280E
www.ti.com.cn
ZHCSHC3B –JANUARY 2018 –REVISED JUNE 2023
1
2
3
4
1
2
3
4
A
B
C
D
EN
PG
VIN
VIN
D
C
B
A
AGND
PGND
PGND
PGND
VSEL
nBYP
AGND
MODE
AGND
PGND
VOUT
VOUT
nBYP
VSEL
EN
AGND
MODE
PG
SW
VOUT
VIN
SW
SW
SW
VOUT
PGND
PGND
VIN
Not to scale
Not to scale
图7-3. TPS6128xD YFF Package 16-Bump DSBGA 图7-4. TPS6128xD YFF Package 16-Bump DSBGA
Top View
Bottom View
表7-2. Pin Functions, TPS6128xD
PIN
I/O
DESCRIPTION
NAME
VIN
NO.
A3, A4
B3, B4
I
Power supply input.
Boost converter output.
VOUT
O
This is the enable pin of the device. On the rising edge of the enable pin, all the registers are reset with their default
values. This input must not be left floating and must be terminated.
EN = Low: The device is forced into shutdown mode. Depending on the logic level applied to the nBYP input, the
converter can either be forced in pass-through mode or it's output can be regulated to a minimum level so as to limit
the input-to-output voltage difference to less than 3.6V (typ). The current consumption is reduced to a few µA. For
more details, refer to 表9-2.
EN
A1
I
EN = High: The device is operating normally featuring automatic dc/dc boost, pass-through mode transition. For more
details, refer to 表9-2.
Power-Good Output (open-drain output to host): A logic high on the PG output indicates that the converter's output
voltage is within its regulation limits. A logic low indicates a fault has occurred (e.g. thermal shutdown, output voltage
out of limits, current limit triggered, and so on). The PG signal is de-asserted automatically once the IC resumes
proper operation.
PG
A2
O
VSEL signal is primarily used to set the output voltage dc/dc boost, pass-through threshold. This pin must not be left
floating and must be terminated.
VSEL
nBYP
B1
C1
I
I
A logic low level on the BYP input forces the device in pass-through mode. For more details, refer to 表9-2. This pin
must not be left floating and must be terminated.
This is the mode selection pin of the device. This pin must not be left floating, must be terminated and can be
connected to AGND. During start-up this pin must be held low. Once the output voltage settled and PG pin indicates
that the converter's output voltage is within its regulation limits the device can be forced in PWM mode operation by
applying a high level on this pin.
MODE
B2
I
MODE = Low: The device is operating in regulated frequency pulse width modulation mode (PWM) at high-load
currents and in pulse frequency modulation mode (PFM) at light load currents. This pin must be held low during
device start-up.
MODE = High: Low-noise mode enabled, regulated frequency PWM operation forced.
Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor.
Power ground pin.
SW
C3, C4
D2, D3, D4
C2, D1
I/O
PGND
AGND
Analog ground pin. This is the signal ground reference for the IC.
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Product Folder Links: TPS61280D TPS61281D TPS61282D, TPS61280E
English Data Sheet: SLVSEA0
TPS61280D, TPS61281D, TPS61282D,, TPS61280E
ZHCSHC3B –JANUARY 2018 –REVISED JUNE 2023
www.ti.com.cn
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
-0.3
MAX
4.7
UNIT
V
Voltage at VOUT (boost mode)(2)
Voltage at VOUT (by pass mode)(2)
DC
DC
5.2
V
Voltage at VIN(2), EN(2), VSEL(2), BYP (2), PG(2)
GPIO(2)
,
DC
5.2
V
–0.3
Voltage at SCL(2), SDA(2)MODE(2)
DC
DC
3.6
5.2
V
V
–0.3
–0.3
Input voltage
Voltage at SW(2)
Transient: 2 ns, 2.3
MHz
5.5
V
–0.3
Differential voltage between VIN and VOUT
Differential voltage between SW and VOUT
Continuous average current into SW (4)
Peak current into SW (5)
DC
DC
4
V
V
A
A
–0.3
–0.3
4.7
1.8
5.5
Input current
Power dissipation
Temperature range
Internally limited
(3)
Operating temperature range, TA
85
°C
°C
°C
–40
–40
–65
Operating virtual junction, TJ
Storage temperature range
150
150
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to network ground terminal.
(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature
may have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature
(TJ(max)), the maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of
the part/package in the application (θJA), as given by the following equation: TA(max) = TJ(max) –(θJA X PD(max)). To achieve optimum
performance, it is recommended to operate the device with a maximum junction temperature of 105°C.
(4) Limit the junction temperature to 105°C for continuous operation at maximum output power.
(5) Limit the junction temperature to 105°C for 15% duty cycle operation.
8.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001, all pins (1)
±2000
V
VESD
Electrostatic discharge
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±1000
±200
V
V
Machine Model - (MM)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
MIN
2.30
3.4
NOM
MAX UNIT
Input voltage range
4.85
3.6
V
V
VI
Input voltage range for in-situ customization by E2PROM write operation
3.5
470
13
L
Inductance
200
9
800
100
nH
µF
mA
°C
CO
IL
Output capacitance
Maximum load current during start-up
Ambient temperature
250
–40
TA
85
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Product Folder Links: TPS61280D TPS61281D TPS61282D, TPS61280E
English Data Sheet: SLVSEA0
TPS61280D, TPS61281D, TPS61282D,, TPS61280E
www.ti.com.cn
ZHCSHC3B –JANUARY 2018 –REVISED JUNE 2023
MIN
NOM
MAX UNIT
125 °C
TJ
Operating junction temperature
–40
8.4 Thermal Information
TPS6128xD/E
THERMAL METRIC(1)
YFF (DSBGA)
UNIT
16 PINS
78
RθJA
RθJCtop
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
0.6
13
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.4
13
ψJB
RθJCbot
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Electrical Characteristics
Minimum and maximum values are at VIN = 2.3 V to 4.85 V, VOUT = 3.4 V (or VIN, whichever is higher), EN = 1.8 V, VSEL =
1.8 V, nBYP = 1.8 V, –40°C ≤TJ ≤125°C; Circuit of Parameter Measurement Information section (unless otherwise
noted). Typical values are at VIN = 3.2 V, VOUT = 3.4 V, EN = 1.8 V, TJ = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
SUPPLY CURRENT
DC/DC boost mode. Device not
switching
47.4
65.6
µA
IOUT = 0 mA, VIN = 3.2 V, VOUT = 3.4 V
Operating quiescent current
into VIN
Pass-through mode (auto)
EN = 1.8 V, BYP = 1.8 V, VIN = 3.6 V
27.4
15.4
42.6
25.6
µA
µA
TPS6128xD/
E
IQ
Pass-through mode (forced)
EN = 1.8 V, BYP = AGND, VOUT = 3.6 V
–40°C ≤TJ
≤85°C
DC/DC boost mode. Device not
switching
IOUT = 0 mA, VIN = 3.2 V, VOUT = 3.4 V
Operating quiescent current
into VOUT
8.9
19.6
µA
EN = 0 V, BYP = 0 V, VIN = 3.6 V
EN = 0 V, BYP = 1.8 V, VIN = 3.6 V
Falling
3
8.9
2
6.6
20.6
2.1
μA
μA
V
TPS6128xD/
E
ISD
Shutdown current
TPS6128xD/
E
VUVLO
Under-voltage lockout threshold
Hysteresis
0.1
V
EN, VSEL, nBYP, MODE, SDA, SCL, GPIO, PG
VIL
VIH
VIL
VIH
Low-level input voltage
0.4
V
V
V
V
V
V
TPS6128xD
TPS61280E
TPS61280D
High-level input voltage
1.2
Low-level input voltage
0.36
High-level input voltage
0.84
Low-level output voltage (SDA)
Low-level output voltage (GPIO)
IOL = 8 mA
0.3
0.3
IOL = 8 mA, GPIOCFG = 0
VOL
TPS6128xD/
E
Low-level output voltage (PG)
IOL = 8 mA
0.3
V
EN, VSEL, BYP,
pull-down resistance
TPS6128xD/
E
RPD
300
Input ≤0.4 V
kΩ
EN, VSEL, BYP, MODE, PG
input capacitance
TPS6128xD/
E
9
9
pF
pF
CIN
Input connected to AGND or VIN
SDA, SCL, GPIO input capacitance TPS61280D
Rising VOUT
Falling VOUT
0.95 x VOUT
0.9 x VOUT
TPS6128xD/
VTHPG
Power good threshold
E
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Product Folder Links: TPS61280D TPS61281D TPS61282D, TPS61280E
English Data Sheet: SLVSEA0
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Minimum and maximum values are at VIN = 2.3 V to 4.85 V, VOUT = 3.4 V (or VIN, whichever is higher), EN = 1.8 V, VSEL =
1.8 V, nBYP = 1.8 V, –40°C ≤TJ ≤125°C; Circuit of Parameter Measurement Information section (unless otherwise
noted). Typical values are at VIN = 3.2 V, VOUT = 3.4 V, EN = 1.8 V, TJ = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
Ilkg
Input connected to AGND
0
µA
TPS6128xD/
E
–40°C ≤TJ
≤85°C
Input leakage current
Input connected VIN
No load. Open loop
0.5
µA
OUTPUT
VOUT
TPS6128xD/
E
Threshold DC voltage accuracy
Regulated DC voltage accuracy
-1.5%
-2%
1.5%
2%
(TH)
2.65 V ≤VIN ≤VOUT_TH - 150 mV
IOUT = 0mA
PWM operation.
TPS6128xD/
E
VOUT
2.65 V ≤VIN ≤VOUT_TH - 150 mV
IOUT = 0 mA
-2%
4%
PFM/PWM operation
Power-save mode
output ripple voltage
PFM operation, IOUT = 1 mA
30
15
mVpk
mVpk
TPS6128xD/
E
ΔVOUT
PWM mode output ripple voltage
PWM operation, IOUT = 500 mA
POWER SWITCH
Low-side switch MOSFET
VIN = 3.2 V, VOUT = 3.5 V
VIN = 3.2 V, VOUT = 3.5 V
VIN = 3.2 V
45
40
80
70
60
2
mΩ
mΩ
mΩ
µA
on resistance
High-side rectifier MOSFET
on resistance
TPS6128xD/
E
rDS(on)
High-side pass-through MOSFET
on resistance
35
EN = AGND, VIN = VOUT = SW = 3.5 V
–40°C ≤TJ ≤85°C
Reverse leakage current into SW
Reverse leakage current into VOUT
0.1
TPS6128xD/
E
Ilkg
EN = BYP = VIN, VIN = 2.9 V, VOUT = 4.4 V, VSW = 0 V
device not switching
0.11
2
µA
–40°C ≤TJ ≤85°C
TPS6128xD/
E
ISINK
VOUT sink capability
0.3
V
EN = AGND, VOUT ≤3.6 V,IOUT = -10 mA
TPS61280D
TPS61281D
VIN = 2.9 V, VOUT = 3.5 V, –40°C ≤TJ ≤125°C, auto
PFM/PWM
Valley inductor current limit
Valley inductor current limit
Valley inductor current limit
2475
3300
4300
3000 3525
4000 4700
5000 6200
mA
mA
mA
VIN = 2.9 V, VOUT = 3.5 V, –40°C ≤TJ ≤125°C, auto
PFM/PWM
TPS61282D
TPS61280E
VIN = 2.9 V, VOUT = 3.4 V, –40°C ≤TJ ≤125°C, auto
PFM/PWM
EN = BYP = GND, VIN = 3.2 V
5000
mA
mA
TPS6128xD/
E
Pass through mode current limit
EN = VIN, BYP = don't care , VIN = 3.2 V
5600
500
7400 9100
Pre-charge mode current limit
(linear mode, phase 1)
650
mA
mA
TPS6128xD/
E
VIN - VOUT >= 300 mV
Pre-charge mode current limit
(linear mode, phase 2)
2000
OSCILLATOR
TPS6128xD/
E
fOSC
Oscillator frequency
VIN = 2.7 V, VOUT = 3.5 V
2.3
MHz
THERMAL SHUTDOWN, HOT DIE DETECTOR
Thermal shutdown(1)
TPS6128xD/
E
140
-10
160
°C
°C
Hot die detector accuracy(1)
TPS61280D
105
10
TIMING
TPS6128xD/
E
VIN = 3.2 V, VOUT_TH = 01011 (3.4 V), RLOAD = 50 Ω
Time from active VIN to VOUT settled
Start-up time
500
µs
ns
GPIO rise time(1)
TPS61280D
200
(1) Specified by characterization. Not tested in production.
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8.6 I2C Interface Timing Characteristics(1)
PARAMETER
TEST CONDITIONS
Standard mode
Fast mode
MIN
MAX
100
400
1
UNIT
kHz
kHz
Fast mode plus
MHz
MHz
MHz
MHz
MHz
3.4
3.4
1.7
1.7
High-speed mode (write operation), CB –100 pF max
f(SCL)
SCL Clock Frequency
High-speed mode (read operation), CB –100 pF max
High-speed mode (write operation), CB –400 pF max
High-speed mode (read operation), CB –400 pF max
Standard mode
Fast mode
4.7
1.3
0.5
4
μs
μs
μs
μs
ns
Bus Free Time Between a STOP and
START Condition
tBUF
Fast mode plus
Standard mode
Fast mode
600
260
160
4.7
1.3
0.5
160
320
4
Hold Time (Repeated) START
Condition
tHD, tSTA
Fast mode plus
High-speed mode
Standard mode
Fast mode
ns
ns
μs
μs
μs
ns
tLOW
LOW Period of the SCL Clock
Fast mode plus
High-speed mode, CB –100 pF max
High-speed mode, CB –400 pF max
Standard mode
ns
μs
ns
ns
ns
ns
Fast mode
600
260
60
Fast mode plus
tHIGH
HIGH Period of the SCL Clock
High-speed mode, CB –100 pF max
High-speed mode, CB –400 pF max
Standard mode
120
4.7
600
260
160
250
100
50
μs
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Fast mode
Setup Time for a Repeated START
Condition
tSU, tSTA
Fast mode plus
High-speed mode
Standard mode
Fast mode
tSU, tDAT Data Setup Time
Fast mode plus
High-speed mode
Standard mode
10
0
3.45
0.9
Fast mode
0
tHD, tDAT Data Hold Time
Fast mode plus
0
0
70
150
1000
300
120
40
High-speed mode, CB –100 pF max
High-speed mode, CB –400 pF max
Standard mode
0
Fast mode
20 + 0.1 CB
Fast mode plus
tRCL
Rise Time of SCL Signal
10
20
High-speed mode, CB –100 pF max
High-speed mode, CB –400 pF max
Standard mode
80
20 + 0.1 CB
20 + 0.1 CB
1000
300
120
80
Fast mode
Rise Time of SCL Signal After a Repeated
START Condition and After an
Acknowledge BIT
Fast mode plus
tRCL1
10
20
High-speed mode, CB –100 pF max
High-speed mode, CB –400 pF max
160
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PARAMETER
TEST CONDITIONS
Standard mode
MIN
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20 + 0.1 CB
300
300
120
40
Fast mode
Fast mode plus
tFCL
tRDA
tFDA
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
10
20
High-speed mode, CB –100 pF max
High-speed mode, CB –400 pF max
Standard mode
80
1000
300
120
80
Fast mode
20 + 0.1 CB
Fast mode plus
10
20
High-speed mode, CB –100 pF max
High-speed mode, CB –400 pF max
Standard mode
160
300
300
120
80
Fast mode
20 + 0.1 CB
Fast mode plus
10
20
High-speed mode, CB –100 pF max
High-speed mode, CB –400 pF max
Standard mode
160
4
μs
ns
Fast mode
600
260
160
tSU, tSTO Setup Time of STOP Condition
Fast mode plus
ns
High-Speed mode
ns
Standard mode
400
400
550
400
pF
pF
pF
pF
Fast mode
CB
Capacitive Load for SDA and SCL
Fast mode plus
High-Speed mode
(1) Specified by design. Not tested in production.
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8.7 I2C Timing Diagrams
SDA
t
t
BUF
f
t
f
t
t
LOW
t
r
su;DAT
t
t
r
hd;STA
SCL
t
t
t
hd;STA
t
su;STA
su;STO
hd;DAT
HIGH
S
Sr
P
S
图8-1. Serial Interface Timing Diagram for Standard-, Fast-, Fast-Mode Plus
Sr
Sr P
t
fDA
t
rDA
SDAH
t
hd;DAT
t
su;STO
t
t
t
su;DAT
su;STA
hd;STA
SCLH
t
fCL
t
t
rCL1
rCL1
t
rCL
t
t
t
t
HIGH
HIGH
LOW
LOW
See Note A
= MCS Current Source Pull-Up
= R Resistor Pull-Up
See Note A
(P)
Note A: First rising edge of the SCLH signal after Sr and after each acknowledge bit.
图8-2. Serial Interface Timing Diagram for H/S-Mode
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8.8 Typical Characteristics
50
48
46
44
42
40
38
36
34
32
30
70
65
60
55
50
45
40
35
30
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
C001
C002
Junction Temperature (°C)
Junction Temperature (°C)
VIN = 3.2 V
VOUT = 3.5 V
VIN = 3.2 V
VOUT = 3.5 V
TJ = –40 to 125°C
TJ = –40 to 125°C
图8-3. High side Rds(on) vs Junction Temperature
图8-4. Low side Rds(on) vs Junction Temperature
50
48
46
44
42
40
38
36
34
32
30
60
50
40
TJ = 30°C
TJ = -40°C
T= 85°C
J
30
-40
-20
0
20
40
60
80
100
120
2.3
2.5
2.7
2.9
3.1
C003
C004
Junction Temperature (°C)
Input Voltage (V)
VIN = 3.2 V
Bypass
VIN = 2.3 - 3.4 V
EN = High
VOUT = 3.4 V
Bypass = High
IOUT = 0 mA
TJ = –40 to 125°C
图8-5. Bypass FET Rds(on) vs Junction
图8-6. Quiescent Current at Boost Mode vs Input
Temperature
Voltage
20
18
16
14
35
33
31
29
27
25
23
21
TJ=30°C
TJ=30°C
12
10
19
TJ=-40°C
T = 85°C
TJ=-40°C
17
T = 85°C
J
J
15
3.5
4.5
3.5
4.5
C005
C006
Input Voltage (V)
Input Voltage (V)
VIN = 3.5 - 4.4 V
EN = High
VOUT = 3.4 V
Bypass = Low
IOUT = 0 mA
VIN = 3.6 - 4.4 V
EN = High
VOUT = 3.4 V
Bypass = High
IOUT = 0 mA
图8-7. Quiescent Current at Forced Bypass Mode 图8-8. Quiescent Current at Auto Bypass Mode vs
vs Input Voltage
Input Voltage
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5
13
12
11
10
9
4
3
2
1
8
7
6
TJ = 30°C
TJ = 30°C
5
TJ = -40°C
T= -40°C
J
4
T = 85°C
TJ = 85°C
J
0
3
2.3
3.3
4.3
2.3
3.3
4.3
C007
C008
Input Voltage (V)
Input Voltage (V)
VIN = 2.3 - 4.4 V
EN = Low
VOUT = 4.4 V
Bypass = Low
VSW = 0 V
VIN = 2.3 - 4.4 V
EN = Low
VOUT = 4.4 V
Bypass = High
VSW = 0 V
图8-9. Shutdown Current at Low IQ mode vs Input
图8-10. Shutdown Current vs Input Voltage
Voltage
4.5
4.0
3.5
3.0
2.20
2.00
2.5
2.0
TPS61281D
TPS61282D
110
VIN Rising
VFalling
IN
1.80
-40
-20
0
20
40
60
80
100
120
-40
10
Temperature ( C)
60
O
C009
C010
Junction Temperature (°C)
A.
VIN = 3.2 V
EN = High
VOUT = 3.5 V
VIN = 3.2 V
VOUT = 3.5 V
TJ = –40 to 125°C
TJ = –40 to 125°C
Bypass = High
图8-12. VIN UVLO Threshold Rising/Falling vs
图8-11. Switch Valley Current Limit: TPS61281D,
Junction Temperature
TPS61282D vs Input Voltage
1.10
1.10
EN Rising
nBYP Rising
EN Falling
nBYP Falling
1.00
0.90
0.80
0.70
0.60
0.50
1.00
0.90
0.80
0.70
0.60
0.50
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
C011
C012
Junction Temperature (°C)
Junction Temperature (°C)
VIN = 3.2 V
VOUT = 3.5 V
VIN = 3.2 V
TJ = –40 to 125°C
TJ = –40 to 125°C
图8-13. EN Logic High Threshold Rising/Falling vs 图8-14. BYP Logic High Threshold Rising/Falling
Junction Temperature
vs Junction Temperature
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9 Detailed Description
9.1 Overview
The TPS6128xD/E is a high-efficiency step-up converter featuring pass-through mode optimized to provide low-
noise voltage supply for 2G RF power amplifiers (PAs) in mobile phones and/or to pre-regulate voltage for
supplying subsystem like eMMC memory, audio codec, LCD bias, antenna switches, RF engine PMIC and so
on. It is designed to allow the system to operate at maximum efficiency for a wide range of power consumption
levels from a low-, wide- voltage battery cell.
The capability of the TPS6128xD/E to step-up the voltage as well as to pass-through the input battery voltage
when its level is high enough allow systems to operate at maximum performance over a wide range of battery
voltages, thereby extending the battery life between charging. The device also addresses brownouts caused by
the peak currents drawn by the APU and GPU which can cause the battery rail to droop momentarily. Using the
TPS6128xD/E device as a pre-regulator eliminates system brownout condition while maintaining a stable supply
rail for critical sub-system to function properly.
The TPS6128xD/E synchronous step-up converter typically operates at a quasi-constant 2.3-MHz frequency
pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the TPS6128xD/E
converter operates in power-save mode with pulse frequency modulation (PFM).
In general, a dc/dc step-up converter can only operate in "true" boost mode, that is the output “boosted” by a
certain amount above the input voltage. The TPS6128xD/E device operates differently as it can smoothly
transition in and out of zero duty cycle operation. Depending upon the input voltage, output voltage threshold
and load current, the integrated bypass switch automatically transitions the converter into pass-through mode to
maintain low-dropout and high-efficiency. The device exits pass-through mode (0% duty cycle operation) if the
total dropout resistance in bypass mode is insufficient to maintain the output voltage at it's nominal level. Refer
to the typical characteristics section (DC Output Voltage vs. Input Voltage) for further details.
During PWM operation, the converter uses a novel quasi-constant on-time valley current mode control scheme
to achieve excellent line/load regulation and allows the use of a small ceramic inductor and capacitors. Based on
the VIN/VOUT ratio, a simple circuit predicts the required on-time. At the beginning of the switching cycle, the low-
side N-MOS switch is turned-on and the inductor current ramps up to a peak current that is defined by the on-
time and the inductance. In the second phase, once the on-timer has expired, the rectifier is turned-on and the
inductor current decays to a preset valley current threshold. Finally, the switching cycle repeats by setting the on
timer again and activating the low-side N-MOS switch.
The current mode architecture provides excellent transient load response, requiring minimal output filtering.
Internal soft-start and loop compensation simplifies the design process while minimizing the number of external
components.
The TPS6128xD/E directly and accurately controls the average input current through intelligent adjustment of the
valley current limit, allowing an accuracy of ±17.5%. Together with an external bulk capacitor, the TPS6128xD/E
allows an application to be interfaced directly to its load, without overloading the input source due to appropriate
set average input current limit. An open-drain output (PG or GPIO/nFAULT) provides a signal to issue an
interrupt to the system if any fault is detected on the device (thermal shutdown, output voltage out-of limits, and
so on).
The output voltage can be dynamically adjusted between two values (floor and roof voltages) by toggling a logic
control input (VSEL) without the need for external feedback resistors. This features can either be used to raise
the output voltage in anticipation of a positive load transient or to dynamically change the PA supply voltage
depending on its mode of operation and/or transmitting power.
The TPS61280D integrates an I2C compatible interface allowing transfers up to 3.4Mbps. This communication
interface can be used to set the output voltage threshold at which the converter transitions between boost and
pass-through mode, for reprogramming the mode of operation (PFM/PWM or forced PWM), for settings the
average input current limit or resetting the output voltage for instance.
Configuration parameters can be changed by writing the desired values to the appropriate I2C register(s). The
I2C registers are volatile and their contents are lost when power is removed from the device. By writing to the 节
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9.6.10, it is possible to store the active configuration in non-volatile E2PROM; during power-up, the contents of
the E2PROM are copied into the I2C registers and used to configure the device.
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9.2 Functional Block Diagram
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9.3 Feature Description
9.3.1 Voltage Scaling Management (VSEL)
In order to maintain a certain minimum output voltage under heavy load transients, the output voltage set point
can be dynamically increased by asserting the VSEL input. The functionality also helps to mitigate undershoot
during severe line transients, while minimizing the output voltage during more benign operating conditions to
save power.
The output voltage ramps up (floor to roof transition) at pre-defined rate defined by the average input current limit
setting. The required time to ramp down the voltage (roof to floor transition) largely depends on the amount of
capacitance present at the converter's output as well as on the load current. 表 9-1 shows the ramp rate control
when transitioning to a lower voltage.
表9-1. Ramp Down Rate vs. Target Mode
Mode Associated with Floor Voltage
Output Voltage Ramp Rate
Forced PWM
Output capacitance is being discharged at a rate of approx. 50mA (or higher) constant current
in addition to the load current drawn
PFM
Output capacitance is being discharged (solely) by the load current drawn
9.3.2 Spread Spectrum, PWM Frequency Dithering
The goal is to spread out the emitted RF energy over a larger frequency range so that the resulting EMI is similar
to white noise. The end result is a spectrum that is continuous and lower in peak amplitude, making it easier to
comply with electromagnetic interference (EMI) standards and with the power supply ripple requirements in
cellular and non-cellular wireless applications. Radio receivers are typically susceptible to narrowband noise that
is focused on specific frequencies.
Switching regulators can be particularly troublesome in applications where electromagnetic interference (EMI) is
a concern. Switching regulators operate on a cycle-by-cycle basis to transfer power to an output. In most cases,
the frequency of operation is either fixed or regulated, based on the output load. This method of conversion
creates large components of noise at the frequency of operation (fundamental) and multiples of the operating
frequency (harmonics).
The spread spectrum architecture varies the switching frequency by ca. ±15% of the nominal switching
frequency thereby significantly reducing the peak radiated and conducting noise on both the input and output
supplies. The frequency dithering scheme is modulated with a triangle profile and a modulation frequency fm.
0 dBV
F
Dfc
ENV,PEAK
Dfc
Non-modulated harmonic
F
1
Side-band harmonics
window after modulation
0 dBVref
B = 2×fm ×(1+ mf )= 2×(Dfc + fm )
Bh = 2×fm ×(1+ mf ×h)
B = 2×fm ×(1+ mf )= 2×(Dfc + fm
)
图9-1. Spectrum of a Frequency Modulated Sin.
图9-2. Spread Bands of Harmonics in Modulated
Square Signals 1
Wave with Sinusoidal Variation in Time
1
Spectrum illustrations and formulae (图9-1 and 图9-2) copyright IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY,
VOL. 47, NO.3, AUGUST 2005.
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The above figures show that after modulation the sideband harmonic is attenuated compared to the non-
modulated harmonic, and the harmonic energy is spread into a certain frequency band. The higher the
modulation index (mf) the larger the attenuation.
δ ´ ƒc
mƒ
=
ƒm
(1)
where
• fc is the carrier frequency (approx. 2.3MHz)
• fm is the modulating frequency (approx. 40kHz)
• δis the modulation ratio (approx 0.15)
Dƒc
d =
ƒc
(2)
The maximum switching frequency fc is limited by the process and finally the parameter modulation ratio (δ),
together with fm, which is the side-band harmonics bandwidth around the carrier frequency fc. The bandwidth of
a frequency modulated waveform is approximately given by the Carson’s rule and can be summarized as:
B = 2 ´ ¦m ´ 1 + m = 2 ´ D¦ + ¦m
(
)
(
)
¦
c
(3)
fm < RBW: The receiver is not able to distinguish individual side-band harmonics, so, several harmonics are
added in the input filter and the measured value is higher than expected in theoretical calculations.
fm > RBW: The receiver is able to properly measure each individual side-band harmonic separately, so the
measurements match with the theoretical calculations.
9.4 Device Functional Modes
9.4.1 Power-Save Mode
The TPS6128xD/E integrates a power-save mode to improve efficiency at light load. In power save mode the
converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output
voltage with several pulses and goes into power save mode once the output voltage exceeds the set threshold
voltage. The PFM mode is left and PWM mode entered in case the output current can not longer be supported in
PFM mode.
图9-3. Power-Save Mode Ripple
9.4.2 Pass-Through Mode
The TPS6128xD/E contains an internal switch for bypassing the dc/dc boost converter during pass-through
mode. When the input voltage is larger than the preset output voltage, the converter seamlessly transitions into
0% duty cycle operation and the bypass FET is fully enhanced. Entry in pass-through mode is triggered by
condition where VOUT >(1+2%)* VOUT_NORM and no switching has occurred during past 8µs.
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In this mode of operation, the load (2G RF PA for instance) is directly supplied from the battery for maximum RF
output power, highest efficiency and lowest possible input-to-output voltage difference. The device consumes
only a standby current of 15µA (typ). In pass-through mode, the device is short-circuit protected by a very fast
current limit detection scheme.
During this operation, the output voltage follows the input voltage and will not fall below the programmed output
voltage threshold as the input voltage decreases. The output voltage drop during pass-through mode depends
on the load current and input voltage, the resulting output voltage is calculated as:
VOUT = V - (RDSON(BP) x IOUT
)
IN
(4)
(5)
Conversely, the efficiency in pass-through mode is defined as:
IOUT
η = 1 - RDSON(BP)
V
IN
• in which RDSON(BP) is the typical on-resistance of the bypass FET
4.5
4.4
4.3
4.2
4.1
4
3.9
3.8
3.7
3.6
3.5
3.4
3.3
Vout_nom = 3.15V
3.2
3.1
3
Vout_nom = 3.35V
Vout_nom = 3.3V
Vout_nom = 3.5V
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5
Input Voltage (V)
G000
图9-4. DC Output Voltage vs. Input Voltage
Pass-through mode exit is triggered when the output voltage reaches the pre-defined threshold (that is, 3.4V).
During pass-through mode, the TPS6128xD/E device is short-circuit protected by a fast current limit detection
scheme. If the current in the pass-through FET exceeds approximately 7.3 Amps a fault is declared and the
device cycles through a start-up procedure.
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9.4.3 Mode Selection
Depending on the settings of 节 9.6.5 the device can be operated at a quasi-constant 2.3-MHz frequency PWM
mode or in automatic PFM/PWM mode. In this mode, the converter operates in pseudo-fixed frequency PWM
mode at moderate to heavy loads and in the PFM mode during light loads, which maintains high efficiency over a
wide load current range. For more details, see the 节9.6.5 description.
The quasi-constant frequency PWM mode has the tightest regulation and the best line/load transient
performance. In forced PWM mode, the device features a unique RDS(ON) management function to maintain high
broadband efficiency as well as low resistance in pass-through mode.
In the TPS61280D/E device, the GPIO pin can be configured (via the 节 9.6.5) to select the operating mode of
the device. In the other TPS6128xD/E devices, the MODE pin is used to select the operating mode. Pulling this
pin high forces the converter to operate in the PWM mode even at light load currents. The advantage is that the
converter modulates its switching frequency according to a spread spectrum PWM modulation technique
allowing simple filtering of the switching harmonics in noise-sensitive applications.
For additional flexibility, it is possible to switch from power-save mode (GPIO or MODE input = L) to PWM mode
(GPIO or MODE input = H) during operation. This allows efficient power management by adjusting the operation
of the converter to the specific system requirements (that is, 2G RF PA Rx/Tx operation).
Entry to forced pass-through mode (nBYP = L) initiates with a current limited transition followed by a true bypass
state. To prevent reverse current to the battery, the devices waits until the output discharges below the input
voltage level before entering forced pass-through mode. Care should be taken to prohibit the output voltage from
collapsing whilst transitioning into forced pass-through mode under heavy load conditions and/or limited output
capacitance. This can be easily done by adding capacitance to the output of the converter. In forced pass-
through mode, the output follows the input below the preset output threshold voltage (VOUT_TH).
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9.4.4 Current Limit Operation
The TPS6128xD/E device features a valley inductor current limit scheme.
In dc/dc boost mode, the TPS6128xD/E device employs a current limit detection scheme in which the voltage
drop across the synchronous rectifier is sensed during the off-time. In the TPS61280D the current limit threshold
can be set via an I2C register. TPS6128xD/E devices have a fixed current limit threshold. See 节 6 for detailed
information.
The output voltage is reduced as the power stage of the device operates in a constant current mode. The
maximum continuous output current (IOUT(MAX)), before entering current limit (CL) operation, can be defined by
方程式6.
V I N
I O U T ( M A X _ D C ) = I
´
´ h
L I M I T
V O U T
(6)
where
• ηis the efficiency
• The inductor peak-to-peak current ripple (ΔIL) is calculated by 方程式7
V
D
f
IN
DIL =
´
L
(7)
The output current, IOUT(DC), is the average of the rectifier ripple current waveform. When the load current is
increased such that the trough is above the current limit threshold, the off-time is increased to allow the current
to decrease to this threshold before the next on-time begins (so called frequency fold-back mechanism). When
the current limit is reached the output voltage decreases during further load increase.
图9-5 illustrates the inductor and rectifier current waveforms during current limit operation.
I
PEAK
I
L
Current Limit
Threshold
I
VALLEY
Rectifier
Current
I
DI
OUT
L
I
OUT(DC)
Increased
Load Current
I
IN(DC)
f
Inductor
Current
I
IN(DC)
DI
L
V
D
f
IN
×
ΔI
=
L
L
图9-5. Inductor/Rectifier Currents in Current Limit Operation (DC/DC Boost Mode)
During pass-through mode, the TPS6128xD/E device is short-circuit protected by a very fast current limit
detection scheme. If the current in the bypass FET exceeds approximately 7.5Amps a fault is declared and the
device cycles through a start-up procedure.
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9.4.5 Start-Up and Shutdown Mode
The TPS6128xD/E automatically powers-up as soon as the input voltage is applied. The device has an internal
soft-start circuit that limits the inrush current during start-up. The first phase in the start-up procedure is to bias
the output node close to the input level (so called pre-charge phase).
In this operating mode, the device limits its output current to ca. 500mA. Should the output voltage not have
reached the input level within a maximum duration of 750µs, the device automatically increases its pre-charge
current to ca. 2000mA. If the output voltage still fails to reach its target after 1.5ms, a fault condition is declared.
After waiting 1ms, a restart is attempted.
When output voltage being close to Vout, the device enters into boost startup mode (for Auto Mode only). The
device provides a reduced current limit of ~1.25A (I2C programable for TPS61280D to set it back to normal
current limit) when the output voltage is below pre-set voltage to avoid the high inrush current from battery.
During start-up, it is recommended to keep DC load current draw below 250mA.
The TPS6128xD/E device contains a thermal regulation loop that monitors the die temperature during the pre-
charge phase. If the die temperature rises to high values of about 110°C, the device automatically reduces the
current to prevent the die temperature from increasing further. Once the die temperature drops about 10°C
below the threshold, the device will automatically increase the current to the target value. This function also
reduces the current during a short-circuit condition.
When the EN and nBYP pins are set high, the device enters normal operation (that is, automatic dc/dc boost,
pass-through mode) and ensures that the output voltage remains above a pre-defined threshold (that is, 3.3 V).
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Setting the EN pin low (nBYP = 1) forces the TPS6128xD/E device in shutdown mode with a current
consumption of <8.5 µA typical. In this mode, the output of the converter is regulated to a minimum level so as to
limit the input-to-output voltage difference to less than 3.6 V (typical). The device is capable of sinking up to 10
mA output current and prohibits reverse current flow from the output to the input. For proper operation, the EN
pin must be terminated and must not be left floating.
Changing operating mode from auto mode (EN = nBYP = 1) to low IQ Pass-through mode (EN = nBYP = 0) with
device pins EN and nBYP can either be done controlling EN and nBYP pins from same control signal (delay
between signal < 60ns) or first switching in forced pass-through mode (EN = 1, nBYP = 0) followed by switching
to low IQ Pass-through mode (EN = nBYP = 0).
The TPS6128xD/E device also features the possibility of shutting the converter output for a short period of time,
either via the nRST/nFAULT (GPIO). Pulling this input low initiates a reset of the converter's output. The
sequence is falling edge-triggered and consists of a discharge phase (down to ca. 600 mV or lower) of the
capacitance located at the converter's output followed by a start-up phase.
表9-2. Mode of Operation
EN Input
nBYP Input
Device State
The device is shut down in pass-through mode featuring a shutdown current down to ca. 3µA typ.
The load current capability is limited (up to ca. 250mA).
0
0
The device is shut down and the output voltage is reduced to a minimum value (VIN - VOUT ≤3.6V).
The device shutdown current is approximately 8.5µA typ.
0
1
1
1
0
1
The device is active in forced pass-through mode.
The device supply current is approximately 15µA typ. from the battery. The device is short circuit protected
by a current limit of ca.7300mA.
The device is active in auto mode (dc/dc boost, pass-through).
The device supply current is approximately 50µA typ. from the battery.
9.4.6 Undervoltage Lockout
The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and the battery
from excessive discharge. The I2C control interface and the output stage of the converter are disabled once the
falling VIN trips the under-voltage lockout threshold VUVLO (2 V typical). The device starts operation once the
rising VIN trips VUVLO threshold plus its hysteresis of 100 mV at typ. 2.1 V.
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9.4.7 Thermal Shutdown
As soon as the junction temperature, TJ, exceeds 160°C (typ.) the device goes into thermal shutdown. In this
mode the bypass, high-side and low-side MOSFETs are turned-off. When the junction temperature falls below
the thermal shutdown minus its hysteresis, the device continuous the operation.
9.4.8 Fault State and Power-Good
The TPS6128xD/E enters the fault state under any of the followings conditions:
• The output voltage fails to achieve the required level during a start-up phase.
• The output voltage falls out of regulation (in pre-charge mode).
• The device has entered thermal shutdown.
Once a fault is triggered, the regulator stops operating and disconnects the load. After waiting 1ms, the device
attempts to restart. The TPS61280D device can be configured to signal a fault condition by pulling the open-
drain GPIO pin (nFAULT) low for a short period of time. The nFAULT output provides a falling edge triggered
interrupt signal to the host. To ensure proper operation, the GPIO port needs to be pull high quick enough, that
is, faster than ca. 200ns. To do so, it is recommended to use a GPIO pull-up resistor in the range of 1kΩ to
10kΩ.
The TPS6128xD/E (simple logic I/F version) device only provide a power-good output (PG) for signaling the
system when the regulator has successfully completed start-up and no faults have occurred. Power-good also
functions as an early warning flag for excessive die temperature and overload conditions.
• PG is asserted high when the start-up sequence is successfully completed.
• PG is pulled low when the output voltage falls approximately 10% below its regulation level or the die
temperature exceeds 115°C. PG is re-asserted high when the device cools below ca. 100°C.
• Any fault condition causes PG to be de-asserted.
• PG is pulled high when the device is operating in forced pass-through mode (that is, nBYP = L).
• PG is pulled high when the device is in shutdown mode.
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9.5 Programming
9.5.1 Serial Interface Description (TPS61280D/E)
I2C™ is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors (see I2C-Bus
Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-
up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices
connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or
a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device
addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A
slave device receives and/or transmits data on the bus under control of the master device.
The TPS6128xD/E device works as a slave and supports the following data transfer modes, as defined in the
I2C-Bus Specification: standard mode (100 kbps) and fast mode (400 kbps), fast mode plus (1 Mbps) and high-
speed mode (3.4 Mbps). The interface adds flexibility to the power supply solution, enabling most functions to be
programmed to new values depending on the instantaneous application requirements. Register contents remain
intact as long as supply voltage remains above 2.1V.
The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-
mode in this document. The protocol for high-speed mode is different from F/S-mode, and it is referred to as HS-
mode. The TPS6128xD/E device supports 7-bit addressing; 10-bit addressing and general call address are not
supported. The device 7bit address is defined as ‘111 0101’.
It is recommended that the I2C masters initiates a STOP condition on the I2C bus after the initial power up of
SDA and SCL pull-up voltages to ensure reset of the TPS6128xD/E I2C engine.
9.5.2 Standard-, Fast-, Fast-Mode Plus Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in 图 9-6. All I2C-compatible devices should
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
图9-6. START and STOP Conditions
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see 图 9-7). All devices recognize the
address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see 图 9-8) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with
a slave has been established.
DATA
CLK
Data line
stable;
data valid
Change
of data
allowed
图9-7. Bit Transfer on the Serial Interface
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The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to
high while the SCL line is high (see 图 9-6). This releases the bus and stops the communication link with the
addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop
condition, all devices know that the bus is released, and they wait for a start condition followed by a matching
address.
Attempting to read data from register addresses not listed in this section will result in 00h being read out.
图9-8. Acknowledge on the I2C Bus
图9-9. Bus Protocol
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9.5.3 HS-Mode Protocol
The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.
This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS
master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the
start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that
transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the
internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start
conditions should be used to secure the bus in HS-mode.
Attempting to read data from register addresses not listed in this section will result in 00h being read out.
9.5.4 TPS6128xD/E I2C Update Sequence
The TPS6128xD/E requires a start condition, a valid I2C address, a register address byte, and a data byte for a
single update. After the receipt of each byte, TPS6128xD/E device acknowledges by pulling the SDA line low
during the high period of a single clock pulse. A valid I2C address selects the TPS6128xD/E. TPS6128xD/E
performs an update on the falling edge of the acknowledge signal that follows the LSB byte.
7
8
8
1
1
1
1
1
1
S
Slave Address
R/W
A
Register Address
A
Data
P
A/A
“0” Write
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
Sr = REPEATED START condition
P = STOP condition
From Master to TPS6128xD
From TPS6128xD to Master
图9-10. : “Write”Data Transfer Format in Standard-, Fast, Fast-Plus Modes
7
8
7
8
1
1
1
1
1
1
1
1
1
S
Slave Address
R/W
A
Register Address
A
Sr
Slave Address
R/W
A
Data
A/A
P
“0” Write
“1” Read
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
Sr = REPEATED START condition
P = STOP condition
From Master to TPS6128xD
From TPS6128xD to Master
图9-11. “Read”Data Transfer Format in Standard-, Fast, Fast-Plus Modes
F/S Mode
HS Mode
F/S Mode
8
7
8
8
1
1
1
1
1
1
1
1
HS-Master Code
A
Sr
Slave Address
R/W
A
Register Address
A
Data
A/A
P
S
Data Transferred
(n x Bytes + Acknowledge)
HS Mode Continues
Slave Address
Sr
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
Sr = REPEATED START condition
P = STOP condition
From Master to TPS6128xD
From TPS6128xD to Master
图9-12. Data Transfer Format in H/S-Mode
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9.6 Register Maps
9.6.1 Slave Address Byte
MSB
LSB
1
1
1
0
1
A1
A0
The slave address byte is the first byte received following the START condition from the master device.
9.6.2 Register Address Byte
MSB
LSB
0
0
0
0
0
D2
D1
D0
Following the successful acknowledgment of the slave address, the bus master will send a byte to the
TPS6128xD, which will contain the address of the register to be accessed.
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9.6.3 I2C Registers, E2PROM, Write Protect
Configuration parameters can be changed by writing the desired values to the appropriate I2C register(s). The
I2C registers are volatile and their contents are lost when power is removed from the device. By writing to the 节
9.6.10, it is possible to store the active configuration in non-volatile E2PROM; during power-up, the contents of
the E2PROM are copied into the I2C registers and used to configure the device.
备注
An active high Write Protect (WP) bit prevents the configuration parameters from being changed by
accident. Once the E2PROM memory has been programmed with Write Protect (WP) bit set, its
content will be locked and can not be reprogrammed any more.
Configuration parameters can be read from the I2C register(s) or E2PROM registers at any time (the WP bit has
no effect on read operations).
9.6.4 E2PROM Configuration Parameters
表9-3 shows the memory map of the configuration parameters.
表9-3. Configuration Memory Map
Register
Address
Factory
Default
Register Name
节9.6.5
Description
01h
02h
xxh
xxh
Sets miscellaneous configuration bits
Sets the floor output voltage threshold boost / pass-through mode change
(VSEL = L)
节9.6.6
Sets the roof output voltage threshold boost / pass-through mode change
(VSEL = H)
03h
xxh
节9.6.7
04h
05h
xxh
xxh
Sets the average input current limit in dc/dc boost mode
Returns status flags
节9.6.8
节9.6.9
Controls whether read and write operations access
I2C or E2PROM registers
FFh
00h
节9.6.10
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The following procedure details how to save the content of all I2C registers to the E2PROM non-volatile
configuration memory.
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (for example EAh)
3. TPS6128xD acknowledges (SDA low)
4. Bus master sends address of 节9.6.10 (FFh)
5. TPS6128xD acknowledges (SDA low)
6. Bus master sends data to be written to the Control Register (C0h)
7. TPS6128xD acknowledges (SDA low)
8. Bus master sends STOP condition
Control Register Address
Control Register Data
C0h
P
S
7-Bit Slave Address
0
A
A
A
EAh
FFh
图9-13. Saving Contents of all I2C Registers to E2PROM
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9.6.5 CONFIG Register [reset = 0x01]
Memory location: 0x01
图9-14. CONFIG Register
7
RESET
R/W
6
R/W
Y
5
R/W
Y
4
3
2
1
0
R/W
Y
ENABLE
RESERVED
R/W
GPIOCFG
R/W
SSFM
R/W
MODE_CTRL
R/W
Stored in E2
N
N
Y
Y
Y
表9-4. CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
Device reset bit.
0: Normal operation. or line breaks
7
RESET
R/W
0
1: Default values are set to all internal registers. The device
operation is cycled (ON-OFF-ON), that is, the converter is
disabled for a short period of time and the output is reset.
Device enable bits.
00: Device operation follows hardware control signal (refer to
表9-2).
01: Device operates in auto transition mode (dc/dc boost,
bypass) regardless of the nBYP control signal (EN = 1).
10: Device is forced in pass-through mode regardless of the
nBYP control signal (EN = 1).
11: Device is in shutdown mode. The output voltage is
reduced to a minimum value (VIN - VOUT ≤3.6V) regardless
of the nBYP control signal (EN = 1).
6:5
ENABLE
R/W
R/W
0
0
Reserved bit.
This bits is reserved for future use. During write operations
data intended for this bit is ignored, and during read
operations 0 is returned.
4
RESERVED
GPIO port configuration bit.
0 for TPS61280D
1 for TPS61280E
0: GPIO port is configured to support manual reset input
(nRST) and interrupt generation output (nFAULT).
1: GPIO port is configured as a device mode selection input.
3
2
GPIOCFG
SSFM
R/W
R/W
Spread modulation control.
0: Spread spectrum modulation is disabled.
1: Spread spectrum modulation is enabled in PWM mode
0
1
Device mode of operation bits.
00: Device operation follows hardware control signal (GPIO
must be configured as mode selection input).
01: PFM with automatic transition into PWM operation.
10: Forced PWM operation.
1:0
MODE_CTRL
R/W
11: PFM with automatic transition into PWM operation (VSEL
= L), forced PWM operation (VSEL = H).
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9.6.6 VOUTFLOORSET Register [reset = 0x02]
Memory location: 0x02
图9-15. VOUTFLOORSET Register
7
6
5
R/W
N
4
R/W
Y
3
R/W
Y
2
1
R/W
Y
0
R/W
Y
RESERVED
R/W
VOUTFLOOR_TH
R/W
R/W
Stored in E2
N
N
Y
表9-5. VOUTFLOORSET Register Field Descriptions
Reset
Reset
Bit
Field
Type
(TPS6128 (TPS612 Description
0D)
80E)
Reserved bit.
This bits is reserved for future use. During write operations
data intended for this bit is ignored, and during read
operations 0 is returned.
7:5
4
RESERVED
R/W
R/W
0
0
Output voltage threshold, dc/dc boost / pass-through mode
change.
0
0
00000: 2.850V
00001: 2.900V
00010: 2.950V
00011: 3.000V
00100: 3.050V
00101: 3.100V
00110: 3.150V
00111: 3.200V
01000: 3.250V
01001: 3.300V
01010: 3.350V
01011: 3.400V
01100: 3.450V
01101: 3.500V
01110: 3.550V
01111: 3.600V
10000: 3.650V
10001: 3.700V
10010: 3.750V
10011: 3.800V
10100: 3.850V
10101: 3.900V
10110: 3.950V
10111: 4.000V
11000: 4.050V
11001: 4.100V
11010: 4.150V
11011: 4.200V
11100: 4.250V
11101: 4.300V
11110: 4.350V
11111: 4.400V
3
2
1
R/W
R/W
R/W
0
1
1
1
0
1
VOUTFLOOR_TH
0
R/W
0
1
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9.6.7 VOUTROOFSET Register [reset = 0x03]
Memory location: 0x03
图9-16. VOUTROOFSET Register
7
6
5
R/W
N
4
R/W
Y
3
R/W
Y
2
1
R/W
Y
0
R/W
Y
RESERVED
R/W
VOUTROOF_TH
R/W
R/W
Stored in E2
N
N
Y
表9-6. VOUTROOFSET Register Field Descriptions
Reset
Reset
Bit
Field
Type
(TPS6128 (TPS612 Description
0D)
80E)
you can use Para elements with role attributes set for IP-
XACT
or line breaks
You cannot use "morerows" in these tables, see wiki for
more information 'Register Guidelines'
7:5
4
RESERVED
R/W
R/W
0
0
Output voltage threshold, dc/dc boost / pass-through mode
change.
0
0
00000: 2.850V
00001: 2.900V
00010: 2.950V
00011: 3.000V
00100: 3.050V
00101: 3.100V
00110: 3.150V
00111: 3.200V
01000: 3.250V
01001: 3.300V
01010: 3.350V
01011: 3.400V
01100: 3.450V
01101: 3.500V
01110: 3.550V
01111: 3.600V
10000: 3.650V
10001: 3.700V
10010: 3.750V
10011: 3.800V
10100: 3.850V
10101: 3.900V
10110: 3.950V
10111: 4.000V
11000: 4.050V
11001: 4.100V
11010: 4.150V
11011: 4.200V
11100: 4.250V
11101: 4.300V
11110: 4.350V
11111: 4.400V
3
2
1
R/W
R/W
R/W
1
0
1
1
1
0
VOUTROOF_TH
0
R/W
0
0
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9.6.8 ILIMSET Register [reset = 0x04]
Memory location: 0x04
图9-17. ILIMSET Register
7
6
R/W
N
5
4
3
R/W
Y
2
R/W
Y
1
R/W
Y
0
R/W
Y
RESERVED
ILIM OFF
R/W
Soft-start
R/W
ILIM
R/W
Stored in E2
N
N
Y
表9-7. ILIMSET Register Field Descriptions
Reset
Reset
Bit
Field
Type
R/W
R/W
(TPS6128 (TPS612 Description
0D)
80E)
Reserved bit.
This bits is reserved for future use. During write operations
data intended for this bit is ignored, and during read
operations 0 is returned.
7:6
5
RESERVED
0
0
Enable/Disable Current Limit
0 : Current Limit Enabled
1 : Current Limit Disabled
ILIM OFF
Soft-start
0
1
0
1
Soft-start selection bit.
0: DC/DC boost soft-start current is limited per ILIM bit
settings
4
R/W
1: DC/DC boost soft-start current is limited to ca. 1250mA
inductor valley current
3
2
1
R/W
R/W
R/W
1
0
1
1
1
1
Inductor valley current limit in dc/dc boost mode
(COUTRNG bit = 0)(1)
1000: 1500mA
1001: 2000mA
1010: 2500mA
1011: 3000mA
1100: 3500mA
1101: 4000mA
1110: 4500mA
1111: 5000mA
.
ILIM
0
R/W
1
1
(1) Refer to 节9.4.5 Mode section for additional information.
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9.6.9 Status Register [reset = 0x05]
Memory location: 0x05
图9-18. Status Register
7
6
HOTDIE
R
5
DCDCMODE
R
4
OPMODE
R
3
ILIMPT
R
2
ILIMBST
R
1
FAULT
R
0
PGOOD
R
TSD
R
Stored in E2
N
N
N
N
N
N
N
N
表9-8. Status Register Field Descriptions
Bit
Field
Type
Reset
Description
Thermal shutdown status bit.
0: Normal operation.
7
TSD
R
0
1: Thermal shutdown tripped. This flag is reset after readout.
Instantaneous die temperature bit.
0: TJ < 115°C.
1: TJ > 115°C.
6
5
4
HOTDIE
R
R
R
0
0
0
DC/DC mode of operation status bit.
1: Device operates in PFM mode.
0: Device operates in PWM mode.
DCDCMODE
OPMODE
Device mode of operation status bit.
0: Device operates in pass-through mode.
1: Device operates in dc/dc mode.
Current limit status bit (pass-through mode).
0: Normal operation.
1: Indicates that the bypass FET current limit has triggered. This
flag is reset after readout.
3
2
1
0
ILIMPT
ILIMBST
FAULT
R
R
R
R
0
0
0
0
Current limit status bit (dc/dc boost mode).
0: Normal operation.
1: Indicates that the average input current limit has triggered for
1.5ms in dc/dc boost mode. This flag is reset after readout.
FAULT status bit.
0: Normal operation.
1: Indicates that a fault condition has occurred. This flag is reset
after readout.
Power Good status bit.
0: Indicates the output voltage is out of regulation.
1: Indicates the output voltage is within its nominal range. This
bit is set if the converter is forced in pass-through mode.
PGOOD
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9.6.10 E2PROMCTRL Register [reset = 0xFF]
Memory location: 0xFF
图9-19. E2PROMCTRL Register
7
WEN
6
5
4
R/W
N
3
R/W
N
2
1
R/W
N
0
R/W
N
WP
R/W
ISE2PROMWP
R
RESERVED
R/W
R/W
Stored in E2
N
Y
N
N
表9-9. E2PROMCTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
E2PROM Write Enable bit.
0: No operation.
1: Forces the contents of selected I2C register bits to be copied
into E2PROM, thereby making them the default values during
power-up. When the contents of all the I2C register bits have
been written to the E2PROM, the device automatically resets
this bit.
7
WEN
R/W
0
E2PROM Write Protect bit.
0: Normal operation.
1: Forces the E2PROM content to be locked following a write
sequence (WEN = 1). This protects the E2PROM content from
undesirable write actions making it virus safe. This process is
non reversible.
6
WP
R/W
0
E2PROM Write Protect Status bit.
0: E2PROM content is not write protected. E2PROM content can
still be updated.
5
ISE2PROMWP
RESERVED
R
0
0
1: E2PROM content is write protected. E2PROM content is
permanently locked.
Reserved bit.
This bits is reserved for future use. During write operations data
intended for this bit is ignored, and during read operations 0 is
returned.
4:0
R/W
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10 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
10.1 Application Information
The devices are step up dc/dc converters with true bypass function integrated. They are typically used as
preregulators with input voltage ranges from 2.3V to 4.8V, extend the battery run time and overcome input
current and input voltage limitations of the system being powered.
While the input voltage higher than boost/bypass threshold, the high-efficient integrated pass-through path
connects the battery to the powered system directly.
If the input voltage becomes lower than boost/bypass threshold, the device seamlessly transitions into boost
mode operation with a maximum available output current of 3 A.
The following design procedure can be used to select component values for the TPS61281D and TPS61282D
(also applicable for TPS61280D/E just by I2C program).
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10.2 Typical Application
10.2.1 TPS61281D with 2.5V-4.35 VIN, 1500 mA Output Current (TPS61280D with default I2C
Configuration)
LM3242
SuPA
BUCK / BYPASS
CIN
10 µF
3
CIN
4.7 µF
2
WL8PM27
SuPA
BUCK
CIN
4.7 µF
WIF
PMIC
Vcore1, 1.05V
SMPS
SMPS
LDO
CDECOUPLING
10 µF
TPS61281D
Vcore2, 1.15V
SW
SW
VIN
VIN
VOUT
VOUT
VBAT’
L
eMMC, 2.95V
LCD, 2.80V
0.47 μH
00mV
CDECOUPLING
10 µF
2.7V
CO (x2)
10µF X5R 6.3V (0603)
LDO
Battery
Antenna switche
2.60V
2.7V .. 4.35V
LDO
CI
1.5µF X5R 6.3V (0402)
Note: Resistive load equivalent
for the measurement result.
Voltage Select
Enable
VSEL
EN
1.8V
Forced Bypass / Auto
PFM/FPWM
BYP
Interrupt
MODE
PGND
PGND
PGND
PG
AGND
AGND
Copyright © 2016, Texas Instruments Incorpo
图10-1. TPS61281D Application Circuit with 1500mA Output Current
10.2.1.1 Design Requirement
表10-1. Design Parameters
REFERENCE
DESCRIPTION
SAMPLE VALUES
VIN
Input voltage range
2.5V-4.35V
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表10-1. Design Parameters (continued)
REFERENCE
DESCRIPTION
Output voltage range at VSEL = Low
Output voltage range VSEL = High
Output current
SAMPLE VALUES
VOUT = 3.15 V if VIN ≤3.15 V, VOUT = VIN if VIN > 3.15 V
VOUT= 3.35 V if VIN ≤3.35 V, VOUT = VIN if VIN > 3.35 V
1500mA
VOUT
VOUT
IOUT
10.2.1.2 Detailed Design Parameters
10.2.1.2.1 Inductor Selection
A boost converter normally requires two main passive components for storing energy during the conversion, an
inductor and an output capacitor are required. It is advisable to select an inductor with a saturation current rating
higher than the possible peak current flowing through the power switches.
The inductor peak current varies as a function of the load, the input and output voltages and can be estimated
using 方程式8.
V xD
IOUT
V
IN
IN
IL(PEAK)
=
+
with D = 1-
2 x f x L
(1-D) x h
VOUT
(8)
Selecting an inductor with insufficient saturation performance can lead to excessive peak current in the
converter. This could eventually harm the device and reduce it's reliability.
When selecting the inductor, as well as the inductance, parameters of importance are: maximum current rating,
series resistance, and operating temperature. The inductor DC current rating should be greater than the
maximum input average current, refer to 方程式9 and the 节9.4.4 section for more details.
VOUT
1
IL(DC)
=
x
x IOUT
V
h
IN
(9)
The TPS6128xD series of step-up converters have been optimized to operate with a effective inductance in the
range of 200 nH to 800 nH. Larger or smaller inductor values can be used to optimize the performance of the
device for specific operating conditions. For more details, see the 节10.2.1.2.4 section.
In high-frequency converter applications, the efficiency is essentially affected by the inductor AC resistance (that
is, quality factor) and to a smaller extent by the inductor DCR value. To achieve high efficiency operation, care
should be taken in selecting inductors featuring a quality factor above 25 at the switching frequency. Increasing
the inductor value produces lower RMS currents, but degrades transient response. For a given physical inductor
size, increased inductance usually results in an inductor with lower saturation current.
The total losses of the coil consist of both the losses in the DC resistance, R(DC) , and the following frequency-
dependent components:
• The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
• Additional losses in the conductor from the skin effect (current displacement at high frequencies)
• Magnetic field losses of the neighboring windings (proximity effect)
• Radiation losses
For good efficiency, the inductor DC resistance should be less than 30 mΩ. The following inductor series from
different suppliers have been used with the TPS6128xD converters.
表10-2. List of Inductors
SERIES
DIMENSIONS (in mm)
2.5 x 2.0 x 1.0 max. height
2.5 x 2.0 x 1.2 max. height
2.5 x 2.0 x 1.0 max. height
DC INPUT CURRENT LIMIT SETTING
DFE252010C
DFE252012C
DFR252010C
≤3000 mA
≤3500 mA
≤3000 mA
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表10-2. List of Inductors (continued)
SERIES
DIMENSIONS (in mm)
2.5 x 2.0 x 1.2 max. height
2.5 x 2.0 x 1.2 max. height
2.0 x 1.6 x 1.0 max. height
2.0 x 1.6 x 1.2 max. height
2.0 x 1.6 x 1.2 max. height
DC INPUT CURRENT LIMIT SETTING
DFE252012C
DFE252012P
DFE201610C
DFE201612C
DFE201612P
≤3500 mA
≤3500 mA
≤2000 mA
≤3000 mA
≤3000 mA
10.2.1.2.2 Output Capacitor
For the output capacitor, it is recommended to use small ceramic capacitors placed as close as possible to the
VOUT and GND pins of the IC. If, for any reason, the application requires the use of large capacitors which can
not be placed close to the IC, using a smaller ceramic capacitor in parallel to the large one is highly
recommended. This small capacitor should be placed as close as possible to the VOUT and GND pins of the IC.
To get an estimate of the recommended minimum output capacitance, 方程式10 can be used.
IOUT x (VOUT - V )
IN
CMIN
=
f x DV x VOUT
(10)
where
• f is the switching frequency which is 2.3 MHz (typ.) and ΔV is the maximum allowed output ripple.
With a chosen ripple voltage of 20 mV, a minimum effective capacitance of 10 μF is needed. The total ripple is
larger due to the ESR and ESL of the output capacitor. This additional component of the ripple can be calculated
using 方程式11
I
ΔI
2
æ
L ö
OUT
ΔVOUT(ESR) = ESR x
+
ç
÷
1 - D
è
ø
(11)
(12)
(13)
I
ΔIL
2
1
æ
ö
OUT
ΔVOUT(ESL) = ESL x
+
- IOUT
x
ç
÷
1 - D
tSW(RISE)
è
ø
I
ΔIL
2
1
æ
ö
OUT
ΔVOUT(ESL) = ESL x
-
- IOUT
x
ç
÷
1 - D
tSW(FALL)
è
ø
where
• IOUT = output current of the application
• D = duty cycle
• ΔIL = inductor ripple current
• tSW(RISE) = switch node rise time
• tSW(FALL) = switch node fall time
• ESR = equivalent series resistance of the used output capacitor
• ESL = equivalent series inductance of the used output capacitor
An MLCC capacitor with twice the value of the calculated minimum should be used due to DC bias effects. This
is required to maintain control loop stability. The output capacitor requires either an X7R or X5R dielectric. Y5V
and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive
at high frequencies. There are no additional requirements regarding minimum ESR. Larger capacitors cause
lower output voltage ripple as well as lower output voltage drop during load transients.
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In applications featuring high (pulsed) load currents (e.g. ≥ 2 Amps), it is recommended to run the converter
with a reasonable amount of effective output capacitance and low-ESL device, for instance x2 22 µF X5R 6.3V
(0603) MLCC capacitors connected in parallel with a 1 µF X5R 6.3 V (0306-2T) MLCC LL capacitor.
DC bias effect: high cap. ceramic capacitors exhibit DC bias effects, which have a strong influence on the
device's effective capacitance. Therefore the right capacitor value has to be chosen very carefully. Package size
and voltage rating in combination with material are responsible for differences between the rated capacitor value
and it's effective capacitance. For instance, a 10 µF X5R 6.3 V (0603) MLCC capacitor would typically show an
effective capacitance of less than 5 µF (under 3.5 V bias condition, high temperature).
For RF Power Amplifier applications, the output capacitor loading is combined between the dc/dc converter and
the RF Power Amplifier (x2 10 µF X5R 6.3 V (0603) + PA input cap 4.7 µF X5R 6.3 V (0402)) are recommended.
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High values of output capacitance are mainly achieved by putting capacitors in parallel. This reduces the overall
series resistance (ESR) to very low values. This results in almost no voltage ripple at the output and therefore
the regulation circuit has no voltage drop to react on. Nevertheless, for accurate output voltage regulation even
with low ESR, the regulation loop can switch to a pure comparator regulation scheme.
10.2.1.2.3 Input Capacitor
Multilayer ceramic capacitors are an excellent choice for input decoupling of the step-up converter as they have
extremely low ESR and are available in small footprints. Input capacitors should be located as close as possible
to the device. While a 4.7-μF input capacitor is sufficient for most applications, larger values may be used to
reduce input current ripple without limitations.
Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce
ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even
damage the part. Additional "bulk" capacitance (electrolytic or tantalum) should in this circumstance be placed
between CI and the power source lead to reduce ringing than can occur between the inductance of the power
source leads and CI.
10.2.1.2.4 Checking Loop Stability
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
• Switching node, SW
• Inductor current, IL
• Output ripple voltage, VOUT(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between
the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply
all of the current required by the load. VOUT immediately shifts by an amount equal to ΔI(LOAD) x ESR, where
ESR is the effective series resistance of COUT. ΔI(LOAD) begins to charge or discharge COUT generating a
feedback error signal used by the regulator to return VOUT to its steady-state value. The results are most easily
interpreted when the device operates in PWM mode.
During this recovery time, VOUT can be monitored for settling time, overshoot or ringing that helps judge the
converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin. Because the
damping factor of the circuitry is directly related to several resistive parameters (that is, MOSFET rDS(on)) that are
temperature dependant, the loop stability analysis has to be done over the input voltage range, load current
range, and temperature range.
The TPS6128xD series of step-up converters have been optimized to operate with a effective inductance in the
range of 200 nH to 800 nH and with output capacitors in the range of 8 µF to 100 µF. The internal compensation
is optimized for an output filter of L = 0.5 µH and CO = 15 µF.
表10-3. Component List
DESCRIPTION
REFERENCE
PART NUMBER, MANUFACTURER(1)
GRM155R60J155ME80D
2 x GRM188R60J106ME84
DFE252012CR470
CIN
COUT
L
1.5μF, 6.3V, 0402, X5R ceramic
2 x 10μF, 6.3V, 0603, X5R ceramic
470nH, 47mΩ, 2.5mm x 2.0mm x 1.2mm
(1) See Third-Party Products Disclaimer
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10.2.1.3 Application Performance Curves
100.0
100.0
90.0
80.0
95.0
90.0
70.0
VIN = 2.5V
VIN = 2.7V
VIN = 3.0V
60.0
VIN = 3.6V
VIN = 4.3V
VIN = 3.6V
VIN = 4.3V
VIN = 3.0V
VIN = 2.7V
VIN = 2.5V
85.0
0.0001
0.001
0.01
Current (A)
0.1
1
2
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9
Current (A)
VOUT = 3.15 V
VSEL = Low
Mode = Low
VOUT = 3.15 V
VSEL = Low
Mode = Low
图10-2. TPS61281D Efficiency vs Output Current
图10-3. TPS61281D Efficiency vs Output Current
100.0
100.0
90.0
80.0
70.0
95.0
90.0
VIN = 3.6V
VIN = 2.5V
VIN = 4.3V
VIN = 2.7V
VIN = 2.5V
VIN = 2.7V
VIN = 3.0V
VIN = 3.6V
VIN = 4.3V
VIN = 3.0V
60.0
0.0001
85.0
0.001
0.01
Current (A)
0.1
1
2
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9
Current (A)
VOUT = 3.35 V
VSEL = High
Mode = Low
VOUT = 3.35 V
VSEL = High
Mode = Low
图10-4. TPS61281D Efficiency vs Output Current
图10-5. TPS61281D Efficiency vs Output Current
3.276
3.213
3.244
3.213
3.181
3.15
3.181
3.15
3.118
3.118
VIN = 2.5V
VIN = 2.5V
VIN = 2.7V
3.087
VIN = 2.7V
VIN = 2.9V
VIN = 3.0V
3.087
VIN = 2.9V
VIN = 3.1V
3.055
3.055
1.5
1.9
2.3
Current (A)
2.7
0.0001
0.001
0.01
0.1
1
2
Current (A)
VOUT = 3.15 V
Mode = Low
VOUT = 3.15 V
Mode = Low
图10-7. TPS61281D DC Output Voltage vs Output
图10-6. TPS61281D DC Output Voltage vs Output
Current
Current
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3.484
3.451
3.417
3.384
3.35
VIN = 2.5V
VIN = 2.7V
VIN = 2.9V
VIN = 3.1V
VIN = 3.2V
3.417
3.384
3.35
3.317
3.284
3.25
3.317
VIN = 2.5V
VIN = 2.7V
3.284
VIN = 2.9V
VIN = 3.1V
3.25
1.6
2
2.4
2.8
0.0001
0.001
0.01
0.1
1
2
Current (A)
Current (A)
Mode = Low
VOUT = 3.35 V
Mode = Low
VOUT = 3.35 V
图10-9. TPS61281D DC Output Voltage vs Output
图10-8. TPS61281D DC Output Voltage vs Output
Current
Current
4.5
4.4
4.3
4.2
4.1
4
4.5
4.4
4.3
4.2
4.1
4
3.9
3.9
3.8
3.7
3.6
3.5
3.8
3.7
3.6
3.5
3.4
3.4
3.3
3.2
3.1
IOUT = 1mA
IOUT = 1mA
IOUT = 100mA
IOUT = 1000mA
IOUT = 1500mA
3.3
3.2
IOUT = 100mA
IOUT = 1000mA
IOUT = 1500mA
3.1
3
3
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5
Input Voltage (V)
Input Voltage (V)
VOUT = 3.35 V
VSEL = High
Mode = Low
VOUT = 3.15 V
VSEL = Low
图10-11. TPS61281D DC Output Voltage vs Input
图10-10. TPS61281D DC Output Voltage vs Input
Voltage
Voltage
3.1
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.5
2.6
2.7
2.8 2.9
Input Voltage (V)
3
3.1
3.2
VOUT = 3.35 V
TA = 85°C
Mode = Low
图10-12. TPS61281D Maximum Output Current vs
Input Voltage
图10-13. Boost to Pass-Through Mode Exit / Entry
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图10-14. TPS61281D Dynamic Voltage
图10-15. TPS61281D Dynamic Voltage
Management (VSEL) Load Current 50 mA
Management (VSEL) Load Current 500 mA
图10-16. TPS61281D Forced Pass-Through to
图10-17. TPS61280D, 81A Load Transient
Boost Mode Transition
Response In PFM/PWM Operation
图10-18. TPS61280D, 81A Load Transient
图10-19. Start-Up at No Load
Response In PFM/PWM Operation
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图10-20. Start-Up at 30-ΩLoad
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10.2.2 TPS61282D with 2.5V-4.35 VIN, 2000 mA Output Current (TPS61280D with I2C Programmable)
LM3242
SuPA
BUCK/BYPASS
CIN
10 µF
3G PA
Note: Resistive load equivalent
for the measurement result.
CIN
4.7 µF
2G PA
WL8PM27
SuPA
BUCK
CIN
4.7 µF
WIFI PA
PMIC
Vcore1, 1.05V
Vcore2, 1.15V
eMMC, 2.95V
LCD, 2.80V
SMPS
SMPS
LDO
CDECOUPLING
10 µF
TPS61282D
SW
VOUT
VOUT
VBAT’
L
SW
VIN
VIN
200 to 600mV
0.47 μH
CDECOUPLING
10 µF
2.7V
CO (x4)
10µF X5R 6.3V (0603)
LDO
Battery
Antenna switches
2.60V
2.7V .. 4.35V
LDO
CI
1.5µF X5R 6.3V (0402)
Note: Resistive load equivalent
for the measurement result.
Voltage Select
Enable
VSEL
EN
1.8V
Forced Bypass / Auto
PFM/FPWM
BYP
Interrupt
MODE
PGND
PGND
PGND
PG
AGND
AGND
Copyright © 2016, Texas Instruments Incorporated
图10-21. TPS61282D Application Circuit with 2000 mA Output Current
10.2.2.1 Design Requirements
表10-4. Design Parameters
REFERENCE
DESCRIPTION
PART NUMBER, MANUFACTURER
2.5 V to 4.35 V
VIN
Input voltage range
VOUT
VOUT
IOUT
Output voltage range at VSEL=Low
Output voltage range VSEL=High
Output Current
VOUT = 3.3 V if VIN ≤3.3 V, VOUT= VIN if VIN > 3.3 V
VOUT = 3.5 V if VIN ≤3.5 V, VOUT= VIN if VIN > 3. 5V
2000 mA
表10-5. Component List
DESCRIPTION
REFERENCE
PART NUMBER, MANUFACTURER(1)
GRM155R60J155ME80D
4 x GRM188R60J106ME84
DFE252012CR470
CI
CO
L
1.5 μF, 6.3 V, 0402, X5R ceramic
4 x 10 μF, 6.3 V, 0603, X5R ceramic
470 nH, 47 mΩ, 2.5 mm x 2.0 mm x 1.2 mm
(1) See Third-Party Products Disclaimer
10.2.2.2 Detailed Design Procedures
See 节10.2.1 for all Detailed Design Procedures.
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10.2.2.3 Application Performance Curves
100.0
100.0
95.0
90.0
80.0
70.0
90.0
85.0
VIN = 2.5V
VIN = 2.7V
VIN = 3.0V
VIN = 3.6V
VIN = 4.3V
VIN = 2.5V
VIN = 2.7V
VIN = 3.0V
VIN = 3.3V
VIN = 4.3V
60.0
0.0001
0.001
0.01
Current (A)
0.1
1
2
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9
Current (A)
VOUT = 3.3 V
VSEL = Low
Mode = Low
VOUT = 3.3 V
VSEL = Low
Mode = Low
图10-22. TPS61282D Efficiency vs Output Current
图10-23. TPS61282D Efficiency vs Output Current
100.0
100.0
90.0
80.0
70.0
95.0
90.0
VIN = 2.5V
VIN = 2.7V
VIN = 3.0V
VIN = 3.3V
VIN = 4.3V
VIN = 2.5V
VIN = 2.7V
VIN = 3.0V
VIN = 3.3V
VIN = 4.3V
85.0
0.1 0.3
60.0
0.0001
0.001
0.01
0.1
1
2
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9
Current (A)
Current (A)
VOUT = 3.5 V
VSEL = High
Mode = Low
VOUT = 3.5 V
VSEL = High
Mode = Low
图10-25. TPS61282D Efficiency vs Output Current
图10-24. TPS61282D Efficiency vs Output Current
3.432
3.333
3.399
3.3
3.366
3.333
3.3
3.267
VIN = 2.5V
3.267
VIN = 2.5V
VIN = 2.7V
VIN = 2.9V
VIN = 3.1V
3.234
3.201
VIN = 2.7V
VIN = 2.9V
VIN = 3.1V
VIN = 3.2V
3.234
3.201
2
2.4
2.8
3.2
3.6
4
0.0001
0.001
0.01
0.1
1
2
Current (A)
Current (A)
VOUT = 3.3 V
Mode = Low
VOUT = 3.3 V
Mode = Low
图10-27. TPS61282D DC Output Voltage vs Output
图10-26. TPS61282D DC Output Voltage vs Output
Current
Current
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3.64
3.57
3.605
3.57
3.535
3.5
3.535
3.5
3.465
3.43
VIN = 2.5V
VIN = 2.7V
VIN = 2.9V
VIN = 3.1V
VIN = 3.2V
VIN = 3.4V
3.465
3.43
VIN = 2.5V
VIN = 2.7V
VIN = 2.9V
VIN = 3.1V
3.395
3.395
1.
8
2.2
2.6
3
3.4
3.8
0.0001
0.001
0.01
0.1
1
2
Current (A)
Current (A)
VOUT = 3.5 V
Mode = Low
VOUT = 3.5 V
Mode = Low
图10-29. TPS61282D DC Output Voltage vs Output
图10-28. TPS61282D DC Output Voltage vs Output
Current
Current
4.5
4.4
4.3
4.2
4.1
4
4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.9
3.8
3.7
3.6
3.5
3.6
3.5
IOUT=1mA
I = 100mA
OUT
3.4
3.3
3.2
3.1
3.0
3.4
3.3
IOUT = 1mA
IOUT = 100mA
IOUT = 1000mA
IOUT = 2000mA
IOUT=1000mA
3.2
3.1
IOUT = 2000mA
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5
3
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5
C013
Input Voltage(V)
Input Voltage (V)
VOUT = 3.5 V
VSEL = High
Mode = Low
VOUT = 3.3 V
VSEL = Low
Mode = Low
图10-31. TPS61282D DC Output Voltage vs Input
图10-30. TPS61282D DC Output Voltage vs Input
Voltage
Voltage
图10-32. Boost to Pass-Through Mode Exit / Entry
图10-33. TPS61282D Dynamic Voltage
Management (VSEL) Load Current 50mA
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图10-34. TPS61282D Dynamic Voltage
图10-35. TPS61282D Line Transient
Management (VSEL) Load Current 500mA
图10-36. TPS61282D Load Transient Response In 图10-37. TPS61282D Load Transient Response In
PWM Operation
PFM/PWM Operation
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11 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 2.3 V and 4.8 V. This input
supply should be well regulated. If the input supply is located more than a few inches from the TPS61280D,
TPS61281D or TPS61282D converter additional bulk capacitance may be required in addition to the ceramic
bypass capacitors. An electrolytic or tantalum capacitor with a value of 47 μF is a typical choice.
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12 Layout
12.1 Layout Guidelines
• For all switching power supplies, the layout is an important step in the design, especially at high peak
currents and high switching frequencies.
• If the layout is not carefully done, the regulator could show stability problems as well as EMI problems.
• Therefore, use wide and short traces for the main current path and for the power ground tracks.
• To minimize voltage spikes at the converter's output:
– Place the output capacitor(s) as close as possible to GND and VOUT, as shown in 图12-1.
– The input capacitor and inductor should also be placed as close as possible to the IC.
– Use a common ground node for power ground and a different one for control ground to minimize the
effects of ground noise.
– Connect these ground nodes at any place close to the ground pins of the IC.
– Junction-to-ambient thermal resistance is highly application and board-layout dependent.
– It is suggested to maximize the pour area for all planes other than SW. Especially the ground pour should
be set to fill available PWB surface area and tied to internal layers with a cluster of thermal vias.
12.2 Layout Example
L
Vin
Vout
GND
图12-1. Suggested Layout (Top)
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12.3 Thermal Information
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB
• Introducing airflow in the system
As power demand in portable designs is more and more important, designers must figure the best trade-off
between efficiency, power dissipation and solution size. Due to integration and miniaturization, junction
temperature can increase significantly which could lead to bad application behaviors (that is, premature thermal
shutdown or worst case reduce device reliability).
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where
high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.
The device operating junction temperature (TJ) should be kept below 125°C.
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13 Device and Documentation Support
13.1 Device Support
13.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息,不能构成与此类产品或服务或保修的适用性有关的认可,不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
13.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
13.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
13.4 Trademarks
I2C™ is a trademark of NXP Semiconductors.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
13.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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ZHCSHC3B –JANUARY 2018 –REVISED JUNE 2023
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14.1 Package Summary
A4
B4
C4
D4
A3
B3
C3
D3
A2
B2
C2
D2
A1
B1
C1
D1
YMLLLLS
TPS6128xD
D
A1
E
图14-2. Chip Scale Package (Top View)
图14-1. Chip Scale Package (Bottom View)
Code:
• YM —Year Month date code
• LLLL —Lot trace code
• S —Assembly site code
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PACKAGE OPTION ADDENDUM
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25-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS61280DYFFR
TPS61280DYFFT
TPS61281DYFFR
TPS61281DYFFT
TPS61282DYFFR
TPS61282DYFFT
ACTIVE
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
YFF
16
16
16
16
16
16
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
TPS
61280D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
YFF
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
TPS
61280D
YFF
TPS
61281D
YFF
TPS
61281D
YFF
TPS
61282D
YFF
TPS
61282D
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Apr-2022
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Apr-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS61280DYFFR
TPS61280DYFFT
TPS61281DYFFR
TPS61281DYFFT
TPS61282DYFFR
TPS61282DYFFT
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
YFF
YFF
YFF
YFF
YFF
YFF
16
16
16
16
16
16
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
1.78
1.78
1.78
1.78
1.78
1.78
1.78
1.78
1.78
1.78
1.78
1.78
0.69
0.69
0.69
0.69
0.69
0.69
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
Q1
Q1
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Apr-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS61280DYFFR
TPS61280DYFFT
TPS61281DYFFR
TPS61281DYFFT
TPS61282DYFFR
TPS61282DYFFT
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
YFF
YFF
YFF
YFF
YFF
YFF
16
16
16
16
16
16
3000
250
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
20.0
20.0
20.0
20.0
20.0
20.0
3000
250
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
YFF0016
DSBGA - 0.625 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
0.625 MAX
C
SEATING PLANE
0.05 C
0.30
0.12
BALL TYP
1.2 TYP
D
C
B
SYMM
1.2
D: Max = 1.696 mm, Min =1.636 mm
E: Max = 1.696 mm, Min =1.636 mm
TYP
0.4 TYP
A
1
2
3
4
0.3
0.2
16X
0.015
SYMM
C A B
0.4 TYP
4219386/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFF0016
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
16X ( 0.23)
(0.4) TYP
4
3
1
2
A
B
C
SYMM
D
SYMM
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
(
0.23)
METAL
(
0.23)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219386/A 05/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information,
see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0016
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
16X ( 0.25)
1
2
3
4
A
(0.4) TYP
B
SYMM
METAL
TYP
C
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4219386/A 05/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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