TPS61288RQQR [TI]
TPS61288 18-V, 15-A, Fully Integrated Synchronous Boost Converter;
| 型号： | TPS61288RQQR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TPS61288 18-V, 15-A, Fully Integrated Synchronous Boost Converter |
| 文件： | 总30页 (文件大小：2797K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS61288
SLVSFP3B – AUGUST 2020 – REVISED DECEMBER 2021
TPS61288 18-V, 15-A, Fully Integrated Synchronous Boost Converter
1 Features
3 Description
•
Wide input voltage and output voltage range
– VIN : 2.0 V to 18 V
– 2.4-V Minimum input voltage for start-up
– VOUT : 4.5 V to 18 V
High efficiency and power capability
– 15-A peak switch current limit
– Two 6.5-mΩ (LS) / 8.5-mΩ (HS) MOSFETs
– Switching frequency: 500 kHz
– Up to 94.7% efficiency at VIN = 3.6 V, VOUT = 13
V, and IOUT = 2 A
The TPS61288 is a high-power density, fully-
integrated synchronous boost converter with a 6.5-
mΩ power switch and a 8.5-mΩ rectifier switch to
provide a high efficiency and small size solution
in portable systems. The TPS61288 has a wide
input voltage range from 2 V (2.4 V rising) to 18
V to support applications with single-cell or two-cell
Lithium batteries. The device has 15-A switch current
capability and is capable of providing an output
voltage up to 18 V.
•
– Up to 96.9% efficiency at VIN = 7.2 V, VOUT = 16
V, and IOUT = 2.5 A
Extend the system operating time
– Typical 110-µA quiescent current into VOUT pin
– Maximum 2.1-µA current into VIN pin during
shutdown
– Smooth on-time/off-time (SOO) modulation at
light load and low duty cycle and no DC offset
between PFM and PWM
The TPS61288 employs peak current control topology
with SOO modulation to regulate the output voltage.
The device operates in the pulse width modulation
(PWM) mode in moderate to heavy load condition. It
automatically runs in the pulse frequency modulation
(PFM) mode in light load and low duty cycle condition.
SOO modulation realizes accurate regulation over
wide load/VIN range while maintaining high efficiency
and low output ripple. The switching frequency
in the PWM mode is 500 kHz. The TPS61288
provides 19-V output overvoltage protection, cycle-by-
cycle overcurrent protection, and thermal shutdown
protection.
•
•
•
Rich protection
– Output overvoltage protection at 19 V
– Cycle-by-cycle overcurrent protection
– Thermal shutdown
2.5-mm × 3.0-mm QFN package with HotRod™
Lite option
The TPS61288 is available in a 2.5-mm × 3.0-mm
QFN package.
2 Applications
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
•
•
•
Bluetooth™ speaker
Source driver of LCD display
USB type-C power delivery
TPS61288
QFN (11)
2.5-mm × 3.0-mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VIN
VOUT
SW
VOUT
R1
Control
BST
FB
VIN
EN
ON
R2
OFF
COMP
Cc
Rc
VCC
Cp
PGND
AGND
Typical Application Circuit
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS61288
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SLVSFP3B – AUGUST 2020 – REVISED DECEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................4
6.5 Electrical Characteristics ............................................5
6.6 Typical Characteristics................................................7
7 Detailed Description........................................................9
7.1 Overview.....................................................................9
7.2 Functional Block Diagram...........................................9
7.3 Feature Description...................................................10
7.4 Device Functional Modes..........................................10
8 Application and Implementation..................................12
8.1 Application Information............................................. 12
8.2 Typical Application.................................................... 12
9 Power Supply Recommendations................................19
10 Layout...........................................................................20
10.1 Layout Guidelines................................................... 20
10.2 Layout Example...................................................... 20
11 Device and Documentation Support..........................22
11.1 Receiving Notification of Documentation Updates..22
11.2 Support Resources................................................. 22
11.3 Trademarks............................................................. 22
11.4 Electrostatic Discharge Caution..............................22
11.5 Glossary..................................................................22
12 Mechanical, Packaging, and Orderable
Information.................................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2020) to Revision B (December 2021)
Page
•
Added HotRod Lite option...................................................................................................................................1
Changes from Revision * (September 2020) to Revision A (December 2020)
Page
•
Changed device status from Advance Information to Production Data.............................................................. 1
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5 Pin Configuration and Functions
VCC AGND SW BST
VIN
EN
FB
COMP
SW
PGND
VOUT
Figure 5-1. 11-Pin RQQ VQFN Package (Top View)
Table 5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NUMBER
FB
1
I
Voltage feedback. Connect to the center tape of a resistor divider to program the output
voltage.
Output of the internal error amplifier, the loop compensation network should be
connected between this pin and the AGND pin.
COMP
PGND
SW
2
3
O
PWR
Power ground of the IC. It is connected to the source of the low-side MOSFET.
The switching node pin of the converter. It is connected to the drain of the internal
low-side power MOSFET and the source of the internal high-side power MOSFET.
4,9
5
PWR
VOUT
EN
PWR
Boost converter output
Enable logic input. Logic high level enables the device. Logic low level disables the
device and turns it into shutdown mode.
6
I
I
VIN
7
IC power supply input
Power supply for high-side MOSFET gate driver. A ceramic capacitor of 0.1 µF must be
connected between this pin and the SW pin.
BST
8
O
-
AGND
VCC
10
11
Signal ground of the IC
Output of the internal regulator. A ceramic capacitor of more than 1.0 µF is required
between this pin and ground.
O
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
-40
MAX
SW+6
20
UNIT
V
Voltage
Voltage
Voltage
TJ
BST
VIN, VOUT, SW
Other pins
V
6
V
Operating Junction Temperature
Storage temperature
150
150
°C
°C
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JS-002, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.0
4.5
0.8
1
NOM
MAX
18
UNIT
V
VIN
VOUT
L
Input voltage range
Output voltage range
18
V
Effective inductance range
Effective input capacitance range
Effective output capacitance range
Operating junction temperature
5.6
µH
µF
µF
°C
CIN
COUT
TJ
10
10
1000
125
–40
6.4 Thermal Information
TPS61288
TPS61288
THERMAL METRIC(1)
RQQ (VQFN) - 11 PINS
RQQ (VQFN) - 11 PINS
UNIT
EVM(2)
33.6
n/a
Standard
71.4
n/a
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
n/a
n/a
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.7
2.7
ΨJB
13.4
n/a
15.8
n/a
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Measured on TPS61288EVM, 4-layer, 2oz copper PCB.
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6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 2.5 V to 9 V and VOUT = 16 V. Typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
Input voltage under voltage lockout
(UVLO) threshold
VIN rising
2.3
1.9
2.4
2
V
V
VUVLO
Input voltage under voltage lockout
(UVLO) threshold
VIN falling, VOUT > 3 V
1.8
1.9
under voltage lock out hysteresis
Vcc regulated votlage
VUVLO rising - VUVLO falling
ICC = 5 mA, VIN = 9 V
400
4.8
2
mV
V
VCC
VCC_UVLO Vcc falling threshold
VCC falling
V
EN = High, No switching, 2.4 V < VIN
16 V, VOUT > 1.1 VIN, -40°C ≤ TJ ≤ 85 °C
<
IQ_IN
Quiescent current into VIN pin
3
10
165
2.1
1
uA
uA
uA
uA
EN = High, No switching, 2.4 V < VIN < 16
V, VOUT > 1.1 VIN, -40 °C ≤ TJ ≤ 85 °C
IQ_OUT
ISD
Quiescent current into VOUT pin
Shutdown current into VIN pin
Reverse leakage current into SW
110
EN = Low, No switching, 2.4 V < VIN < 18
V, -40 °C ≤ TJ ≤ 85 °C
EN = Low, No switching, VSW = 0V, 4.5 V
< VOUT < 18 V, -40 °C ≤ TJ ≤ 85°C
ISD_SW
OUTPUT
VREF
Feedback regulation reference voltage
Feedback input bias current
Over Voltage Protection
PWM Operation
Rising threshold
0.588
18.3
0.6
0.612
20
V
nA
V
IFB
VOVP
19
19.5
VOVP_HYS Over Voltage Protection Hysteresis
600
mV
POWER SWITCH
RDS(on)
RDS(on)
High-side FET on resistance
Low-side FET on resistance
VCC = 5 V
VCC = 5 V
8.5
6.5
mΩ
mΩ
CURRENT LIMIT
VIN = 7.2 V, VOUT = 16 V, L = 2.2 uH, -20
°C ≤ TJ ≤ 125 °C
ILIM
Switching Peak Current Limit
12
15
17.1
1.2
A
LOGIC INTERFACE
VIH
EN High-level input voltage
V
V
VIL
EN Low-level input voltage
0.4
50
VHYS
REN
Hysteresis of the control logic
Pull down resistor for control pin
mV
kΩ
850
1100
ERROR AMPLIFIER
VCOMP_H COMP output high voltage
VCOMP_L COMP output low voltage
VFB = VREF - 200 mV
VFB = VREF + 200 mV
1.88
0.55
180
V
V
Gm
Error amplifier trans conductance
µS
Power stage trans-conductance(inductor
peak current / comp voltage)
KCOMP
ISINK
13.5
A / V
Comp pin sink current
VFB = VREF + 200 mV, VCOMP = 1.5 V
VFB = VREF + 200 mV, VCOMP = 1.5 V
20
20
µA
µA
ISOURCE Comp pin source current
SWITCHING TIME
VIN = 7.2V, VOUT = 16V; L = 2.2 uH,
Cout(eff) = 50 uF
TSS
Soft start time
3
ms
VIN = 7.2V, VOUT = 16V; VIN = 3.6V, VOUT
= 13V
fSW
Switching frequency
Minimum on-time
440
500
60
600
110
kHz
ns
tON_MIN
PROTECTION
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6.5 Electrical Characteristics (continued)
TJ = –40°C to 125°C, VIN = 2.5 V to 9 V and VOUT = 16 V. Typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
160
20
MAX
UNIT
°C
TSD
Thermal shutdown
Junction temperature rising
TSD_HYS Thermal shutdown hysteresis
°C
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6.6 Typical Characteristics
TA = 25°C, fSW = 500 kHz, unless otherwise noted.
100
13.06
13.04
13.02
VIN=3.6V
VIN=6.0V
VIN=7.2V
VIN=8.4V
80
60
40
20
0
VIN=2.7 V
VIN=3.6 V
VIN=4.2 V
VIN=7.2 V
1E-5
0.0001
0.001 0.01
Output Current (A)
0.10.2 0.5 1 2 3 5
1E-5
0.0001
0.001 0.01
Output Current (A)
0.10.2 0.5 1 2 3 5
VIN = 2.7 V; 3.6 V; 4.2 V; 7.2 V
VOUT = 13 V
VIN = 2.7 V; 3.6 V; 4.2 V; 7.2 V
VOUT = 13 V
Figure 6-1. Efficiency vs Output Current VOUT = 13 V
Figure 6-2. Output Voltage vs Output Current, VOUT = 13 V
100
13.06
VIN=3.6V
VIN=6.0V
VIN=7.2V
VIN=8.4V
80
60
13.04
40
VIN=3.6 V
VIN=6.0 V
20
VIN=7.2 V
VIN=8.4 V
0
1E-5
13.02
1E-5
0.0001
0.001 0.01
Output Current (A)
0.10.2 0.5 1 2 3 5
0.0001
0.001 0.01
Output Current (A)
0.10.2 0.5 1 2 3 5
VIN = 3.6 V; 6 V; 7.2 V; 8.4 V
VOUT = 16 V
VIN = 3.6 V; 6 V; 7.2 V; 8.4 V
VOUT = 16 V
Figure 6-3. Efficiency vs Output Current, VOUT = 16 V
Figure 6-4. Output Voltage vs Output Current, VOUT = 16 V
100
5.52
VIN=2.3V
VIN=3.6V
VIN=4.2V
80
60
40
5.51
5.5
20
VIN=2.3 V
VIN=3.6 V
VIN=4.2 V
0
1E-5
5.49
1E-5
0.0001
0.001
0.01
Output Current (A)
0.1
0.5
2 3 5 10
0.0001
0.001
0.01
Output Current (A)
0.1
0.5
2 3 5 10
Separate power VIN and 3.3 V signal VIN
VOUT = 5.5 V
Separate power VIN and 3.3 V signal VIN
VOUT = 5.5 V
Figure 6-5. Efficiency vs Output Current, VOUT = 5.5 V
Figure 6-6. Output Voltage vs Output Current, VOUT = 5.5 V
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6.6 Typical Characteristics (continued)
565
560
555
550
545
540
535
601.5
600
VIN = 7.2V VOUT = 16V
VIN = 3.6V VOUT = 13V
598.5
597
595.5
594
530
525
VIN = 3.6V VOUT=13V
VIN = 7.2V VOUT=16V
-40
-20
0
20
40
60
80
100 120 140
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
Figure 6-7. Switching Frequency vs Temperature
Figure 6-8. Reference Voltage vs Temperature
8
122.5
VIN=2.0V
120
117.5
115
VIN=3.6V
VIN=7.2V
VIN=10.0V
7
6
5
4
3
2
1
0
112.5
110
107.5
105
102.5
100
VOUT=4.5V
VOUT=13V
VOUT=18V
97.5
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
VIN = 2.0 V; 3.6 V; 7.2 V; 10 V
VOUT = 13 V
VIN = 3.6 V
VOUT = 4.5 V; 13 V; 18 V
Figure 6-9. Quiescent Current into VIN vs Temperature
Figure 6-10. Quiescent Current into VOUT vs Temperature
1.5
VIN=2.0V
VIN=3.6V
VIN=7.2V
VIN=18V
1.25
1
0.75
0.5
0.25
0
-40
0
40
80
120
160
Temperature (èC)
Figure 6-11. Shutdown Current vs Temperature
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7 Detailed Description
7.1 Overview
The TPS61288 is a fully-integrated synchronous boost converter with a 6.5-mΩ power switch and a 8.5-mΩ
rectifier switch to output high power from a single cell or two-cell Lithium batteries. The device is capable of
providing an output voltage of 18 V and delivering up to 35-W power from a single cell Lithium battery and 45-W
power from a two cells Lithium battery.
The TPS61288 employs the peak current control topology with the SOO modulation to regulate the output
voltage. In the moderate-to-heavy load condition, the TPS61288 operates in the quasi-constant frequency pulse
width modulation (PWM) mode. As conventional adaptive off-time converters, the device varies the off-time as a
function of input and output voltage to maintain a nearly constant frequency 500 kHz. In the light load condition,
the device runs in the pulse frequency modulation (PFM) mode. Off-time is modulated by the feedback loop
and extended as load becoming lighter. Zero current detection in high-side N-MOSFET enables the device
running in discontinuous conduction mode (DCM) to optimize light-load efficiency. The TPS61288 implements
the cycle-by-cycle current limit to protect the device from overload conditions during boost switching. The typical
switch peak current limit is 15 A. The TPS61288 uses external loop compensation, which provides flexibility to
use different inductors and output capacitors. The peak current control scheme gives excellent transient line and
load response with minimal output capacitance.
7.2 Functional Block Diagram
L1
VIN
C5
C1
SW
VIN
BST
VOUT
AGND
VOUT
C2
Deadtime
Control Logic
C4
LDO
gate
VCC
R1
C3
PGND
FB
SW
Comp
gm
R2
gate
1/K
VIN
SS
Comp
COMP
EN
Vref
Rc
Cc
SS Vref
Shutdown
Shutdown
Control
ON/
OFF
Cp
OVP
VOUT
VIN / VCC
UVLO
Thermal
Shutdown
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7.3 Feature Description
7.3.1 Enable and Start-up
The TPS61288 has a soft start function to prevent high inrush current during start-up. When the EN pin is pulled
high, the internal soft-start capacitor is charged with a constant current. During this time, the soft-start capacitor
voltage is compared with the internal reference (0.6 V). The lower one is fed into the internal positive input of
the error amplifier. The output of the error amplifier (which determines the inductor peak current value) ramps up
slowly as the soft-start capacitor voltage goes up. The soft-start phase is completed after the soft-start capacitor
voltage exceeds the internal reference (0.6 V). When the EN pin is pulled low, the voltage of the soft-start
capacitor is discharged to ground.
7.3.2 Undervoltage Lockout (UVLO)
The UVLO circuit prevents the device from malfunctioning at low input voltage and the battery from excessive
discharge. The TPS61288 has both VIN UVLO and VCC UVLO function. It disables the device from switching
when the falling voltage at the VIN pin trips the falling UVLO threshold VUVLO, which is typically 1.9 V. The device
starts operating when the rising voltage at the VIN pin trips the rising UVLO threshold typically 2.3 V. It also
disables the device when the falling voltage at the VCC pin trips the UVLO threshold VCC_UVLO, which is typically
2.1 V.
7.3.3 Switching Peak Current Limit
To avoid an accidental large peak current, the TPS61288 has an internal cycle-by-cycle current limit. The
low-side switch is turned off immediately as soon as the switch current touches the typical 15-A current limit.
7.3.4 Overvoltage Protection
If the output voltage at the VOUT pin is detected above 19 V (typical value), the TPS61288 stops switching
immediately until the voltage at the VOUT pin drops the hysteresis value lower than the output overvoltage
protection threshold. This function prevents overvoltage on the output and secures the circuits connected to the
output from excessive overvoltage.
7.3.5 Thermal Shutdown
A thermal shutdown is implemented to prevent damages due to excessive heat and power dissipation. Typically,
the thermal shutdown happens at a junction temperature of 160°C. When the thermal shutdown is triggered, the
device stops switching until the junction temperature falls below typically 140°C, then the device starts switching
again.
7.4 Device Functional Modes
7.4.1 PWM
The synchronous boost converter TPS61288 operates at a quasi-constant frequency pulse width modulation
(PWM) in moderate to heavy load condition. Based on the VIN to VOUT ratio, a circuit predicts the required
off-time of the switching cycle. At the beginning of each switching cycle, the low-side N-MOSFET switch, shown
in Section 7.2, is turned on, and the inductor current ramps up to a peak current that is determined by the output
of the internal error amplifier. After the peak current is reached, the current comparator trips, and it turns off the
low-side N-MOSFET switch and the inductor current goes through the body diode of the high-side N-MOSFET
in a dead-time duration. After the dead-time duration, the high-side N-MOSFET switch is turned on. Because the
output voltage is higher than the input voltage, the inductor current decreases. The high-side switch is not turned
off until the calculated off-time is reached. After a short dead-time duration, the low-side switch turns on again
and the switching cycle is repeated.
7.4.2 PFM
The TPS61288 provides a seamless transition from PWM to PFM operation with smooth on-time/off-time (SOO)
mode and enables automatic pulse-skipping mode that provides excellent efficiency over a wide load range. As
load current decreasing or VIN rising, the output of the internal error amplifier decreases to lower the inductor
peak current, delivering less power to the load. When the output current further decreases, the inductor current
will decrease to zero during the off-time. The converter senses inductor current and prevents negative flow by
shutting off the high-side MOSFET until the beginning of the next switching cycle.
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When the inductor peak current reaches to 2.6 A (typical), along with decreasing peak current, the TPS61288
extends its off-time of the switching period to deliver less energy to the output and regulate the output voltage to
the target. The output of the error amplifier continuously goes down and reaches a threshold with respect to the
1.3-A (typical) peak current, the output of the error amplifier is clamped at this value and does not decrease any
more.
With SOO mode, the TPS61288 keeps the output voltage equal to the setting voltage. In addition, the output
voltage ripple is much smaller at light load due to low peak current. Refer to Figure 7-1.
VOUT_REG
IL
toff
toff
PFM
PWM
Figure 7-1. PFM Mode Diagram
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPS61288 is designed for outputting voltage up to 18 V with the 15-A switch current capability. The
TPS61288 operates at a quasi-constant frequency pulse-width modulation (PWM) in moderate to heavy load
condition. In light load condition, the converter operates in PFM mode with single pulse. The PFM mode brings
high efficiency over the entire load range. The converter uses the adaptive constant off-time peak current
control scheme, which provides excellent transient line and load response with minimal output capacitance. The
TPS61288 can work with different inductor and output capacitor combinations by external loop compensation.
8.2 Typical Application
L1 2.2ꢁH
VIN = 2.7 to 4.4V
VOUT
SW
VOUT
C4
6*22ꢁF
C5
0.1ꢁF
R1
294kꢀ
C1
10ꢁF
Control
BST
FB
VIN
EN
*
C6
27pF
ON
R2
14.3kꢀ
C2
0.1ꢁF
OFF
COMP
Cc
1nF
VCC
Cp
30pF
C3
2.2ꢁF
Rc
36.5kꢀ
PGND
AGND
* Note: Recommend adding C6 when R2>15kꢀ
Figure 8-1. TPS61288 3.6-V to 13-V/2.3-A Output Converter
8.2.1 Design Requirements
Table 8-1. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUES
Input voltage range
Output voltage
2.7 to 4.4 V
13 V
Output voltage ripple
Output current rating
100 mV peak-to-peak
2.3 A
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8.2.2 Detailed Design Procedure
8.2.2.1 Setting Output Voltage
The output voltage is set by an external resistor divider (R1, R2 in the Figure 8-1 circuit diagram). For the best
accuracy, R2 should be smaller than 300 kΩ to ensure the current flowing through R2 is at least 100 times
larger than the FB pin leakage current. Changing R2 towards a lower value increases the immunity against noise
injection. When R2 is higher than 15 kΩ, TI recommends adding a 27-pF ceramic capacitor (C6 in the Figure
8-1) in parallel with the R2 for noise immunity.
The value of R1 is then calculated as:
(VOUT - VREF )ìR2
R1 =
VREF
(1)
8.2.2.2 Inductor Selection
Since the selection of the inductor affects the steady state of the power supply operation, transient behavior,
loop stability, and boost converter efficiency, the inductor is the most important component in switching power
regulator design. The three most important specifications to the performance of the inductor are the inductor
value, DC resistance, and saturation current.
The TPS61288 is designed to work with inductor values between 1.0 and 4.7 µH. A 1.0-µH inductor is typically
available in a smaller or lower-profile package, while a 4.7-µH inductor produces lower inductor current ripple. If
the boost output current is limited by the peak current protection of the IC, using a 4.7-µH inductor can maximize
the output current capability of the controller.
Inductor values can have ±20% or even ±30% tolerance with no current bias. When the inductor current
approaches saturation level, its inductance can decrease 20% to 35% from the value at 0-A current, depending
on how the inductor vendor defines saturation. When selecting an inductor, make sure its rated current,
especially the saturation current, is larger than its peak current during the operation.
Follow Equation 2 to Equation 4 to calculate the peak current of the inductor. To calculate the current in the worst
case, use the minimum input voltage, maximum output voltage, and maximum load current of the application.
To leave enough design margin, TI recommends using the minimum switching frequency, the inductor value with
–30% tolerance, and a low-power conversion efficiency for the calculation.
In a boost regulator, calculate the inductor DC current as in Equation 2.
VOUT ìIOUT
IDC
=
V ì h
IN
(2)
where
•
•
•
•
VOUT is the output voltage of the boost regulator.
IOUT is the output current of the boost regulator.
VIN is the input voltage of the boost regulator.
η is the power conversion efficiency.
Calculate the inductor current peak-to-peak ripple as in Equation 3.
1
IPP
=
1
1
L ì(
+
)ì ƒSW
VOUT - V
V
IN
IN
(3)
where
•
•
•
IPP is the inductor peak-to-peak ripple.
L is the inductor value.
ƒSW is the switching frequency.
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•
•
VOUT is the output voltage.
VIN is the input voltage.
Therefore, the peak current, ILpeak, seen by the inductor is calculated with Equation 4.
IPP
ILpeak = IDC
+
2
(4)
Set the current limit of the TPS61288 higher than the peak current, ILpeak. Then select the inductor with
saturation current higher than the setting current limit.
Boost converter efficiency is dependent on the resistance of its current path, the switching loss associated with
the switching MOSFETs, and the core loss of the inductor. The TPS61288 has optimized the internal switch
resistance. However, the overall efficiency is affected significantly by the DC resistance (DCR) of the inductor,
equivalent series resistance (ESR) at the switching frequency, and the core loss. Core loss is related to the core
material and different inductors have different core loss. For a certain inductor, larger current ripple generates
higher DCR and ESR conduction losses and higher core loss. Usually, a data sheet of an inductor does not
provide the ESR and core loss information. If needed, consult the inductor vendor for detailed information.
Generally, TI would recommend an inductor with lower DCR and ESR. However, there is a tradeoff among the
inductance of the inductor, DCR and ESR resistance, and its footprint. Furthermore, shielded inductors typically
have higher DCR than unshielded inductors. Table 8-2 lists recommended inductors for the TPS61288. Verify
whether the recommended inductor can support the user's target application with the previous calculations and
bench evaluation. In this application, Cyntec's inductor, CMLE105T-2R2MS-99 is selected for its small size and
low DCR.
Table 8-2. Recommended Inductors
PART NUMBER
L (µH)
2.2
DCR MAX (mΩ) SATURATION CURRENT/HEAT SIZE MAX (L × W × H VENDOR
RATING CURRENT (A)
mm)
CMLE105T-2R2MS-99
CMLE105T-1R0MS-99
XAL1060-222ME
4.5
2.5
26.0 / 19.5
10.3 x 11.5 x 5.0
Cyntec
Cyntec
Coilcraft
Sumida
1.0
2.2
2.2
36.0 / 25.5
10.3 x 11.5 x 5.0
10.0 x 11.3 x 6.0
11.5 × 10.3 × 4.0
4.95
7.0
32.0 / 20.0
104CDMCCDS-2R2MC
18.0 / 15.0
8.2.2.3 Input Capacitor Selection
For good input voltage filtering, TI recommends low-ESR ceramic capacitors. The VIN pin is the power supply for
the TPS61288. A 0.1-μF ceramic bypass capacitor is recommended as close as possible to the VIN pin of the
TPS61288. The VCC pin is the output of the internal LDO. A ceramic capacitor of more than 1.0 μF is required at
the VCC pin to get a stable operation of the LDO.
For the power stage, because of the inductor current ripple, the input voltage changes if there is parasite
inductance and resistance between the power supply and the inductor. It is recommended to have enough input
capacitance to make the input voltage ripple less than 100 mV. Generally, 10-μF input capacitance is sufficient
for most applications.
Note
DC bias effect: High-capacitance ceramic capacitors have a DC bias effect, which has a strong
influence on the final effective capacitance. Therefore, the right capacitor value must be chosen
carefully. The differences between the rated capacitor value and the effective capacitance result from
package size and voltage rating in combination with material. A 10-V rated 0805 capacitor with 10 μF
can have an effective capacitance of less 5 μF at an output voltage of 5 V.
8.2.2.4 Output Capacitor Selection
For small output voltage ripple, TI recommends a low-ESR output capacitor like a ceramic capacitor. Typically,
three 22-μF ceramic output capacitors work for most applications. Higher capacitor values can be used to
improve the load transient response. Take care when evaluating the derating of the capacitor under DC
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bias. The bias can significantly reduce capacitance. Ceramic capacitors can lose most of their capacitance
at rated voltage. Therefore, leave margin on the voltage rating to ensure adequate effective capacitance. From
the required output voltage ripple, use the following equations to calculate the minimum required effective
capacitance COUT
:
(VOUT - VIN_MIN)ìIOUT
VOUT ì ƒSW ìCOUT
V
=
ripple _ dis
(5)
(6)
V
= ILpeak ìRC _ESR
ripple _ESR
where
•
•
•
•
•
•
•
•
Vripple_dis is output voltage ripple caused by charging and discharging of the output capacitor.
Vripple_ESR is output voltage ripple caused by ESR of the output capacitor.
VIN_MIN is the minimum input voltage of boost converter.
VOUT is the output voltage.
IOUT is the output current.
ILpeak is the peak current of the inductor.
ƒSW is the converter switching frequency.
RC_ESR is the ESR of the output capacitors.
8.2.2.5 Loop Stability
The TPS61288 requires external compensation, which allows the loop response to be optimized for each
application. The COMP pin is the output of the internal error amplifier. An external compensation network,
comprised of resistor RC, and ceramic capacitors CC and CP, is connected to the COMP pin.
The power stage small signal loop response of constant off-time (COT) with peak current control can be
modeled by Equation 7.
S
S
l1+
p ×l1-
p
:
RO× 1-D
;
2NB
2NB
RHPZ
ESRZ
GPS(S)=KCOMP
×
×
S
2NB
2
1+
P
(7)
where
•
•
•
D is the switching duty cycle.
RO is the output load resistance.
KCOMP is power stage trans-conductance (inductor peak current / comp voltage), which is 13.5 A/V.
2
ƒP
=
2p ì RO ì CO
(8)
(9)
where
•
CO is output capacitor.
1
ƒESRZ
=
2p ì RESR ì CO
where
RESR is the equivalent series resistance of the output capacitor.
•
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2
RO ì 1 - D
(
)
ƒRHPZ
=
2p ì L
(10)
The COMP pin is the output of the internal transconductance amplifier. Equation 11 shows the small signal
transfer function of compensation network.
≈
∆
«
’
÷
S
1 +
2 ì p ì ƒCOMZ ◊
GEA ì REA ì VREF
VOUT
Gc(S) =
ì
≈
∆
«
’≈
’
÷
S
S
1 +
1 +
÷∆
2 ì p ì ƒCOMP1 ◊«
2 ì p ì ƒCOMP2 ◊
(11)
where
•
•
•
•
•
•
GEA is the transconductance of the amplifier.
REA is the output resistance of the amplifier.
VREF is the reference voltage at the FB pin.
VOUT is the output voltage.
ƒCOMP1, ƒCOMP2 are the frequency of the poles of the compensation network.
ƒCOMZ is the zero's frequency of the compensation network.
The next step is to choose the loop crossover frequency, ƒC. The higher frequency that the loop gain stays
above zero before crossing over, the faster the loop response is. It is generally accepted that the loop gain cross
over no higher than the lower of either 1/10 of the switching frequency, ƒSW, or 1/5 of the RHPZ frequency,
ƒRHPZ
.
Then set the value of RC, CC, and CP (in Figure 8-1) by following these equations.
2N×VOUT×C ×B
C
O
RC=
:
;
1-D ×VREF×GEA×KCOMP
(12)
where
ƒC is the selected crossover frequency.
•
The value of CC can be set by Equation 13.
RO×CO
CC=
2RC
(13)
(14)
The value of CP can be set by Equation 14.
RESR×CO
CP=
RC
If the calculated value of CP is less than 10 pF, it can be left open.
Designing the loop for greater than 45° of phase margin and greater than 10-dB gain margin eliminates output
voltage ringing during the line and load transient.
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8.2.3 Application Curves
Vout(AC)
20mV/div
Vout(AC)
50mV/div
SW
5.0V/div
IL
2.0A/div
SW
5.0V/div
IL
Time Scale: 2.0…s/div
Time Scale: 1.0…s/div
VOUT = 13 V
2.0A/div
VIN = 3.6 V
IOUT = 2.3 A
VIN = 3.6 V
VOUT = 13 V
IOUT = 100 mA
Figure 8-2. Switching Waveforms in CCM
Figure 8-3. Switching Waveforms in 100 mA load
Vout(AC)
20mV/div
EN
2.0V/div
SW
5.0V/div
Vout
5.0V/div
IL
2.0A/div
IL
2.0A/div
Time Scale: 20…s/div
Time Scale: 500µs/div
VIN = 3.6 V
VOUT = 13 V
IOUT = 10 mA
VIN = 3.6 V
VOUT = 13 V
RLOAD = 10 Ω
Figure 8-4. Switching Waveforms in 10 mA load
Figure 8-5. Start-up Waveforms
Vout(AC)
500mV/div
EN
2.0V/div
Vout
5.0V/div
IL
2.0A/div
IL
2.0A/div
Iout
1.0A/div
Time Scale: 500µs/div
VIN = 3.6 V
Time Scale: 500µs/div
VIN = 3.6 V
VOUT = 13 V
RLOAD = 10 Ω
VOUT = 13 V
Figure 8-6. Shutdown Waveforms
Figure 8-7. Load Transient (IOUT = 1 to 2 A)
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Vout(AC)
50mV/div
Vin
1.0V/div
Vout(AC)
500mV/div
IL
5.0A/div
IL
Iout
2.0A/div
1.0A/div
Time Scale: 50ms/div
VIN = 3.6 V
Time Scale: 500µs/div
VOUT = 13 V
IOUT = 1 A
VOUT = 13 V
Figure 8-8. Line Transient (VIN = 2.7 V to 4.2 V)
Figure 8-9. Load Sweep (IOUT = 0 to 2 A)
Vin
1.0V/div
Vout(AC)
50mV/div
IL
2.0A/div
Time Scale: 10ms/div
VOUT = 13 V
IOUT = 1 A
Figure 8-10. Line Sweep (VIN = 2.7 V to 4.2 V)
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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.0 V to 18 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the converter, additional bulk
capacitance can be required in addition to the ceramic bypass capacitors. A typical choice is an electrolytic or
tantalum capacitor with a value of 47 μF.
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10 Layout
10.1 Layout Guidelines
As for all switching power supplies, especially those running at high switching frequency and high currents,
layout is an important design step. If layout is not carefully done, the regulator can suffer from instability and
noise problems. To maximize efficiency, switch rise and fall times are very fast. To prevent radiation of high-
frequency noise (for example, EMI), proper layout of the high-frequency switching path is essential. Minimize
the length and area of all traces connected to the SW pin, and always use a ground plane under the switching
regulator to minimize interplane coupling.
The input capacitor needs to be close to the VIN pin and GND pin in order to reduce the Iinput supply ripple.
The layout should also be done with well consideration of the thermal as this is a high power density device. The
SW, VOUT, and PGND pins that improves the thermal capabilities of the package should be soldered with the
large polygon, using thermal vias underneath the SW pin could improve thermal performance.
10.2 Layout Example
The bottom layer is a large ground plane connected to the PGND plane and AGND plane on top layer by vias.
AGND
L1
VIN
VOUT
VCC
VIN EN
VOUT
BST
SW
SW
AGND
VCC
FB COMP PGND
COUT
VOUT
CIN
AGND
PGND
Figure 10-1. Layout Example
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10.2.1 Thermal Considerations
The maximum IC junction temperature should be restricted to 125°C under normal operating conditions.
Calculate the maximum allowable dissipation, PD(max), and keep the actual power dissipation less than or equal
to PD(max). The maximum-power-dissipation limit is determined using Equation 15.
125 - TA
RqJA
PD(max)
=
(15)
where
•
•
TA is the maximum ambient temperature for the application.
RθJA is the junction-to-ambient thermal resistance given in the Thermal Information table.
The TPS61288 comes in a thermally-enhanced VQFN package. The real junction-to-ambient thermal resistance
of the package greatly depends on the PCB type, layout, and thermal pad connection. Using thick PCB copper
and soldering the thermal pad to a large ground plate enhance the thermal performance. Using more vias
connects the ground plate on the top layer and bottom layer around the IC without solder mask also improves
the thermal capability.
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
HotRod™ and TI E2E™ are trademarks of Texas Instruments.
Bluetooth™ is a trademark of Bluetooth SIG.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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17-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS61288LRQQR
TPS61288RQQR
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
RQQ
RQQ
11
11
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
61288L
61288
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS61288RQQR
VQFN-
HR
RQQ
11
3000
180.0
12.4
2.8
3.3
1.1
4.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN-HR RQQ 11
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
TPS61288RQQR
3000
Pack Materials-Page 2
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RQQ0011A
3.1
2.9
A
B
2.6
2.4
PIN 1 IDENTIFICATION
(0.1) TYP
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
0.45
0.35
0.45
0.35
4X
(0.1) TYP
0.1
C A B
1.15
0.95
2X
0.05
C
4
1.35
1.15
2X
0.25
3
5
6
0.3
0.2
6X
0.1
C
A
B
2
1
0.05
C
1.05
0.95
2X 0.375
0.4
0.3
6X
7
PIN 1 ID
C0.15
8
11
0.6
2X
0.275
0.175
0.4
2X
3X 0.5
1.5
0.3
2X
0.2
0.1
0.05
0.1
C A B
C
A B
0.05
C
C
0.475
0.275
2X
4225610/A 12/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RQQ0011A
(1.5)
6X (0.25)
3X (0.5)
2X (0.4875)
2X (0.225)
2X (0.575)
6X (0.55)
11
8
2X (0.7)
7
1
(1.175)
2X
2X
(0.4)
(0.25)
6
5
(0.875)
2
3
PKG
2X (0.375)
2X (0.2)
4X (0.4)
(0.25)
4
2X (1.45)
(1)
2X (1.25)
2X (0.65)
2X (1.425)
PKG
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
SOLDER MASK
OPENING
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225610/A 12/2019
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RQQ0011A
(1.5)
6X (0.25)
3X (0.5)
2X (0.4875)
2X (0.225)
2X (0.575)
6X (0.55)
11
8
2X (0.25)
2X (0.7)
7
1
(1.175)
(0.4)
2X
6
5
(0.875)
2
3
PKG
2X (0.375)
2X (0.175)
4X (0.35)
(0.25)
4
2X (1.45)
(1)
2X (1.25)
2X (1.425)
2X (0.625)
PKG
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PIN 3 & 5: 89%
SCALE: 20X
4225610/A 12/2019
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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