TPS613784-Q1 [TI]

TPS61378-Q1 25-Î¼A Quiescent Current Synchronous Boost Converter with Load Disconnect;


型号：	TPS613784-Q1
厂家：	TEXAS INSTRUMENTS
描述：	TPS61378-Q1 25-Î¼A Quiescent Current Synchronous Boost Converter with Load Disconnect
文件：	总36页 (文件大小：4027K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS61378-Q1

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SLVSET0A – MAY 2020 – REVISED OCTOBER 2020

TPS61378-Q1 25-µA Quiescent Current Synchronous Boost Converter with Load

Disconnect

1 Features

3 Description

•

AEC-Q100 qualified for automotive applications

– Device temperature grade 1: –40°C to 125°C

ambient operating temperature range

Function Safety-Capable

– Documentation available to aid functional safety

system design

Flexible input and output operation range

– Input voltage range: 2.3 V to 14 V

– Programmable output voltage range: 4.0 V to

18.5 V

– 5 V, 5.25 V, 5.5 V fixed output options

– Programmable peak current limit: 1 A to 4.8 A

Avoid AM band interference and crosstalk

– Dynamically programmable switching

frequency: 200 kHz to 2.2 MHz

– Spread spectrum frequency modulation

– Optional clock synchronization

Minimize solution size for space constraint

applications

– Integrated LS/HS/ISO FET: R_DS(ON)50 mΩ/50

mΩ/100 mΩ

– Support up to 2.2 MHz with small L-C

Minimized light load and idle state current

consumption

– 25-µA Quiescent current into VIN pin

– 0.5-µA Shutdown current into VIN pin

– Selectable auto PFM and forced PWM mode

– True load disconnect during shutdown or fault

conditions

The TPS61378-Q1 is a fully-integrated synchronous

boost converter with load disconnect function

integrated. The input voltage covers from 2.3 V to 14

V, while the maximal output votlage up to 18.5 V. The

switching current limit is programmable from 1 A to

4.8 A. It consumes 25 uA quiescent current from Vin.

The TPS61378-Q1 employs the peak current mode

control with the switching frequency programmable

from 200 kHz to 2.2 MHz. The device works in fixed

frequency PWM operation in medium to heavy load.

There are two optional modes in light load by

configuring the MODE pin: Auto PFM mode and

Forced PWM to balance the efficiency and noise

immunity in light load. The switching frequency can be

synchronized to an external clock. The TPS61378-Q1

uses the spread spectrum of the internal clock for

more EMI friendly at FPWM mode. In addition, there

is an internal soft-start time to limit the inrush current.

•

The TPS61378-Q1 has various fixed output voltage

versions to save the external feedback resistor. It

supports the external loop compensation so that the

stability and transient response could be optimized at

wider Vout/Vin range. It also integrates robust

protection features including the output short

protection, output over voltage protection and thermal

shutdown protection. The TPS61378-Q1 is available

in a 3-mm x 3-mm 16-pin QFN package with wettable

flank.

Device Information

PART NUMBER

PACKAGE⁽¹⁾

BODY SIZE (NOM)

•

Integrated protection features

TPS61378QRTE

VQFN-16

3.0-mm x 3.0-mm

– Support VIN close to VOUT operation

– Input undervoltage lockout and output

overvoltage protection

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

VIN

– Hiccup output short circuit protection

– Power good indicator

– Thermal shutdown protection at 165°C

Higher than 90% efficiency under 0.8-A load from

3.3-V to 9-V conversion

VCC

BST

VIN

OUT

•

TPS61378-Q1

VOUT

FREQ

2 Applications

COMP

ILIM

•

Advanced driver-assistance system (ADAS)

Automotive infotainment and cluster

Body electronics and lighting

MODE/SYNC

GND

Emergency call (eCall)

Typical Application

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION

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DATA.

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings ....................................... 5

7.2 ESD Ratings .............................................................. 5

7.3 Recommended Operating Conditions ........................5

7.4 Thermal Information ...................................................5

7.5 Electrical Characteristics ............................................6

7.6 Typical Characteristics................................................8

8 Detailed Description......................................................11

8.1 Overview................................................................... 11

8.2 Functional Block Diagrams....................................... 12

8.3 Feature Description...................................................12

8.4 Device Functional Modes..........................................14

9 Application and Implementation..................................16

9.1 Application Information............................................. 16

9.2 Typical Application.................................................... 16

10 Power Supply Recommendations..............................25

11 Layout...........................................................................26

11.1 Layout Guidelines................................................... 26

11.2 Layout Example...................................................... 26

12 Device and Documentation Support..........................27

12.1 Device Support....................................................... 27

12.2 Receiving Notification of Documentation Updates..27

12.3 Support Resources................................................. 27

12.4 Trademarks.............................................................27

12.5 Glossary..................................................................27

12.6 Electrostatic Discharge Caution..............................27

13 Mechanical, Packaging, and Orderable

Information.................................................................... 27

4 Revision History

Changes from Revision * (May 2020) to Revision A (October 2020)

Page

Changed TPS61378-Q1 device status from Advance Information to Production Data...................................... 1

Updated the numbering format for tables, figures and cross-references throughout the document...................1

•

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5 Device Comparison Table

PART NUMBER

OUTPUT VOLTAGE (V)

RESISTOR FROM FB TO GND (R_{FB_LOW}

)

SPREAD SPECTRUM

R_{FB_LOW}≤ 2 kΩ

5.25

2 kΩ < R_{FB_LOW}≤ 4 kΩ

4 kΩ < R_{FB_LOW}≤ 8 kΩ

R_{FB_LOW}≥ 16 kΩ

TPS61378-Q1

Enable

5.5

Adjustable

5.7

R_{FB_LOW}≤ 2 kΩ

6.2

2 kΩ < R_{FB_LOW}≤ 4 kΩ

4 kΩ < R_{FB_LOW}≤ 8 kΩ

R_{FB_LOW}≥ 16 kΩ

TPS613781-Q1⁽¹⁾

TPS613782-Q1⁽¹⁾

TPS613783-Q1⁽¹⁾

TPS613784-Q1⁽¹⁾

TPS613785-Q1⁽¹⁾

Enable

Disable

R_{FB_LOW}≤ 2 kΩ

2 kΩ < R_{FB_LOW}≤ 4 kΩ

4 kΩ < R_{FB_LOW}≤ 8 kΩ

R_{FB_LOW}≥ 16 kΩ

R_{FB_LOW}≤ 2 kΩ

5.25

2 kΩ < R_{FB_LOW}≤ 4 kΩ

4 kΩ < R_{FB_LOW}≤ 8 kΩ

R_{FB_LOW}≥ 16 kΩ

5.5

Adjustable

5.7

6.2

R_{FB_LOW}≤ 2 kΩ

2 kΩ < R_{FB_LOW}≤ 4 kΩ

4 kΩ < R_{FB_LOW}≤ 8 kΩ

R_{FB_LOW}≥ 16 kΩ

R_{FB_LOW}≤ 2 kΩ

2 kΩ < R_{FB_LOW}≤ 4 kΩ

4 kΩ < R_{FB_LOW}≤ 8kΩ

R_{FB_LOW}≥ 16 kΩ

(1) Product Preview. Contact TI factory for more information.

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6 Pin Configuration and Functions

VIN

ILIM

BST

Exposed

Thermal Pad

OUT

Figure 6-1. 16-Pin WQFN RTE Package (Transparent Top View)

Table 6-1. Pin Functions

I/O

DESCRIPTION

NAME

NO.

VIN

IC power supply input

Power supply for high-side N-MOSFET gate drivers. A capacitor must be connected

between this pin and SW pin.

BST

The switching node pin of the converter. It is connected to the drain of the internal low-side

FET and the source of the high-side FET.

3, 4

PWR

Mode selection pin. MODE = high, forced PWM mode. MODE = low or floating, auto PFM

mode. This pin can also be used to synchronize the external clock. Refer to Table 8-1 for

details.

MODE/SYNC

VCC

Output of internal regulator. A ceramic capacitor with more than 1 μF must be connected

between this pin and GND.

GND

7, 8

PWR

Power ground of the IC. It is connected to the source of the low-side FET.

Output of the isolation FET. Connect load to this pin to achieve input/output isolation.

Output of the drain of the HS FET. Connect this pin as the output can disable the load

disconnect/short protection feature (or short this pin with VO pin).

OUT

PWR

Power good indicator, open drain output

Current limit setting pin. Use a resistor to set the desired peak current limit. Refer to Section

8.3.7 for details.

ILIM

Feedback pin. Use a resistor divider to set the desired output voltage. Refer to Section

9.2.2.1 for details.

Output of the internal trans-conductance error amplifier. An external RC network is

connected to this pin to optimize the loop stability and response time.

COMP

Enable logic input

Frequency setting pin. Connect a resistor between this pin and GND pin to set the desired

frequency.

FREQ

Thermal Pad

The thermal pad should be connected to power ground plane for good power dissipation.

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

-0.3

–0.3

-0.3

–40

–65

MAX

UNIT

Voltage range at terminals ⁽²⁾

VIN

VO, SW, OUT

BST

SW + 6

MODE/SYNC, FB, FREQ, ILIM, VCC, COMP, EN

(3)

T_J

Operating junction temperature

Storage temperature

150

°C

T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltage values are with respect to network ground terminal.

(3) High junction temperatures degrade operating lifetime. Operating lifetime is de-rated for junction temperatures greater than 125°C

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per AEC Q100-002⁽²⁾

(1)

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per AEC Q100-011, all pins⁽³⁾

Charged-device model (CDM), per AEC Q100-011, corner pins

(1,4,5,8,9,12,13,16)⁽³⁾

V_(ESD)

±750

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges

in to the device.

(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows

safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary

precautions.

(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe

manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary

precautions.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

2.3

NOM

MAX

UNIT

V_IN

Input voltage

V_OUT

T_A

Outputvoltage

18.5

125

Operating ambient temperature

–40

°C

7.4 Thermal Information

TPS61378-Q1

RTE

THERMAL METRIC⁽¹⁾

UNIT

16 PINS

46.2

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

43.5

18.5

Junction-to-top characterization parameter

Junction-to-board characterization parameter

1.1

ψ_JB

18.5

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TPS61378-Q1

RTE

THERMAL METRIC⁽¹⁾

UNIT

16 PINS

8.8

R_θJC(bot)

Junction-to-case (bottom) thermal resistance

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

7.5 Electrical Characteristics

T_J= -40 to 125°C, L = 1 µH, V_IN= 3.3 V and V_OUT= 9 V (VO pin). Typical values are at T_J= 25°C, (unless

otherwise noted)

MIN

TYP

MAX

UNIT

POWER SUPPLY

V_IN

Input voltage range

2.3

2.2

V_INrising

V_INfalling

2.2

2.04

160

2.2

V_{IN_UVLO}

VIN under voltage lockout threshold

V_{IN_HYS}

VIN UVLO hysteresis

V_{CC_UVLO}VCC UVLO threshold

V_CCrising

V_{CC_HYS}

V_CC

VCC UVLO hysteresis

VCC regulation

V_CChysteresis

I_VCC= 6 mA, V_OUT= 9V

150

4.8

IC enabled, no load,

V_IN= 3.3 V, V_OUT= 18.5 V, V_FB

V_REF+ 0.1 V,

I_Q

Quiescent current into V_INpin

Quiescent current into OUT pin

µA

IC enabled, no load,

V_IN= 3.3 V, V_OUT= 18.5 V, V_FB

V_REF+ 0.1 V,

I_Q

I_SD

Shutdown current into VIN pin

Leakage current into SW

IC disabled, V_IN=14 V, EN = GND

IC disabled, V_IN= OUT = SW =14 V

IC disabled, OUT= VO = 5 V, SW = 0

0.6

µA

I_{SW_LKG}

I_{VO_LKG}

Reverse leakage current into VO

OUTPUT VOLTAGE

Output over-voltage protection

threshold

V_OVP

V_IN= 3.3 V, V_OUTrising

19.3

20.5

Output over-voltage protection

hysteresis

V_{OVP_HYS}

V_IN= 3.3 V, OVP threshold

0.5

VOLTAGE REFERENCE

T_J= -40 to 125°C, FB to GND

resistance ≥ 16 kΩ

V_REF

Reference Voltage at FB pin

0.788

0.8

0.812

V_{OUT_5V}

V_{OUT_5.25V}

V_{OUT_5.5V}

I_{FB_LKG}

T_J= -40 to 125°C, R_FB= 2.0 kΩ

T_J= -40 to 125°C, R_FB= 4.0 kΩ

T_J= -40 to 125°C, R_FB= 8.0 kΩ

4.85

5.1

5.000

5.238

5.500

5.15

5.35

5.65

5.35

Leakage current into FB pin

POWER SWITCH

R_DS(on)

Low-side MOSFET on resistance

V_CC= 4.85 V

mΩ

High-side MOSFET on resistance

Isolation MOSFET on resistance

100

CURRENT LIMIT

I_{LIM_SW}Peak switching current limit FPWM

R_LIM= 20 kΩ , Duty cycle = 65%

4.8

5.55

Peak switching current limit Auto

PFM

I_{LIM_SW}

R_LIM= 102 kΩ, Duty cycle = 65%,

4.7uH

I_{LIM_SW}

Peak switching current limit FPWM

0.75

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T_J= -40 to 125°C, L = 1 µH, V_IN= 3.3 V and V_OUT= 9 V (VO pin). Typical values are at T_J= 25°C, (unless

otherwise noted)

MIN

TYP

MAX

UNIT

Peak switching current limit Auto

PFM

R_LIM= 102 kΩ, Duty cycle = 65%,

4.7uH

I_{LIM_SW}

0.75

Peak switching current limit at

softstart

V_IN= 3.3 V, V_OUT= 0 V, R_LIM= 20

kΩ

I_{LIM_SS_1}

0.9

1.15

1.4

SWITCHING FREQUENCY

Fsw

Switching frequency

R_FREQ= 18 kΩ

R_FREQ= 218 kΩ

R_FREQ= 18 kΩ

2050

180

2200

200

2400

230

kHz

Fsw

Switching frequency

Maximum Duty Cycle

Minimal on time

D_max

t_{ON_min}

F_DITHER

F_pattern

10%

0.4%

Fsw

ERROR AMPLIFIER

I_SINK

COMP pin sink current

V_FB= V_REF+ 0.2V

V_FB= V_REF- 0.2V

I_SOURCE

V_CCLPH

V_CCLPL

G_mEA

COMP pin source current

COMP pin high clamp voltage

COMP pin high low voltage

Error amplifier trans conductance

V_FB= V_REF- 0.2V, ILIM = 4.8 A

V_FB= V_REF+ 0.2V,

V_COMP= 1.0 V

1.3

0.6

POWER GOOD

V_{PG_TH}

V_{PG_HYS}

I_{PG_SINK}

PG threhold for rising FB voltage

Reference to V_REF

V_PG= 0.4 V

90%

PG hysteresis

PG pin sink current capability

t_{PG_DELAY}PG delay time

2.5

3.4

4.3

DOWN MODE

Delay time between EN high and

device working

t_{EN_DELAY}

0.4

t_SS

Softstart time

2.5

1.8

t_{HCP_ON}

t_{HCP_OFF}

Hiccup on time

Hiccup off time

SYNC TIMING

f_{SYNC_MIN}

200

kHz

f_{SYNC_MAX}

2200

EN/SYNC LOGIC

EN, MODE/SYNC pins Logic high

threshold

VI_H

1.2

EN, MODE/SYNC pins Logic Low

threshold

VI_L

0.4

EN, MODE/SYNC pins internal pull

down resistor

R_DOWN

800

kΩ

THERMAL SHUTDOWN

t_{SD_R}Thermal shutdown rising threshold

t_{SD_F}

TJ rising

165

145

°C

Thermal shutdown falling threshold TJ falling

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7.6 Typical Characteristics

V_IN= 3.3 V, V_OUT= 9 V (VO pin), T_A= 25°C, Fsw = 2.2 MHz, unless otherwise noted.

100

Vin = 2.7 V

Vin = 3.3 V

Vin = 3.8 V

Vin = 2.7 V

Vin = 3.3 V

Vin = 3.8 V

1E-5

0.0001

0.001

0.01

0.1

0.0001

0.001

0.01

0.1

Output Current (A)

D016

D015

VOUT = 5 V

Auto PFM

Fsw = 2.2 MHz

VOUT = 5 V

FPWM

Fsw = 2.2 MHz

Figure 7-1. 5 V_OUTEfficiency vs Output Current

Figure 7-2. 5 V_OUTEfficiency vs Output Current

100

Vin = 2.7 V

Vin = 3.3 V

Vin = 5 V

Vin = 3.3 V

Vin = 5 V

1E-5

0.0001

0.001

0.01

0.1

0.0001

0.001

0.01

0.1

Output Current (A)

D007

D006

VOUT = 9 V

Auto PFM

Fsw = 2.2 MHz

VOUT = 9 V

FPWM

Fsw = 2.2 MHz

Figure 7-3. 9 V_OUTEfficiency vs Output Current

Figure 7-4. 9 V_OUTEfficiency vs Output Current

9.05

Vin = 2.7 V

Vin = 3.3 V

Vin = 5 V

T_J= -40 °C

T_J= 25 °C

T_J= 125 °C

9.04

9.03

9.02

9.01

0.0001

0.001

0.01

0.1

Output Current (A)

D009

2.3

2.6

2.9

3.2

3.5

3.8

4.1

4.4

4.7

VOUT = 9 V

PFM

Fsw = 2.2 MHz

Input Voltage (V)

D001

Figure 7-6. Quiescent Current into V_INvs Input

Voltage

Figure 7-5. 9 V_OUTRegulation vs Output Current

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0.5

5.7

5.6

5.5

5.4

5.3

5.2

5.1

T_J= -40 °C

T_J= 25 °C

T_J= 125 °C

5V Output (V)

5.238V Output (V)

5.5V Output (V)

0.4

0.3

0.2

0.1

4.9

-40

2.3

2.6

2.9

3.2

3.5

3.8

4.1

4.4

4.7

-20

100

120

140

Input Voltage (V)

D002

Temperature (°C)

D014

Figure 7-7. Shutdown Current vs Input Voltage

Figure 7-8. Fixed Output Voltage vs Temperature

0.805

0.804

0.803

0.802

0.801

0.8

FPWM

4.5

3.5

2.5

0.799

0.798

0.797

0.796

0.795

1.5

0.5

-40

-20

100

120

140

100

110

Temperature (°C)

Resistor (kW)

D003

D004

Figure 7-9. Reference Voltage vs Temperature

Figure 7-10. Current Limit vs Setting Resistance

2.4

2.3

Rising

Falling

2.1

1.8

1.5

1.2

0.9

0.6

0.3

2.2

2.1

100

125

150

175

200

225

-40

-20

100

120

140

Resistor (kW)

Temperature (°C)

D010

D005

Figure 7-12. V_INUVLO Threshold Voltage vs

Temperature

Figure 7-11. Switching Frequency vs Setting

Resistance

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1.2

3.5

3.475

3.45

Rising

Falling

1.1

0.9

0.8

0.7

0.6

0.5

0.4

3.425

3.4

-40

-20

100

120

140

-40

-20

100

120

140

Temperature (°C)

D012

D011

Figure 7-14. PG Delay Time vs Temperature

Figure 7-13. EN Threshold Voltage vs Temperature

150

5.2

Low Side FET (mW)

5Vin Current Limit (A)

3.3Vin Current Limit (A)

2.7Vin Current Limit (A)

140

High Side FET (mW)

Isolation FET (mW)

130

5.1

120

110

100

4.9

4.8

4.7

-40

-20

100

120

140

Duty Cycle (%)

Temperature (°C)

D008

D013

Figure 7-16. Duty Cycle vs Current Limit

Figure 7-15. R_DSONvs Temperature

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8 Detailed Description

8.1 Overview

The TPS61378-Q1 is a fully integrated synchronous boost converter with load disconnect function. It supports

output voltage up to 18.5 V with maximum 4.8-A programmable switching peak current limit. The input voltage

ranges from 2.3 V to 14 V while consuming 25-µA quiescent current.

The TPS61378-Q1 utilizes the fixed frequency peak current control scheme, which has an internal oscillator and

supports adjustable switching frequency from 200 kHz to 2.2 MHz.

The TPS61378-Q1 operates with fixed frequency pulse width modulation (PWM) from medium to heavy load. At

the beginning of each switching cycle, the low-side N-MOSFET switch is turned on, and the inductor current

ramps up to a peak current that is determined by the output of the internal error amplifier (EA). Once the

switching peak current triggers the output of the EA, the low-side N-MOSFET is turned off and the high-side N-

MOSFET is turned on after a short dead time. The high-side N-MOSFET switch is not turned off until the next

cycle as determined by the internal oscillator. The low-side switch turns on again after a short dead time and the

switching cycle is repeated.

The TPS61378-Q1 provides either Auto PFM or Forced PWM option for the light load operation by configuring

the MODE/SYNC pin. In Forced PWM mode, the switching frequency remains constant across the entire load

range, which helps to avoid the frequency variation with load. The internal oscillator can be synchronized to an

external clock applied on the MODE / SYNC pin. Spread spectrum modulation of the frequency in Forced PWM

mode helps to optimize the EMI performance for automotive applications. In Auto PFM mode, the switching

frequency can decrease, resulting in higher efficiency.

The TPS61378-Q1 implements a cycle-by-cycle current limit to protect the device from overload during the boost

operation phase. If the output current further increases and triggers the output voltage to fall below the input

voltage, the TPS61378-Q1 enters into hiccup mode short protection.

There is a built-in soft-start time which prevents the inrush current during the start-up. The TPS61378-Q1 also

provides a power good (PG) indicator to enable the power sequence control for start-up.

The TPS61378-Q1 also has a number of protection features including output short protection, output over

voltage protection (OVP), and thermal shutdown protection (OTP).

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8.2 Functional Block Diagrams

VIN

OUT

BST

VIN

OUT

VCC

VOUT

1/K

Logic

BST

ULVO

LDO

& BIAS

COMP

VUVLO

Fixed

Output

OVP

SCP

ISO

VCC

OTP

Soft

Start

VCC

MODE

COMP

CLIM

Slope Compensation

COMP

Vref

VO Voltage

SELECT

PGOOD

VOVP

COMP

OVP

OTP

1/N

VOUT

Dithering

OSC

SYNC

MODE

FREQ

Current Limit SELECT

VOTP

Temp

GND

COMP

ILIM

MODE/

SYNC

8.3 Feature Description

8.3.1 VCC Power Supply

The internal LDO in the TPS61378-Q1 outputs a regulated voltage of 4.8 V with 10-mA output current capability.

A ceramic capacitor is connected between the VCC pin and GND pin to stabilize the VCC voltage and also

decouple the noise on the VCC pin. The value of this ceramic capacitor should be above 1 µF. A ceramic

capacitor with an X7R or X5R grade dielectric with a voltage rating higher than 10 V is recommended.

8.3.2 Input Undervoltage Lockout (UVLO)

An undervoltage lockout (UVLO) circuit stops the operation of the converter when the input voltage drops below

the UVLO threshold of 2.04 V (typical). A hysteresis of 160 mV (typical) is added so that the device cannot be

enabled again until the input voltage exceeds 2.2 V (typical). This function is implemented to prevent

malfunctioning of the device when the input voltage is between 2.04 V and 2.2 V.

8.3.3 Enable and Soft Start

When the input voltage is above the UVLO threshold and the EN pin is pulled above 1.2 V, the TPS61378-Q1 is

enabled. The TPS61378-Q1 starts to monitor the FB pin. With a typical 400-µs delay time after EN is pulled high,

the TPS61378-Q1 starts switching. There is an internal built-in start-up time which is typically 2.5 ms to limit the

inrush current during start-up.

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8.3.4 Shut Down

When the input voltage is below the UVLO threshold or the EN pin is pulled low, the TPS61378-Q1 is in

shutdown mode and all the functions are disabled. The input voltage is isolated from the output to minimize the

leakage currents.

8.3.5 Switching Frequency Setting

The TPS61378-Q1 uses a fixed frequency control scheme and the switching frequency can be programmed

between 200 kHz and 2.2 MHz using a resistor from the FREQ pin to GND. The resistor must be connected

when the oscillator is synchronized by an external clock. The resistance is defined by Equation 1.

41.9

(₅₉(/*V) =

;

4_(4'3GÀ + 1.05

(1)

where

R_FREQis the resistance between the FREQ pin and the GND pin

•

For instance, the switching frequency is 2.2 MHz if the resistance between the FREQ pin and GND is 18 kΩ.

This pin cannot be left floating or tied to VCC.

8.3.6 Spread Spectrum Frequency Modulation

The TPS61378-Q1 uses a triangle waveform to spread the switching frequency with ±10% of normal frequency.

The frequency of the triangle waveform is typically 0.4% of the switching frequency. For example, if the normal

switching frequency of TPS61378-Q1 is programmed to 2.2 MHz, the spread spectrum function will modulate the

switching frequency in the range of 1.98 MHz to 2.42 MHz in a triangle behavior with 8.8 kHz rate .

The spread spectrum is only available while the clock of the TPS61378-Q1 is free running at its natural

frequency. Any of the following conditions overrides spread spectrum, turning it off:

•

An external clock is applied to the MODE/SYNC pin

The device works in the PFM operation at light load.

8.3.7 Adjustable Peak Current Limit

The TPS61378-Q1 adopts a cycle-by-cycle peak current limit internally. The low-side switch is turned off

immediately as soon as the switch peak current triggers the limit threshold. The peak switch current limit can be

set by a resistor from the ILIM pin to ground. The relationship between the current limit and the resistor is shown

in Equation 2.

90.56

R_LIMkW = 1.184 +

(

)

I_LIM

(

)

(2)

Where

•

R_ILIMis the resistance between the ILIM pin and the GND pin

I_LIMis switch peak current limit

For instance, the current limit is set to 4.8 A if the R_LIMis 20 kΩ; This pin cannot be left floating or connected to

VCC.

8.3.8 Bootstrap

The TPS61378-Q1 has an integrated bootstrap regulator circuit. A small ceramic capacitor is needed between

the BST pin and SW pin to provide the gate drive supply voltage for the high-side switches. The bootstrap

capacitor is charged during the time when the low-side switch is in the ON state. The value of this ceramic

capacitor should be above 0.1 µF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating

higher than 6.3 V is recommended.

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8.3.9 Load Disconnect

The TPS61378-Q1 integrates a load disconnect function when the input source is DC, which completely cuts off

the path between the input side and the output side during shutdown.

The output disconnect function also allows the output short protection and minimize the inrush current at start-

up.

8.3.10 MODE/SYNC Configuration

Table 8-1 summarizes the MODE/SYNC function and the entry condition.

Table 8-1. MODE/SYNC Configuration

MODE/SYNC PIN CONFIGURATION

Logic Low or Floating

MODE

Auto PFM Mode

Forced PWM Mode

Logic High

External Synchronization

The TPS61378-Q1 can be synchronized to an external clock applied to the MODE / SYNC pin.

8.3.11 Overvoltage Protection (OVP)

If the output voltage exceeds the OVP threshold (typical 20 V), the TPS61378-Q1 stops switching immediately

until the output voltage drops below the recovery threshold (typical 19.5 V). This function protects the device

against excessive voltage.

8.3.12 Output Short Protection/Hiccup

In addition to the cycle-by-cycle current limit function, the TPS61378-Q1 also has the output short protection. If

the output current causes low-side FET to reach current limit and pull the output voltage below the input voltage,

the device enters into short circuit protection mode which triggers the hiccup timer. When the hiccup timer is

triggered, the device limits the current to a relative lower level for 1.8 ms and then shuts down. After 67 ms, it will

restart. If the short condition disappears, the device will automatically restart.

When FB voltage is below ≤ 0.1 V during fault condition, current limit threshold is reduced to 1/5 of the

programmed current limit, and frequency is clamped to 1.1 MHz if the FREQ pin setting is greater than 1.1 MHz.

8.3.13 Power Good Indicator

The TPS61378-Q1 integrates a power good function. The PG pin asserts when the output voltage rises above

90% of the target output voltage. The PG pin is an open-drain output before the VOUT reaches the 90% target

output voltage. The PG pin becomes active low after a typical 3.4-ms delay time after the VOUT reaches 90% of

the target output voltage. When the output voltage drops below 85% of the target output voltage, the PG logic

goes low immediately without delay.

8.3.14 Thermal Shutdown

A thermal shutdown is implemented to prevent damage due to the excessive heat and power dissipation.

Typically, the thermal shutdown occurs at the junction temperature exceeding 165°C. When the thermal

shutdown is triggered, the device stops switching and recovers when the junction temperature falls below 145°C

(typical).

8.4 Device Functional Modes

8.4.1 Forced PWM Mode

The TPS61378-Q1 enters forced PWM Mode by pulling the MODE/SYNC pin to logic high for more than five

switching cycles. In forced PWM mode, the TPS61378-Q1 keeps the switching frequency constant at light load

condition. When the load current decreases, the output of the internal error amplifier will also decrease to keep

the inductor peak current down. When the output current decreases further, the high-side switch is not turned off

even if the current of the high-side switch goes negative to keep the frequency constant.

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8.4.2 Auto PFM Mode

The TPS61378-Q1 enters auto PFM Mode by pulling the MODE/SYNC pin to logic low for more than five

switching cycles or leave the pin floating. The TPS61378-Q1 improves the efficiency at light load when operating

in PFM mode. When the output current decreases to a certain level, the output voltage of the error amplifier is

clamped by the internal circuit. If the output current reduces further, the inductor current through the high-side

switch will be clamped but not further lowered. Pulses are skipped to improve the efficiency at light load.

8.4.3 External Clock Synchronization

The TPS61378-Q1 supports external clock synchronization with a range of 200 kHz to 2.2 MHz. The TPS61378-

Q1 remains in the forced PWM Mode and operates in CCM across the entire load range if the oscillator is

synchronized by an external clock. Spread spectrum feature is disabled when external synchronization is used.

8.4.4 Down Mode

The TPS61378-Q1 features Down Mode operation when input voltage is close to or higher than output voltage.

In Down Mode, output voltage is regulated at target value even when V_IN> VO. The high-side and low-side FETs

of the TPS61378-Q1 are switching devices that always work in boost operation, where the isolation FET always

works as a linear device.

For boost circuits, on-time or duty cycle is reduced as input voltage approaches output voltage. The TPS61378-

Q1 enters Down Mode when V_INreaches 85% (typical) of VO voltage at 2.2 MHz; while exiting Down Mode

requires V_INto be reduced below 85% (typical) of VO voltage at 2.2 MHz.

In normal operation, isolation FET is fully on.

When Down Mode is triggered and V_INis less than VO pin voltage, the OUT pin will have a fixed 2 V (typical)

above VO pin voltage. Isolation FET works in LDO mode to regulate VO pin voltage with a 2 V constant voltage

drop.

When Down Mode is triggered and V_INis 100 mV (typical) higher than VO pin voltage, the OUT pin will have an

approximated 3 V (typical) above V_INpin voltage, as V_INkeeps rising, the OUT pin will continue raise with 3 V on

top of V_IN, isolation FET works in LDO mode to regulate VO pin voltage with a voltage differential of OUT pin and

VO pin.

Refer to Figure 8-1.

Vin > Vo

Vin < Vo

Down Mode

Entering

Threshold

Down Mode

Exiting

Threshold

Voltage

OUT

VIN

Figure 8-1. Down Mode

Care should be taken during short-to-ground condition when operation V_INis above 6 V. During hiccup on, the

device operates in Down Mode and isolation FET voltage drop is V_IN+ 3 V (OUT pin to VO pin).

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The TPS61378-Q1 is a 25-µA quiescent current boost converter which supports 2.3-V to 14-V input voltage

range. It also supports load disconnect to minimize the leakage current. The following design procedure can be

used to select component values for the TPS61378-Q1.

9.2 Typical Application

VIN

VCC

OUT

BST

VIN

TPS61378-Q1

VOUT

FREQ

COMP

ILIM

MODE/SYNC

GND

Figure 9-1. Typical Application

9.2.1 Design Requirements

A typical application example is dual cameras powered through a coax cable, which normally requires 9.0-V

output as its bias voltage and consumes less than 600 mA current. 800 mA load current is designed to provide

margin. The following design procedure can be used to select external component values for the TPS61378-Q1.

Table 9-1. Design Requirements

PARAMETERS

Input Voltage

VALUES

3.3 V to 6.4 V

9.0 V

Output Voltage

Switching Frequency

Output Current

2.2 MHz

800 mA

Output Voltage Ripple

± 25 mV

9.2.2 Detailed Design Procedure

9.2.2.1 Programming the Output Voltage

There are two ways to set the output voltage of the TPS61378-Q1: adjustable or fixed. If the resistance between

FB and GND is higher than 16 kΩ during start-up, the TPS61378-Q1 works as an adjustable output version. The

FB pin is connected to the negative input of the internal error amplifier directly. The output voltage can be

programmed by adjusting the external resistor divider R_Upperand R_Loweraccording to Equation 3. When the

output voltage is in well regulation, the typical voltage at the FB pin is V_REFof 0.8 V.

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(4_7LLAN+ 4_.KSAN

)

8₁₇₆= 8_4'(

4_.KSAN

(3)

For some applications where the resistor needs to be as low as possible, the low-side divider can be 20 kΩ. The

reference voltage is 0.8 V, the high-side divider is 205 kΩ for 9-V output voltage.

For other applications without specific requirements on divider resistance, you can choose R_Lowerto be

approximately 80.6 kΩ. Slightly increasing or decreasing R_Lowercan result in closer output voltage matching

when using standard values resistors.

For the best accuracy, R_Loweris recommended to be smaller than 100 kΩ to ensure that the current following

through R_Loweris at least 100 times larger than FB pin leakage current. Changing R_Lowertowards the lower value

increases the robustness against noise injection. Changing the R_Lowerto higher values reduces the quiescent

current for achieving higher efficiency at light load.

If the resistance between FB and GND is less than 16 kΩ during start-up, the TPS61378-Q1 works as a fixed

output voltage version. The TPS61378-Q1 uses the internal resistor divider.

For 5-V fixed output voltage, the FB pin can be connected to the GND directly or use a R_Lowerwith less than 2

kΩ resistance.

For 5.25-V fixed output voltage, R_Loweris between 2.0 kΩ and 4.0 kΩ and no R_Upperis needed.

For 5.5-V fixed output voltage, the R_Loweris between 4.0 kΩ and 8.0 kΩ and no R_Upperis needed.

9.2.2.2 Setting the Switching Frequency

The switching frequency of the TPS61378-Q1 is set at 2.2 MHz. Use Equation 1 to calculate the required resistor

value. The calculated value is 18 kΩ to get the frequency of 2.2 MHz.

9.2.2.3 Setting the Current Limit

The current limit of the TPS61378-Q1 can be programmed by an external resistor. For a target current limit of 4.8

A, use Equation 2. The calculated resistor value is 20 kΩ.

9.2.2.4 Selecting the Inductor

A boost converter normally requires two main passive components for storing the energy during the power

conversion: an inductor and an output capacitor. The inductor affects the steady state efficiency (including the

ripple and efficiency) as well as the transient behavior and loop stability, which makes the inductor the most

critical component in application.

When selecting the inductor, as well as the inductance, the other important parameters are:

•

The maximum current rating (RMS and peak current should be considered)

The series resistance

Operating temperature

The TPS61378-Q1 has built-in slope compensation to avoid subharmonic oscillation associated with the current

mode control. If the inductor value is too low and makes the inductor peak-to-peak ripple higher than 2 A, the

slope compensation may not be adequate, and the loop can be unstable. Therefore, it is recommended to make

the peak-to-peak current ripple between 800 mA to 2 A when selecting the inductor.

The inductance can be calculated by Equation 4, Equation 5, and Equation 6:

_IN´ D

DI_L=

L ´ f_SW

(4)

(5)

V_OUT´ I_OUT

DI_{L _R}= Ripple% ´

h ´ V

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h ´ V

Ripple % V_OUT´ I_OUT

V ´ D

L =

ƒ_SW

(6)

where

•

Δ_ILis the peak-peak inductor current ripple

V_INis the input voltage

D is the duty cycle

L is the inductor

ƒ_SWis the switching frequency

Ripple % is the ripple ration versus the DC current

V_OUTis the output voltage

I_OUTis the output current

η is the efficiency

The current flowing through the inductor is the inductor ripple current plus the average input current. During

power-up, load faults, or transient load conditions, the inductor current can increase above the peak inductor

current calculated.

Inductor values can have ±20% or even ±30% tolerance with no current bias. When the inductor current

approaches the saturation level, its inductance can decrease 20% to 35% from the value at 0-A bias current

depending on how the inductor vendor defines saturation. When selecting an inductor, make sure its rated

current, especially the saturation current, is larger than its peak current during the operation.

The inductor peak current varies as a function of the load, the switching frequency, the input and output voltages

and it can be calculated by Equation 7 and Equation 8.

I_PEAK= I

´ DI_L

(7)

where

•

I_PEAKis the peak current of the inductor

I_INis the input average current

Δ_ILis the ripple current of the inductor

The input DC current is determined by the output voltage, the output current can be calculated by:

V_OUT´ I_OUT

V_IN´ h

(8)

where

•

I_INis the input current of the inductor

V_OUTis the output voltage

V_INis the input voltage

η is the efficiency

While the inductor ripple current depends on the inductance, the frequency, the input voltage, and duty cycle are

calculated by Equation 4. Replace Equation 4 and Equation 8 into Equation 7 and get the inductor peak current:

I_OUT

V_IN´ D

I_PEAK

(1- D) ´ h

L ´ f_SW

(9)

where

•

I_PEAKis the peak current of the inductor

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•

I_OUTis the output current

D is the duty cycle

η is the efficiency

V_INis the input voltage

L is the inductor

ƒ_SWis the switching frequency

The heat rating current (RMS) is as below:

(DI_L)²

I_{L _RMS}= I

(10)

where

•

I_{L_RMS}is the RMS current of the inductor

I_INis the input current of the inductor

Δ_ILis the ripple current of the inductor

It is important the peak current does not exceed the inductor saturation current and the RMS current is not over

the temperature related rating current of the inductors.

For a given physical inductor size, increasing inductance usually results in an inductor with lower saturation

current. The total losses of the coil consists of the DC resistance (DCR) loss and the following frequency

dependent loss:

•

The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)

Additional losses in the conductor from the skin effect (current displacement at high frequencies)

Magnetic field losses of the neighboring windings (proximity effect)

For a certain inductor, the larger current ripple (smaller inductor) generates the higher DC and also the

frequency-dependent loss. An inductor with lower DCR is basically recommended for higher efficiency. However,

it is usually a tradeoff between the loss and foot print. Table 9-2 lists some recommended inductors.

Table 9-2. Recommended Inductors

DCR Typ (mΩ) SATURATION

PART NUMBER

L (μH)

SIZE (L × W × H mm)

VENDOR⁽¹⁾

MAX

4.1

8.9

CURRENT (A)

XEL4030-471MEB

0.47

15.5

4 x 4 x 3

Coilcraft

Murata

TDK

XEL4030-102MEB

4 x 4 x 3

DFE2HCAHR47MJ0L

DFE322520FD-1R0M

TFM322512ALMAR47MTAA

TFM322512ALMA1R0MTAA

0.47

5.1

7.5

7.6

5.1

2.5 x 2 x 1.2

3.2 x 2.5 x 2

3.2 x 2.5 x 1.2

0.47

TDK

(1) See Third-party Products Disclaimer

9.2.2.5 Selecting the Output Capacitors

The output capacitor is mainly selected to meet the requirements at load transient or steady state. Then the loop

is compensated for the output capacitor selected. The output ripple voltage is related to the equivalent series

resistance (ESR) of the capacitor and its capacitance. Assuming a capacitor with zero ESR, the minimum

capacitance needed for a given ripple can be calculated by Equation 11:

I_OUT´ (V_OUT- V )

C_OUT

f_SW´ DV ´ V_OUT

(11)

where

C_OUTis the output capacitor

•

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•

I_OUTis the output current

V_OUTis the output voltage

V_INis the input voltage

Δ_Vis the output voltage ripple required

ƒ_SWis the switching frequency

The additional output ripple component caused by ESR is calculated by Equation 12:

DV_ESR= I_OUT´ R_ESR

(12)

where

•

ΔV_ESRis the output voltage ripple caused by ESR

R_ESRis the resistor in series with the output capacitor

For the ceramic capacitor, the ESR ripple can be neglected. However, for the tantalum or electrolytic capacitors,

it must be considered if used.

The minimum ceramic output capacitance needed to meet a load transient requirement can be estimated using

Equation 13:

DI_STEP

C_OUT

2p ´ f_BW´ DV_TRAN

(13)

where

•

ΔI_STEPis the transient load current step

ΔV_TRANis the allowed voltage dip for the load current step

ƒ_BWis the control loop bandwidth (that is, the frequency where the control loop gain crosses zero)

For the output capacitor on the OUT pin, the effective capacitance is recommended between 0.22 μF to 1 μF.

Care must be taken when evaluating the derating of a ceramic capacitor under the DC bias. Ceramic capacitors

can derate by as much as 70% of its capacitance at its rated voltage. Therefore, enough margins on the voltage

rating should be considered to ensure adequate capacitance at the required output voltage.

9.2.2.6 Selecting the Input Capacitors

Multilayer ceramic capacitors are an excellent choice for the input decoupling of the step-up converter as they

have extremely low ESR and are available in small footprints. Input capacitors should be located as close as

possible to the device. While a 22-µF input capacitor or equivalent is sufficient for the most applications, larger

values can be used to reduce input current ripple.

Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the

power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce

ringing at the V_INpin. This ringing can couple to the output and be mistaken as loop instability or could even

damage the part. Additional "bulk" capacitance (electrolytic or tantalum) in this circumstance, should be placed

between C_INand the power source lead to reduce ringing that can occur between the inductance of the power

source leads and C_IN.

9.2.2.7 Loop Stability and Compensation

9.2.2.7.1 Small Signal Model

The TPS61378-Q1 uses the fixed frequency peak current mode control; there is an internal adaptive slope

compensation to avoid the subharmonic oscillation. With the inductor current information sensed, the small-

signal model of the power stage reduces from a two-pole system, created by L and C_OUT, to a single-pole

system, created by R_OUTand C_OUT. The single-pole system is easily used with the loop compensation. Figure

9-2 shows the equivalent small signal elements of a boost converter.

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VIN

VOUT

C_IN

R_ESR

R_OUT

R_SENSE

C_OUT

Slope

Comp

I_SENSE

VOUT

R_UP

G_EA

R_DOWN

V_REF

R_C

R_EA

Figure 9-2. TPS61378-Q1 Control Equivalent Circuitry Model

The small signal of power stage is:

2è × B

(1 +

)(1 F

)

4₁₇₆× (1 F &)

2 × 4_5'05'

'54

4*2

-₂₅(5) =

2è × B

(1 +

)

(14)

where

•

D is the duty cycle

R_OUTis the output load resistor

R_SENSEis the equivalent internal current sense resistor, which is typically 118 mΩ

The single pole of the power stage is:

f_P=

2p ´ R_OUT´ C_OUT

(15)

where

•

C_OUTis the output capacitance, for a boost converter having multiple, identical output capacitors in parallel,

simply combine the capacitors with the equivalent capacitance

The zero created by the ESR of the output capacitor is:

f_ESR

2p ´ R_ESR´ C_OUT

(16)

where

R_ESRis the equivalent resistance in series of the output capacitor

•

The right-hand plane zero is:

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R_OUT´ (1- D)²

2p ´ L

f_RHP

(17)

where

•

D is the duty cycle

R_OUTis the output load resistor

L is the inductance

Equation 18 shows the equation for feedback resistor network and the error amplifier.

R_DOWN

2´ p ´ f_Z

H_EA(S) = G_EA´R_EA

_UP+ R_DOWN

(1+

)´(1+

)

2´ p ´ f_P1

2´ p ´ f_P2

(18)

where

•

R_EAis the output impedance of the error amplifier and typical R_EA= 500 MΩ.

ƒ_P1, ƒ_P2is the pole's frequency of the compensation, f_Zis the zero’s frequency of the compensation network.

network

f_P1

2p ´ R_EA´ C_c

(19)

where

•

C_Cis the zero capacitor compensation

f_P2

2p ´ R_C´ C_P

(20)

where

•

C_Pis the pole capacitor compensation

R_Cis the resistor of the compensation network

f_Z=

2p ´R_C´C_C

(21)

9.2.2.7.2 Loop Compensation Design Steps

With the small signal models coming out, the next step is to calculate the compensation network parameters with

the given inductor and output capacitance.

1. Set the Cross Over Frequency, ƒ_C.

The first step is to set the loop crossover frequency, ƒ_C. The higher crossover frequency, the faster the loop

response is. It is generally accepted that the loop gain cross over no higher than the lower of either 1/10 of

the switching frequency, ƒ_SW, or 1/5 of the RHPZ frequency, ƒ_RHPZ. Then calculate the loop compensation

network values of R_C, C_C, and C_Pby following equations.

2. Set the Compensation Resistor, R_C.

By placing ƒ_Zbelow ƒ_C, for frequencies above ƒ_C, R_C| | R_EA~ = R_Cand so R_C× G_EAsets the compensation

gain. Setting the compensation gain, K_COMP-dB, at ƒ_Z, results in the total loop gain, T_(s)= K_PS(s)× H_EA(s)being

zero at ƒ_C.

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Therefore, to approximate a single-pole roll-off up to f_P2, rearrange Equation 18 to solve for RC so that the

compensation gain, K_EA, at f_Cis the negative of the gain, K_PS, read at frequency f_Cfor the power stage bode

plot or more simply:

R_DOWN

K_EA(f_C) = 20 ´ log(G_EA´ R_C´

) = - K_PS(f_C)

R_UP+ R_DOWN

(22)

where

•

K_EAis gain of the error amplifier network

K_PSis the gain of the power stage

G_EAis the transconductance of the amplifier, the typical value of G_EA= 70 µA / V

3. Set the Compensation Zero capacitor, C_C.

Place the compensation zero at the power stage R_OUT,C_OUTpole’s position, so to get:

f_Z=

2p ´ R_C´ C_C

(23)

(24)

Set ƒ_Z= ƒ_P, and get

_OUT´C_OUT

C_C

2R_C

4. Set the Compensation Pole Capacitor, C_P.

Place the compensation pole at the zero produced by the R_ESRand the C_OUT. It is useful for canceling

unhelpful effects of the ESR zero.

f_P2

2p ´ R_C´ C_P

(25)

(26)

f_ESR

2p ´ R_ESR´ C_OUT

Set ƒ_P2= ƒ_ESR, and get

R_ESR´ C_OUT

C_P=

R_C

(27)

9.2.2.7.3 Selecting the Bootstrap Capacitor

The bootstrap capacitor between the BST and SW pin supplies the gate current to charge the high-side FET

device gate during each cycle’s turn-on and also supplies charge for the bootstrap capacitor. The recommended

value of the bootstrap capacitor is 0.1 µF to 1 µF. C_BSTshould be a good quality, low ESR, ceramic capacitor

located at the pins of the device to minimize potentially damaging voltage transients caused by trace inductance.

A value of 0.1 µF was selected for this design example.

9.2.2.7.4 V_CCCapacitor

The primary purpose of the V_CCcapacitor is to supply the peak transient currents of the driver and bootstrap

capacitor as well as provide stability for the V_CCregulator. The value of C_VCCshould be at least 10 times greater

than the value of C_BST, and should be a good quality, low-ESR, ceramic capacitor. C_VCCshould be placed close

to the pins of the IC to minimize potentially damaging voltage transients caused by the trace inductance. A value

of 2.2 µF was selected for this design example.

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9.2.3 Application Curves

Figure 9-3. Switching Waveform V_IN= 5 V, V_OUT= 9

V, I_OUT= 800 mA, FPWM

Figure 9-4. Switching Waveform V_IN= 5 V, V_OUT= 9

V, I_OUT= 0 mA, Auto PFM

Figure 9-6. Start-up from EN Waveform V_IN= 5 V,

V_OUT= 9 V, I_OUT= 500 mA, FPWM

Figure 9-5. Load Transient V_IN= 5 V, V_OUT= 9 V,

I_OUT= 300 mA to 800 mA, FPWM

Figure 9-7. Shutdown from EN Waveforms V_IN= 5

V, V_OUT= 9 V, I_OUT= 500 mA, FPWM

Figure 9-8. Short Circuit Protection V_IN= 5 V, V_OUT

= 9 V, FPWM

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Figure 9-10. Hiccup Short Circuit Protection V_IN= 5

V, V_OUT= 9 V, FPWM

Figure 9-9. Short Circuit Recovery V_IN= 5 V, V_OUT

9 V, I_OUT= 0 mA, FPWM

10 Power Supply Recommendations

The TPS61378-Q1 is designed to operate from an input voltage supply range between 2.3 V to 14 V. This input

supply should be well regulated. If the input supply is located more than a few inches from the device, the bulk

capacitance can be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value

of 47 µF is a typical choice.

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11 Layout

11.1 Layout Guidelines

As for all switching power supplies, the layout is an important step in the design, especially at high peak currents

and high switching frequencies. If the layout is not carefully done, the regulator can show stability problems as

well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground

paths. The input and output capacitor, as well as the inductor should be placed as close as possible to the IC.

11.2 Layout Example

The bottom layer is a large GND plane connected by vias.

GND

VIN

ILIM

BST

GND

OUT

VIN

GND

Figure 11-1. Recommended Layout

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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21-Jan-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS613783QWRTERQ1

TPS613785QWRTERQ1

TPS61378QWRTERQ1

PREVIEW

ACTIVE

WQFN

RTE

3000 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

2G8H

2G9H

2ELH

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

21-Jan-2021

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Oct-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS61378QWRTERQ1

WQFN

RTE

3000

330.0

12.4

3.3

1.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Oct-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

WQFN RTE 16

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 35.0

TPS61378QWRTERQ1

3000

Pack Materials-Page 2

PACKAGE OUTLINE

RTE0016K

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

3.15

2.85

PIN 1 INDEX AREA

3.15

2.85

0.1 MIN

(0.13)

SECTION A-A

TYPICAL

0.8

0.7

SEATING PLANE

0.08

0.05

0.00

1.66 0.1

(0.2) TYP

EXPOSED

THERMAL PAD

12X 0.5

(0.16)

TYP

SYMM

1.5

0.30

0.18

16X

PIN 1 ID

(OPTIONAL)

0.1

C A B

SYMM

0.05

0.5

0.3

16X

4224938/B 06/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RTE0016K

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.66)

SYMM

16X (0.6)

16X (0.24)

SYMM

(2.8)

(0.58)

TYP

12X (0.5)

(

0.2) TYP

VIA

(R0.05)

ALL PAD CORNERS

(0.58) TYP

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4224938/B 06/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RTE0016K

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.51)

16X (0.6)

16X (0.24)

SYMM

(2.8)

12X (0.5)

METAL

ALL AROUND

SYMM

(2.8)

(R0.05) TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 17:

84% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

4224938/B 06/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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TPS613784-Q1 [TI]

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