TPS62422-Q1 [TI]
用于 ADAS 摄像头应用的汽车类 2.25MHz 固定输出电压双路 1000mA/600mA 降压转换器;
| 型号： | TPS62422-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 用于 ADAS 摄像头应用的汽车类 2.25MHz 固定输出电压双路 1000mA/600mA 降压转换器 转换器 |
| 文件： | 总41页 (文件大小：2364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS62406-Q1, TPS62407-Q1, TPS62422-Q1, TPS62423-Q1, TPS62424-Q1
ZHCSHZ2E –DECEMBER 2014 –REVISED MARCH 2022
TPS624xx-Q1 汽车2.25 MHz 固定输出电压双路降压转换器
1 特性
3 说明
• 符合汽车应用要求
• 具有符合AEC-Q100 标准的下列特性：
TPS624xx-Q1 器件系列是适用于汽车应用（例如高级
驾驶辅助系统 (ADAS)）的双路同步降压直流/直流转换
器。该系列可提供两组由标准 3.3 V 或5 V 电压轨供电
的独立输出电压轨，以及经过优化的固定输出电压，为
ADAS 摄像头模块中的 CMOS 成像仪或串行器-解串器
供电。
– 器件温度等级1：–40°C 至125°C 的工作结温
范围
– 器件HBM ESD 分类等级2
– 器件CDM ESD 分类等级C4B
• 高效率- 高达95%
• VIN 范围为2.5 V 至6 V
EasyScale™ 串行接口支持在运行过程中对输出电压进
行修改。固定输出电压版本 TPS624xx-Q1 支持对低功
耗处理器进行单引脚控制的简单动态电压调节。
• 2.25 MHz 固定频率运行
• 输出电流TPS62406-Q1 1000mA/400mA
• 输出电流TPS62407-Q1 400mA/600mA
• 输出电流TPS62422-Q1 1000mA/600mA
• 输出电流TPS62423-Q1 800mA/800mA
• 输出电流TPS62424-Q1 800mA/800mA
• 固定输出电压
• EasyScale™ 可选单引脚串行接口
• 轻负载电流状态下进入节能模式
• 180° 异相运行
TPS624xx-Q1 器件系列可在 2.25 MHz 固定开关频率
下运行，在轻负载电流情况下会进入省电模式，以便在
整个负载电流范围内保持高效率。对于低噪声应用，可
通过拉高 MODE/DATA 引脚来强制器件进入固定频率
PWM 模式。关断模式可以将电流消耗降低至 1.2 μA
的典型值。此器件允许使用小型电感器和电容器，可实
现一个小型解决方案尺寸。
器件信息(1)
• PWM 模式下的输出电压精度±1%
• 适用于两个转换器的典型32 μA 静态电流
• 可实现最低压降的100% 占空比
封装尺寸（标称值）
器件型号
TPS62406-Q1
TPS62407-Q1
TPS62422-Q1
TPS62423-Q1
TPS62424-Q1
封装
2 应用
VSON (10)
3.00mm × 3.00mm
• 汽车负载点稳压器
• ADAS 摄像头模块
• 后视镜更换(CMS)
• 信息娱乐系统与仪表组
TPS62406-Q1
100
90
80
70
60
50
40
30
20
10
VIN = 2.5 to 6 V
VIN
FB1
2.2 µH
VOUT1 = 1.125 V
1000 mA
10 µF
SW1
DEF_1
SW2
10 µF
EN1
EN2
2.2 µH
VOUT2 = 1.2 V
400 mA
MODE/
DATA
10 µF
ADJ2
GND
VIN = 2.5 V
VIN = 3.5 V
VIN = 5 V
VOUT2 = 1.2 V
MODE/DATA = low
0
0.1
1
10
Output Current (mA)
100
400
简化版原理图
D002
TPS62406-Q1 效率与输出电流间的关系， VOUT2
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSCH9
TPS62406-Q1, TPS62407-Q1, TPS62422-Q1, TPS62423-Q1, TPS62424-Q1
ZHCSHZ2E –DECEMBER 2014 –REVISED MARCH 2022
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes..........................................13
8.5 Programming............................................................ 15
9 Application and Implementation..................................21
9.1 Application Information............................................. 21
9.2 Typical Application.................................................... 21
9.3 System Examples..................................................... 27
10 Power Supply Recommendations..............................29
11 Layout...........................................................................30
11.1 Layout Guidelines................................................... 30
11.2 Layout Example...................................................... 30
12 Device and Documentation Support..........................31
12.1 支持资源..................................................................31
12.2 接收文档更新通知................................................... 31
12.3 Trademarks.............................................................31
12.4 Electrostatic Discharge Caution..............................31
12.5 术语表..................................................................... 31
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................5
7.6 Timing Requirements..................................................8
7.7 Switching Characteristics............................................8
7.8 Typical Characteristics................................................9
8 Detailed Description......................................................10
8.1 Overview...................................................................10
8.2 Functional Block Diagram......................................... 11
8.3 Feature Description...................................................12
Information.................................................................... 32
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision D (August 2018) to Revision E (March 2022)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Removed manual package option addendum, tape and reel information, and package drawings.................. 32
Changes from Revision * (December 2014) to Revision A (October 2015)
Page
• Changed the IOUT1 and IOUT2 current for the TPS62406-Q1 device in the Device Comparison Table .............. 3
• Changed forward current limit PMOS and NMOS for the TPS62406-Q1...........................................................5
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ZHCSHZ2E –DECEMBER 2014 –REVISED MARCH 2022
5 Device Comparison Table
PART NUMBER
DEFAULT OUTPUT VOLTAGE
OUTPUT CURRENT
IOUT1
DEF_1 = High 1.125 V
DEF_1 = Low 1.125 V
VOUT1
VOUT2
VOUT1
VOUT2
VOUT1
VOUT2
VOUT1
VOUT2
VOUT1
VOUT2
Fixed default
1000 mA
400 mA
400 mA
600 mA
1000 mA
600 mA
800 mA
800 mA
800 mA
800 mA
TPS62406-Q1
TPS62407-Q1
TPS62422-Q1
TPS62423-Q1
TPS62424-Q1
Fixed default 1.2 V
IOUT2
IOUT1
IOUT2
IOUT1
IOUT2
IOUT1
IOUT2
IOUT1
IOUT2
DEF_1 = High 1.225 V
DEF_1 = Low 1.225 V
Fixed default
Fixed default
Fixed default
Fixed default
Fixed default 1.85 V
DEF_1 = High 1.8 V
DEF_1 = Low 1.15 V
Fixed default 1.2V
DEF_1 = High 1.5 V
DEF_1 = Low 1.2 V
Fixed default 1.8V
DEF_1 = High 1.3 V
DEF_1 = Low 1.1 V
Fixed default 1.8V
6 Pin Configuration and Functions
ADJ2
1
2
3
4
5
10
9
SW2
EN2
GND
EN1
SW1
MODE/DATA
VIN
Thermal Pad
8
FB1
7
DEF_1
6
图6-1. DRC Package 10-Pin VSON With Thermal Pad Top View
表6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Output voltage sense pin for the internal feedback divider. This pin must connect directly to the output. If
using the EasyScale interface-on converter 2, this pin must also connect directly to the output.
ADJ2
1
I
This pin defines the output voltage of converter 1 and is a digital input, that selects between two fixed
default output voltages. See 节5 for output voltage setting of the different device options. For TPS62406-
Q1 and TPS62407-Q1 the output voltage is same independent of DEF_1 pin level. This pin must be
terminated.
DEF_1
5
I
EN1
EN2
FB1
GND
7
9
4
8
I
I
Enable input for converter 1, active-high. This pin must be terminated.
Enable input for converter 2, active-high. This pin must be terminated.
Output voltage sense pin for the internal feedback divider. This pin is connected to the output.
GND for both converters; connect this pin to the thermal pad.
I
—
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表6-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
This pin has two functions:
1. Operation-mode selection: With low level, enables power-save mode where the device operates in
PFM mode at light loads and automatically enters PWM mode at heavy loads. Pulling this PIN to
high forces the device to operate in PWM mode over the whole load range.
MODE/DATA
2
I/O
2. EasyScale interface function: One-wire serial interface to change the output voltage of both
converters. The pin has an open-drain output to provide an acknowledge condition if requested.
The current into the open-drain output stage may not exceed 500 μA. The EasyScale interface is
active if either EN1 or EN2 is high.
SW1
SW2
6
I/O Switch pin of converter 1. Connect to inductor
I/O Switch pin of converter 2. Connect to inductor
10
Input pin, connect to supply or battery voltage, 2.5 V to 6 V. Connect the input capacitor CIN as close as
possible between VIN pin and GND pin.
VIN
3
I
Thermal pad
Connect to GND
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ZHCSHZ2E –DECEMBER 2014 –REVISED MARCH 2022
7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
Input voltage(2)
Voltage(2)
VIN
7
–0.3
–0.3
–0.3
–0.3
EN, MODE/DATA, DEF_1
SW1, SW2
V
VIN + 0.3, ≤7
7
V
ADJ2, FB1
V
VIN + 0.3, ≤7
≤0.5
Current
MODE/DATA
mA
°C
°C
Maximum operating junction temperature, TJmax
Storage temperature, Tstg
150
150
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per AEC Q100-002(1)
V
Electrostatic
discharge
V(ESD)
All pins
Charged device model (CDM), per AEC
Q100-011
V
Corner pins (1, 5, 6, and 10)
±750
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
MAX UNIT
VIN
TJ
Supply voltage
2.5
6
V
Operating junction temperature
125
°C
–40
7.4 Thermal Information
TPS624xx-Q1
DRC (VSON)
10 PINS
42.7
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
46.9
18.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.5
ψJT
18.3
ψJB
RθJC(bot)
3.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
VIN = 3.6 V, EN1 = EN2 = VIN, MODE = GND, L1 = L2 = 2.2 μH, COUT1 = COUT2 = 20 μF, TJ = –40°C to 125°C, typical
values are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VIN Input voltage range
2.5
6
V
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VIN = 3.6 V, EN1 = EN2 = VIN, MODE = GND, L1 = L2 = 2.2 μH, COUT1 = COUT2 = 20 μF, TJ = –40°C to 125°C, typical
values are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
One converter, no load on the output. PFM mode
enabled (MODE/DATA = GND) device not switching,
EN1 = 1 or EN2 = 1
19
35
Two converters, no load on the output. PFM mode
enabled (MODE/DATA = GND) device not switching,
EN1 = EN2 = 1
μA
32
50
IQ
Operating quiescent current
No load on the output, MODE/DATA = GND, for one
converter(1)
23
No load on the output, MODE/DATA = VIN, for one
converter(1)
3.6
mA
EN1, EN2 = GND, VIN = 3.6 V(2)
1.2
0.1
1.5
3
1.5
ISD
Shutdown current
μA
EN1, EN2 = GND, VIN ramped from 0 V to 3.6 V(3)
Falling
Rising
2.35
2.4
VUVLO
Undervoltage lockout threshold
V
ENABLE EN1, EN2
VIH
VIL
IIN
High-level input voltage range, EN1, EN2
1.2
0
VIN
0.4
1
V
V
Low-level input voltage range, EN1, EN2
Input bias current, EN1, EN2
EN1, EN2 = GND or VIN
0.05
0.01
0.01
μA
DEF_1 INPUT
VDEF_1H
DEF_1 high-level digital input voltage range
0.9
0
VIN
0.4
1
V
V
VDEF_1L
DEF_1 low-level digital input voltage range
Input bias current DEF_1
IIN
DEF_1 = GND or VIN
μA
MODE/DATA
VIH
VIL
High-level input voltage range, MODE/DATA
Low-level input voltage range, MODE/DATA
Input bias current, MODE/DATA
1.2
0
VIN
0.4
1
V
V
IIN
MODE/DATA = GND or VIN
μA
V
VOH
VOL
Acknowledge output voltage high
Open drain, through external pullup resistor
Open drain, sink current 500 μA
VIN
0.4
Acknowledge output voltage low
0
V
POWER SWITCH
P-channel MOSFET on-resistance, converter
1 and 2
rDS(on)
VIN = VGS = 3.6 V
VDS = 6 V
280
620
1
mΩ
μA
mΩ
ILK_PMOS
rDS(on)
P-channel leakage current
N-channel MOSFET on-resistance converter
1 and 2
VIN = VGS = 3.6 V
200
6
450
Includes N-channel leakage current,
VIN = open, VSW = 6 V, EN = GND(4)
ILK_SW1/SW2 Leakage current into SW1 or SW2 pin
7.5
μA
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VIN = 3.6 V, EN1 = EN2 = VIN, MODE = GND, L1 = L2 = 2.2 μH, COUT1 = COUT2 = 20 μF, TJ = –40°C to 125°C, typical
values are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TPS62406-Q1
VOUT1
1.18
1.4
1.61
2.5 V ≤VIN ≤6 V
TPS62406-Q1
VOUT2
0.68
0.68
0.75
1.18
0.75
1
0.8
0.8
1
0.92
0.92
1.15
1.61
1.15
1.38
1.38
1.38
1.38
2.5 V ≤VIN ≤6 V
2.5 V ≤VIN ≤6 V
2.5 V ≤VIN ≤6 V
2.5 V ≤VIN ≤6 V
2.5 V ≤VIN ≤6 V
2.5 V ≤VIN ≤6 V
2.5 V ≤VIN ≤6 V
2.5 V ≤VIN ≤6 V
2.5 V ≤VIN ≤6 V
TPS62407-Q1
VOUT1
TPS62407-Q1
VOUT2
TPS62422-Q1
VOUT1
1.4
1
Forward current limit
PMOS and NMOS
ILIMF
A
TPS62422-Q1
VOUT2
TPS62423-Q1
VOUT1
1.2
1.2
1.2
1.2
TPS62423-Q1
VOUT2
1
TPS62424-Q1
VOUT1
1
TPS62424-Q1
VOUT2
1
TSD
Thermal shutdown
Increasing junction temperature
Decreasing junction temperature
150
20
°C
°C
Thermal shutdown hysteresis
OUTPUT
Vref
Internal Reference voltage
600
1%
mV
Voltage positioning active,
MODE/DATA = GND,
VOUTx(PFM)
2.5%
1%
–1.5%
device operating in PFM mode,
VIN = 2.5 V to 5 V(5) (6)
MODE/DATA = GND;
DC output voltage accuracy
device operating in PWM mode,
0%
0%
–1%
–1%
VIN = 2.5 V to 6 V(6)
VOUTx(PWM)
VIN = 2.5 V to 6 V, MODE/DATA = VIN
,
Fixed PWM operation,
1%
0.5
0 mA < IOUT1 < 400 mA ; 0 mA < IOUT2 < 600 mA(7)
PWM operation mode
DC output voltage load regulation
%/A
(1) Device is switching with no load on the output, L1 = L2 = 3.3 μH, value includes losses of the coil.
(2) These values are valid after enabling the device one time (EN1 or EN2 = high) and maintaining supply voltage VIN.
(3) These values are valid when the device is disabled (EN1 and EN2 low) and supply voltage VIN is powered up. The values remain valid
until enabling the device the first time (EN1 or EN2 = high). After the first enable, Note 3 becomes valid.
(4) An internal resistor of 1 MΩ connects pins SW1 and SW2 to GND.
(5) Configuration L1 or L2 typ. 2.2 μH, COUTx typ 20 μF. See parameter measurement information, the output voltage ripple in PFM
mode depends on the effective capacitance of the output capacitor; larger output capacitors lead to tighter output voltage tolerance.
(6) In power-save mode, the device typically enters PWM operation at IPSM = VIN / 32 Ω.
(7) For VOUTx > 2 V, VIN min = VOUTx + 0.5 V
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7.6 Timing Requirements
MIN
NOM
MAX
UNIT
INTERFACE TIMING
tStart
Start time
2
μs
μs
μs
μs
μs
μs
tH_LB
tL_LB
tL_HB
tH_HB
tEOS
High-time low bit, logic 0 detection
Low-time low bit, logic 0 detection
Low-time high bit, logic 1 detection
High-time high bit, logic 1 detection
End of stream
Signal level on MODE/DATA pin is > 1.2 V
Signal level on MODE/DATA pin < 0.4 V
Signal level on MODE/DATA pin < 0.4 V
Signal level on MODE/DATA pin is > 1.2 V
2
2 x tH_LB
2
200
400
200
400
2 x tL_HB
2
Duration of acknowledge condition
(MODE/DATE line pulled low by the
device)
tACKN
VIN 2.5 V to 6 V
400
520
μs
tvalACK
ttimeout
Acknowledge valid time
2
μs
μs
Time-out for entering power-save mode MODE/DATA pin changes from high to low
520
7.7 Switching Characteristics
VIN = 3.6 V, EN1 = EN2 = VIN, MODE = GND, L1 = L2 = 2.2 μH, COUT1 = COUT2 = 20 μF, TJ = –40°C to 125°C, typical
values are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OSCILLATOR
3 V ≤VIN ≤6 V(1)
2
2.25
2.7
fSW
Oscillator frequency
MHz
OUTPUT
tStart up
Start-up time
Activation time to start switching(2)
170
750
μs
μs
Time to ramp from 5% to 95% of
VOUTx
tRamp
VOUTx ramp-up time
(1) For VOUTx > 2 V, VIN min = VOUTx + 0.5 V
(2) This time is valid if one converter turns from shutdown mode (EN2 = 0) to active mode (EN2 = 1) with the other converter already
enabled (for example, EN1 = 1). In case both converters are turned from shutdown mode (EN1 and EN2 = 0) to active mode (EN1
and/or EN2 = 1), a typical value of typ 80 μs for ramp up of internal circuits must be added. After tStart, the converter starts switching
and ramps VOUTx
.
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7.8 Typical Characteristics
2.6
2.4
2.2
2
30
28
26
24
22
20
18
16
1.8
1.6
1.4
1.2
1
-40èC
25èC
-40èC
25èC
85èC
125èC
14
12
10
85èC
125èC
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
6
2
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
6
D011
D012
IOUT = 400 mA
MODE/DATA = high
EN1 = high
EN2 = low MODE/DATA = low
图7-1. TPS62407-Q1 Switching Frequency
图7-2. TPS26407-Q1 Quiescent Current, One
Converter On
0.55
50
45
40
35
–40°C
25°C
85°C
0.5
0.45
0.4
0.35
0.3
0.25
-40èC
25èC
30
25
85èC
0.2
125èC
0.15
2
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
6
6.5
2.5
3
3.5
4
4.5
5
5.5
6
D001
Input Voltage (V)
EN1 = EN2 = High
MODE/DATA = low
图7-4. rDS(on) PMOS vs VIN
图7-3. TPS26407-Q1 Quiescent Current, Both
Converters On
0.3
–40°C
25°C
85°C
0.25
0.2
0.15
0.1
0.05
2.5
3
3.5
4
4.5
5
5.5
6
Input Voltage (V)
图7-5. rDS(on) NMOS vs VIN
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8 Detailed Description
8.1 Overview
The TPS624xx-Q1 device includes two synchronous step-down converters. The converters operate with typically
2.25-MHz fixed-frequency pulse-width modulation (PWM) at moderate to heavy load currents. With the power-
save mode enabled, the converters automatically enter power-save mode at light load currents and operate in
PFM (pulse frequency modulation).
During PWM operation, the converters use a unique fast-response voltage-mode controller scheme with input-
voltage feed-forward to achieve good line and load regulation, allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch
turns on and the inductor current ramps up until the comparator trips and the control logic turns off the switch.
Each converter integrates two current limits, one in the P-channel MOSFET and another one in the N-channel
MOSFET. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET turns off
and the N-channel MOSFET turns on. If the current in the N-channel MOSFET is above the N-MOS current limit
threshold, the N-channel MOSFET remains on until the current drops below its current limit.
The two DC-DC converters operate synchronized to each other. A 180° phase shift between converter 1 and
converter 2 decreases the input rms current.
8.1.1 Converter 1
It is possible to change the output voltage of converter 1 with the EasyScale serial Interface. This makes the
device very flexible for output-voltage adjustment. In this case, the device uses an internal resistor network.
The output voltage can also be selected using the DEF_1 pin configuration as a digital input. For these voltage
version the DEF_1 pin select the same output voltage for DEF_1=high or DEF_1=low.
8.1.2 Converter 2
It is also possible to change the output voltage of converter 2 via the EasyScale interface.
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8.2 Functional Block Diagram
VIN
PMOS Current
Limit Comparator
VIN
Converter 1
FB_VOUT
VREF +1%
Thermal
Softstart
Shutdown
Skip Comp.
FB_VOUT
VREF- 1%
EN1
Skip Comp. Low
VREF
Gate Driver
Control
Stage
Ext. res. network
Error Amp.
Internal
compensated
FB
VOUT1
DEF1
Int. Resistor
Network
PWM
Comp.
SW1
Cff 25pF
MODE
Register
RI 1
Sawtooth
Generator
DEF1_High
DEF1_Low
GND
RI..N
FB1
Average
Current Detector
Skip Mode Entry
NMOS Current
Limit Comparator
Note 1
CLK 0°
Reference
Load Comparator
2.25MHz
Oscillator
Easy Scale
Interface
ACK
Mode/
DATA
Undervoltage
Lockout
PMOS Current
Limit Comparator
CLK 180°
MOSFET
Open drain
VIN
FB_VOUT
Converter 2
Int. Resistor
Network
VREF +1%
Skip Comp.
Register
FB_VOUT
VREF- 1%
DEF2
Note 2
Skip Comp. Low
VREF
Gate Driver
Control
Stage
Cff 25pF
Error Amp.
RI 1
Internal
compensated
PWM
Comp.
RI..N
SW2
MODE
FB_VOUT2
ADJ2
EN2
Sawtooth
Generator
GND
Thermal
Shutdown
Average
Current Detector
Skip Mode Entry
NMOS Current
Limit Comparator
CLK 180°
Softstart
Load Comparator
GND
A. In the fixed output-voltage version, the DEF_1 pin connects to an internal digital input and disconnects from the error amplifier.
B. To set the output voltage of converter 2 through the EasyScale™ interface, the ADJ2 pin must directly connect to VOUT2
.
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8.3 Feature Description
8.3.1 Enable
The device has a separate EN pin for each converter to start up each converter independently. If EN1 or EN2 is
set to high, the corresponding converter starts up with soft start.
Pulling EN1 and EN2 pin low forces the device into shutdown, with a shutdown quiescent current of typically 1.2
μA. In this mode, the P- and N-channel MOSFETs turn off and the entire internal control circuitry switches off.
For proper operation, terminate the EN1 and EN2 pins, do not leave them floating.
8.3.2 DEF_1 Pin Function
The DEF_1 pin, dedicated to converter 1, makes the output voltage selection very flexible to support dynamic
voltage management. Having this pin tied to a low level sets the output voltage according to the value in register
REG_DEF_1_Low. The default voltage is 1.125 V for TPS62406-Q1. Having the pin tied to a high level sets the
output voltage according to the value in register REG_DEF_1_High. The default value in this case is 1.125 V as
well. The level of the DEF_1 pin selects between the two registers, REG_DEF_1_Low and REG_DEF_1_High,
for the output-voltage setting. One can change the content of each register (and therefore output voltage)
individually through the EasyScale interface. This makes the device very flexible in terms of output voltage
setting; see 表8-3
8.3.3 180° Out-of-Phase Operation
In PWM mode, the converters operate with a 180° turn-on phase shift of the PMOS (high side) transistors. This
prevents the high-side switches of both converters from turning on simultaneously, reducing the input current
ripple. This feature reduces the surge current drawn from the supply.
8.3.4 Short-Circuit Protection
Both outputs are short-circuit protected with maximum output current = ILIMF(P-MOS and N-MOS). Once the
PMOS switch reaches its current limit, it turns off and the NMOS switch turns on. The PMOS only turns on again
once the current in the NMOS decreases below the NMOS current limit.
8.3.5 Thermal Shutdown
As soon as the junction temperature, TJ, exceeds 150°C (typical) the device goes into thermal shutdown. In this
mode, the P- and N-channel MOSFETs turn off. The device continues its operation when the junction
temperature falls below the thermal-shutdown hysteresis.
8.3.6 EasyScale Interface: One-Pin Serial Interface for Dynamic Output-Voltage Adjustment
8.3.6.1 General
The EasyScale interface is a simple but very flexible one-pin interface to configure the output voltage of both
DC-DC converters. A master-slave structure is the basis of the interface, where the master is typically a
microcontroller or application processor. 图 8-3 and 表 8-2 give an overview of the protocol. The protocol
consists of a device-specific address byte and a data byte. The device-specific address byte is fixed to 4E hex.
The data byte consists of five bits for information, two address bits, and the RFA bit. The RFA bit set to high
indicates the request-for-acknowledge condition. The acknowledge condition only applies after correct reception
of the protocol.
The advantage of the EasyScale interface compared to other one-pin interfaces is that its bit detection is to a
large extent independent from the bit transmission rate. It can automatically detect bit rates between 1.7 kb/s
and up to 160 kb/s. Furthermore, the interface shares the MODE/DATA pin and requires no additional pin.
8.3.6.2 Protocol
Transmission of all bits is MSB first and LSB last. 图8-4 shows the protocol without the acknowledge request (bit
RFA = 0), 图8-5 with the acknowledge request (bit RFA = 1).
Prior to both bytes, device address byte and data byte, one must apply a start condition. For this, pull the MODE/
DATA pin high for at least tStart before the bit transmission starts with the falling edge. In case the MODE/DATA
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line was already at a high level (forced PWM mode selection), the device requires no start condition prior to the
device address byte.
Close the transmission of each byte with an end-of-stream condition for at least tEOS
.
8.4 Device Functional Modes
8.4.1 Power-Save Mode
Setting the MODE/DATA pin to low for both converters enables power-save mode. If the load current of a
converter decreases, this converter enters power-save-mode operation automatically. The transition of a
converter to power-save mode is independent from the operating condition of the other converter. During power-
save mode, the converter operates with reduced switching frequency in PFM mode and with a minimum
quiescent current to maintain high efficiency. The converter positions the output voltage in PFM mode to typically
1% above nominal VOUTx. This voltage positioning feature minimizes voltage drops caused by a sudden load
step.
In order to optimize the converter efficiency at light load, the device monitors average inductor current. The
device changes from PWM mode to power-save mode if in PWM mode the inductor current falls below a certain
threshold. The typical output current threshold, which one can calculate using 方程式 1 for each converter,
depends on VIN.
方程式1: Average output current threshold to enter PFM mode
VIN
DCDC
I
+
OUT_PFM_enter
32 W
(1)
方程式2: Average output current threshold to leave PFM mode
VIN
DCDC
I
+
OUT_PFM_leave
24 W
(2)
To keep the output-voltage ripple in power-save mode low, a single threshold comparator (skip comparator)
monitors the output voltage. As the output voltage falls below the skip-comparator threshold (skip comp) of 1%
above nominal VOUTx, the corresponding converter starts switching for a minimum time period of typically 1 μs
and provides current to the load and the output capacitor. Therefore, the output voltage increases and the device
maintains switching until the output voltage trips the skip comparator threshold (skip comp) again. At this
moment, all switching activity stops and the quiescent current reduces to minimum. The output capacitor
supplies the load until the output voltage has dropped below the threshold again. Hereupon, the device starts
switching again.
The converter leaves power-save mode and enters PWM mode if the output current exceeds the IOUT_PFM_leave
current or if the output voltage falls below a second comparator threshold, called the skip-comparator-low (Skip
Comp Low) threshold. This skip-comparator-low threshold is 2% below nominal VOUTx and enables a fast
transition from power-save mode to PWM mode during a load step.
Power-save mode typically reduces the quiescent current to 19 μA for one converter and 32 μA for both
converters active. This single-skip comparator threshold method in power-save mode results in a very low
output-voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor.
Increasing output capacitor values minimizes the output ripple. One can disable the power-save mode by setting
the MODE/DATA pin to high. Both converters then operate in fixed PWM mode. Power-save mode enable or
disable applies to both converters.
8.4.1.1 Dynamic Voltage Positioning
This feature reduces the voltage under- and overshoots at load steps from light to heavy load and from heavy to
light load. Power-save-mode operation activates dynamic voltage positioning and provides more headroom for
both the voltage drop at a load step and the voltage increase when a load is switched off, which improves load-
transient behavior.
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At light loads, in which the converter operates in PFM mode, the output voltage regulation is typically 1% higher
than the nominal value. In case of a load transient from light load to heavy load, the output voltage drops until it
reaches the skip comparator low threshold set to 2% below the nominal value and enters PWM mode. During a
load transition from heavy load to light load, the device also minimizes voltage overshoot because of active
regulation turning on the N-channel switch.
Smooth
Fast load transient
increased load
+1%
PFM Mode
light load
PFM Mode
light load
V
OUT_NOM
PWM Mode
medium/heavy load
PWM Mode
medium/heavy load
PWM Mode
medium/heavy load
COMP_LOW threshold -2%
图8-1. Dynamic Voltage Positioning
8.4.1.2 Soft Start
The two converters have an internal soft-start circuit that limits the inrush current during startup. 图 8-2 shows
control of the output-voltage ramp-up during soft start.
EN
95%
5%
V
OUT
t
t
Startup
RAMP
图8-2. Soft Start
8.4.1.3 100% Duty-Cycle Low-Dropout Operation
The converters offer a low input-to-output voltage difference while still maintaining operation with the use of the
100% duty-cycle mode. In this mode, the P-channel switch is constantly on. This is particularly useful in battery-
powered applications to achieve longest operation time by taking full advantage of the whole battery-voltage
range. The minimum input voltage to maintain regulation depends on the load current and output voltage, which
one can calculate as:
ǒRDSon
Ǔ
Vin
+ Vout
) Iout
) R
max
L
max
max
min
(3)
with
• IOUTxmax = maximum output current plus inductor ripple current
• rDS(on)max = maximum P-channel switch rDS(on)
• RL = dc resistance of the inductor
• VOUTxmax = nominal output voltage plus maximum output-voltage tolerance
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With decreasing load current, the device automatically switches into pulse-skipping operation, in which the
power stage operates intermittently based on load demand. Running cycles periodically minimizes the switching
losses, and the device runs with a minimum quiescent current, maintaining high efficiency.
8.4.1.4 Undervoltage Lockout
The undervoltage lockout circuit prevents the device from malfunction at low input voltages and from excessive
discharge of the battery, and disables the converters. The undervoltage lockout threshold is typically 1.5 V;
maximum of 2.35 V. In case the interface overwrites the default register values, the new values in the registers
REG_DEF_1_High, REG_DEF_1_Low and REG_DEF_2 remain valid as long the supply voltage does not fall
below the undervoltage lockout threshold, independent of disabling of the converters.
8.4.2 Mode Selection
The MODE/DATA pin allows mode selection between forced PWM mode and power-save mode for both
converters. Furthermore, this pin is a multipurpose pin and provides (besides mode selection) a one-pin interface
to receive serial data from a host to set the output voltage, as described in the EasyScale Interface section.
Connecting this pin to GND enables the automatic PWM and power-save-mode operation. The converters
operate in fixed-frequency PWM mode at moderate-to-heavy loads, and in the PFM mode during light loads,
maintaining high efficiency over a wide load-current range.
Pulling the MODE/DATA pin high forces both converters to operate constantly in the PWM mode, even at light
load currents. The advantage is that the converters operate with a fixed frequency, allowing simple filtering of the
switching frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the power-
save mode during light loads. For additional flexibility, it is possible to switch from power-save mode to forced
PWM mode during operation. This allows efficient power management by adjusting the operation of the
converter to the specific system requirements.
In the case of changing the operation mode from forced PWM mode (MODE/DATA = high) to power-save mode
(MODE/DATA = 0), enabling the power-save mode occurs after a delay time of ttimeout, which is 520 μs
maximum.
Setting the MODE/DATA to 1 enables forced-PWM-mode operation immediately.
8.5 Programming
8.5.1 Addressable Registers
Three registers with a data content of 5 bits are addressable. With 5-bit data content, 32 different values for each
register are available. 表 8-1 shows the addressable registers to set the output voltage when the DEF_1 pin
works as a digital input. In this case, converter 1 has a related register for each DEF_1 pin condition, and one
register for converter 2. A high or low condition on pin DEF_1 selects either the content of register
REG_DEF_1_High or REG_DEF_1_Low, thus setting the output voltage of converter 1 according to the values
in Selectable Output Voltage Converter 1, With Pin DEF_1 as Digital Input. Use of a precise internal resistor
divider network to generate these output voltages makes external resistors unnecessary (less board space) and
provides higher output-voltage accuracy. Enabling at least one of the converters (EN1 or EN2 is high) activates
the interface. After the startup time tStart (170 μs), the interface is ready for data reception.
表8-1. Addressable Registers for Default Fixed-Output Voltage Options (PIN DEF_1 = Digital Input)
DEVICE
REGISTER
DESCRIPTION
DEF_1
PIN
A1
A0
D4
D3
D2
D1
D0
REG_DEF_1_High
Converter 1 output voltage setting for
DEF_1 = High condition. The content of the
register is active with the DEF_1 pin high.
High
0
1
Output voltage setting, see 表8-3
REG_DEF_1_Low
REG_DEF_2
Converter 1 output voltage setting for
DEF_1 = Low condition.
Low
0
1
1
0
0
1
Output voltage setting, see 表8-3
Output voltage setting, see 表8-4
TPS624xx-Q1 ,
Converter 2 output voltage
Not
applicable
Do not use
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8.5.1.1 Bit Decoding
The bit detection is based on a PWM scheme, where the criterion is the relation between the low time and high
time of the low or high bit (tL_xB and tH_xB). Bit detection can be simplified to:
High bit: tH_HB > tL_HB, but with tH_HB at least 2× tL_HB, see 图8-3.
Low bit: tL_LB > tH_LB, but with tL_LB at least 2× tH_LB, see 图8-3.
The bit detection starts with a falling edge on the MODE/DATA pin and ends with the next falling edge. Detection
of a 0 or 1 depends on the relation between tL_xB and tH_xB
.
8.5.1.2 Acknowledge
The device only applies the acknowledge condition if all of the following occurs:
• A set RFA bit requests an acknowledge
• The transmitted device address matches with the device address of the device
• Correct reception of 16 bits occurred
In this case, the device turns on the internal ACKN-MOSFET and pulls the MODE/DATA pin low for the time
t
ACKN, which is 520 μs maximum. The acknowledge condition is valid after an internal delay time tvalACK. This
means the internal ACKN-MOSFET turns on after tvalACK, on detection of the last falling edge of the protocol.
The master controller keeps the line low during this time.
The master device can detect the acknowledge condition with its input by releasing the MODE/DATA pin after
tvalACK and reading back a 0.
In case of an invalid device address, or not-correctly-received protocol, application of a no-acknowledge
condition does not occur; thus, the internal MOSFET does not turn on, and the external pullup resistor pulls the
MODE/DATA pin high after tvalACK. One can use the MODE/DATA pin again after the acknowledge condition
ends.
备注
The master device must have an open-drain output in order to request the acknowledge condition.
In case of a push-pull output stage, TI recommends using a series resistor in the MODE/DATA line to limit the
current to 500 μA in case of an accidentally requested acknowledge, to protect the internal ACKN-MOSFET.
8.5.1.3 Mode Selection
Use of the MODE/DATA pin for two functions, interface and mode selection, necessitates a determination of
when to decode the bit stream or to change the operation mode.
The device enters forced PWM mode operation immediately whenever the MODE/DATA pin turns to high level.
The device also stays in forced PWM mode during the entire protocol reception time.
With a falling edge on the MODE/DATA pin, the device starts bit decoding. If the MODE/DATA pin stays low for
at least ttimeout, the device gets an internal time-out and enables power-save-mode operation.
The device ignores a protocol sent within this time because the first interpretation of a falling edge for the mode
change is at the start of the first bit. In this case, TI recommends sending the protocol first, and then changing to
power-save mode at the end of the protocol.
DATA IN
Device Address
DATABYTE
D4 D3 D2
Start DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
RFA A1
A0
D1 D0
EOS Start
EOS
0
1
0
0
1
1
1
0
DATA OUT ACK
图8-3. EasyScale Protocol Overview
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表8-2. EasyScale Bit Description
BIT
NAME TRANSMISSION
DESCRIPTION
NUMBER
DIRECTION
Device
address
byte
7
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
RFA
A1
IN
IN
IN
IN
IN
IN
IN
IN
IN
0 MSB device address
6
1
5
0
4
0
4E hex
3
1
2
1
1
1
0
0 LSB device address
Data byte
7 (MSB)
Request for acknowledge; if high, the device applies an acknowledge condition.
6
Address bit 1
Address bit 0
Data bit 4
5
A0
4
D4
3
D3
Data bit 3
2
1
D2
Data bit 2
D1
Data bit 1
0 (LSB)
D0
Data bit 0
ACK
OUT
Acknowledge condition active 0, the device applies this condition only in the case of
a set RFA bit. Open-drain output, the host must pull the line high with a pullup
resistor.
One can only use this feature if the master has an open-drain output stage. In case
of a push-pull output stage, do not request an acknowledge condition.
tStart
tStart
Address Byte
DATA Byte
DATA IN
Mode, Static
High or Low
Mode, Static
High or Low
DA7
0
DA0
0
RFA
D0
1
TEOS
TEOS
0
图8-4. EasyScale Protocol Without Acknowledge
tStart
tStart
Address Byte
DATA Byte
Mode, Static
High or Low
Mode, Static
High or Low
DATA IN
DA7
DA0
0
D0
1
RFA
1
0
TEOS
tvalACK
Acknowledge
true, Data Line
pulled down by
device
ACKN
tACKN
Controller needs to
Pullup Data Line via a
resistor to detect ACKN
DATA OUT
Acknowledge
false, no pull
down
图8-5. EasyScale Protocol Including Acknowledge
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t
t
t
t
Low
Low
High
High
Low Bit
High Bit
(Logic 1)
(Logic 0)
图8-6. EasyScale –Bit Coding
MODE/DATA
t
timeout
Power Save Mode
Forced PWM MODE
Power Save Mode
图8-7. MODE/DATA PIN: Mode Selection
t
t
Address Byte
Start DATA Byte
Start
MODE/DATA
T
EOS
t
T
EOS
timeout
Power Save Mode
Forced PWM MODE
Power Save Mode
图8-8. MODE/DATA Pin: Power-Save-Mode and Interface Communication
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表8-3. Selectable Output Voltages for Converter 1,
With Pin DEF_1 as Digital Input
TPS624xx-Q1 OUTPUT
TPS624xx-Q1
VOLTAGE [V]
D4 D3 D2 D1 D0
VOLTAGE [V]
REGISTER REG_DEF_1_LOW
REGISTER REG_DEF_1_HIGH
0
0.8
0.9
0.925
0.95
0.975
1.0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0.825
0.85
2
3
0.875
0.9
4
5
0.925
0.95
1.025
1.050
1.075
1.1
6
7
0.975
1.0
8
9
1.025
1.050
1.075
1.1
1.125
1.150
1.175
1.2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1.125
1.150
1.175
1.2
1.225
1.25
1.275
1.3
1.225
1.25
1.325
1.350
1.375
1.4
1.275
1.3
1.325
1.350
1.375
1.4
1.425
1.450
1.475
1.5
1.425
1.450
1.475
1.5
1.525
1.55
1.575
1.6
1.525
1.55
1.7
1.8
1.575
1.9
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表8-4. Selectable Output Voltages for Converter 2,
(ADJ2 Connected to VOUT2
)
OUTPUT VOLTAGE [V]
D4 D3 D2 D1 D0
FOR REGISTER REG_DEF_2
0
0.6
0.85
0.9
0.95
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
2
3
4
5
1.05
1.1
1.15
1.2
1.25
1.3
1.35
1.4
1.45
1.5
1.55
1.6
1.7
1.8
1.85
2
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.85
3
3.3
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
9.1.1 Application Information
The TPS624xx-Q1 family of devices are synchronous dual step-down DC-DC converters. The devices provide
two independent output voltage rails. The following information provides guidance on selecting external
components to complete the application design.
9.2 Typical Application
TPS62406-Q1
VIN = 2.5 to 6 V
VIN
FB1
2.2 µH
VOUT1 = 1.125 V
1000 mA
10 µF
SW1
DEF_1
SW2
10 µF
EN1
EN2
2.2 µH
VOUT2 = 1.2 V
400 mA
MODE/
DATA
10 µF
ADJ2
GND
图9-1. Typical Application Schematic
9.2.1 Design Requirements
The step-down converter design can be adapted to different output voltage and load current needs. The
following design procedure is adequate for whole VIN, VOUTx and load current range of the TPS624xx-Q1 family
of devices.
9.2.2 Detailed Design Procedure
9.2.2.1 Output Voltage Setting
9.2.2.1.1 Converter 1 Fixed Default Output-Voltage Setting
The DEF_1 pin selects output voltage VOUT1
.
Pin DEF_1 = low:
• TPS62406-Q1, TPS62407-Q1 = 1.125 V
• TPS62422-Q1 = 1.15V
• TPS62423-Q1 = 1.2V
• TPS62424-Q1 = 1.1V
Pin DEF_1 = high:
• TPS62406-Q1 = 1.125 V
• TPS62407-Q1 = 1.225 V
• TPS62422-Q1 = 1.8V
• TPS62423-Q1 = 1.5V
• TPS62424-Q1 = 1.3V
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9.2.2.1.2 Converter 2 Fixed Default Output-Voltage Setting
ADJ2 pin must be directly connected with VOUT2
:
• TPS62406-Q1, VOUT2 default = 1.2 V
• TPS62407-Q1, VOUT2 default = 1.85 V
• TPS62422-Q1, VOUT2 default = 1.2 V
• TPS62423-Q1, VOUT2 default = 1.8 V
• TPS62424-Q1, VOUT2 default = 1.8 V
9.2.2.2 Output Filter Design (Inductor and Output Capacitor)
The converters operate with a minimum inductance of 1.75 μH and minimum capacitance of 6 μF. The device
operation is optimum with inductors of 2.2 μH to 4.7 μH and output capacitors of 10 μF to 22 μF.
9.2.2.2.1 Inductor Selection
Select the inductor based on its ratings for dc resistance and saturation current. The dc resistance of the
inductor directly influences the efficiency of the converter. Therefore, select an inductor with lowest dc resistance
for highest efficiency.
方程式 4 calculates the maximum inductor current under static load conditions. The saturation-current rating of
the inductor should be higher than the maximum inductor current as calculated with 方程式 5. TI makes this
recommendation because during heavy load transients the inductor current rises above the calculated value.
Vout
1 *
Vin
DI + Vout
L
L ƒ
(4)
where
• ΔIL = Peak-to-peak inductor ripple current
• L = Inductor value
• f = Switching frequency (2.25 MHz typical)
DI
L
I
+ I
)
outmax
Lmax
2
(5)
where
• ILmax = Maximum inductor current
and the highest inductor current occurs at maximum VIN.
Open-core inductors have a soft saturation characteristic and they can usually handle higher inductor currents
versus a comparable shielded inductor.
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
corresponding converter. Take into consideration that the core material from inductor to inductor differs, and this
difference has an impact on the efficiency.
See 表9-1 and the typical application circuit examples for possible inductors.
表9-1. List of Inductors
DIMENSIONS [mm]
3.2 × 2.6 × 1
3 × 3 × 0.9
INDUCTOR TYPE
MIPW3226
LPS3010
SUPPLIER
FDK
Coilcraft
TDK
2.8 × 2.6 × 1
2.8 x 2.6 × 1.4
3 × 3 × 1.4
VLF3010
VLF3014
TDK
LPS3015
Coilcraft
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表9-1. List of Inductors (continued)
DIMENSIONS [mm]
INDUCTOR TYPE
SUPPLIER
3.9 × 3.9 × 1.7
LPS4018
Coilcraft
9.2.2.2.2 Output-Capacitor Selection
The advanced fast-response voltage-mode control scheme of the converters allows the use of tiny ceramic
capacitors with a typical value of 10 μF to 22 μF, without having large output-voltage under- and overshoots
during heavy load transients. Ceramic capacitors with low ESR values result in lowest output-voltage ripple, and
TI therefore recommends them. The output capacitor requires either X7R or X5R dielectric. TI does not
recommend Y5V and Z5U dielectric capacitors because of their wide variation in capacitance.
If using ceramic output capacitors, the capacitor rms ripple-current rating always meets the application
requirements. The rms ripple current calculation is:
Vout
1 *
Vin
1
I
+ Vout
RMSCout
Ǹ
L ƒ
2 3
(6)
At nominal load current, the inductive converters operate in PWM mode and the overall output voltage ripple is
the sum of the voltage spike caused by the output capacitor ESR, plus the voltage ripple caused by charging
and discharging the output capacitor:
Vout
1 *
Vin
1
ǒ
) ESRǓ
DVout + Vout
L ƒ
8 Cout ƒ
(7)
where
• The highest output-voltage ripple occurs at the highest input voltage, VIN.
At light load currents, the converters operate in power-save mode and the output-voltage ripple depends on the
output-capacitor value. The internal comparator delay and the external capacitor set the output-voltage ripple.
Higher output capacitors like 22 μF values minimize the voltage ripple in PFM mode and tighten dc output
accuracy in PFM mode.
9.2.2.2.3 Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, the device requires a low-ESR
input capacitor to prevent large voltage transients that can cause misbehavior of the device or interference with
other circuits in the system. An input capacitor of 10 μF is sufficient.
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9.2.3 Application Curves
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 2.5 V
VIN = 3.5 V
VIN = 5 V
VIN = 2.5 V
VIN = 3.5 V
VIN = 5 V
0.01
0.1
1
10
Output Current (mA)
100
1000
0
50
100 150 200 250 300 350 400 450
Output Current (mA)
D004
D009
VOUT1 = 1.225 V
MODE/DATA = low
VOUT1 = 1.225 V
MODE/DATA = high
图9-2. TPS62407-Q1 Efficiency, VOUT1
图9-3. TPS62407-Q1 Efficiency, VOUT1
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 2.5 V
VIN = 3.5 V
VIN = 5 V
VIN = 2.5 V
VIN = 3.5 V
VIN = 5 V
0.01
0.1
1 10
Output Current (mA)
100
1000
0
100
200
300 400
Output Current (mA)
500
600
700
D005
D0010
VOUT2 = 1.85 V
MODE/DATA = low
VOUT2 = 1.85 V
MODE/DATA = high
图9-4. TPS62407-Q1 Efficiency, VOUT2
图9-5. TPS62407-Q1 Efficiency, VOUT2
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 2.5 V
VIN = 3.5 V
VIN = 5 V
VIN = 2.5 V
VIN = 3.5 V
VIN = 5 V
0.1
1
10
Output Current (mA)
100
1000
0.1
1
10
Output Current (mA)
100
1000
D003
D007
VOUT1 = 1.125 V
MODE/DATA = low
VOUT1 = 1.125 V
MODE/DATA = high
图9-6. TPS62406-Q1 Efficiency, VOUT1
图9-7. TPS62406-Q1 Efficiency, VOUT2
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100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
VIN = 2.5 V
VIN = 3.5 V
VIN = 5 V
VIN = 2.5 V
VIN = 3.5 V
VIN = 5 V
10
0
0
0.1
1
10
Output Current (mA)
100
400
0.1
1
10
Output Current (mA)
100
400
D006
D008
VOUT2 = 1.2 V
MODE/DATA = low
VOUT2 = 1.2 V
MODE/DATA = high
图9-8. TPS62406-Q1 Efficiency, VOUT2
图9-9. TPS62406-Q1 Efficiency, VOUT2
1.175
1.836
Conditions:
VOUT1=1.15V, VOUT2=1.2V @ 1000mA
TA=85OC
Conditions:
VOUT1=1.8V, VOUT2=1.2V @ 600mA
TA=85OC
VIN=2.7V
VIN=3.3V
VIN=3.9V
VIN=4.5V
VIN=5V
VIN=2.7V
VIN=3.3V
VIN=3.9V
VIN=4.5V
VIN=5V
1.171
1.167
1.163
1.159
1.155
1.151
1.147
1.143
1.139
1.135
1.131
1.127
1.828
1.82
1.812
1.804
1.796
1.788
1.78
VIN=5.5V
VIN=6V
VIN=5.5V
VIN=6V
1.772
1.764
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95
Output 1 Current [A]
1
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95
Output 1 Current [A]
1
VOUT1 = 1.15 V, VOUT2 = 1.2 V
MODE/DATA = high
VOUT1 = 1.8 V, VOUT2 = 1.2 V
MODE/DATA = high
图9-10. TPS62422-Q1 VOUT1 vs. IOUT1
图9-11. TPS62422-Q1 VOUT1 vs. IOUT1
1.224
Conditions:
VOUT2=1.2V, VOUT1=1.8V @ 1000mA
TA=85OC
VIN=2.7V
VIN=3.3V
VIN=3.9V
VIN=4.5V
VIN=5V
1.22
1.216
1.212
1.208
1.204
1.2
VO = 1.8 V 20 mV/div
VIN=5.5V
VIN=6V
1.196
1.192
1.188
1.184
1.18
Inductor current = 100 mA/div
1.176
0.3
0.35
0.4
0.45
Output 2 Current [A]
0.5
0.55
0.6
VOUT1 = 1.8 V, VOUT2 = 1.2 V
MODE/DATA = high
Time base - 10 µs/div
Power save mode MODE/DATA = low
IOUT = 10 mA
图9-12. TPS62422-Q1 VOUT2 vs. IOUT2
图9-13. Light-Load Output-Voltage Ripple in
Power-Save Mode
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VO ripple 20 mV/div
VO = 1.8 V 20 mV/div
Inductor current 100 mA/div
Inductor current 200 mA/div
Time base - 400 ns/div
Time base - 200 ns/div
Forced PWM mode MODE/DATA = high
IOUT = 10 mA
PWM mode
VOUT = 1.8 V
IOUT = 400 mA
图9-14. Output-Voltage Ripple in Forced-PWM
图9-15. Output-Voltage Ripple in PWM Mode
Mode
VO = 1.575 V
50 mV/div
MODE/DATA 1 V/div
Forced PWM
Mode
Enable Power Save Mode
Entering PFM Mode
Voltage positioning in PFM
PWM Mode operation
Voltage positioning active
Mode reduces voltage drop
during load step
VO 20 mV/div
IO = 200 mA/div
IO(1) = 360 mA
IO = 40 mA
Time base - 200 µs/div
Time base - 50 µs/div
VOUT = 1.8 V
IOUT = 20 mA
MODE/DATA = low
图9-16. Forced PWM-to-PFM Mode Transition
图9-17. Load-Transient Response, PFM-to-PWM
VO = 1.575 V
VDD = 1 V/div
50 mV/div
PWM Mode operation
IO = 200 mA/div
IO(1) = 360 mA
VO = 50 mV/div
IO = 40 mA
Time base - 400 µs/div
Time base - 50 µs/div
MODE/DATA = low
IOUT1 = 200 mA
VIN = 3.6 to 4.6 V
VOUT1 = 1.575 V
PWM mode
MODE/DATA = high
图9-18. Load-Transient Response, PWM Operation
图9-19. Line-Transient Response
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EN1 and EN2 5 V/div
VO(1)
500 mV/div
SW1 1 V/div
I(coil) 500 mA/div
Time base - 200 µs/div
VIN = 3.8 V
IOUT1max = 400 mA
图9-20. Startup Timing, One Converter
9.3 System Examples
TPS62406-Q1
VIN = 2.5 to 6 V
FB1
VIN
2.2 µH
V
= 1.125 V
OUT1
1000 mA
10 µF
SW1
22 µF
DEF_1
EN1
EN2
2.2 µH
V
= 1.2 V
OUT2
400 mA
SW2
MODE/
DATA
22 µF
ADJ2
GND
图9-21. TPS62406-Q1 Fixed 1.125-V and 1.2-V Outputs
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TPS62407-Q1
VIN = 2.5 to 6 V
VIN
FB1
2.2 µH
V
= 1.225 V
OUT1
400 mA
10 µF
SW1
10 µF
DEF_1
EN1
EN2
2.2 µH
V
= 1.85 V
OUT2
600 mA
SW2
MODE/
DATA
10 µF
ADJ2
GND
图9-22. TPS62407-Q1 Fixed 1.225-V and 1.85-V Outputs
TPS62422-Q1
VIN = 2.5 to 6 V
VIN
FB1
2.2 µH
VOUT1 = 1.15 V
up to 1000 mA
10 µF
SW1
DEF_1
SW2
22 µF
EN1
EN2
2.2 µH
VOUT2 = 1.2 V
up to 600 mA
MODE/
DATA
22 µF
ADJ2
GND
图9-23. TPS62422-Q1 Fixed 1.15-V and 1.2-V Outputs
VOUT1 = 1.8V
up to 1000mA
22 µF
VOUT2 = 1.2V
up to 600mA
22 µF
图9-24. TPS62422-Q1 Fixed 1.8-V and 1.2-V Outputs
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10 Power Supply Recommendations
This device has no special recommendation for the power supply. TI recommends to use the values listed in the
节7.3 table.
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TPS62406-Q1, TPS62407-Q1, TPS62422-Q1, TPS62423-Q1, TPS62424-Q1
ZHCSHZ2E –DECEMBER 2014 –REVISED MARCH 2022
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
• As for all switching power supplies, the layout is an important step in the design. Proper function of the device
demands careful attention to PCB layout.
• It is critical to provide a low-inductance, low-impedance ground path. Therefore, use wide and short traces for
the main current paths as indicated in bold in 图11-1.
• Place the input capacitor as close as possible to the IC pins VIN and GND, the inductor and output capacitor
as close as possible to the pins SW1 and GND.
• Connect the GND pin of the device to the PowerPAD of the PCB and use this pad as a star point. For each
converter, use a common power GND node and a different node for the signal GND to minimize the effects of
ground noise.
• Connect these ground nodes together to the PowerPAD (star point) underneath the IC. Keep the common
path to the GND PIN, which returns the small signal components and the high current of the output
capacitors, as short as possible to avoid ground noise.
• Connect the output voltage-sense lines (FB 1, DEF_1, ADJ2) right to the output capacitor and route them
away from noisy components and traces (for example, the SW1 and SW2 lines).
• If operating the EasyScale interface with high transmission rates, route the MODE/DATA trace away from the
ADJ2 line to avoid capacitive coupling into the ADJ2 pin.
• A GND guard ring between the MODE/DATA pin and ADJ2 pin avoids potential noise coupling.
11.2 Layout Example
COUT
VIN
COUT
GND
图11-1. Layout Diagram
Copyright © 2022 Texas Instruments Incorporated
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www.ti.com.cn
ZHCSHZ2E –DECEMBER 2014 –REVISED MARCH 2022
12 Device and Documentation Support
12.1 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 Trademarks
EasyScale™, the EasyScale™, and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2022 Texas Instruments Incorporated
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ZHCSHZ2E –DECEMBER 2014 –REVISED MARCH 2022
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Mar-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS62406QDRCRQ1
TPS62407QDRCRQ1
TPS62422QDRCRQ1
TPS62423QDRCRQ1
TPS62424QDRCRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSON
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
DRC
10
10
10
10
10
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2406Q
NIPDAU
SHU
NIPDAUAG
NIPDAUAG
NIPDAUAG
2422Q
2423Q
2424Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Mar-2022
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS62406QDRCRQ1
TPS62407QDRCRQ1
TPS62422QDRCRQ1
TPS62423QDRCRQ1
TPS62424QDRCRQ1
VSON
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
DRC
10
10
10
10
10
3000
3000
3000
3000
3000
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS62406QDRCRQ1
TPS62407QDRCRQ1
TPS62422QDRCRQ1
TPS62423QDRCRQ1
TPS62424QDRCRQ1
VSON
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
DRC
10
10
10
10
10
3000
3000
3000
3000
3000
346.0
346.0
338.0
338.0
338.0
346.0
346.0
355.0
355.0
355.0
33.0
33.0
50.0
50.0
50.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
www.ti.com
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED
THERMAL PAD
4X (0.25)
5
6
2X
2
11
SYMM
2.4 0.1
10
1
8X 0.5
0.30
0.18
10X
SYMM
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
0.5
0.3
10X
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
(3.4)
SYMM
(0.95)
8X (0.5)
6
5
(R0.05) TYP
(
0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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