TPS6283810YFPT [TI]
采用 1.2mm x 0.8mm WCSP 封装的 2.4V 至 5.5V 输入、6 引脚 3A 微型降压转换器 | YFP | 6 | -40 to 125;
| 型号： | TPS6283810YFPT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 1.2mm x 0.8mm WCSP 封装的 2.4V 至 5.5V 输入、6 引脚 3A 微型降压转换器 | YFP | 6 | -40 to 125 转换器 |
| 文件： | 总25页 (文件大小：1849K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS6283810
ZHCSJ57 –DECEMBER 2018
采用 1.2mm x 0.8mm WCSP 封装的 TPS6283810 小型 6 引脚 3A 降压转
换器
1 特性
3 说明
1
•
•
•
•
•
•
•
•
•
•
•
•
•
DCS-Control™拓扑
该器件是一款高频同步降压转换器，经优化具有小解决
方案尺寸和高效率等特性。该器件的输入电压范围为
2.4V 至 5.5V，支持常用电池技术。该转换器在中等程
度的负载到高负载时运行于脉宽调制 (PWM) 模式，并
在轻负载时自动进入省电模式运行，从而在整个负载电
流范围内保持高效率。该器件的开关频率为 3.5MHz，
因此能够使用小型外部组件。凭借其所有的 DCS-
control 架构，可实现出色的负载瞬态性能和输出电压
调节精度。其他 特性 还具有过流保护、热关断保护、
有源输出放电和电源良好指示等其他特性。该器件采用
6 引脚 WCSP 封装。
1V 固定输出电压，精度为 1%
26mΩ 和 26mΩ 内部功率 MOSFET
2.4V 至 5.5V 输入电压范围
4μA 运行静态电流
3.5MHz 开关频率
可在轻载条件下实现高效率的省电模式
有源输出放电
电源正常输出
热关断保护
断续短路保护
采用 0.8mm x 1.2mm x 0.5mm 6 引脚 WCSP 封装
使用 TPS6283810 并借助 WEBENCH® 电源设计
器创建定制设计方案
器件信息(1)
器件型号
封装
封装尺寸（标称值）
TPS6283810
YFP (6)
1.2mm x 0.8mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
2 应用
•
•
•
•
消费类无线模块
可穿戴产品
智能手机
光学模块
空白
典型应用原理图
效率
VIN
2.4 V to 5.5 V
VOUT
1.0 V
TPS6283810
L1
0.24 µH
100
95
90
85
80
75
70
VIN
SW
FB
C1
4.7 µF
C2
10 µF
C3
10 µF
R3
100 kꢀ
EN
VPG
PG GND
Copyright Ú 2018, Texas Instruments Incorporated
65
VIN = 2.5V
VIN = 3.3V
60
VIN = 4.2V
VIN = 5.0V
50
55
100m
1m
10m
Load (A)
100m
1
3
D003
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEX7
TPS6283810
ZHCSJ57 –DECEMBER 2018
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
8
9
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application ................................................. 10
Power Supply Recommendations...................... 15
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 ELECTRICAL CHARACTERISTICS........................ 4
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 7
7.4 Device Functional Modes.......................................... 9
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 15
10.3 Thermal Considerations........................................ 15
11 器件和文档支持 ..................................................... 16
11.1 器件支持................................................................ 16
11.2 文档支持................................................................ 16
11.3 社区资源................................................................ 16
11.4 商标....................................................................... 16
11.5 静电放电警告......................................................... 16
11.6 术语表 ................................................................... 16
12 机械、封装和可订购信息....................................... 17
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
2018 年 12 月
*
最初发布版本
2
Copyright © 2018, Texas Instruments Incorporated
TPS6283810
www.ti.com.cn
ZHCSJ57 –DECEMBER 2018
5 Pin Configuration and Functions
YFP Package
Top View
YFP Package
Bottom View
1
2
1
2
A
B
C
EN
VIN
C
B
A
FB
GND
PG
FB
SW
PG
EN
SW
GND
VIN
Not to scale
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Device enable pin. To enable the device, this pin needs to be pulled high. Pulling this pin low
disables the device. Do not leave floating.
EN
A1
I
O
I
Power good open drain output pin. The pull-up resistor can be connected to voltages up to
5.5 V. If unused, leave it floating.
PG
FB
B1
C1
Feedback pin. For the fixed output voltage versions, this pin must be connected to the
output.
GND
SW
C2
B2
A2
Ground pin.
PWR
PWR
Switch pin of the power stage.
Input voltage pin.
VIN
Copyright © 2018, Texas Instruments Incorporated
3
TPS6283810
ZHCSJ57 –DECEMBER 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
–0.3
–0.3
-1.0
-2.5
–40
–65
MAX
6
UNIT
V
VIN, FB, EN, PG
SW (DC)
Voltage at Pins(2)
VIN + 0.3
VIN + 0.3
10
SW (DC, in current limit)
SW (AC, less than 10ns)(3)
Operating Junction, TJ
150
°C
Temperature
Storage, Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) While switching
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN NOM
2.4
MAX UNIT
VIN
Input voltage range
Output voltage range
Output current range(1)
5.5
4
V
V
VOUT
IOUT
0.6
0
3
A
ISINK_PG Sink current at PG pin
1
mA
V
VPG
TJ
Pull-up resistor voltage
5.5
125
Operating junction temperature
–40
°C
(1) Lifetime is reduced when operating continuously at IOUT = 3 A and the junction temperature ≥ 105 °C.
6.4 Thermal Information
TPS6283810
YFP (6-PINS), JEDEC
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
141.3
1.7
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
47.3
0.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
47.5
n/a
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 ELECTRICAL CHARACTERISTICS
TJ = -40 °C to 125 °C, and VIN = 2.4 V to 5.5 V. Typical values are at TJ = 25 °C and VIN = 5 V , unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY
IQ
Quiescent current
Shutdown current
EN = High, no load, device not switching
4
10
µA
µA
ISD
EN = Low, TJ = -40℃ to 85℃
0.05
0.5
4
Copyright © 2018, Texas Instruments Incorporated
TPS6283810
www.ti.com.cn
ZHCSJ57 –DECEMBER 2018
ELECTRICAL CHARACTERISTICS (continued)
TJ = -40 °C to 125 °C, and VIN = 2.4 V to 5.5 V. Typical values are at TJ = 25 °C and VIN = 5 V , unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
2.2
MAX UNIT
Under voltage lock out threshold
Under voltage lock out hysteresis
Thermal shutdown threshold
Thermal shutdown hysteresis
VIN falling
VIN rising
TJ rising
TJ falling
2.1
2.3
V
VUVLO
160
150
20
mV
°C
°C
TJSD
LOGIC INTERFACE EN
VIH
VIL
High-level threshold voltage
Low-level threshold voltage
1.0
V
V
0.4
0.1
IEN,LKG Input leakage current into EN pin
0.01
µA
SOFT START, POWER GOOD
tSS
Soft start time
Time from EN high to 95% of VOUT nominal
VPG rising, VFB referenced to VOUT nominal
VPG falling, VFB referenced to VOUT nominal
VPG rising, VFB referenced to VOUT nominal
VPG falling, VFB referenced to VOUT nominal
Isink = 1 mA
1.25
96
ms
%
%
%
%
V
94
90
98
94
Power good lower threshold
92
VPG
103
108
105
110
107
112
0.4
0.1
Power good upper threshold
VPG,OL Low-level output voltage
IPG,LKG Input leakage current into PG pin
OUTPUT
VPG = 5.0 V
0.01
µA
VOUT
RFB
IDIS
Output voltage accuracy
TPS6283810, PWM mode
VSW = 0.4V; EN = LOW
0.990
75
1.0 1.010
V
Internal resistor divider connected to FB
pin
7.5
MΩ
mA
Output discharge current
400
POWER SWITCH
High-side FET on-resistance
26
26
mΩ
mΩ
A
RDS(on)
Low-side FET on-resistance
High-side FET switch current limit
PWM switching frequency
ILIM
fSW
3.6
4.3
3.5
5.0
IOUT = 1 A, VOUT = 1.0 V
MHz
版权 © 2018, Texas Instruments Incorporated
5
TPS6283810
ZHCSJ57 –DECEMBER 2018
www.ti.com.cn
6.6 Typical Characteristics
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
70.0
60.0
50.0
40.0
30.0
20.0
TJ = 0 °C
TJ = 0 °C
TJ = 25 °C
TJ = 85 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
10.0
TJ = 125 °C
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Input Voltage (V)
Input Voltage (V)
D011
D010
图 2. Low-Side FET On-Resistance
图 1. High-Side FET On-Resistance
8.0
6.0
4.0
2.0
0.0
0.5
0.4
0.3
0.2
0.1
0.0
TJ = -40 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
TJ = -40 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Input Voltage (V)
Input Voltage (V)
D001
D000
图 3. Quiescent Current
图 4. Shutdown Current
6
版权 © 2018, Texas Instruments Incorporated
TPS6283810
www.ti.com.cn
ZHCSJ57 –DECEMBER 2018
7 Detailed Description
7.1 Overview
The synchronous step-down converter adopts a DCS-Control (Direct Control with Seamless transition into Power
Save Mode) topology. This is an advanced regulation topology that combines the advantages of hysteretic,
voltage, and current mode control schemes.
The DCS-Control topology operates in PWM (pulse width modulation) mode for medium to heavy load conditions
and in Power Save Mode at light load currents. In PWM mode, the converter operates with its nominal switching
frequency of 3.5 MHz, having a controlled frequency variation over the input voltage range. As the load current
decreases, the converter enters Power Save Mode, reducing the switching frequency and minimizing the IC
current consumption to achieve high efficiency over the entire load current range. Because DCS-Control supports
both operation modes (PWM and PFM) within a single building block, the transition from PWM mode to Power
Save Mode is seamless and without effects on the output voltage. The devices offer both excellent DC voltage
and superior load transient regulation, combined with very low output voltage ripple, minimizing interference with
RF circuits.
7.2 Functional Block Diagram
PG
VIN
VPG_H
+
œ
VFB
Control Logic
VREF
+
VPG_L
GND
EN
œ
UVLO
Thermal Shutdown
Startup
Peak Current Detect
HICCUP
VSW
VIN
TON
Direct Control
&
VSW
Compensation
SW
Gate
Drive
Modulator
VREF
+
EA
_
Comparator
FB
Zero Current Detect
GND
Fixed VOUT
GND
7.3 Feature Description
7.3.1 Power Save Mode
As the load current decreases, the device enters Power Save Mode (PSM) operation. The power save mode
occurs when the inductor current becomes discontinuous. PSM is based on a fixed on-time architecture and the
switching frequency in PSM is reduced, as related in 公式 1.
版权 © 2018, Texas Instruments Incorporated
7
TPS6283810
ZHCSJ57 –DECEMBER 2018
www.ti.com.cn
Feature Description (接下页)
VOUT
tON = 250ns ì
V
IN
2 ìIOUT
fPSM
=
V
V
- VOUT
tO2 N
ì
ì
IN
IN
VOUT
L
(1)
In Power Save Mode, the output voltage rises slightly above the nominal output voltage. This effect is minimized
by increasing the output capacitor or inductor value.
When the device operates close to 100% duty cycle mode, the device can't enter Power Save Mode regardless
of the load current if the input voltage decreases to typically 10% above the output voltage. The device maintains
output regulation in PWM mode.
7.3.2 100% Duty Cycle Low Dropout Operation
The devices offer low input-to-output voltage difference by entering 100% duty cycle mode. In this mode, the
high-side MOSFET switch is constantly turned on and the low-side MOSFET is switched off. This is particularly
useful in battery powered applications to achieve the longest operation time by taking full advantage of the whole
battery voltage range. The minimum input voltage to maintain output regulation, depending on the load current
and output voltage can be calculated as:
V
= VOUT + IOUT,MAX ´(RDS(on) + RL )
IN,MIN
where
•
•
•
•
VIN,MIN = Minimum input voltage to maintain an output voltage
IOUT,MAX = Maximum output current
RDS(on) = High-side FET ON-resistance
RL = Inductor ohmic resistance (DCR)
(2)
7.3.3 Soft Start
After enabling the device, there is a 250-µs delay before switching starts. Then, an internal soft startup circuitry
ramps up the output voltage which reaches nominal output voltage during the startup time of 1 ms. This avoids
excessive inrush current and creates a smooth output voltage rise slope. It also prevents excessive voltage
drops of primary cells and rechargeable batteries with high internal impedance.
The device is able to start into a pre-biased output capacitor. It starts with the applied bias voltage and ramps the
output voltage to its nominal value.
7.3.4 Switch Current Limit and HICCUP Short-Circuit Protection
The switch current limit prevents the device from high inductor current and from drawing excessive current from
the battery or input voltage rail. Excessive current might occur with a shorted or saturated inductor or a heavy
load or shorted output circuit condition. If the inductor current reaches the threshold ILIM, the high-side MOSFET
is turned off and the low-side MOSFET remains off, while the inductor current flows through its body diode and
quickly ramps down.
When this switch current limits is triggered 32 times, the device stops switching. The device then automatically
starts a new start-up after a typical delay time of 128 µs has passed. This is named HICCUP short-circuit
protection. The device repeats this mode until the high load condition disappears.
7.3.5 Undervoltage Lockout
To avoid mis-operation of the device at low input voltages, under voltage lockout is implemented that shuts down
the device at voltages lower than VUVLO
.
8
版权 © 2018, Texas Instruments Incorporated
TPS6283810
www.ti.com.cn
ZHCSJ57 –DECEMBER 2018
Feature Description (接下页)
7.3.6 Thermal Shutdown
The device goes into thermal shutdown and stops the power stage switching when the junction temperature
exceeds TJSD. When the device temperature falls below the threshold by 20°C, the device returns to normal
operation automatically by switching the power stage again.
7.4 Device Functional Modes
7.4.1 Enable and Disable
The device is enabled by setting the EN pin to a logic High. Accordingly, shutdown mode is forced if the EN pin
is pulled Low with a shutdown current of typically 50 nA. In shutdown mode, the internal power switches as well
as the entire control circuitry are turned off. An internal switch smoothly discharges the output through the SW
pin in shutdown mode. Do not leave the EN pin floating.
The typical threshold value of the EN pin is 0.89 V for rising input signal, and 0.62 V for falling input signal.
7.4.2 Power Good
The device has a power good output. The PG pin goes high impedance once the FB pin voltage is above 96%
and less than 105% of the nominal voltage, and is driven low once the voltage falls below typically 92% or higher
than 110% of the nominal voltage. The PG pin is an open-drain output and is specified to sink up to 1 mA. The
power good output requires a pull-up resistor connecting to any voltage rail less than 5.5 V. The PG signal can
be used for sequencing of multiple rails by connecting it to the EN pin of other converters. Leave the PG pin
unconnected when not used.
The PG rising edge has a 100-µs blanking time and the PG falling edge has a deglitch delay of 20 µs.
表 1. PG Pin Logic
LOGIC STATUS
DEVICE CONDITIONS
HIGH IMPEDANCE
LOW
EN = High, VFB ≥ 96% of Nominal Value
EN = High, VFB ≤ 92% of Nominal Value
EN = High, VFB ≤ 105% of Nominal Value
EN = High, VFB ≥ 110% of Nominal Value
EN = Low
√
√
Enable
√
√
√
√
√
Shutdown
Thermal Shutdown
UVLO
TJ > TJSD
0.7 V < VIN < VUVLO
Power Supply Removal
VIN < 0.7 V
√
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9
TPS6283810
ZHCSJ57 –DECEMBER 2018
www.ti.com.cn
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The following section discusses the design of the external components to complete the power supply design for
several input and output voltage options by using typical applications as a reference.
8.2 Typical Application
VIN
VOUT
1.0 V
TPS6283810
L1
0.24 µH
2.4 V to 5.5 V
VIN
SW
FB
C1
4.7 µF
C2
10 µF
C3
10 µF
R3
100 kꢀ
EN
VPG
PG GND
Copyright Ú 2018, Texas Instruments Incorporated
图 5. Typical Application of Fixed Output
8.2.1 Design Requirements
For this design example, use the parameters listed in 表 2 as the input parameters.
表 2. Design Parameters
DESIGN PARAMETER
Input voltage
EXAMPLE VALUE
2.4 V to 5.5 V
1.0 V
Output voltage
Maximum peak output current
3 A
表 3 lists the components used for the example.
表 3. List of Components of 图 5
REFERENCE
DESCRIPTION
MANUFACTURER(1)
Taiyo Yuden
Murata
C1
C2, C3
L1
4.7 µF, Ceramic capacitor, 6.3 V, X7R, size 0603, JMK107BB7475MA
10 µF, Ceramic capacitor, 10 V, X7R, size 0603, GRM188Z71A106MA73D
0.24 µH, Power Inductor, size 0603, DFE160810S-R24M (DFE18SANR24MG0)
100 kΩ, Chip resistor, 1/16 W, 1%, size 0603
Murata
R3
Std
(1) See Third-party Products disclaimer.
表 4. List of Components of 图 5, Smallest Solution
REFERENCE
DESCRIPTION
MANUFACTURER(1)
C1, C2, C3
10 µF, Ceramic capacitor, 6.3 V, X5R, size 0402, GRM155R60J106ME47
0.24 µH, Power Inductor, size 0603, DFE160810S-R24M (DFE18SANR24MG0)
100 kΩ, Chip resistor, 1/16 W, size 0402
Murata
Murata
Std
L1
R3
(1) See Third-party Products disclaimer.
10
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TPS6283810
www.ti.com.cn
ZHCSJ57 –DECEMBER 2018
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Filter Design
The inductor and the output capacitor together provide a low-pass filter. To simplify this process, 表 5 outlines
possible inductor and capacitor value combinations for most applications. Checked cells represent combinations
that are proven for stability by simulation and lab test. Further combinations should be checked for each
individual application.
表 5. Matrix of Output Capacitor and Inductor Combinations
NOMINAL COUT [µF](2)
NOMINAL L [µH](1)
10
+
2 x 10 or 1 x 22
47
+
100
(3)
0.24
0.33
0.47
+
+
+
+
(1) Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and –30%.
(2) Capacitance tolerance and bias voltage derating is anticipated. The effective capacitance can vary by 20% and –50%.
(3) This LC combination is the standard value and recommended for most applications.
8.2.2.3 Inductor Selection
The main parameter for the inductor selection is the inductor value and then the saturation current of the
inductor. To calculate the maximum inductor current under static load conditions, 公式 3 is given.
DIL
IL,MAX = IOUT,MAX
+
2
VOUT
1-
V
IN
DIL = VOUT
´
L ´ fSW
where
•
•
•
•
IOUT,MAX = Maximum output current
ΔIL = Inductor current ripple
fSW = Switching frequency
L = Inductor value
(3)
It is recommended to choose a saturation current for the inductor that is approximately 20% to 30% higher than
IL,MAX. In addition, DC resistance and size should also be taken into account when selecting an appropriate
inductor. 表 6 lists recommended inductors.
版权 © 2018, Texas Instruments Incorporated
11
TPS6283810
ZHCSJ57 –DECEMBER 2018
www.ti.com.cn
表 6. List of Recommended Inductors(1)
Inductance
Dimensions
Current Rating [A]
DC Resistance [mΩ]
[L x W x H mm]
Part Number
[µH]
Murata, DFE160810S-R24M
(DFE18SANR24MG0)
0.24
4.9
1.6 x 0.8 x 1.0
30
0.24
0.24
0.25
0.24
0.24
6.5
4.9
9.7
3.5
3.5
2.0 x 1.2 x 1.0
1.6 x 0.8 x 0.8
4.0 x 4.0 x 1.2
2.0 x 1.6 x 0.6
2.0 x 1.6 x 0.6
25
22
Murata, DFE201210U-R24M
Cyntec, HTEH16080H-R24MSR
Coilcraft, XFL4012-251ME
7.64
35
Wurth Electronics, 74479977124
Sunlord, MPM201606SR24M
35
(1) See Third-party Products disclaimer.
8.2.2.4 Capacitor Selection
The input capacitor is the low-impedance energy source for the converters which helps to provide stable
operation. A low ESR multilayer ceramic capacitor is recommended for best filtering and must be placed between
VIN and GND as close as possible to those pins. For most applications, 4.7 μF is sufficient, though a larger value
reduces input current ripple.
The architecture of the device allows the use of tiny ceramic output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low
resistance up to high frequencies and to get narrow capacitance variation with temperature, TI recommends
using X7R or X5R dielectrics. The recommended typical output capacitor value is 2 x 10 μF or 1 x 22 µF; this
capacitance can vary over a wide range as outline in the output filter selection table.
8.2.3 Application Curves
VIN = 5.0 V, VOUT = 1.0 V, TA = 25 ºC, BOM = 表 3, unless otherwise noted.
100
95
90
85
80
75
70
65
60
55
50
1.011
1.008
1.005
1.002
0.999
0.996
0.993
0.990
VIN = 2.5V
VIN = 3.3V
VIN = 4.2V
VIN = 5.0V
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
100m
1m
10m
Load (A)
100m
1
3
100m
1m
10m
Load (A)
100m
1
3
D003
D031
VOUT = 1.0 V
VOUT = 1.0 V
图 6. Efficiency
图 7. Load Regulation
12
版权 © 2018, Texas Instruments Incorporated
TPS6283810
www.ti.com.cn
ZHCSJ57 –DECEMBER 2018
VIN = 5.0 V, VOUT = 1.0 V, TA = 25 ºC, BOM = 表 3, unless otherwise noted.
5.0
ICOIL
1A/DIV
4.0
3.0
2.0
1.0
0.0
VOUT
10mV/DIV
AC
VSW
5V/DIV
VIN = 2.5V
VIN = 3.3V
VIN = 4.2V
VIN = 5.0V
Time - 200ns/DIV
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Load (A)
D013
D008
IOUT = 3.0 A
VOUT = 1.0 V
图 9. PWM Operation
图 8. Switching Frequency
VEN
5V/DIV
ICOIL
1A/DIV
VPG
5V/DIV
VOUT
10mV/DIV
AC
VOUT
1V/DIV
VSW
5V/DIV
ICOIL
0.5A/DIV
Time - 1ꢀs/DIV
Time - 200ꢀs/DIV
D014
D015
IOUT = 50 mA
No Load
图 11. Startup and Shutdown with No-Load
图 10. PSM Operation
VPG
5V/DIV
VEN
5V/DIV
VPG
5V/DIV
ILOAD
2A/DIV
VOUT
1V/DIV
VOUT
50mV/DIV
AC
ICOIL
2A/DIV
Time - 200ꢀs/DIV
Time - 10ꢀs/DIV
D016
D017
IOUT = 3.0 A
图 12. Startup and Shutdown with Load
IOUT = 0.1 A to 3 A
图 13. Load Transient
版权 © 2018, Texas Instruments Incorporated
13
TPS6283810
ZHCSJ57 –DECEMBER 2018
www.ti.com.cn
VIN = 5.0 V, VOUT = 1.0 V, TA = 25 ºC, BOM = 表 3, unless otherwise noted.
VPG
5V/DIV
ICOIL
2A/DIV
VOUT
0.5V/DIV
Time - 100ꢀs/DIV
D018
IOUT = 3 A
图 14. HICCUP Short Circuit Protection
14
版权 © 2018, Texas Instruments Incorporated
TPS6283810
www.ti.com.cn
ZHCSJ57 –DECEMBER 2018
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 2.4 V to 5.5 V. Ensure that the input
power supply has a sufficient current rating for the application.
10 Layout
10.1 Layout Guidelines
The printed-circuit-board (PCB) layout is an important step to maintain the high performance of the device. See
and 图 15 for the recommended PCB layout.
•
The input/output capacitors and the inductor should be placed as close as possible to the IC. This keeps the
power traces short. Routing these power traces direct and wide results in low trace resistance and low
parasitic inductance.
•
•
The low side of the input and output capacitors must be connected properly to the power GND to avoid a
GND potential shift.
The sense traces connected to FB is a signal trace. Special care should be taken to avoid noise being
induced. Keep these traces away from SW nodes. The connection of the output voltage trace for the FB
resistors should be made at the output capacitor.
•
Refer to and 图 15 for an example of component placement, routing and thermal design.
10.2 Layout Example
图 15. PCB Layout of Fixed Output Voltage Application
10.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power
dissipation limits of a given component.
Two basic approaches for enhancing thermal performance are:
•
•
Improving the power dissipation capability of the PCB design
Introducing airflow in the system
For more details on how to use the thermal parameters, see the Thermal Characteristics Application Notes,
SZZA017 and SPRA953.
版权 © 2018, Texas Instruments Incorporated
15
TPS6283810
ZHCSJ57 –DECEMBER 2018
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.2 文档支持
11.2.1 开发支持
11.2.1.1 使用 WEBENCH® 工具创建定制设计
单击此处，使用该器件并借助 WEBENCH® 电源设计器创建定制设计方案。
1. 首先输入输入电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化该设计的关键参数，如效率、尺寸和成本。
3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。
WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案以常用 CAD 格式导出
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。
11.2.2 相关文档
请参阅如下相关文档：
•
•
《热工特性应用手册》，SZZA017
《热工特性应用手册》，SPRA953
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
DCS-Control, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
16
版权 © 2018, Texas Instruments Incorporated
TPS6283810
www.ti.com.cn
ZHCSJ57 –DECEMBER 2018
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
版权 © 2018, Texas Instruments Incorporated
17
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS6283810YFPR
TPS6283810YFPT
ACTIVE
ACTIVE
DSBGA
DSBGA
YFP
YFP
6
6
3000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
1DU
1DU
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Feb-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS6283810YFPR
TPS6283810YFPT
DSBGA
DSBGA
YFP
YFP
6
6
3000
250
180.0
180.0
8.4
8.4
0.9
0.9
1.3
1.3
0.62
0.62
4.0
4.0
8.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Feb-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS6283810YFPR
TPS6283810YFPT
DSBGA
DSBGA
YFP
YFP
6
6
3000
250
182.0
182.0
182.0
182.0
20.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
YFP0006
DSBGA - 0.5 mm max height
S
C
A
L
E
1
0
.
0
0
0
DIE SIZE BALL GRID ARRAY
B
E
A
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.05 C
0.19
0.13
BALL TYP
0.4
TYP
SYMM
C
B
D: Max = 1.19 mm, Min = 1.13 mm
E: Max = 0.79 mm, Min = 0.73 mm
0.8
SYMM
TYP
0.4 TYP
A
0.25
0.21
C A B
6X
0.015
1
2
4223410/A 11/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFP0006
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
6X ( 0.23)
2
1
A
B
(0.4) TYP
SYMM
C
SYMM
LAND PATTERN EXAMPLE
SCALE:50X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
(
0.23)
METAL
(
0.23)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4223410/A 11/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFP0006
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
6X ( 0.25)
1
2
A
B
(0.4) TYP
SYMM
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:50X
4223410/A 11/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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