TPS628503DRLR [TI]
采用 SOT-583 封装的 2.7V 至 6V、3A 可调频率降压转换器 | DRL | 8 | -40 to 150;
| 型号： | TPS628503DRLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 SOT-583 封装的 2.7V 至 6V、3A 可调频率降压转换器 | DRL | 8 | -40 to 150 转换器 |
| 文件： | 总40页 (文件大小：3144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS628501, TPS628502, TPS628503
ZHCSLX5A –MARCH 2021 –REVISED JUNE 2022
TPS62850x 采用SOT583 封装的2.7V 至6V、1A/2A/3A 降压转换器
1 特性
3 说明
• 提供功能安全
TPS62850x 是一系列引脚对引脚 1A、2A（持续）和
3A（峰值）易用型高效同步降压直流/直流转换器。它
们基于峰值电流模式控制拓扑，低阻开关可支持高达
2A 的持续输出电流和 3A 的峰值电流。用户可通过外
部方式在 1.8MHz 至 4MHz 范围内调节开关频率，亦
可在该频率范围内将其同步至外部时钟。在 PWM 和
PFM 模式下，TPS62850x 会在轻负载时自动进入省电
模式， 从而在整个负载范围内保持高效率。
TPS62850x 在 PWM 模式下提供 1% 的输出电压精
度，这有助于设计具有高输出电压精度的电源，从而满
足数字处理器和FPGA 的严格电源电压要求。
– 可帮助进行功能安全系统设计的文档
• 输入电压范围：2.7V 至6V
• 输出电压范围为0.6V 至5.5V
• 反馈电压精度为1%
（整个温度范围）
• TJ = -40°C 至+150°C
• 1A、2A（持续）和3A（峰值）系列器件
• 可调开关频率及同步范围为
1.8MHz 至4MHz
• 强制PWM 或PWM 和PFM 操作
• 静态电流17µA（典型值）
• 精密使能输入可实现：
– 用户定义的欠压锁定
– 准确排序
• 100% 占空比模式
• 有源输出放电
TPS62850x 采用 8 引脚 1.6mm x 2.1mm SOT583 封
装。
器件信息
封装(1)
封装尺寸（标称值）
器件型号
TPS628501
TPS628502
TPS628503
1.60mm × 2.10 mm
• 具有窗口比较器的电源正常输出
• 有关具有可调软启动的器件选项，请参阅
TPS628511
SOT583
（包括引脚）
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
• 电机驱动器
• 工厂自动化和控制
• 楼宇自动化
• 测试和测量
• 通用POL
L
100
95
90
85
80
75
70
65
V
IN
TPS62850x
0.47mH
VOUT
2.7 V - 6 V
VIN
SW
CIN
R 1
CFF
2*10 mF
0603
COUT
EN
FB
2*10 mF
0603
MODE/SYNC
R2
R3
COMP/FSET
PG
60
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
GND
55
50
100m
简化版原理图
1m
10m 100m
Output Current (A)
1
3
效率与IOUT 间的关系，VOUT = 3.3V
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSEC8
TPS628501, TPS628502, TPS628503
ZHCSLX5A –MARCH 2021 –REVISED JUNE 2022
www.ti.com.cn
Table of Contents
9.4 Device Functional Modes..........................................13
10 Application and Implementation................................15
10.1 Application Information........................................... 15
10.2 Typical Application.................................................. 17
10.3 System Examples................................................... 27
11 Power Supply Recommendations..............................29
12 Layout...........................................................................29
12.1 Layout Guidelines................................................... 29
12.2 Layout Example...................................................... 30
13 Device and Documentation Support..........................31
13.1 Device Support....................................................... 31
13.2 接收文档更新通知................................................... 31
13.3 支持资源..................................................................31
13.4 Trademarks.............................................................31
13.5 Electrostatic Discharge Caution..............................31
13.6 术语表..................................................................... 31
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................8
8 Parameter Measurement Information............................9
8.1 Schematic................................................................... 9
9 Detailed Description......................................................10
9.1 Overview...................................................................10
9.2 Functional Block Diagram.........................................10
9.3 Feature Description...................................................10
Information.................................................................... 32
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (March 2021) to Revision A (June 2022)
Page
• Added TPS628503............................................................................................................................................. 3
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5 Device Comparison Table
DEVICE NUMBER
OUTPUT
VOUT
FOLDBACK
SPREAD SPECTRUM
CLOCKING (SSC)
SOFT START
OUTPUT
VOLTAGE
CURRENT DISCHARGE CURRENT LIMIT
TPS628501DRLR
TPS628502DRLR
1 A
2 A
ON
ON
OFF
OFF
by COMP/FSET pin
by COMP/FSET pin
internal 1 ms
internal 1 ms
adjustable
adjustable
TPS628503DRLR
3 A
ON
OFF
by COMP/FSET pin
internal 1 ms
adjustable
6 Pin Configuration and Functions
GND SW
PG
FB
1
VIN EN
图6-1. 8-Pin SOT583 DRL Package (Top View)
表6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
This is the enable pin of the device. Connect to logic low to disable the device. Pull high to
enable the device. Do not leave this pin unconnected.
EN
2
I
I
FB
5
8
Voltage feedback input. Connect the resistive output voltage divider to this pin.
Ground pin
GND
The device runs in PFM/PWM mode when this pin is pulled low. When the pin is pulled high,
the device runs in forced PWM mode. Do not leave this pin unconnected. The mode pin can
also be used to synchronize the device to an external frequency. See 节7.5 for the detailed
specification for the digital signal applied to this pin for external synchronization.
MODE/SYNC
COMP/FSET
3
I
Device compensation and frequency set input. A resistor from this pin to GND defines the
compensation of the control loop as well as the switching frequency if not externally
synchronized.
4
I
PG
6
7
O
Open-drain power-good output
SW
This is the switch pin of the converter and is connected to the internal Power MOSFETs.
Power supply input. Make sure the input capacitor is connected as close as possible
between pin VIN and GND.
VIN
1
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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–3
MAX
6.5
UNIT
V
VIN
SW (DC)
VIN + 0.3
10
Pin voltage(2)
SW (AC, less than 10 ns)(3)
COMP/FSET, PG
VIN + 0.3
6.5
–0.3
–0.3
–65
EN, MODE/SYNC, FB
Storage temperature
Tstg
150
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to the network ground terminal
(3) While switching
7.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating temperature range (unless otherwise noted)
MIN
2.7
0.6
0.32
8
NOM
MAX
6
UNIT
V
VIN
Input voltage range
VOUT
L
Output voltage range
5.5
1.2
200
V
Effective inductance
0.47
10
μH
μF
μF
kΩ
mA
A
COUT
CIN
Effective output capacitance(1)
Effective input capacitance(1)
5
10
RCF
ISINK_PG
IOUT
TJ
4.5
0
100
2
Sink current at PG pin
Output current, TPS628503(2)
0
3
Junction temperature
150
°C
–40
(1) The values given for all the capacitors in the table are effective capacitance, which includes the DC bias effect. Due to the DC bias
effect of ceramic capacitors, the effective capacitance is lower than the nominal value when a voltage is applied. Please check the
manufacturer's DC bias curves for the effective capacitance vs DC voltage applied. Further restrictions may apply. Please see the
feature description for COMP/FSET about the output capacitance vs compensation setting and output voltage.
(2) This part is designed for a 2-A continuous output current at a junction temperature of 105°C or 3-A continuous output current at a
junction temperature of 85°C; exceeding the output current or the junction temperature can significantly reduce lifetime.
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7.4 Thermal Information
DRL (JEDEC)(2)
DRL (EVM)
UNIT
THERMAL METRIC(1)
8 PINS
110
41.3
20
8 PINS
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
60
n/a
n/a
n/a
n/a
n/a
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.8
ΨJT
YJB
20
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) JEDEC standard PCB with four layers, no thermal vias
7.5 Electrical Characteristics
Over operating junction temperature range (TJ = –40°C to +150°C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ
= 25°C. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
EN = VIN, no load, device not switching,
MODE = GND, VOUT = 0.6 V
IQ
Quiescent current
17
36
48
μA
μA
μA
EN = GND, nominal value at TJ = 25°C,
maximum value at TJ = 150°C
ISD
ISD
Shutdown current
Shutdown current
1.5
EN = GND, TJ = –40°C to 85°C,
including HSFET leakage
5.5
VIN rising
VIN falling
TJ rising
TJ falling
2.45
2.1
2.6
2.5
170
15
2.7
2.6
V
V
VUVLO
Undervoltage lockout threshold
Thermal shutdown threshold
Thermal shutdown hysteresis
°C
°C
TJSD
CONTROL and INTERFACE
VEN,IH Input threshold voltage at EN, rising edge
VEN,IL
1.05
0.96
1.1
1.0
1.15
1.05
V
V
Input threshold voltage at EN, falling edge
High-level input-threshold voltage at
MODE/SYNC
VIH
1.1
V
nA
V
IEN,LKG
VIL
ILKG
tDelay
Input leakage current into EN
VIH = VIN or VIL = GND
125
0.3
Low-level input-threshold voltage at
MODE/SYNC
Input leakage current into MODE/SYNC
Enable delay time
100
520
nA
µs
Time from EN high to device starts
switching; VIN applied already
135
200
1.3
Time from EN high to device starts
switching; VIN applied already,
VIN ≥3.3 V
tDelay
Enable delay time
480
µs
Time from device starts switching to
power good; device not in current limit
tRamp
fSYNC
Output voltage ramp time
0.8
1.8
1.8
4
ms
Frequency range on MODE/SYNC pin for
synchronization
MHz
Duty cycle of synchronization signal at
MODE/SYNC
20%
80%
Time to lock to external frequency
50
µs
Resistance from COMP/FSET to GND for Internal frequency setting with
0
2.5
kΩ
logic low
f = 2.25 MHz
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7.5 Electrical Characteristics (continued)
Over operating junction temperature range (TJ = –40°C to +150°C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ
= 25°C. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Internal frequency setting with
f = 2.25 MHz
Voltage on COMP/FSET for logic high
VIN
V
UVP power-good threshold voltage;
DC level
VTH_PG
VTH_PG
Rising (%VFB
)
92%
87%
95%
90%
98%
93%
UVP power-good threshold voltage;
DC level
Falling (%VFB
)
)
OVP power-good threshold voltage;
DC level
Rising (%VFB
)
107%
104%
110%
113%
111%
VTH_PG
OVP power-good threshold voltage;
DC level
Falling (%VFB
107%
0.07
VPG,OL
IPG,LKG
Low-level output voltage at PG
Input leakage current into PG
ISINK_PG = 2 mA
VPG = 5 V
0.3
V
100
nA
For a high level to low level transition on
the power-good output
tPG
PG deglitch time
40
µs
OUTPUT
VFB
Feedback voltage, adjustable version
0.6
1
V
Input leakage current into FB, adjustable
version
IFB,LKG
VFB
VFB = 0.6 V
70
1%
2%
nA
Feedback voltage accuracy
PWM, VIN ≥VOUT + 1 V
–1%
–1%
PFM, VIN ≥VOUT + 1 V, VOUT ≥1.0 V,
VFB
Feedback voltage accuracy
C
o,eff ≥10 µF, L = 0.47 µH
PFM, VIN ≥VOUT + 1 V, VOUT < 1.0 V,
o,eff ≥15 µF, L = 0.47 µH
VFB
Feedback voltage accuracy
3%
–1%
C
Load regulation
PWM
0.05
0.02
%/A
%/V
Ω
Line regulation
PWM, IOUT = 1 A, VIN ≥VOUT + 1 V
RDIS
fSW
Output discharge resistance
100
4
MODE = high, see the FSET pin
functionality about setting the switching
frequency.
PWM switching frequency range
PWM switching frequency range
1.8
1.8
2.25
2.25
MHz
MODE = low, see the FSET pin
functionality about setting the switching
frequency.
fSW
3.5
MHz
MHz
fSW
fSW
PWM switching frequency
With COMP/FSET tied to GND or VIN
2.025
2.475
12%
50
Using a resistor from COMP/FSET to
GND
PWM switching frequency tolerance
–12%
ton,min
ton,min
Minimum on time of high-side FET
Minimum on time of low-side FET
High-side FET on-resistance
Low-side FET on-resistance
35
10
65
33
ns
ns
VIN = 3.3 V, TJ = –40°C to 125°C
120
70
3.5
44
5
VIN ≥5 V
mΩ
mΩ
µA
RDS(ON)
VIN ≥5 V
High-side MOSFET leakage current
High-side MOSFET leakage current
Low-side MOSFET leakage current
Low-side MOSFET leakage current
SW leakage
TJ = –40°C to 85°C
0.01
0.01
µA
µA
TJ = –40°C to 85°C
70
11
µA
V(SW) = 0.6 V, current into SW pin
-0.05
3.45
µA
DC value, for TPS628503;
VIN = 3 V to 6 V
ILIMH
ILIMH
High-side FET switch current limit
High-side FET switch current limit
4.5
3.4
5.1
3.9
A
A
DC value, for TPS628502;
VIN = 3 V to 6 V
2.85
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7.5 Electrical Characteristics (continued)
Over operating junction temperature range (TJ = –40°C to +150°C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ
= 25°C. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
2.6
MAX
UNIT
A
DC value, for TPS628501;
VIN = 3 V to 6 V
ILIMH
High-side FET switch current limit
Low-side FET negative current limit
2.1
3.0
ILIMNEG
DC value
A
–1.8
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7.6 Typical Characteristics
140
80
76
72
68
64
60
56
52
48
44
40
36
32
28
24
20
VIN = 2.7V
VIN = 3.3V
VIN = 5.0V
VIN = 2.7V
VIN = 3.3V
VIN = 5.0V
VIN = 6.0V
130
120
VIN = 6.0V
110
100
90
80
70
60
50
40
-40
0
25 85
Junction Temperature (°C)
125
150
-40
0
25 85
Junction Temperature (°C)
125
150
D002
D002
图7-1. RDS (ON) of High-Side Switch
图7-2. RDS (ON) of Low-Side Switch
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8 Parameter Measurement Information
8.1 Schematic
L
V
IN
TPS62850x
0.47mH
VOUT
2.7 V - 6 V
VIN
SW
CIN
2*10 mF
0603
R 1
CFF
COUT
2*10 mF
0603
EN
FB
MODE/SYNC
R2
R3
COMP/FSET
PG
GND
图8-1. Measurement Setup
表8-1. List of Components
DESCRIPTION
REFERENCE
MANUFACTURER (1)
IC
L
TPS628502
Texas Instruments
Murata
Murata
Murata
Murata
Any
0.47-µH inductor DFE252012PD
2 × 10 µF / 6.3 V GRM188D70J106MA73
CIN
COUT
COUT
RCF
CFF
R1
2 × 10 µF / 6.3 V GRM188D70J106MA73 for VOUT ≥1 V
3 × 10 µF / 6.3 V GRM188D70J106MA73 for VOUT < 1 V
8.06 kΩ
10 pF
Any
Depending on VOUT
Depending on VOUT
100 kΩ
Any
R2
Any
R3
Any
(1) See the Third-party Products Disclaimer.
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9 Detailed Description
9.1 Overview
The TPS62850x synchronous switch mode power converters are based on a peak current mode control
topology. The control loop is internally compensated.
To optimize the bandwidth of the control loop to the wide range of output capacitance that can be used with
TPS62850x, the internal compensation has two settings. See 节9.3.2. One out of the two compensation settings
is chosen either by a resistor from COMP/FSET to GND, or by the logic state of this pin. The regulation network
achieves fast and stable operation with small external components and low-ESR ceramic output capacitors. The
devices can be operated without a feedforward capacitor on the output voltage divider, however, using a typically
10-pF feedforward capacitor improves transient response.
The devices support forced fixed frequency PWM operation with the MODE pin tied to a logic high level. The
frequency is defined as either 2.25 MHz internally fixed when COMP/FSET is tied to GND or VIN, or in a range
of 1.8 MHz to 4 MHz defined by a resistor from COMP/FSET to GND. Alternatively, the devices can be
synchronized to an external clock signal in a range from 1.8 MHz to 4 MHz, applied to the MODE pin with no
need for additional passive components. An internal PLL allows the internal clock to be changed to an external
clock during operation. The synchronization to the external clock is done on a falling edge of the clock applied at
MODE to the rising edge on the SW pin. This allows a roughly 180° phase shift when the SW pin is used to
generate the synchronization signal for a second converter. When the MODE pin is set to a logic low level, the
device operates in power save mode (PFM) at low output current and automatically transfers to fixed frequency
PWM mode at higher output current. In PFM mode, the switching frequency decreases linearly based on the
load to sustain high efficiency down to very low output current.
9.2 Functional Block Diagram
VIN
SW
Bias
Regulator
Gate Drive and Control
Oscillator
Ipeak
Izero
EN
MODE/SYNC
gm
GND
FB
Device
Control
PG
+
-
Bandgap
COMP/FSET
Thermal
Shutdown
9.3 Feature Description
9.3.1 Precise Enable (EN)
The voltage applied at the enable pin of the TPS62850x is compared to a fixed threshold of 1.1 V for a rising
voltage. This allows the user to drive the pin by a slowly changing voltage and enables the use of an external RC
network to achieve a power-up delay.
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The Precise Enable input provides a user-programmable undervoltage lockout by adding a resistor divider to the
input of the Enable pin.
The enable input threshold for a falling edge is typically 100 mV lower than the rising edge threshold. The
TPS62850x starts operation when the rising threshold is exceeded. For proper operation, the enable (EN) pin
must be terminated and must not be left floating. Pulling the enable pin low forces the device into shutdown, with
a shutdown current of typically 1 μA. In this mode, the internal high-side and low-side MOSFETs are turned off
and the entire internal control circuitry is switched off.
9.3.2 COMP/FSET
This pin allows to set three different parameters:
• Internal compensation settings for the control loop (two settings available)
• The switching frequency in PWM mode from 1.8 MHz to 4 MHz
• Enable/disable spread spectrum clocking (SSC)
A resistor from COMP/FSET to GND changes the compensation as well as the switching frequency. The change
in compensation allows the user to adopt the device to different values of output capacitance. The resistor must
be placed close to the pin to keep the parasitic capacitance on the pin to a minimum. The compensation setting
is sampled at start-up of the converter, so a change in the resistor during operation only has an effect on the
switching frequency but not on the compensation.
To save external components, the pin can also be directly tied to VIN or GND to set a pre-defined setting. Do not
leave the pin floating.
The switching frequency has to be selected based on the input voltage and the output voltage to meet the
specifications for the minimum on-time and minimum off-time.
Example: VIN = 5 V, VOUT = 0.6 V --> duty cycle = 0.6 V / 5 V = 0.12
• --> ton,min = 1 / fs × 0.12
• --> fsw,max = 1 / ton,min × 0.12 = 1 / 0.05 µs × 0.12 = 2.4 MHz
The compensation range has to be chosen based on the minimum capacitance used. The capacitance can be
increased from the minimum value as given in 表 9-1, up to the maximum of 200 µF in both compensation
ranges. If the capacitance of an output changes during operation, for example, when load switches are used to
connect or disconnect parts of the circuitry, the compensation has to be chosen for the minimum capacitance on
the output. With large output capacitance, the compensation must be done based on that large capacitance to
get the best load transient response. Compensating for large output capacitance but placing less capacitance on
the output can lead to instability.
The switching frequency for the different compensation setting is determined by the following equations.
For compensation (comp) setting 1 with spread spectrum clocking (SSC) disabled:
Space
18MHz ×kW
RCF(kW) =
fS(MHz)
(1)
For compensation (comp) setting 1 with spread spectrum clocking (SSC) enabled:
Space
60MHz ×kW
RCF(kW) =
fS(MHz)
(2)
Space
For compensation (comp) setting 2 with spread spectrum clocking (SSC) disabled:
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Space
180MHz ×kW
RCF(kW) =
fS(MHz)
(3)
表9-1. Switching Frequency, Compensation and Spread Spectrum Clocking
MINIMUM
MINIMUM OUTPUT
OUTPUT
MINIMUM OUTPUT
CAPACITANCE
CAPACITANCE
RCF
COMPENSATION
SWITCHING FREQUENCY
CAPACITANCE
FOR VOUT < 1 V
FOR 1 V ≤VOUT < 3.3 V FOR VOUT ≥3.3 V
for smallest output capacitance
(comp setting 1)
1.8 MHz (10 kΩ) .. 4 MHz (4.5 kΩ)
according to 方程式1
15 µF
15 µF
10 µF
10 µF
8 µF
8 µF
10 kΩ.. 4.5 kΩ
33 kΩ.. 15 kΩ
SSC disabled
for smallest output capacitance
(comp setting 1)
1.8 MHz (33 kΩ) .. 4 MHz (15 kΩ)
according to Equation 2
SSC enabled
for best transient response
(larger output capacitance)
(comp setting 2)
1.8 MHz (100 kΩ) ..4 MHz (45 kΩ)
30 µF
15 µF
30 µF
18 µF
10 µF
18 µF
15 µF
8 µF
100 kΩ.. 45 kΩ
tied to GND
tied to VIN
according to Equation 3
SSC disabled
for smallest output capacitance
(comp setting 1)
internally fixed 2.25 MHz
internally fixed 2.25 MHz
SSC disabled
for best transient response
(larger output capacitance)
(comp setting 2)
15 µF
SSC enabled
Refer to 节10.1.3.2 for further details on the output capacitance required depending on the output voltage.
A resistor value that is too high for RCF is decoded as "tied to VIN". A value below the lowest range is decoded as
"tied to GND". The minimum output capacitance in 表9-1 is for capacitors close to the output of the device. If the
capacitance is distributed, a lower compensation setting can be required.
9.3.3 MODE / SYNC
When MODE/SYNC is set low, the device operates in PWM or PFM mode, depending on the output current. The
MODE/SYNC pin allows you to force PWM mode when set high. The pin also allows you to apply an external
clock in a frequency range from 1.8 MHz to 4 MHz for external synchronization. The specifications for the
minimum on-time and minimum off-time must be observed when setting the external frequency. For use with
external synchronization on the MODE/SYNC pin, the internal switching frequency must be set by RCF to a
similar value to the externally applied clock. This ensures that if the external clock fails, the switching frequency
stays in the same range and the compensation settings are still valid.
9.3.4 Spread Spectrum Clocking (SSC)
The device offers spread spectrum clocking as an option. When SSC is enabled, the switching frequency is
randomly changed in PWM mode when the internal clock is used. The frequency variation is typically between
the nominal switching frequency and up to 288 kHz above the nominal switching frequency. When the device is
externally synchronized by applying a clock signal to the MODE/SYNC pin, the TPS62850x follows the external
clock and the internal spread spectrum block is turned off. SSC is also disabled during soft start.
9.3.5 Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout prevents misoperation of the device by switching off both the
power FETs. When enabled, the device is fully operational for input voltages above the rising UVLO threshold
and turns off if the input voltage trips below the threshold for a falling supply voltage.
9.3.6 Power Good Output (PG)
Power good is an open-drain output that requires a pullup resistor to any voltage up to the recommended input
voltage level. It is driven by a window comparator. PG is held low when the device is disabled, in undervoltage
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lockout in thermal shutdown, and not in soft start. When the output voltage is in regulation hence, within the
window defined in the electrical characteristics, the output is high impedance.
VIN must remain present for the PG pin to stay low. If the power good output is not used, it is recommended to tie
it to GND or leave open. The PG indicator features a de-glitch, as specified in the electrical characteristics, for
the transition from "high impedance" to "low" of its output.
表9-2. PG Status
EN
X
DEVICE STATUS
PG STATE
undefined
low
VIN < 2 V
low
VIN ≥2 V
2 V ≤VIN ≤UVLO OR in thermal shutdown OR VOUT not in
high
high
low
regulation OR device in soft start
VOUT in regulation
high impedance
9.3.7 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 170°C
(typ), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and PG
goes low. When TJ decreases below the hysteresis amount of typically 15°C, the converter resumes normal
operation, beginning with soft start. During a PFM pause, the thermal shutdown is not active. After a PFM pause,
the device needs up to 9 µs to detect a junction temperature that is too high. If the PFM burst is shorter than this
delay, the device does not detect a junction temperature that is too high.
9.4 Device Functional Modes
9.4.1 Pulse Width Modulation (PWM) Operation
The TPS62850x has two operating modes: forced PWM mode is discussed in this section and PWM/PFM as
discussed in 节9.4.2.
With the MODE/SYNC pin set to high, the TPS62850x operates with pulse width modulation in continuous
conduction mode (CCM). The switching frequency is either defined by a resistor from the COMP pin to GND or
by an external clock signal applied to the MODE/SYNC pin. With an external clock applied to MODE/SYNC, the
TPS62850x follows the frequency applied to the pin. In general, the frequency range in forced PWM mode is 1.8
MHz to 4 MHz. However, the frequency needs to be in a range the TPS62850x can operate at, taking the
minimum on-time into account.
9.4.2 Power Save Mode Operation (PWM/PFM)
When the MODE/SYNC pin is low, power save mode is allowed. The device operates in PWM mode as long as
the peak inductor current is above the PFM threshold of approximately 0.8 A. When the peak inductor current
drops below the PFM threshold, the device starts to skip switching pulses. In power save mode, the switching
frequency decreases with the load current maintaining high efficiency. In addition, the frequency set with the
resistor on COMP/FSET must be in a range of 1.8 MHz to 3.5 MHz.
9.4.3 100% Duty-Cycle Operation
The duty cycle of a buck converter operated in PWM mode is given as D = VOUT / VIN. The duty cycle increases
as the input voltage comes close to the output voltage and the off-time gets smaller. When the minimum off-time
of typically 10 ns is reached, the TPS62850x skips switching cycles while it approaches 100% mode. In 100%
mode, it keeps the high-side switch on continuously. The high-side switch stays turned on as long as the output
voltage is below the target. In 100% mode, the low-side switch is turned off. The maximum dropout voltage in
100% mode is the product of the on-resistance of the high-side switch plus the series resistance of the inductor
and the load current.
9.4.4 Current Limit and Short Circuit Protection
The TPS62850x is protected against overload and short circuit events. If the inductor current exceeds the
current limit ILIMH, the high-side switch is turned off and the low-side switch is turned on to ramp down the
inductor current. The high-side switch turns on again only if the current in the low side-switch has decreased
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below the low side current limit. Due to internal propagation delay, the actual current can exceed the static
current limit. The dynamic current limit is given as:
V
L
Ipeak(typ) = ILIMH
+
×tPD
(4)
where
• ILIMH is the static current limit as specified in the Electrical Characteristics
• L is the effective inductance at the peak current
• VL is the voltage across the inductor (VIN - VOUT
)
• tPD is the internal propagation delay of typically 50 ns
The current limit can exceed static values, especially if the input voltage is high and very small inductances are
used. The dynamic high-side switch peak current can be calculated as follows:
V
IN -VOUT
Ipeak(typ) = ILIMH
+
×50ns
L
(5)
9.4.5 Foldback Current Limit and Short Circuit Protection
This is valid for devices where foldback current limit is enabled. Contact Texas Instruments for more information
on this option.
When the device detects current limit for more than 1024 subsequent switching cycles, it reduces the current
limit from its nominal value to typically 1.3 A. Foldback current limit is left when the current limit indication goes
away. If device operation continues in current limit, after 3072 switching cycles, it tries for full current limit for
1024 switching cycles.
9.4.6 Output Discharge
The purpose of the discharge function is to ensure a defined down-ramp of the output voltage when the device is
being disabled and to keep the output voltage close to 0 V when the device is off. The output discharge feature
is only active once the TPS62850x has been enabled at least once since the supply voltage was applied. The
discharge function is enabled as soon as the device is disabled, in thermal shutdown, or in undervoltage lockout.
The minimum supply voltage required for the discharge function to remain active is typically 2 V. Output
discharge is not activated during a current limit or foldback current limit event.
9.4.7 Soft Start
The internal soft-start circuitry controls the output voltage slope during start-up. This avoids excessive inrush
current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high
impedance power sources or batteries. When EN is set high to start operation, the device starts switching after a
delay of about 200 μs then the internal reference and hence VOUT rises with a slope defined by an internally
defined slope of 150 µs or 1 ms (OTP option).
9.4.8 Input Overvoltage Protection
When the input voltage exceeds the absolute maximum rating, the device is set to PFM mode so it cannot
transfer energy from the output to the input.
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10 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
10.1.1 Programming the Output Voltage
The output voltage of the TPS62850x is adjustable. It can be programmed for output voltages from 0.6 V to 5.5
V using a resistor divider from VOUT to GND. The voltage at the FB pin is regulated to 600 mV. The value of the
output voltage is set by the selection of the resistor divider from Equation 6. It is recommended to choose
resistor values that allow a current of at least 2 µA, meaning the value of R2 must not exceed 400 kΩ. Lower
resistor values are recommended for highest accuracy and the most robust design.
V
OUT
æ
ö
R1
= R
-1
FB
2 × ç
è
÷
V
ø
(6)
10.1.2 Inductor Selection
The TPS62850x family is designed for a nominal 0.47-µH inductor with a switching frequency of typically 2.25
MHz. Larger values can be used to achieve a lower inductor current ripple but they can have a negative impact
on efficiency and transient response. Smaller values than 0.47 µH cause a larger inductor current ripple, which
causes larger negative inductor current in forced PWM mode at low or no output current. For a higher or lower
nominal switching frequency, the inductance must be changed accordingly. See 节7.3 for details.
The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-to-
PFM transition point, and efficiency. In addition, the inductor selected has to be rated for appropriate saturation
current and DC resistance (DCR). Equation 7 calculates the maximum inductor current.
DIL(max)
IL(max) = IOUT(max)
+
2
(7)
(8)
V
OUT
æ
ö
V
1-
OUT × ç
÷
IN
1
V
è
Lmin
ø
DIL(max)
=
×
f
SW
where
• IL(max) is the maximum inductor current
• ΔIL(max) is the peak-to-peak inductor ripple current
• Lmin is the minimum inductance at the operating point
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表10-1. Typical Inductors
NOMINAL
SWITCHING
FREQUENCY
INDUCTANCE
[µH]
CURRENT [A]
DIMENSIONS
[LxBxH] mm
TYPE
FOR DEVICE
MANUFACTURER(2)
(1)
XFL4015-471ME
XFL4015-701ME
0.47 µH, ±20%
0.70 µH, ±20%
0.80 µH, ±20%
0.56 µH, ±20%
0.68 µH, ±20%
0.68 µH, ±20%
0.68 µH, ±20%
0.47 µH, ±20%
0.68 µH, ±20%
0.47 µH, ±20%
3.5
TPS628501 / 502
TPS628501 / 502
TPS628501 / 502
TPS628501 / 502
TPS628501 / 502
TPS628501
2.25 MHz
2.25 MHz
2.25 MHz
2.25 MHz
2.25 MHz
2.25 MHz
2.25 MHz
2.25 MHz
2.25 MHz
2.25 MHz
4 × 4 × 1.6
4 × 4 × 1.6
Coilcraft
Coilcraft
Coilcraft
Coilcraft
Coilcraft
Coilcraft
Murata
3.3
2.0
XEL3520-801ME
3.5 × 3.2 × 2.0
3.5 × 3.2 × 1.5
3.0 × 3.0 × 1.2
2 × 1.9 × 1
XEL3515-561ME
4.5
XFL3012-681ME
2.1
XPL2010-681ML
1.5
DFE252012PD-R68M
DFE252012PD-R47M
DFE201612PD-R68M
DFE201612PD-R47M
see data sheet
see data sheet
see data sheet
see data sheet
TPS628501 / 502
TPS628501 / 502
TPS628501 / 502
TPS628501 / 502
2.5 × 2 × 1.2
2.5 × 2 × 1.2
2 × 1.6 × 1.2
2 × 1.6 × 1.2
Murata
Murata
Murata
(1) Lower of IRMS at 20°C rise or ISAT at 20% drop.
(2) See the Third-party Products Disclaimer.
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is also
useful to get lower ripple current, but increases the transient response time and size as well.
10.1.3 Capacitor Selection
10.1.3.1 Input Capacitor
For most applications, 10-µF nominal is sufficient and is recommended. The input capacitor buffers the input
voltage for transient events and also decouples the converter from the supply. A low-ESR multilayer ceramic
capacitor (MLCC) is recommended for the best filtering and must be placed between VIN and GND as close as
possible to those pins.
10.1.3.2 Output Capacitor
The architecture of the TPS62850x allows the use of tiny ceramic output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low
resistance up to high frequencies and to get narrow capacitance variation with temperature, it is recommended
to use X7R or X5R dielectric. Using a higher value has advantages, like smaller voltage ripple and a tighter DC
output accuracy in power save mode.
The COMP/FSET pin allows the user to select two different compensation settings based on the minimum
capacitance used on the output. The maximum capacitance is 200 µF in any of the compensation settings. The
minimum capacitance required on the output depends on the compensation setting and output voltage.
For output voltages below 1 V, the minimum increases linearly from 10 µF at 1 V to 15 µF at 0.6 V with the
compensation setting for smallest output capacitance. Other compensation ranges are equivalent. See 表9-1 for
details.
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10.2 Typical Application
L
V
IN
TPS62850x
VIN
0.47mH
VOUT
2.7 V - 6 V
CIN
SW
R 1
CFF
2*10 mF
0603
COUT
2*10 mF
0603
EN
FB
MODE/SYNC
R2
R3
COMP/FSET
PG
GND
图10-1. Typical Application
10.2.1 Design Requirements
The design guidelines provide a component selection to operate the device within the recommended operating
conditions.
10.2.2 Detailed Design Procedure
V
OUT
æ
ö
R1
= R
-1
FB
2 × ç
è
÷
V
ø
(9)
With VFB = 0.6 V:
表10-2. Setting the Output Voltage
NOMINAL OUTPUT VOLTAGE
VOUT
R1
R2
CFF
EXACT OUTPUT VOLTAGE
0.8 V
1.0 V
1.1 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
0.7988 V
1.0 V
16.9 kΩ
20 kΩ
51 kΩ
30 kΩ
47 kΩ
68 kΩ
51 kΩ
40.2 kΩ
15 kΩ
19.6 kΩ
1.101 V
1.2 V
39.2 kΩ
68 kΩ
1.5 V
76.8 kΩ
80.6 kΩ
47.5 kΩ
88.7 kΩ
1.803 V
2.5 V
3.315 V
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10.2.3 Application Curves
All plots have been taken with a nominal switching frequency of 2.25 MHz when set to PWM mode, unless
otherwise noted. The BOM is according to 表8-1.
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m
Output Current (A)
100m
1
3
0
0.5
1
1.5
Output Current (A)
2
2.5
3
3
3
VOUT = 3.3 V
PFM
TA = 25°C
VOUT = 3.3 V
PWM
TA = 25°C
图10-2. Efficiency Versus Output Current
图10-3. Efficiency Versus Output Current
100
95
90
85
80
75
70
95
90
85
80
75
65
60
55
50
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
70
65
100m
1m
10m 100m
Output Current (A)
1
3
0
0.5
1
1.5
Output Current (A)
2
VOUT = 1.8 V
PFM
TA = 25°C
VOUT = 1.8 V
PWM
TA = 25°C
图10-4. Efficiency Versus Output Current
图10-5. Efficiency Versus Output Current
100
95
90
85
80
75
70
95
90
85
80
75
70
65
60
55
50
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.7 V
65
60
55
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m 100m
Output Current (A)
1
3
0
0.5
1
1.5
Output Current (A)
2
2.5
VOUT = 1.1 V
PFM
TA = 25°C
VOUT = 1.1 V
PWM
TA = 25°C
图10-6. Efficiency Versus Output Current
图10-7. Efficiency Versus Output Current
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90
85
80
75
70
65
60
55
50
45
90
85
80
75
70
65
60
55
50
45
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
40
100m
1m
10m 100m
Output Current (A)
1
3
0
0.5
1
1.5
Output Current (A)
2
2.5
3
VOUT = 0.6 V
PFM
TA = 25°C
VOUT = 0.6 V
PWM
TA = 25°C
图10-8. Efficiency Versus Output Current
图10-9. Efficiency Versus Output Current
3.33
3.324
3.318
3.312
3.306
3.3
3.33
3.324
3.318
3.312
3.306
3.3
3.294
3.288
3.282
3.294
3.288
3.282
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
3.276
3.27
3.276
3.27
100m
1m
10m 100m
Output Current (A)
1
3
100m
1m
10m 100m
Output Current (A)
1
3
VOUT = 3.3 V
PFM
TA = 25°C
VOUT = 3.3 V
PWM
TA = 25°C
图10-10. Output Voltage Versus Output Current
图10-11. Output Voltage Versus Output Current
1.82
1.816
1.812
1.808
1.804
1.8
1.82
1.816
1.812
1.808
1.804
1.8
1.796
1.796
1.792
1.788
1.784
1.78
1.792
1.788
1.784
1.78
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m 100m
Output Current (A)
1
3
100m
1m
10m 100m
Output Current (A)
1
3
VOUT = 1.8 V
PFM
TA = 25°C
VOUT = 1.8 V
PWM
TA = 25°C
图10-12. Output Voltage Versus Output Current
图10-13. Output Voltage Versus Output Current
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1.11
1.108
1.106
1.104
1.102
1.1
1.11
1.108
1.106
1.104
1.102
1.1
1.098
1.098
1.096
1.094
1.092
1.09
1.096
1.094
1.092
1.09
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m 100m
Output Current (A)
1
3
100m
1m
10m 100m
Output Current (A)
1
3
VOUT = 1.1 V
PFM
TA = 25°C
VOUT = 1.1 V
PWM
TA = 25°C
图10-14. Output Voltage Versus Output Current
图10-15. Output Voltage Versus Output Current
0.612
0.606
0.6045
0.603
0.6015
0.6
0.61
0.608
0.606
0.604
0.602
0.6
0.5985
0.597
VIN = 2.7 V
VIN = 3.3 V
VIN = 2.7 V
0.598
VIN = 3.3 V
0.5955
0.594
VIN = 4.0 V
VIN = 5.0 V
VIN = 4.0 V
VIN = 5.0 V
0.596
0.594
100m
1m
10m 100m
Output Current (A)
1
3
100m
1m
10m 100m
Output Current (A)
1
3
VOUT = 0.6 V
PWM
TA = 25°C
VOUT = 0.6 V
PFM
TA = 25°C
图10-17. Output Voltage Versus Output Current
图10-16. Output Voltage Versus Output Current
3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
VIN=2.7V
VIN=3.3V
VIN=4.2V
VIN=5.0V
VIN=6.0V
VIN=2.7V
VIN=3.3V
VIN=4.2V
VIN=5.0V
VIN=6.0V
1.00
0.75
0.50
0.25
0.00
1.00
0.75
0.50
0.25
0.00
35
45
55
65
75
85
95
105 115 125
35
45
55
65
75
85
95
105 115 125
Ambient temperature (èC)
Ambient temperature (èC)
VOUT = 0.6 V
PWM
VOUT = 1.1 V
PWM
θJA = 60°C/W
θJA = 60°C/W
图10-18. Output Current Versus Ambient
图10-19. Output Current Versus Ambient
Temperature
Temperature
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3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
VIN=2.7V
VIN=3.3V
VIN=4.2V
VIN=5.0V
VIN=6.0V
VIN=4.2V
VIN=5.0V
VIN=6.0V
0.00
35
45
55
65
75
85
95
105 115 125
35
45
55
65
75
85
95
105 115 125
Ambient temperature (èC)
Ambient temperature (èC)
VOUT = 1.8 V
PWM
VOUT = 3.3 V
PWM
θJA = 60°C/W
θJA = 60°C/W
图10-20. Output Current Versus Ambient
图10-21. Output Current Versus Ambient
Temperature
Temperature
VOUT = 3.3 V
VIN = 5.0 V
PFM
TA = 25°C
VOUT = 3.3 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
图10-22. Load Transient Response
图10-23. Load Transient Response
VOUT = 1.8 V
VIN = 5.0 V
PFM
TA = 25°C
VOUT = 1.8 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
图10-24. Load Transient Response
图10-25. Load Transient Response
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VOUT = 1.2 V
VIN = 5.0 V
PFM
TA = 25°C
VOUT = 1.2 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
图10-26. Load Transient Response
图10-27. Load Transient Response
VOUT = 1.0 V
VIN = 5.0 V
PFM
TA = 25°C
VOUT = 1.0 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
图10-28. Load Transient Response
图10-29. Load Transient Response
VOUT = 0.6 V
VIN = 3.3 V
PFM
TA = 25°C
VOUT = 0.6 V
VIN = 3.3 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
图10-30. Load Transient Response
图10-31. Load Transient Response
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VOUT = 3.3 V
IOUT = 0.2 A
PFM
TA = 25°C
VOUT = 3.3 V
IOUT = 2 A
PWM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
图10-32. Line Transient Response
图10-33. Line Transient Response
VOUT = 1.8 V
IOUT = 0.2 A
PFM
TA = 25°C
VOUT = 1.8 V
IOUT = 2 A
PWM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
图10-34. Line Transient Response
图10-35. Line Transient Response
VOUT = 1.2 V
IOUT = 0.2 A
PFM
TA = 25°C
VOUT = 1.2 V
IOUT = 2 A
PWM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
图10-36. Line Transient Response
图10-37. Line Transient Response
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VOUT = 1.0 V
IOUT = 0.2 A
PFM
TA = 25°C
VOUT = 1.0 V
IOUT = 2 A
PWM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
图10-38. Line Transient Response
图10-39. Line Transient Response
VOUT = 0.6 V
IOUT = 0.2 A
PFM
TA = 25°C
VOUT = 0.6 V
IOUT = 2 A
PWM
TA = 25°C
VIN = 3.0 V to 3.6 V to 3.0 V
VIN = 3.0 V to 3.6 V to 3.0 V
图10-40. Line Transient Response
图10-41. Line Transient Response
VOUT = 3.3 V
VIN = 5 V
PFM
TA = 25°C
VOUT = 3.3 V
VIN = 5 V
PWM
TA = 25°C
IOUT = 2 A
IOUT = 0.2 A
图10-42. Output Voltage Ripple
图10-43. Output Voltage Ripple
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VOUT = 1.8 V
VIN = 5 V
PFM
TA = 25°C
VOUT = 1.8 V
VIN = 5 V
PWM
TA = 25°C
IOUT = 2 A
IOUT = 0.2 A
图10-44. Output Voltage Ripple
图10-45. Output Voltage Ripple
VOUT = 1.2 V
VIN = 5 V
PFM
TA = 25°C
IOUT = 0.2 A
VOUT = 1.2 V
VIN = 5 V
PWM
TA = 25°C
IOUT = 2 A
图10-46. Output Voltage Ripple
图10-47. Output Voltage Ripple
VOUT = 1.0 V
VIN = 5 V
PFM
TA = 25°C
IOUT = 0.2 A
VOUT = 1.0 V
VIN = 5 V
PWM
TA = 25°C
IOUT = 2 A
图10-48. Output Voltage Ripple
图10-49. Output Voltage Ripple
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VOUT = 0.6 V
VIN = 3.3 V
PFM
TA = 25°C
VOUT = 0.6 V
VIN = 3.3 V
PWM
TA = 25°C
IOUT = 2 A
IOUT = 0.2 A
图10-50. Output Voltage Ripple
图10-51. Output Voltage Ripple
VOUT = 3.3 V
VIN = 5 V
PWM or PFM
TA = 25°C
VOUT = 1.8 V
VIN = 5 V
PWM or PFM
TA = 25°C
IOUT = 2 A
IOUT = 2 A
图10-52. Start-Up Timing
图10-53. Start-Up Timing
VOUT = 1.2 V
VIN = 5 V
PWM or PFM
TA = 25°C
IOUT = 2 A
VOUT = 1.0 V
VIN = 5 V
PWM or PFM
TA = 25°C
IOUT = 2 A
图10-54. Start-Up Timing
图10-55. Start-Up Timing
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VOUT = 0.6 V
VIN = 3.3 V
PWM or PFM
TA = 25°C
IOUT = 2 A
图10-56. Start-Up Timing
10.3 System Examples
10.3.1 Synchronizing to an External Clock
The TPS62850x can be externally synchronized by applying an external clock on the MODE/SYNC pin. There is
no need for any additional circuitry as long as the input signal meets the requirements given in the electrical
specifications. The clock can be applied / removed during operation, allowing an externally defined fixed
frequency to be switched to a power-save mode or to internal fixed frequency operation.
The value of the RCF resistor must be chosen such that the internally defined frequency and the externally
applied frequency are close to each other. This ensures a smooth transition from internal to external frequency
and vice versa.
L
V
IN
TPS62850x
0.47 mH
VOUT
2.7 V - 6 V
VIN
SW
CIN
R1
2*10 mF
0603
CFF
EN
FB
COUT
MODE/SYNC
COMP/FSET
R2
R 3
2*10 mF
0603
fEXT
PG
GND
图10-57. Schematic using External Synchronization
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VIN = 5 V
IOUT = 0.1 A
VIN = 5 V
IOUT = 0.1 A
RCF = 8.06 kΩ
RCF = 8.06 kΩ
VOUT = 1.8 V
fEXT = 2.5 MHz
VOUT = 1.8 V
fEXT = 2.5 MHz
图10-58. Switching from External Syncronization
图10-59. Switching from External Synchronizaion
to Power-Save Mode (PFM)
to Internal Fixed Frequency
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11 Power Supply Recommendations
The TPS62850x device family does not have special requirements for its input power supply. The output current
of the input power supply needs to be rated according to the supply voltage, output voltage, and output current
of the TPS62850x.
12 Layout
12.1 Layout Guidelines
A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore, the PCB layout of the TPS62850x demands careful attention to ensure operation and to
get the performance specified. A poor layout can lead to issues like the following:
• Poor regulation (both in 节12.2 and load)
• Stability and accuracy weaknesses
• Increased EMI radiation
• Noise sensitivity
See 图 12-1 for the recommended layout of the TPS62850x, which is designed for common external ground
connections. The input capacitor must be placed as close as possible between the VIN and GND pin.
Provide low inductive and resistive paths for loops with high di/dt. Therefore, paths conducting the switched load
current must be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for
wires with high dv/dt. Therefore, the input and output capacitance must be placed as close as possible to the IC
pins and parallel wiring over long distances and narrow traces must be avoided. Loops which conduct an
alternating current must outline an area as small as possible since this area is proportional to the energy
radiated.
Sensitive nodes like FB need to be connected with short wires and not nearby high dv/dt signals (for example,
SW). As they carry information about the output voltage, they must be connected as close as possible to the
actual output voltage (at the output capacitor). The FB resistors, R1 and R2, must be kept close to the IC and be
connected directly to the pin and the system ground plane.
The package uses the pins for power dissipation. Thermal vias on the VIN and GND pins help to spread the heat
into the PCB.
The recommended layout is implemented on the EVM and shown in the TPS628502EVM-092 Evaluation
Module User's Guide.
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12.2 Layout Example
COUT
L
V
OUT
GND
2
Solution size = 30mm
CIN
R2
U1
RCF
V
IN
GND
图12-1. Example Layout
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13 Device and Documentation Support
13.1 Device Support
13.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
13.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS628501DRLR
TPS628502DRLR
TPS628503DRLR
ACTIVE
ACTIVE
ACTIVE
SOT-5X3
SOT-5X3
SOT-5X3
DRL
DRL
DRL
8
8
8
4000 RoHS & Green
4000 RoHS & Green
4000 RoHS & Green
Call TI | SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 150
100
200
300
Samples
Samples
Samples
Call TI | SN
Call TI | SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS628501, TPS628502, TPS628503 :
Automotive : TPS628501-Q1, TPS628502-Q1, TPS628503-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS628501DRLR
TPS628502DRLR
TPS628503DRLR
SOT-5X3
SOT-5X3
SOT-5X3
DRL
DRL
DRL
8
8
8
4000
4000
4000
180.0
180.0
180.0
8.4
8.4
8.4
2.75
2.75
2.75
1.9
1.9
1.9
0.8
0.8
0.8
4.0
4.0
4.0
8.0
8.0
8.0
Q3
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS628501DRLR
TPS628502DRLR
TPS628503DRLR
SOT-5X3
SOT-5X3
SOT-5X3
DRL
DRL
DRL
8
8
8
4000
4000
4000
210.0
210.0
210.0
185.0
185.0
185.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DRL0008A
SOT-5X3 - 0.6 mm max height
S
C
A
L
E
8
.
0
0
0
PLASTIC SMALL OUTLINE
1.3
1.1
B
A
PIN 1
ID AREA
1
8
6X 0.5
2.2
2.0
2X 1.5
NOTE 3
5
4
0.27
0.17
8X
1.7
1.5
0.05
0.00
0.1
C A B
0.05
C
0.6 MAX
SEATING PLANE
0.05 C
0.18
0.08
SYMM
0.4
0.2
8X
SYMM
4224486/E 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, interlead flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4.Reference JEDEC Registration MO-293, Variation UDAD
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EXAMPLE BOARD LAYOUT
DRL0008A
SOT-5X3 - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.67)
SYMM
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4224486/E 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.
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EXAMPLE STENCIL DESIGN
DRL0008A
SOT-5X3 - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.67)
SYMM
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4224486/E 12/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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