TPS62850X-Q1 [TI]
TPS62850x-Q1 2.7-V to 6-V, 1-A / 2-A Automotive Step-Down Converter in SOT583 Package;
| 型号： | TPS62850X-Q1 |
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TEXAS INSTRUMENTS |
| 描述： | TPS62850x-Q1 2.7-V to 6-V, 1-A / 2-A Automotive Step-Down Converter in SOT583 Package |
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TPS628501-Q1, TPS628502-Q1
SLUSDM0B – JULY 2020 – REVISED NOVEMBER 2020
TPS62850x-Q1 2.7-V to 6-V, 1-A / 2-A Automotive Step-Down Converter
in SOT583 Package
1 Features
3 Description
•
AEC-Q100 qualified for automotive applications
– Device temperature grade 1:
–40°C to +125°C TA
Functional Safety-Capable
– Documentation available to aid functional safety
system design
The TPS62850x-Q1 is a family of pin-to-pin 1-A and
2-A high efficiency, easy-to-use synchronous step-
down DC/DC converters. They are based on a peak
current mode control topology. They are designed for
automotive applications such as Infotainment and
Advanced Driver Assistance Systems. Low resistive
switches allow up to 2-A continuous output current at
high ambient temperature. The switching frequency is
externally adjustable from 1.8 MHz to 4 MHz and can
also be synchronized to an external clock in the same
frequency range. In PWM/PFM mode, the
TPS62850x-Q1 automatically enter Power Save Mode
at light loads to maintain high efficiency across the
whole load range. The TPS62850x-Q1 provide a 1%
output voltage accuracy in PWM mode which helps
design a power supply with high output voltage
accuracy.
•
•
•
•
•
•
•
•
TJ = –40°C to +150°C
Input voltage range: 2.7 V to 6 V
Quiescent current 15 µA typical
Output voltage from 0.6 V to 5.5 V
Output voltage accuracy ±1% (PWM operation)
Forced PWM or PWM/PFM operation
Adjustable switching frequency of
1.8 MHz to 4 MHz
Precise ENABLE input allows:
– User-defined undervoltage lockout
– Exact sequencing
100% duty cycle mode
Active output discharge
Spread spectrum clocking - optional
Foldback overcurrent protection - optional
Power-good output with window comparator
•
The TPS62850x-Q1 is available in a SOT583
package.
•
•
•
•
•
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
2.1 mm x 1.6 mm
(incl pins)
TPS628501-Q1
SOT583
2.1 mm x 1.6 mm
(incl pins)
TPS628502-Q1
SOT583
2 Applications
•
•
•
•
•
ADAS camera, ADAS sensor fusion
Surround view ECU
Hybrid and reconfigurable cluster
Head unit, Telematics control unit
External amplifier
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
100
95
L
TPS62850x-Q1
0.47mH
V
IN
VOUT
2.7 V - 6 V
VIN
SW
CIN
R1
90
CFF
2*10 mF
0603
COUT
EN
FB
85
2*10 mF
0603
MODE/SYNC
R2
R3
80
75
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
COMP/FSET
0
0.5
1
Output Current (A)
1.5
2
PG
D002
GND
Efficiency versus IOUT, VOUT = 3.3 V
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS628501-Q1, TPS628502-Q1
SLUSDM0B – JULY 2020 – REVISED NOVEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................5
7.4 Thermal Information ...................................................5
7.5 Electrical Characteristics ............................................6
7.6 Typical Characteristics................................................8
8 Parameter Measurement Information............................9
8.1 Schematic................................................................... 9
9 Detailed Description......................................................10
9.1 Overview...................................................................10
9.2 Functional Block Diagram.........................................10
9.3 Feature Description...................................................10
9.4 Device Functional Modes..........................................13
10 Application and Implementation................................15
10.1 Application Information........................................... 15
10.2 Typical Application.................................................. 16
10.3 System Examples................................................... 26
11 Power Supply Recommendations..............................28
12 Layout...........................................................................28
12.1 Layout Guidelines................................................... 28
12.2 Layout Example...................................................... 29
13 Device and Documentation Support..........................30
13.1 Device Support....................................................... 30
13.2 Receiving Notification of Documentation Updates..30
13.3 Support Resources................................................. 30
13.4 Trademarks.............................................................30
13.5 Electrostatic Discharge Caution..............................30
13.6 Glossary..................................................................30
14 Mechanical, Packaging, and Orderable
Information.................................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2020) to Revision B (November 2020)
Page
•
Changed device status from Advance Information to Production Data.............................................................. 1
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5 Device Comparison Table
DEVICE NUMBER
OUTPUT
Vout
FOLDBACK
TYPICAL
SOFT START
OUTPUT
CURRENT DISCHARGE CURRENT LIMIT OUTPUT CAPACITOR
VOLTAGE
TPS628501QDRLRQ1
TPS628502QDRLRQ1
TPS6285010MQDRLRQ1
TPS6285020MQDRLRQ1
1 A
2 A
1 A
2 A
ON
ON
ON
ON
OFF
OFF
OFF
OFF
2 x 10 μF
2 x 10 μF
2 x 10 μF
2 x 10 μF
internal 1 ms
internal 1 ms
internal 1 ms
internal 1 ms
adjustable
adjustable
fixed 1.8 V
fixed 1.8 V
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6 Pin Configuration and Functions
GND SW
PG
FB
1
VIN EN
Figure 6-1. 8 Pin SOT583 DRL Packae (Top View)
Table 6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
This is the enable pin of the device. Connect to logic low to disable the device. Pull high to
enable the device. Do not leave this pin unconnected.
EN
2
I
I
FB
5
8
Voltage feedback input, connect the resistive output voltage divider to this pin.
Ground pin
GND
The device runs in PFM/PWM mode when this pin is pulled low. When the pin is pulled high,
the device runs in forced PWM mode. Do not leave this pin unconnected. The mode pin can
also be used to synchronize the device to an external frequency. See Section 7.5 for the
detailed specification for the digital signal applied to this pin for external synchronization.
MODE/SYNC
COMP/FSET
3
4
I
Device compensation and frequency set input. A resistor from this pin to GND defines the
compensation of the control loop as well as the switching frequency if not externally
synchronized.
I
PG
6
7
O
Open-drain power-good output
SW
This is the switch pin of the converter and is connected to the internal Power MOSFETs.
Power supply input. Make sure the input capacitor is connected as close as possible
between pin VIN and GND.
VIN
1
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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
– 0.3
– 0.3
– 3
MAX
6.5
UNIT
V
Pin voltage(2)
Pin voltage(2)
Pin voltage(2)
Pin voltage(2)
Pin voltage(2)
Tstg
VIN
SW (DC)
VIN + 0.3
10
V
SW (AC, less than 10ns)(3)
COMP/FSET, PG
EN, MODE/SYNC, FB
Storage temperature
V
– 0.3
– 0.3
–65
VIN + 0.3
6.5
V
V
150
°C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to the network ground terminal
(3) While switching
7.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
Electrostatic
discharge
V(ESD)
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over operating temperature range (unless otherwise noted)
MIN
2.7
0.6
0.32
8
NOM
MAX
6
UNIT
V
VIN
Input voltage range
VOUT
L
Output voltage range
5.5
1.2
200
V
Effective inductance
0.47
10
μH
μF
μF
kΩ
mA
°C
COUT
CIN
Effective output capacitance(1)
Effective input capacitance(1)
10
RCF
ISINK_PG
TJ
4.5
0
100
2
Sink current at PG pin
Junction temperature
–40
150
(1) The values given for all the capacitors in the table are effective capacitance, which includes the DC bias effect. Due to the DC bias
effect of ceramic capacitors, the effective capacitance is lower than the nominal value when a voltage is applied. Please check the
manufacturer´s DC bias curves for the effective capacitance vs DC voltage applied. Further restrictions may apply. Please see the
feature description for COMP/FSET about the output capacitance vs compensation setting and output voltage.
7.4 Thermal Information
TPS62850x-Q1
TPS62850x-Q1
THERMAL METRIC(1)
DRL (JEDEC)(2)
DRL (EVM)
8 PINS
60
UNIT
8 PINS
110
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
41.3
20
n/a
n/a
ΨJT
0.8
n/a
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UNIT
SLUSDM0B – JULY 2020 – REVISED NOVEMBER 2020
TPS62850x-Q1
TPS62850x-Q1
DRL (EVM)
8 PINS
THERMAL METRIC(1)
DRL (JEDEC)(2)
8 PINS
20
YJB
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
n/a
°C/W
°C/W
RθJC(bot)
n/a
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) JEDEC standard PCB with 4 layers, no thermal vias
7.5 Electrical Characteristics
Over operating junction remperature range (TJ = -40°C to +150°C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ
= 25°C. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
EN = VIN, no load, device not switching,
MODE = GND, VOUT = 0.6 V
IQ
Quiescent current
17
36
48
μA
μA
EN = GND, Nominal value at TJ = 25°C,
Max value at TJ = 150°C
ISD
Shutdown current
1.5
VIN rising
VIN falling
TJ rising
TJ falling
2.45
2.1
2.6
2.5
170
15
2.7
2.6
V
V
VUVLO
Undervoltage lock out threshold
Thermal shutdown threshold
Thermal shutdown hysteresis
°C
°C
TJSD
CONTROL and INTERFACE
VEN,IH Input threshold voltage at EN, rising edge
VEN,IL
1.05
0.96
1.1
1.0
1.15
1.05
V
V
Input threshold voltage at EN, falling edge
High-level input-threshold voltage at
MODE/SYNC
VIH
1.1
V
nA
V
IEN,LKG
VIL
ILKG
tDelay
Input leakage current into EN
VIH = VIN or VIL = GND
125
0.3
Low-level input-threshold voltage at
MODE/SYNC
Input leakage current into MODE/SYNC
Enable delay time
100
520
nA
µs
Time from EN high to device starts
switching; VIN applied already
135
200
1.3
Time from EN high to device starts
switching; VIN applied already,
VIN ≥ 3.3 V
tDelay
Enable delay time
480
µs
Time from device starts switching to
power good; device not in current limit
tRamp
fSYNC
Output voltage ramp time
0.8
1.8
20
1.8
4
ms
Frequency range on MODE/SYNC pin for
synchronization
MHz
Duty cycle of synchronization signal at
MODE/SYNC
80
%
µs
kΩ
Time to lock to external frequency
50
resistance from COMP/FSET to GND for internal frequency setting with
logic low
0
2.5
f = 2.25 MHz
internal frequency setting with
f = 2.25 MHz
Voltage on COMP/FSET for logic high
VIN
95
90
V
%
%
UVP power good threshold voltage;
DC level
VTH_PG
VTH_PG
rising (%VFB
)
92
87
98
93
UVP power good threshold voltage;
DC level
falling (%VFB
)
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Over operating junction remperature range (TJ = -40°C to +150°C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ
= 25°C. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
rising (%VFB
falling (%VFB
MIN
TYP
MAX
UNIT
OVP power good threshold voltage;
DC level
)
107
110
113
%
VTH_PG
OVP power good threshold voltage;
DC level
)
104
107
111
%
VPG,OL
IPG,LKG
Low-level output voltage at PG
Input leakage current into PG
ISINK_PG = 2 mA
VPG = 5 V
0.07
0.3
V
100
nA
for a high level to low level transition on
the power good output
tPG
PG deglitch time
40
µs
OUTPUT
VFB
Feedback voltage, adjustable version
Feedback voltage, fixed voltage version
0.6
1.8
V
V
VFB
for TPS6285010M, TPS6285020M
VFB = 0.6 V
Input leakage current into FB, adjustable
version
IFB,LKG
1
1
70
nA
Input current into FB, fixed voltage
versions
IFB,LKG
VFB
µA
%
Feedback voltage accuracy
Feedback voltage accuracy
PWM, VIN ≥ VOUT + 1 V
-1
-1
1
2
PFM, VIN ≥ VOUT + 1 V, VOUT ≥ 1.0 V,
Cout,eff ≥ 10 µF, L = 0.47µH
VFB
%
PFM, VIN ≥ VOUT + 1 V, VOUT < 1.0 V,
Cout,eff ≥ 15 µF, L = 0.47µH
VFB
Feedback voltage accuracy
-1
3
%
Load regulation
PWM
0.05
0.02
%/A
%/V
Ω
Line regulation
PWM, IOUT = 1 A, VIN ≥ VOUT + 1 V
RDIS
fSW
Output discharge resistance
100
4
MODE = high, see the FSET pin
functionality about setting the switching
frequency
PWM Switching frequency range
PWM Switching frequency range
1.8
1.8
2.25
2.25
MHz
MHz
MODE = low, see the FSET pin
functionality about setting the switching
frequency
fSW
3.5
fSW
fSW
PWM Switching frequency
with COMP/FSET tied to GND or VIN
2.025
-12
2.475
12
MHz
%
using a resistor from COMP/FSET to
GND
PWM Switching frequency tolerance
ton,min
ton,min
Minimum on-time of high-side FET
Minimum on-time of low-side FET
VIN = 3.3 V, TJ = -40°C to 125°C
35
10
50
ns
ns
VIN ≥ 5 V
High-side FET on-resistance
65
120
70
mΩ
RDS(ON)
Low-side FET on-resistance
High-side MOSFET leakage current
High-side MOSFET leakage current
Low-side MOSFET leakage current
Low-side MOSFET leakage current
SW leakage
VIN ≥ 5 V
TJ = 85°C
33
2.5
mΩ
µA
µA
µA
µA
µA
0.01
3.7
44
TJ = 85°C
0.01
70
11
V(SW) = 0.6V, current into SW pin
-0.05
2.85
DC value, for TPS628502;
VIN = 3 V to 6 V
ILIMH
High-side FET switch current limit
3.4
3.9
3.0
A
DC value, for TPS628501;
VIN = 3 V to 6 V
ILIMH
High-side FET switch current limit
Low-side FET negative current limit
2.1
2.6
A
A
ILIMNEG
DC value
-1.8
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7.6 Typical Characteristics
140
80
76
72
68
64
60
56
52
48
44
40
36
32
28
24
20
VIN = 2.7V
VIN = 3.3V
VIN = 5.0V
VIN = 2.7V
VIN = 3.3V
VIN = 5.0V
VIN = 6.0V
130
120
VIN = 6.0V
110
100
90
80
70
60
50
40
-40
0
25 85
Junction Temperature (°C)
125
150
-40
0
25 85
Junction Temperature (°C)
125
150
D002
D002
Figure 7-1. RDS (ON) of High-side Switch
Figure 7-2. RDS (ON) of Low-side Switch
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8 Parameter Measurement Information
8.1 Schematic
L
V
IN
TPS62850x-Q1
0.47mH
VOUT
2.7 V - 6 V
VIN
SW
CIN
R1
CFF
2*10 mF
0603
COUT
EN
FB
2*10 mF
0603
MODE/SYNC
R2
R3
COMP/FSET
PG
GND
Figure 8-1. Measurement Setup
Table 8-1. List of Components
DESCRIPTION
REFERENCE
MANUFACTURER (1)
IC
L
TPS628502QDRLRQ1
Texas Instruments
Murata
Murata
Murata
Murata
Any
0.47-µH inductor DFE252012PD
CIN
COUT
COUT
RCF
CFF
R1
2 x 10 µF / 6.3 V GCM188D70J106M
2 x 10 µF / 6.3 V GCM188D70J106M for Vout ≥ 1 V
3 x 10 µF / 6.3 V GCM188D70J106M for Vout < 1 V
8,06 kΩ
10 pF
Any
Depending on VOUT
Depending on VOUT
100 kΩ
Any
R2
Any
R3
Any
(1) See the Third-party Products Disclaimer.
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9 Detailed Description
9.1 Overview
The TPS62850x-Q1 synchronous switch mode power converters are based on a peak current mode control
topology. The control loop is internally compensated.
To optimize the bandwidth of the control loop to the wide range of output capacitance that can be used with the
TPS62850x-Q1, the internal compensation has two settings. See Section 9.3.2. One out of the two
compensation settings is chosen either by a resistor from COMP/FSET to GND, or by the logic state of this pin.
The regulation network achieves fast and stable operation with small external components and low-ESR ceramic
output capacitors. The devices can be operated without a feedforward capacitor on the output voltage divider,
however, using a typically 10-pF feedforward capacitor improves transient response.
The devices support forced fixed frequency PWM operation with the MODE pin tied to a logic high level. The
frequency is defined as either 2.25 MHz internally fixed when COMP/FSET is tied to GND or VIN, or in a range
of 1.8 MHz to 4 MHz defined by a resistor from COMP/FSET to GND. Alternatively, the devices can be
synchronized to an external clock signal in a range from 1.8 MHz to 4 MHz, applied to the MODE pin with no
need for additional passive components. An internal PLL allows you to change from internal clock to external
clock during operation. The synchronization to the external clock is done on a falling edge of the clock applied at
MODE to the rising edge on the SW pin. This allows a roughly 180° phase shift when the SW pin is used to
generate the synchronization signal for a second converter. When the MODE pin is set to a logic low level, the
device operates in power save mode (PFM) at low output current and automatically transfers to fixed frequency
PWM mode at higher output current. In PFM mode, the switching frequency decreases linearly based on the
load to sustain high efficiency down to very low output current.
9.2 Functional Block Diagram
VIN
SW
Bias
Regulator
Gate Drive and Control
Oscillator
Ipeak
Izero
EN
MODE/SYNC
gm
GND
FB
Device
Control
PG
+
-
Bandgap
COMP/FSET
Thermal
Shutdown
9.3 Feature Description
9.3.1 Precise Enable (EN)
The voltage applied at the enable pin of the TPS62850x-Q1 is compared to a fixed threshold of 1.1 V for a rising
voltage. This allows you to drive the pin by a slowly changing voltage and enables the use of an external RC
network to achieve a power-up delay.
The Precise Enable input provides a user-programmable undervoltage lockout by adding a resistor divider to the
input of the Enable pin.
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The enable input threshold for a falling edge is typically 100 mV lower than the rising edge threshold. The
TPS62850x-Q1 starts operation when the rising threshold is exceeded. For proper operation, the enable (EN)
pin must be terminated and must not be left floating. Pulling the enable pin low forces the device into shutdown,
with a shutdown current of typically 1 μA. In this mode, the internal high-side and low-side MOSFETs are turned
off and the entire internal control circuitry is switched off.
9.3.2 COMP/FSET
This pin allows to set three different parameters:
•
•
•
Internal compensation settings for the control loop (two settings available)
The switching frequency in PWM mode from 1.8 MHz to 4 MHz
Enable/disable spread spectrum clocking (SSC)
A resistor from COMP/FSET to GND changes the compensation as well as the switching frequency. The change
in compensation allows you to adopt the device to different values of output capacitance. The resistor must be
placed close to the pin to keep the parasitic capacitance on the pin to a minimum. The compensation setting is
sampled at start up of the converter, so a change in the resistor during operation only has an effect on the
switching frequency but not on the compensation.
To save external components, the pin can also be directly tied to VIN or GND to set a pre-defined setting. Do not
leave the pin floating.
The switching frequency has to be selected based on the input voltage and the output voltage to meet the
specifications for the minimum on-time and minimum off-time.
Example: VIN = 5 V, VOUT = 0.6 V --> duty cycle = 0.6 V / 5 V = 0.12
•
•
--> ton,min = 1 / fs × 0.12
--> fsw,max = 1 / ton,min × 0.12 = 1 / 0.05 µs × 0.12 = 2.4 MHz
The compensation range has to be chosen based on the minimum capacitance used. The capacitance can be
increased from the minimum value as given in Table 9-1, up to the maximum of 200 µF in both compensation
ranges. If the capacitance of an output changes during operation, for example, when load switches are used to
connect or disconnect parts of the circuitry, the compensation has to be chosen for the minimum capacitance on
the output. With large output capacitance, the compensation must be done based on that large capacitance to
get the best load transient response. Compensating for large output capacitance but placing less capacitance on
the output can lead to instability.
The switching frequency for the different compensation setting is determined by the following equations.
For compensation (comp) setting 1 with spread spectrum clocking (SSC) disabled:
Space
18MHz ×kW
RCF(kW) =
fS(MHz)
(1)
(2)
For compensation (comp) setting 1 with spread spectrum clocking (SSC) enabled:
Space
60MHz ×kW
RCF(kW) =
fS(MHz)
Space
For compensation (comp) setting 2 with spread spectrum clocking (SSC) disabled:
Space
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180MHz ×kW
RCF(kW) =
fS(MHz)
(3)
Table 9-1. Switching Frequency, Compensation, and Spread Spectrum Clocking
MINIMUM
OUTPUT
CAPACITANCE
FOR VOUT < 1 V
MINIMUM OUTPUT
CAPACITANCE
FOR 1 V ≤ VOUT < 3.3 V FOR VOUT ≥ 3.3 V
MINIMUM OUTPUT
CAPACITANCE
RCF
COMPENSATION
SWITCHING FREQUENCY
for smallest output capacitance
(comp setting 1)
1.8 MHz (10 kΩ) .. 4 MHz (4.5 kΩ)
according to Equation 1
10 kΩ .. 4.5 kΩ
33 kΩ .. 18 kΩ
15 µF
15 µF
10 µF
10 µF
8 µF
8 µF
SSC disabled
for smallest output capacitance
(comp setting 1)
1.8 MHz (33 kΩ) .. 4 MHz (18 kΩ)
according to Equation 2
SSC enabled
for best transient response
(larger output capacitance)
(comp setting 2)
1.8 MHz (100 kΩ) ..4 MHz (45 kΩ)
according to Equation 3
100 kΩ .. 45 kΩ
tied to GND
tied to VIN
30 µF
15 µF
30 µF
18 µF
10 µF
18 µF
15 µF
8 µF
SSC disabled
for smallest output capacitance
(comp setting 1)
internally fixed 2.25 MHz
internally fixed 2.25 MHz
SSC disabled
for best transient response
(larger output capacitance)
(comp setting 2)
15 µF
SSC enabled
Refer to Section 10.1.3.2 for further details on the output capacitance required depending on the output voltage.
A resistor value that is too high for RCF is decoded as "tied to VIN", a value below the lowest range is decoded as
"tied to GND". The minimum output capacitance in Table 9-1 is for capacitors close to the output of the device. If
the capacitance is distributed, a lower compensation setting can be required.
9.3.3 MODE / SYNC
When MODE/SYNC is set low, the device operates in PWM or PFM mode, depending on the output current. The
MODE/SYNC pin allows you to force PWM mode when set high. The pin also allows you to apply an external
clock in a frequency range from 1.8 MHz to 4 MHz for external synchronization. The specifications for the
minimum on-time and minimum off-time has to be observed when setting the external frequency. For use with
external synchronization on the MODE/SYNC pin, the internal switching frequency must be set by RCF to a
similar value than the externally applied clock. This ensures that, if the external clock fails, the switching
frequency stays in the same range and the compensation settings are still valid.
9.3.4 Spread Spectrum Clocking (SSC)
The device offers spread spectrum clocking as an option. When SSC is enabled, the switching frequency is
randomly changed in PWM mode when the internal clock is used. The frequency variation is typically between
the nominal switching frequency and up to 288 kHz above the nominal switching frequency. When the device is
externally synchronized by applying a clock signal to the MODE/SYNC pin, the TPS62850x-Q1 follows the
external clock and the internal spread spectrum block is turned off. SSC is also disabled during soft start.
9.3.5 Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout prevents misoperation of the device by switching off both the
power FETs. When enabled, the device is fully operational for input voltages above the rising UVLO threshold
and turns off if the input voltage trips below the threshold for a falling supply voltage.
9.3.6 Power Good Output (PG)
Power good is an open-drain output that requires a pullup resistor to any voltage up to the recommended input
voltage level. It is driven by a window comparator. PG is held low when the device is disabled, in undervoltage
lockout in thermal shutdown, and not in soft start. When the output voltage is in regulation hence, within the
window defined in the electrical characteristics, the output is high impedance.
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VIN must remain present for the PG pin to stay low. If the power good output is not used, it is recommended to tie
to GND or leave open. The PG indicator features a de-glitch, as specified in the electrical characteristics, for the
transition from "high impedance" to "low" of its output.
Table 9-2. PG Status
EN
X
DEVICE STATUS
PG STATE
undefined
low
VIN < 2 V
low
VIN ≥ 2 V
2 V ≤ VIN ≤ UVLO OR in thermal shutdown OR VOUT not in regulation
OR device in soft start
high
high
low
VOUT in regulation
high impedance
9.3.7 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 170°C
(typ), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and PG
goes low. When TJ decreases below the hysteresis amount of typically 15°C, the converter resumes normal
operation, beginning with soft start. During a PFM pause, the thermal shutdown is not active. After a PFM pause,
the device needs up to 9 µs to detect a junction temperature that is too high. If the PFM burst is shorter than this
delay, the device does not detect a junction temperature that is too high.
9.4 Device Functional Modes
9.4.1 Pulse Width Modulation (PWM) Operation
The TPS62850x-Q1 has two operating modes: Forced PWM mode is discussed in this section and PWM/PFM
as discussed in Section 9.4.2.
With the MODE/SYNC pin set to high, the TPS62850x-Q1 operates with pulse width modulation in continuous
conduction mode (CCM). The switching frequency is either defined by a resistor from the COMP pin to GND or
by an external clock signal applied to the MODE/SYNC pin. With an external clock applied to MODE/SYNC, the
TPS62850x-Q1 follows the frequency applied to the pin. In general, the frequency range in forced PWM mode is
1.8 MHz to 4 MHz. However, the frequency needs to be in a range the TPS62850x-Q1 can operate at, taking the
minimum on-time into account.
9.4.2 Power Save Mode Operation (PWM/PFM)
When the MODE/SYNC pin is low, power save mode is allowed. The device operates in PWM mode as long as
the peak inductor current is above the PFM threshold of about 0.8 A. When the peak inductor current drops
below the PFM threshold, the device starts to skip switching pulses. In power save mode, the switching
frequency decreases with the load current maintaining high efficiency. In addition, the frequency set with the
resistor on COMP/FSET must be in a range of 1.8 MHz to 3.5 MHz.
9.4.3 100% Duty-Cycle Operation
The duty cycle of a buck converter operated in PWM mode is given as D = VOUT / VIN. The duty cycle
increases as the input voltage comes close to the output voltage and the off-time gets smaller. When the
minimum off-time of typically 10 ns is reached, the TPS62850x-Q1 skips switching cycles while it approaches
100% mode. In 100% mode, it keeps the high-side switch on continuously. The high-side switch stays turned on
as long as the output voltage is below the target. In 100% mode, the low-side switch is turned off. The maximum
dropout voltage in 100% mode is the product of the on-resistance of the high-side switch plus the series
resistance of the inductor and the load current.
9.4.4 Current Limit and Short Circuit Protection
The TPS62850x-Q1 is protected against overload and short circuit events. If the inductor current exceeds the
current limit I LIMH, the high-side switch is turned off and the low-side switch is turned on to ramp down the
inductor current. The high-side switch turns on again only if the current in the low side-switch has decreased
below the low side current limit. Due to internal propagation delay, the actual current can exceed the static
current limit. The dynamic current limit is given as:
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V
L
Ipeak(typ) = ILIMH
+
×tPD
(4)
where
•
•
•
•
ILIMH is the static current limit as specified in the electrical characteristics
L is the effective inductance at the peak current
VL is the voltage across the inductor (VIN - VOUT
)
tPD is the internal propagation delay of typically 50 ns
The current limit can exceed static values, especially if the input voltage is high and very small inductances are
used. The dynamic high-side switch peak current can be calculated as follows:
V
IN -VOUT
Ipeak(typ) = ILIMH
+
×50ns
(5)
9.4.5 Foldback Current Limit and Short Circuit Protection
This is valid for devices where foldback current limit is enabled.
When the device detects current limit for more than 1024 subsequent switching cycles, it reduces the current
limit from its nominal value to typically 1.3 A. Foldback current limit is left when the current limit indication goes
away. If device operation continues in current limit, it would, after 3072 switching cycles, try again full current
limit for again 1024 switching cycles.
9.4.6 Output Discharge
The purpose of the discharge function is to ensure a defined down-ramp of the output voltage when the device is
being disabled and to keep the output voltage close to 0 V when the device is off. The output discharge feature
is only active once the TPS62850x-Q1 has been enabled at least once since the supply voltage was applied.
The discharge function is enabled as soon as the device is disabled, in thermal shutdown, or in undervoltage
lockout. The minimum supply voltage required for the discharge function to remain active typically is 2 V. Output
discharge is not activated during a current limit or foldback current limit event.
9.4.7 Soft Start
The internal soft-start circuitry controls the output voltage slope during start-up. This avoids excessive inrush
current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high
impedance power sources or batteries. When EN is set high to start operation, the device starts switching after a
delay of about 200 μs then the internal reference and hence VOUT rises with a slope defined by an internally
defined slope of 150 µs or 1 ms (OTP option).
9.4.8 Input Overvoltage Protection
When the input voltage exceeds the absolute maximum rating, the device is set to PFM mode so it cannot
transfer energy from the output to the input.
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
10.1.1 Programming the Output Voltage
The output voltage of the TPS62850x-Q1 is adjustable. It can be programmed for output voltages from 0.6 V to
5.5 V, using a resistor divider from VOUT to GND. The voltage at the FB pin is regulated to 600 mV. The value of
the output voltage is set by the selection of the resistor divider from Equation 6. It is recommended to choose
resistor values which allow a current of at least 2 µA, meaning the value of R2 must not exceed 400 kΩ. Lower
resistor values are recommended for highest accuracy and most robust design.
V
OUT
æ
ö
R1
= R
-1
FB
2 × ç
è
÷
V
ø
(6)
10.1.2 External Component Selection
10.1.2.1 Inductor Selection
The TPS62850x-Q1 is designed for a nominal 0.47-µH inductor with a switching frequency of typically 2.25 MHz.
Larger values can be used to achieve a lower inductor current ripple but they can have a negative impact on
efficiency and transient response. Smaller values than 0.47 µH cause a larger inductor current ripple which
causes larger negative inductor current in forced PWM mode at low or no output current. For a higher or lower
nominal switching frequency, the inductance must be changed accordingly. See Section 7.3 for details.
The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-to-
PFM transition point, and efficiency. In addition, the inductor selected has to be rated for appropriate saturation
current and DC resistance (DCR). Equation 7 calculates the maximum inductor current.
DIL(max)
IL(max) = IOUT(max)
+
2
(7)
(8)
V
OUT
æ
ö
V
1-
OUT × ç
÷
IN
1
V
è
Lmin
ø
DIL(max)
=
×
f
SW
where
•
•
•
IL(max) is the maximum inductor current
ΔIL(max) is the peak-to-peak inductor ripple current
Lmin is the minimum inductance at the operating point
Table 10-1. Typical Inductors
NOMINAL
SWITCHING
FREQUENCY
DIMENSIONS
[LxWxH] mm
TYPE
INDUCTANCE
CURRENT (1)
FOR DEVICE
MANUFACTURER(2)
XFL4015-471ME
XFL4015-701ME
XEL3520-801ME
XEL3515-561ME
XFL3012-681ME
0.47 µH, ±20%
0.70 µH, ±20%
0.80 µH, ±20%
0.56 µH, ±20%
0.68 µH, ±20%
3.5 A
3.3 A
2.0 A
4.5 A
2.1 A
TPS628501 / 502
TPS628501 / 502
TPS628501 / 502
TPS628501 / 502
TPS628501 / 502
2.25 MHz
2.25 MHz
2.25 MHz
2.25 MHz
2.25 MHz
4 x 4 x 1.6
4 x 4 x 1.6
Coilcraft
Coilcraft
Coilcraft
Coilcraft
Coilcraft
3.5 x 3.2 x 2.0
3.5 x 3.2 x 1.5
3.0 x 3.0 x 1.2
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Table 10-1. Typical Inductors (continued)
NOMINAL
SWITCHING
FREQUENCY
DIMENSIONS
[LxWxH] mm
TYPE
INDUCTANCE
CURRENT (1)
FOR DEVICE
MANUFACTURER(2)
XPL2010-681ML
0.68 µH, ±20%
0.68 µH, ±20%
0.47 µH, ±20%
0.68 µH, ±20%
0.47 µH, ±20%
1.5 A
TPS628501
2.25 MHz
2.25 MHz
2.25 MHz
2.25 MHz
2.25 MHz
2 x 1.9 x 1
2.5 x 2 x 1.2
2.5 x 2 x 1.2
2 x 1.6 x 1.2
2 x 1.6 x 1.2
Coilcraft
Murata
Murata
Murata
Murata
DFE252012PD-R68M
DFE252012PD-R47M
DFE201612PD-R68M
DFE201612PD-R47M
see data sheet
see data sheet
see data sheet
see data sheet
TPS628501 / 502
TPS628501 / 502
TPS628501 / 502
TPS628501 / 502
(1) Lower of IRMS at 20°C rise or ISAT at 20% drop.
(2) See the Third-party Products Disclaimer.
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is also
useful to get lower ripple current, but increases the transient response time and size as well.
10.1.3 Capacitor Selection
10.1.3.1 Input Capacitor
For most applications, 10-µF nominal is sufficient and is recommended. The input capacitor buffers the input
voltage for transient events and also decouples the converter from the supply. A low-ESR multilayer ceramic
capacitor (MLCC) is recommended for best filtering and must be placed between VIN and GND as close as
possible to those pins.
10.1.3.2 Output Capacitor
The architecture of the TPS62850x-Q1 allows the use of tiny ceramic output capacitors with low equivalent
series resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its
low resistance up to high frequencies and to get narrow capacitance variation with temperature, it is
recommended to use X7R or X5R dielectric. Using a higher value has advantages like smaller voltage ripple and
a tighter DC output accuracy in power save mode.
The COMP/FSET pin allows you to select two different compensation settings based on the minimum
capacitance used on the output. The maximum capacitance is 200 µF in any of the compensation settings. The
minimum capacitance required on the output depends on the compensation setting and output voltage.
For output voltages below 1 V, the minimum increases linearly from 10 µF at 1 V to 15 µF at 0.6 V with the
compensation setting for smallest output capacitance. Other compensation ranges are equivalent. See Table 9-1
for details.
10.2 Typical Application
L
V
IN
TPS62850x-Q1
0.47mH
VOUT
2.7 V - 6 V
VIN
SW
CIN
R1
CFF
2*10 mF
0603
COUT
EN
FB
2*10 mF
0603
MODE/SYNC
R2
R3
COMP/FSET
PG
GND
Figure 10-1. Typical Application
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10.2.1 Design Requirements
The design guidelines provide a component selection to operate the device within the recommended operating
conditions.
10.2.2 Detailed Design Procedure
V
OUT
æ
ö
R1
= R
-1
FB
2 × ç
è
÷
V
ø
(9)
With VFB = 0.6 V:
Table 10-2. Setting the Output Voltage
NOMINAL OUTPUT VOLTAGE VOUT
R1
R2
CFF
EXACT OUTPUT VOLTAGE
0.8 V
1.0 V
1.1 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
16.9 kΩ
20 kΩ
51 kΩ
30 kΩ
47 kΩ
68 kΩ
51 kΩ
40.2 kΩ
15 kΩ
19.6 kΩ
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
0.7988 V
1.0 V
39.2 kΩ
68 kΩ
1.101 V
1.2 V
76.8 kΩ
80.6 kΩ
47.5 kΩ
88.7 kΩ
1.5 V
1.803 V
2.5 V
3.315 V
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10.2.3 Application Curves
All plots have been taken with a nominal switching frequency of 2.25 MHz when set to PWM mode, unless
otherwise noted. The BOM is according to Table 8-1.
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
0
0.5
1
Output Current (A)
1.5
2
100m
1m
10m 100m
Output Current (A)
1
D002
D002
VOUT = 3.3 V
PWM
TA = 25°C
VOUT = 3.3 V
PFM
TA = 25°C
Figure 10-3. Efficiency versus Output Current
Figure 10-2. Efficiency versus Output Current
100
95
90
85
80
75
70
95
90
85
65
60
55
50
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
80
75
100m
1m
10m 100m
Output Current (A)
1
0
0.5
1
Output Current (A)
1.5
2
D002
D002
VOUT = 1.8 V
PFM
TA = 25°C
VOUT = 1.8 V
PWM
TA = 25°C
Figure 10-4. Efficiency versus Output Current
Figure 10-5. Efficiency versus Output Current
100
95
90
85
80
75
70
90
85
80
65
60
55
50
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
75
70
100m
1m
10m 100m
Output Current (A)
1
0
0.5
1
Output Current (A)
1.5
2
D002
D002
VOUT = 1.1 V
PFM
TA = 25°C
VOUT = 1.1 V
PWM
TA = 25°C
Figure 10-6. Efficiency versus Output Current
Figure 10-7. Efficiency versus Output Current
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90
85
80
75
70
65
60
55
50
45
90
85
80
75
70
65
60
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
40
0
0.5
1
Output Current (A)
1.5
2
100m
1m
10m
Output Current (A)
100m
1
D002
D002
VOUT = 0.6 V
PWM
TA = 25°C
VOUT = 0.6 V
PFM
TA = 25°C
Figure 10-9. Efficiency versus Output Current
Figure 10-8. Efficiency versus Output Current
3.33
3.324
3.318
3.312
3.306
3.3
3.33
3.324
3.318
3.312
3.306
3.3
3.294
3.288
3.294
3.288
3.282
3.282
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
3.276
3.27
3.276
3.27
100m
1m
10m
Output Current (A)
100m
1
2
100m
1m
10m
Output Current (A)
100m
1
2
D002
D002
VOUT = 3.3 V
PWM
TA = 25°C
VOUT = 3.3 V
PFM
TA = 25°C
Figure 10-11. Output Voltage versus Output
Current
Figure 10-10. Output Voltage versus Output
Current
1.82
1.816
1.812
1.808
1.804
1.8
1.82
1.816
1.812
1.808
1.804
1.8
1.796
1.796
1.792
1.788
1.784
1.78
1.792
1.788
1.784
1.78
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m
Output Current (A)
100m
1
2
100m
1m
10m
Output Current (A)
100m
1
2
D002
D002
VOUT = 1.8 V
PFM
TA = 25°C
VOUT = 1.8 V
PWM
TA = 25°C
Figure 10-12. Output Voltage versus Output
Current
Figure 10-13. Output Voltage versus Output
Current
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1.11
1.108
1.106
1.104
1.102
1.1
1.11
1.108
1.106
1.104
1.102
1.1
1.098
1.098
1.096
1.094
1.092
1.09
1.096
1.094
1.092
1.09
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
100m
1m
10m
Output Current (A)
100m
1
2
100m
1m
10m
Output Current (A)
100m
1
2
D002
D002
VOUT = 1.1 V
PFM
TA = 25°C
VOUT = 1.1 V
PWM
TA = 25°C
Figure 10-14. Output Voltage versus Output
Current
Figure 10-15. Output Voltage versus Output
Current
0.612
0.606
0.6045
0.603
0.6015
0.6
0.61
0.608
0.606
0.604
0.602
0.6
0.5985
0.597
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 2.7 V
0.598
VIN = 3.3 V
0.5955
0.594
VIN = 4.0 V
VIN = 5.0 V
0.596
0.594
100m
1m
10m 100m
Output Current (A)
1
2
100m
1m
10m 100m
Output Current (A)
1
2
D002
D002
VOUT = 0.6 V
PWM
TA = 25°C
VOUT = 0.6 V
PFM
TA = 25°C
Figure 10-17. Output Voltage versus Output
Current
Figure 10-16. Output Voltage versus Output
Current
VOUT = 3.3 V
VIN = 5.0 V
PFM
TA = 25°C
VOUT = 3.3 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
Figure 10-18. Load Transient Response
Figure 10-19. Load Transient Response
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VOUT = 1.8 V
VIN = 5.0 V
PFM
TA = 25°C
VOUT = 1.8 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
Figure 10-20. Load Transient Response
Figure 10-21. Load Transient Response
VOUT = 1.2 V
VIN = 5.0 V
PFM
TA = 25°C
VOUT = 1.2 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
Figure 10-22. Load Transient Response
Figure 10-23. Load Transient Response
VOUT = 1.0 V
VIN = 5.0 V
PFM
TA = 25°C
VOUT = 1.0 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
Figure 10-24. Load Transient Response
Figure 10-25. Load Transient Response
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VOUT = 0.6 V
VIN = 3.3 V
PFM
TA = 25°C
VOUT = 0.6 V
VIN = 3.3 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
IOUT = 0.2 A to 1.8 A to 0.2 A
Figure 10-26. Load Transient Response
Figure 10-27. Load Transient Response
VOUT = 3.3 V
IOUT = 0.2 A
PFM
TA = 25°C
VOUT = 3.3 V
IOUT = 2 A
PWM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
Figure 10-28. Line Transient Response
Figure 10-29. Line Transient Response
VOUT = 1.8 V
IOUT = 0.2 A
PFM
TA = 25°C
VOUT = 1.8 V
IOUT = 2 A
PWM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
Figure 10-30. Line Transient Response
Figure 10-31. Line Transient Response
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VOUT = 1.2 V
IOUT = 0.2 A
PFM
TA = 25°C
VOUT = 1.2 V
IOUT = 2 A
PWM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
Figure 10-32. Line Transient Response
Figure 10-33. Line Transient Response
VOUT = 1.0 V
IOUT = 0.2 A
PFM
TA = 25°C
VOUT = 1.0 V
IOUT = 2 A
PWM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VIN = 4.5 V to 5.5 V to 4.5 V
Figure 10-34. Line Transient Response
Figure 10-35. Line Transient Response
VOUT = 0.6 V
IOUT = 0.2 A
PFM
TA = 25°C
VOUT = 0.6 V
IOUT = 2 A
PWM
TA = 25°C
VIN = 3.0 V to 3.6 V to 3.0 V
VIN = 3.0 V to 3.6 V to 3.0 V
Figure 10-36. Line Transient Response
Figure 10-37. Line Transient Response
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VOUT = 3.3 V
VIN = 5 V
PFM
TA = 25°C
VOUT = 3.3 V
VIN = 5 V
PWM
TA = 25°C
IOUT = 2 A
IOUT = 0.2 A
Figure 10-38. Output Voltage Ripple
Figure 10-39. Output Voltage Ripple
VOUT = 1.8 V
VIN = 5 V
PFM
TA = 25°C
VOUT = 1.8 V
VIN = 5 V
PWM
TA = 25°C
IOUT = 2 A
IOUT = 0.2 A
Figure 10-40. Output Voltage Ripple
Figure 10-41. Output Voltage Ripple
VOUT = 1.2 V
VIN = 5 V
PFM
TA = 25°C
VOUT = 1.2 V
VIN = 5 V
PWM
TA = 25°C
IOUT = 2 A
IOUT = 0.2 A
Figure 10-42. Output Voltage Ripple
Figure 10-43. Output Voltage Ripple
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VOUT = 1.0 V
VIN = 5 V
PFM
TA = 25°C
VOUT = 1.0 V
VIN = 5 V
PWM
TA = 25°C
IOUT = 2 A
IOUT = 0.2 A
Figure 10-44. Output Voltage Ripple
Figure 10-45. Output Voltage Ripple
VOUT = 0.6 V
VIN = 3.3 V
PFM
TA = 25°C
VOUT = 0.6 V
VIN = 3.3 V
PWM
TA = 25°C
IOUT = 2 A
IOUT = 0.2 A
Figure 10-46. Output Voltage Ripple
Figure 10-47. Output Voltage Ripple
VOUT = 3.3 V
VIN = 5 V
PWM or PFM
CSS = 4.7 nF
TA = 25°C
IOUT = 2 A
VOUT = 1.8 V
VIN = 5 V
PWM or PFM
CSS = 4.7 nF
TA = 25°C
IOUT = 2 A
Figure 10-48. Start-Up Timing
Figure 10-49. Start-Up Timing
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VOUT = 1.2 V
VIN = 5 V
PWM or PFM
CSS = 4.7 nF
TA = 25°C
IOUT = 2 A
VOUT = 1.0 V
VIN = 5 V
PWM or PFM
CSS = 4.7 nF
TA = 25°C
IOUT = 2 A
Figure 10-50. Start-Up Timing
Figure 10-51. Start-Up Timing
VOUT = 0.6 V
VIN = 3.3 V
PWM or PFM
CSS = 4.7 nF
TA = 25°C
IOUT = 2 A
Figure 10-52. Start-Up Timing
10.3 System Examples
10.3.1 Fixed Output Voltage Versions
Versions with an internally fixed output voltage allow you to remove the external feedback voltage divider. This
not only allows you to reduce the total solution size but also provides higher accuracy as there is no additional
error caused by the external resistor divider. The FB pin needs to be tied to the output voltage directly as shown
in Figure 10-53. The application runs with an internally defined switching frequency of 2.25 MHz by connecting
COMP/FSET to GND.
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L
V
IN
TPS62850x-Q1
0.47mH
2.7V - 6V
VOUT
VIN
SW
CIN
2*10 mF
0603
EN
FB
COUT
MODE/SYNC
2*10 mF
0603
R3
COMP/FSET
PG
GND
Figure 10-53. Schematic for Fixed Output Voltage Versions
10.3.2 Synchronizing to an External Clock
The TPS62850x-Q1 can be externally synchronized by applying an external clock on the MODE/SYNC pin.
There is no need for any additional circuitry as long as the input signal meets the requirements given in the
electrical specifications. The clock can be applied / removed during operation, allowing you to switch from an
externally defined fixed frequency to power-save mode or to internal fixed frequency operation.
The value of the R CF resistor must be chosen such that the internally defined frequency and the externally
applied frequency are close to each other. This ensures a smooth transition from internal to external frequency
and vice versa.
L
V
IN
TPS62850x-Q1
0.47 mH
VOUT
2.7 V - 6 V
VIN
SW
CIN
R1
2*10 mF
0603
C
FF
EN
FB
COUT
MODE/SYNC
COMP/FSET
R2
R 3
2*10 mF
0603
fEXT
PG
GND
Figure 10-54. Schematic using External Synchronization
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VIN = 5 V
RCF = 8.06 kΩ
fEXT = 2.5 MHz
IOUT = 0.1 A
VIN = 5 V
RCF = 8.06 kΩ
fEXT = 2.5 MHz
IOUT = 0.1 A
VOUT = 1.8 V
VOUT = 1.8 V
Figure 10-55. Switching from External
Figure 10-56. Switching from External
Syncronization to Power-Save Mode (PFM)
Synchronizaion to Internal Fixed Frequency
11 Power Supply Recommendations
The TPS62850x-Q1 device family does not have special requirements for its input power supply. The output
current of the input power supply needs to be rated according to the supply voltage, output voltage, and output
current of the TPS62850x-Q1.
12 Layout
12.1 Layout Guidelines
A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore, the PCB layout of the TPS62850x-Q1 demands careful attention to ensure operation
and to get the performance specified. A poor layout can lead to issues like poor regulation (both in Section 12.2
and load), stability and accuracy weaknesses, increased EMI radiation, and noise sensitivity.
See for the recommended layout of the TPS62850x-Q1, which is designed for common external ground
connections. The input capacitor must be placed as close as possible between the VIN and GND pin.
Provide low inductive and resistive paths for loops with high di/dt. Therefore, paths conducting the switched load
current must be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for
wires with high dv/dt. Therefore, the input and output capacitance must be placed as close as possible to the IC
pins and parallel wiring over long distances and narrow traces must be avoided. Loops which conduct an
alternating current should outline an area as small as possible, as this area is proportional to the energy
radiated.
Sensitive nodes like FB need to be connected with short wires and not nearby high dv/dt signals (for example,
SW). As they carry information about the output voltage, they must be connected as close as possible to the
actual output voltage (at the output capacitor). The FB resistors, R1 and R2, must be kept close to the IC and be
connected directly to the pin and the system ground plane.
The package uses the pins for power dissipation. Thermal vias on the VIN and GND pins help to spread the heat
into the pcb.
The recommended layout is implemented on the EVM and shown in the TPS628502EVM-092 Evaluation
Module User's Guide.
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12.2 Layout Example
COUT
L
V
OUT
GND
CIN
R2
U1
R4
V
IN
GND
Figure 12-1. Example Layout
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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12-Nov-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS6285010MQDRLRQ1
TPS628501QDRLRQ1
TPS6285020MQDRLRQ1
TPS628502QDRLRQ1
PREVIEW
PREVIEW
PREVIEW
PREVIEW
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
DRL
DRL
DRL
DRL
8
8
8
8
4000
4000
4000
4000
TBD
TBD
TBD
Call TI
Call TI
Call TI
SN
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Call TI
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
200Q
XPS628501QDRLRQ1
XPS628502QDRLRQ1
ACTIVE
ACTIVE
SOT-5X3
SOT-5X3
DRL
DRL
8
8
4000
4000
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
TBD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Nov-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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