TPS629203 [TI]

TPS629210 3-V to 17-V, 1-A Low IQ Buck Converter in SOT583 Package;


型号：	TPS629203
厂家：	TEXAS INSTRUMENTS
描述：	TPS629210 3-V to 17-V, 1-A Low IQ Buck Converter in SOT583 Package
文件：	总32页 (文件大小：1608K)
中文：	中文翻译
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TPS629210

SLVSGE0A – AUGUST 2021 – REVISED SEPTEMBER 2021

TPS629210 3-V to 17-V, 1-A Low I_QBuck Converter in SOT583 Package

1 Features

3 Description

•

High-efficiency DCS-Control^™topology

Low quiescent current: 4 µA typical

Dynamically selectable forced PWM or auto power

save mode operations

2.5-MHz or 1.0-MHz selectable switching

frequencies

The TPS6292xx family of devices are highly efficient,

small, and highly flexible synchronous step-down DC-

DC converters that are easy to use. A wide 3-V

to 17-V input voltage range supports a wide variety

of systems powered from either 12-V, 5-V, or 3.3-V

supply rails, or single-cell or multi-cell Li-Ion batteries.

The TPS629210 can be configured to run at either

2.5-MHz or 1-MHz in a Forced PWM mode or a

variable frequency mode. In Auto PFM mode, the

device automatically transitions to Power Save mode

at light loads to maintain high efficiency. The low

4-µA typical quiescent current also provides high

efficiency down to the smallest loads. TI's AEE mode

holds a high conversion efficiency through the whole

operation range without the need of using different

inductors by automatically adjusting the switching

frequency based on input and output voltages. In

addition to selecting the switching frequency behavior,

the MODE/Smart-CONFIG input pin can also be used

to select between different combinations of external/

internal feedback dividers and enabling/disabling the

output voltage discharge capability. In the internal

feedback configuration, a resistor between the FB/

VSET pin and GND can be used to select between

18 different output voltage options (see Table 8-2).

•

Output current up to 1 A

R_DSON: 300-mΩ high-side, 100-mΩ low-side

Output voltage accuracy of ± 1% over temperature

Configurable output voltage options:

– V_FBexternal divider: 0.6 V to 5.5 V

– VSET internal divider:

•

18 options between 0.4 V and 5.5 V

•

No external bootstrap capacitor required

Output overcurrent and overtemperature protection

100% duty cycle mode

Precise enable input

Power-good output

Selectable active output discharge

Pin-to-pin compatible with TPS629206 and

TPS629203 devices

•

0.5-mm pitch 8-pin SOT583 package

2 Applications

•

VIN

Appliances

Building automation

Digital still camera

Electronic point of sale (ePOS)

Grid infrastructure

Modems

Device Information

PART NUMBER

PACKAGE⁽¹⁾

BODY SIZE (NOM)

TPS629210

SOT583 (8)

1.60 mm x 2.10 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

PC and notebooks

Personal electronics

VOUT

0.4V œ 5.5V

2.2 µH

3V œ 17V

VIN

22 ꢀF

4.7 ꢀF

VOS

FB/

VSET

MODE/

S-CONF

GND

Efficiency vs Output Current

(12 V to 3.3 V at 2.5 MHz)

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change

without notice.

TPS629210

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings ....................................... 5

7.2 ESD Ratings .............................................................. 5

7.3 Recommended Operating Conditions ........................5

7.4 Thermal Information ...................................................6

7.5 Electrical Characteristics ............................................6

8 Detailed Description........................................................8

8.1 Overview.....................................................................8

8.2 Functional Block Diagram...........................................8

8.3 Feature Description.....................................................9

8.4 Device Functional Modes..........................................13

9 Application and Implementation..................................16

9.1 Application Information............................................. 16

9.2 Typical Application.................................................... 19

10 Power Supply Recommendations..............................20

11 Layout...........................................................................21

11.1 Layout Guidelines................................................... 21

11.2 Layout Example...................................................... 21

11.3 Thermal Considerations..........................................22

12 Device and Documentation Support..........................23

12.1 Device Support....................................................... 23

12.2 Receiving Notification of Documentation Updates..23

12.3 Support Resources................................................. 23

12.4 Trademarks.............................................................23

12.5 Electrostatic Discharge Caution..............................23

12.6 Glossary..................................................................23

13 Mechanical, Packaging, and Orderable

Information.................................................................... 23

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (August 2021) to Revision A (September 2021)

Page

•

Switched pin 6 and 7 in Table 6-1 ......................................................................................................................4

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5 Device Comparison Table

INPUT

VOLTAGE

DEVICE NUMBER

OUTPUT CURRENT

PWM MODE

V_OADJUST

MARKING

TPS629203

TPS629206

TPS629210

0 A – 0.3 A

0 A – 0.6 A

0 A – 1 A

3 V – 17 V

Selectable Auto PWM/PFM or Externaly programmable

Forced PWM or 18 internal options

T210

T206

T203

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6 Pin Configuration and Functions

Figure 6-1. TPS629210 Pinout

Table 6-1. Pin Functions

I/O

DESCRIPTION

NAME

NO.

Depending on device configuration (see Section 8.3.1)

•

FB: Voltage feedback input. Connect a resistive output voltage divider to this pin.

FB/VSET

VSET: Output voltage setting pin. Connect a resistor to GND to choose the output

voltage according to Table 8-2.

Open-drain power-good output

VOS

Output voltage sense pin. Connect directly to the positive pin of the output capacitor.

Switch pin of the converter. Connected to the internal power switches

Ground pin

GND

Power supply input. Make sure the input capacitor is connected as close as possible

between the VIN pin and GND.

VIN

Enable/Disable pin including a threshold comparator. Connect to logic low to disable the

device. Pull high to enable the device. Do not leave this pin unconnected.

MODE/S-

CONF

Device Mode selection (Auto PFM/PWM or Forced PWM operation) and Smart-CONFIG pin.

Connect a resistor to configure the device according to Table 8-1.

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7 Specifications

7.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted)⁽¹⁾

MIN

0.3

MAX

UNIT

Voltage⁽²⁾

Current

T_stg

VIN, EN, PG, MODE/S-CONF

SW (DC)

–0.3

–3.0

–0.3

V_IN+ 0.3

SW (AC, less than 10 ns)⁽³⁾

FB/VSET, VOS

°C

Storage temperature

–65

150

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.

If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltage values are with respect to network ground terminal.

(3) While switching

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001, all pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over operating junction temperature range (unless otherwise noted)

MIN

3.0

0.4

2.5

NOM

MAX

UNIT

V_I

Input voltage range

V_O

Output voltage range

Effective input capacitance

Effective output capacitance⁽¹⁾

Output inductance

5.5

C_I

4.7

µF

µH

C_O

200 ⁽¹⁾

4.7⁽³⁾

2.2⁽²⁾

I_OUT

I_{SINK_PG}

T_J

Output current

Sink current at PG pin

Junction temperature ⁽⁴⁾

°C

–40

125

(1) This is for capacitors directly at the output of the device. More capacitance is allowed if there is a series resistance associated to the

capacitor.

(2) Nominal inductance value

(3) Larger values of inductance can be used to reduce the ripple current, but they may have a negative impact on efficiency and the

overvall transient responce.

(4) Operating lifetime is derated at junction temperatures greater than 150°C.

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UNIT

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7.4 Thermal Information

TPS629210

THERMAL METRIC⁽¹⁾

SOT583 8 PIN

JEDEC PCB

TPS6292xxEVM-xxx

R_θJA

R_θJB

Junction-to-ambient thermal resistance

Junction-to-board thermal resistance

131.7

38.5

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

V_I= 3 V to 17 V, T_J= –40°C to + 125°C, Typical values at V_I= 12 V and T_A= 25 °C,unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY

Operating quiescent current (Power

Save mode)

I_OUT= 0 mA, T_J= –40°C to 125°C,

device not switching

I_Q

µA

Operating quiescent current (PWM

mode)

V_IN= 12 V, V_OUT= 1.2 V; I_OUT= 0

mA, , device switching

I_Q;PWM

I_SD

V_UVLO

Shutdown current into VIN pin

Undervoltage lockout

EN = 0 V, T_J= –40°C to 85°C

V_INrising

0.3

2.925

2.775

230

6.5

3.0

µA

2.85

2.7

Undervoltage lockout

V_INfalling

2.85

Undervoltage lockout hysteresis

CONTROL AND INTERFACE

I_LKG

EN input leakage current

EN = HIGH, T_J= –40°C to 125°C

100

High-level input voltage at the

MODE/S-CONF pin

V_IH;MODE

1.0

Low-level input voltage at the

MODE/S-CONF pin

V_IL;MODE

0.15

Thermal shutdown threshold

T_Jrising

T_Jfalling

170

T_SD

°C

Thermal shutdown hysteresis

V_IH

V_IL

High-level input voltage at the EN pin

Low-level input voltage at the EN pin

0.97

0.87

94%

89%

1.0

1.03

0.93

98%

96%

0.9

V_FBrising, referenced to V_FBnominal

V_FBfalling, referenced to V_FBnominal

hysteresis

96%

92%

V_PG

Power-good threshold

V_{PG_HYS}

V_PG,OL

I_PG,LKG

t_PG,DLY

Power-good threshold hysteresis

Low-level output voltage at the PG pin I_SINK= 1 mA

0.4

Input leakage current into the PG pin

Power-good delay time

V_PG= 5 V, T_J= –40°C to 125°C

100

µs

POWER SWITCHES

I_LKG;SWLeakage current into the SW pin

EN = 0 V, V_SW= V_OS= 5.5 V, T_J=

–40°C to 125°C

µA

High-side FET on resistance

Low-side FET on resistance

High-side FET current limit

Low-side FET current limit

Low-side FET sink current limit

Minimum on time

300

100

1.8

1.6

0.9

R_DS;ON

mΩ

1.4

1.2

0.7

2.2

2.0

1.2

I_LIM

I_LIM;SINK

T_ON(MIN)

f_SW

Switching frequency

1.0-MHz selection

1.0

100

MHz

I_LKG;VOS

OUTPUT

Leakage current into the VOS pin

800

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V_I= 3 V to 17 V, T_J= –40°C to + 125°C, Typical values at V_I= 12 V and T_A= 25 °C,unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

–0.5%

–1%

TYP

MAX

+0.5%

+1%

UNIT

VSET configuration selected, T_J=

25°C

V_O

Output voltage regulation

V_O

Output voltage regulation

VSET configuration selected

Adjustable configuration selected

FB option selected

V_FB

I_FB

Feedback regulation voltage

Feedback voltage regulation

Input leakage current into the FB pin

0.6

–1%

+1%

100

Adjustable configuration, V_FB= 0.6 V

µs

I_O= 0 mA, time from EN rising

edge until start switching, external FB

Configuration selected

Start-up delay time

500

1500

1800

T_delay

I_O= 0 mA, time from EN rising

edge until start switching, VSET

configuration selected

750

µs

I_O= 0 mA after T_delay, from first

switching pulse until target V_O

T_SS

Soft-start time

600

7.5

700

µs

Ω

Discharge = ON option selected, EN =

LOW,

R_DISCH

Active discharge resistance

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8 Detailed Description

8.1 Overview

The TPS629210 synchronous switched mode power converter is based on DCS-Control (Direct Control with

Seamless Transition into Power Save mode), an advanced regulation topology that combines the advantages

of hysteretic, voltage mode, and current mode control. This control loop takes information about output voltage

changes and feeds it directly to a fast comparator stage. It sets the switching frequency, which is constant for

steady state operating conditions, and provides immediate response to dynamic load changes. To get accurate

DC load regulation, a voltage feedback loop is used. The internally compensated regulation network achieves

fast and stable operation with small external components and low-ESR capacitors.

8.2 Functional Block Diagram

VIN

V_I

Ref

1.0V

HS Limit

V_O

Internal/External

Divider

Device Control

& Logic

Power Control

/VSET

Power Save Mode

Forced PWM

Resistor-to-

Digital

Gate

Driver

Smart-Enable

Ref-System

UVLO

100% Mode

V_FB

Start-up Handling

Smart-CONFIG

PG-Control

Thermal Shutdown

Resistor-to-

Digital

MODE

/S-CONF

LS Limit

MODE Detection

V_O

Direct

Control

V_I

VOS

V_F

T_ONtimer

V_O

Device

Control

V_REF

DCS-Control

GND

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8.3 Feature Description

8.3.1 Mode Selection and Device Configuration (MODE/S-CONF Pin)

The MODE/S-CONF pin is an input with two functions. It can be used to customize the device behavior in two

ways:

1. Select the device mode (Forced PWM or Auto PFM/PWM operation) traditionally with a HIGH- or LOW-

level.

2. Select the device configuration (switching frequency, internal/external feedback, output discharge, and

PFM/PWM mode) by connecting a single resistor to this pin.

The device interprets this pin during its start-up sequence after the internal OTP readout and before it starts

switching in soft start. If the device reads a HIGH- or LOW-level, the Dynamic Mode Change is active and

PFM/PWM mode can be changed during operation. If the device reads a resistor value, there is no further

interpretation during operation and the device mode or other configurations cannot be changed afterwards.

EN & UVLO

Precise

Enable

detection

PG -> High

Switching

Operation

OTP

Readout

S-CONF

Readout

VSET

Readout

Softstart

Resistor-to-Digitial

readout &

interpretation

No interpretation of

MODE/S-CONF or VSET

MODE-Pin toggling detection

VOUT

Figure 8-1. Interpretation of S-CONF and VSET Flow

Table 8-1. Smart-CONFIG Setting Table

DYNAMIC

MODE

CHANGE

M ODE/S-CONF LEVEL OR

RESISTOR VALUE [Ω] ⁽¹⁾

FB/VSET

OUTPUT

DISCHARGE

MODE (AUTO OR FORCED

PWM)

F_SW(MHz)

Setting Options by Level

GND

HIGH (>1.8V)

Setting Options by Resistor

7.50 k

external FB

up to 2.5⁽²⁾

2.5

yes

Auto PFM/PWM with AEE

Forced PWM

Active

external FB

VSET

up to 2.5⁽²⁾

Auto PFM/PWM with AEE

Forced PWM

9.31 k

2.5

11.50 k

yes

Auto PFM/PWM

Forced PWM

14.30 k

17.80 k

Auto PFM/PWM

Forced PWM

22.10 k

27.40 k

up to 2.5⁽²⁾

yes

Auto PFM/PWM with AEE

Forced PWM

not active

34.00 k

VSET

2.5

42.20 k

VSET

up to 2.5⁽²⁾

Auto PFM/PWM with AEE

Forced PWM

52.30 k

VSET

2.5

64.90 k

VSET

yes

Auto PFM/PWM

Forced PWM

80.60 k

VSET

100.00 k

VSET

Auto PFM/PWM

Forced PWM

124.00 k

VSET

(1) E96 Resistor Series, 1% accuracy, temperature coefficient better or equal than ±200 ppm/°C

(2) F_SWwill vary based on V_INand V_OUT. See Section 8.4.2 for more details.

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8.3.2 Adjustable V_OOperation (External Voltage Divider)

If the device is configured to operate in classical adjustable V_Ooperation, the FB/VSET pin is used as

the feedback pin and needs to sense V_Othrough an external divider network. Figure 8-2 shows the typical

schematic for this configuration.

VIN

3V œ 17V

VOUT

0.6V œ 5.5V

2.2 µH

VIN

22 ꢀF

4.7 ꢀF

VOS

FB/

VSET

MODE/

S-CONF

GND

Figure 8-2. Adjustable V_OOperation Schematic

8.3.3 Selectable V_OOperation (VSET and Internal Voltage Divider)

If the device is configured to VSET operation, the device interprets the VSET pin value following the MODE/

S-CONF readout (see Figure 8-3). There is no further interpretation of the VSET pin during operation and the

output voltage cannot be changed afterwards without toggling the EN pin.

Figure 8-3 shows the typical schematic for this configuration, where V_Ois directly sensed at the VOS terminal of

the device. V_Ois sensed only through the VOS pin by an internal resistor divider. The target V_Ois programmed

by an external resitor connected between VSET and GND (see Table 8-2).

VIN

3V œ 17V

VOUT

0.4V œ 5.5V

2.2 µH

VIN

22 ꢀF

4.7 ꢀF

VOS

FB/

VSET

MODE/

S-CONF

GND

Figure 8-3. Selectable V_OOperation Schematic

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Table 8-2. VSET Selection Table

VSET-#

RESISTOR VALUE [Ω]⁽¹⁾

TARGET V_O[V]

GND

1.2

0.4

0.6

0.8

0.85

1.0

1.1

1.25

1.3

1.35

1.8

1.9

2.5

3.8

5.0

5.1

5.5

3.3

4.87 k

6.04 k

7.50 k

9.31 k

11.50 k

14.30 k

17.80 k

22.10 k

27.40 k

34.00 k

42.20 k

52.30 k

64.90 k

80.60 k

100.00 k

124.00 k

249.00 k or larger/open

(1) E96 Resistor Series, 1% accuracy, temperature coefficient better or equal to ±200 ppm/°C

8.3.4 Smart Enable with Precise Threshold

The voltage applied at the Enable pin of the TPS629210 is compared to a fixed threshold rising voltage. This

allows the user to drive the pin by a slowly changing voltage and enables the use of an external RC network to

achieve a power-up delay.

The Precise Enable input allows the use of a user programmable undervoltage lockout by adding a resistor

divider to the input of the Enable pin.

The enable input threshold for a falling edge is lower than the rising edge threshold. The TPS629210 starts

operation when the rising threshold is exceeded. For proper operation, the EN pin must be terminated and must

not be left floating. Pulling the EN pin low forces the device into shutdown. In this mode, the internal high-side

and low-side MOSFETs are turned off and the entire internal control circuitry is switched off.

An internal resistor pulls the EN pin to GND and avoids the pin to be floating. This prevents an uncontrolled

start-up of the device in case the EN pin cannot be driven to a low level safely. With EN low, the device is in

Shutdown mode. The device is turned on with EN set to a high level. The pulldown control circuit disconnects the

pulldown resistor on the EN pin once the internal control logic and the reference have been powered up. With

EN set to a low level, the device enters Shutdown mode and the pulldown resistor is activated again.

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8.3.5 Power Good (PG)

The TPS629210 has a built-in Power-Good (PG) feature to indicate whether the output voltage has reached its

target and the device is ready. The PG signal can be used for start-up sequencing of multiple rails. The PG pin

is an open-drain output that requires a pullup resistor to any voltage up to the recommended input voltage level.

PG is low when the device is turned off due to EN, UVLO (undervoltage lockout), or thermal shutdown. V_INmust

remain present for the PG pin to stay low.

If the power-good output is not used, it is recommended to tie to GND or leave open.

Table 8-3. Power Good Indicator Functional Table

LOGIC SIGNALS

PG STATUS

V_I

EN PIN

THERMAL SHUTDOWN

V_O

V_Oon target

High Impedance

LOW

HIGH

V_O< target

V_I> UVLO

YES

LOW

UVLO < V_I< 1.8 V

V_I< 1.8 V

LOW

Undefined

8.3.6 Undervoltage Lockout (UVLO)

If the input voltage drops, the undervoltage lockout prevents mis-operation of the device by switching off both

the power FETs. The device is fully operational for voltages above the rising UVLO threshold and turns off if the

input voltage trips below the threshold for a falling supply voltage.

8.3.7 Current Limit and Short Circuit Protection

The TPS629210 is protected against overload and short circuit events. If the inductor current exceeds the

current limit I_{LIM_HS}, the high-side switch is turned off and the low-side switch is turned on to ramp down the

inductor current. The high-side FET turns on again only if the current in the low-side FET has decreased below

the low-side current limit threshold I_{LIM_LS}

Due to internal propagation delay, the actual current can exceed the static current limit during that time. The

dynamic current limit is given in Equation 1.

Ipeak(typ) = ILIMH

´tPD

(1)

where:

•

I_LIMHis the static current limit as specified in the electrical characteristics

L is the effective inductance at the peak current

V_Lis the voltage across the inductor (V_IN– V_OUT

)

t_PDis the internal propagation delay of typically 50 ns

The current limit can exceed static values, especially if the input voltage is high and very small inductances are

used. The dynamic high-side switch peak current can be calculated as follows:

V IN - VO U T

peak ( typ ) = IL IM H

´ 50 ns

(2)

8.3.8 Thermal Shutdown

The junction temperature T_Jof the device is monitored by an internal temperature sensor. If T_Jrises and

exceeds the thermal shutdown threshold T_SD, the device shuts down. Both the high-side and low-side power

FETs are turned off and PG goes low. When T_Jdecreases below the hysteresis, the converter resumes normal

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operation, beginning with soft start. During a PFM skip pause, the thermal shutdown feature is not active. A

shutdown or restart is only triggered during a switching cycle. See Section 8.4.3.

8.4 Device Functional Modes

8.4.1 Forced Pulse Width Modulation (PWM) Operation

The TPS629210 has two operating modes: Forced PWM mode discussed in this section, and Auto PFM/PWM

mode as discussed in Section 8.4.3.

With the MODE/S-CONF pin set to Forced PWM mode, the device operates with pulse width modulation in

continuous conduction mode (CCM) with a nominal switching frequency of either 1.0 MHz or 2.5 MHz. The

frequency variation in PWM is controlled and depends on V_IN, V_OUT, and the inductance. The on time in forced

PWM mode is given by Equation 3.

V_OUT

V_IN

TON =

f_sw

(3)

For very small output voltages, an absolute minimum on time of about 50 ns is kept to limit switching losses. The

operating frequency is thereby reduced from its nominal value, which keeps efficiency high.

8.4.2 AEE (Automatic Efficiency Enhancement)

When the MODE/S-CONF pin is configured for AEE mode, the TPS629210 provides the highest efficiency over

the entire input voltage and output voltage range by automatically adjusting the switching frequency of the

converter. The efficiency of a switched mode converter is determined by the power losses during the conversion.

Traditionally, the efficiency decreases if V_OUTdecreases, V_INincreases, or both. To keep the efficiency high

over the entire duty cycle range (V_OUT/V_INratio), the switching frequency is adjusted while maintaining the ripple

current. Equation 4 and Equation 5 show the typical relationships between the on time and switching frequency

and the input and output voltages:

VIN

TON =100´

[^ns]

VIN -VOUT

(4)

(5)

V_IN-V_OUT

V_IN

F (MHz) =10ìV_OUT

Equation 6 can be used to calculate the inductor ripple current in AEE mode:

V_OUT

1-(

)

1- D

Lì f_SW

V_IN

DI_L=V_OUTì(

) =V_OUTì(

)

Lì f_SW

(6)

Efficiency increases by decreasing switching losses and preserving high efficiency for varying duty cycles, while

the ripple current amplitude remains low enough to deliver the full output current without reaching current limit.

The AEE feature provides an efficiency enhancement for various duty cycles, especially for lower V_OUTvalues,

where fixed frequency converters suffer from a significant efficiency drop. Furthermore, this feature compensates

for the very small duty cycles of high V_INto low V_OUTconversion, which limits the control range in other

topologies.

The TPS629210 operates in AEE mode as long as the output current is higher than half the ripple current of

the inductor. To maintian high efficiency at light loads, the device enters Power Save mode at the boundary to

discontinous mode (DCM), which happens when the output current becomes smaller than half the inductor ripple

current.

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8.4.3 Power Save Mode Operation (Auto PFM/PWM)

When the MODE/S-CONF pin is configured for Auto PFM/PWM mode, Power Save mode is allowed. The device

operates in PWM mode as long the output current is higher than half the ripple current of the inductor. To

maintain high efficiency at light loads, the device enters Power Save mode at the boundary to discontinuous

conduction mode (DCM). This happens if the output current becomes smaller than half the ripple current of the

inductor. Power Save mode is entered seamlessly to make sure there is high efficiency in light-load operation.

The device remains in Power Save mode as long as the inductor current is discontinuous.

In Power Save mode, the switching frequency decreases linearly with the load current maintaining high

efficiency. The transition into and out of Power Save mode is seamless in both directions.

The TPS629210 adjusts the on time (TON) in Power Save mode, depending on the input voltage and the output

voltage to maintain highest efficiency. The on time, in steady-state operation, can be estimated as:

With the MODE/S-CONF pin set to 1.0-MHz operation:

VOUT

610 (µO) =

8+0

(7)

(8)

With the MODE/S-CONF pin set to 2.5-MHz operation:

VIN

TON =100´

[^ns]

VIN -VOUT

Using TON, the typical peak inductor current in Power Save mode is approximated by:

(^{V IN}- ^{VO U T})_{´ TO N}

IL P SM ( peak )

(9)

The output voltage ripple in Power Save mode is given by Equation 10:

²æ

L´VIN

DV =

200´C VIN -VOUT VOUT

(10)

When V_INdecreases to typically 15% above V_OUT, the device does not enter Power Save mode, regardless of

the load current. The device maintains output regulation in PWM mode.

8.4.4 100% Duty-Cycle Operation

The duty cycle of the buck converter operated in PWM mode is given in Equation 11.

VOUT

& =

8+0

(11)

The duty cycle increases as the input voltage comes close to the output voltage and the off time of the

high-side switch gets smaller. When the minimum off time of typically 80 ns is reached, the TPS629210 scales

down its switching frequency while it approaches 100% mode. In 100% mode, it keeps the high-side switch

on continuously as long as the output voltage is below the internal set point. This allows the conversion of

small input to output voltage differences. For example, getting the longest operation time of battery-powered

applications. In 100% duty cycle mode, the low-side FET is switched off.

The minimum input voltage to maintain output voltage regulation, depending on the load current and the output

voltage level, can be calculated as:

VIN(min) =VOUT + ^IOUT(^RDS(on)+ R

)

(12)

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where:

•

I_OUTis the output current

R_DS(on)is the on-state resistance of the high-side FET

R_Lis the DC resistance of the inductor used

8.4.5 Output Discharge Function

The purpose of the discharge function is to make sure there is a defined down-ramp of the output voltage when

the device is being disabled but also to keep the output voltage close to 0 V when the device is off. The output

discharge feature is only active once the TPS629210 has been enabled at least once since the supply voltage

was applied. The internal discharge resistor is connected to the VOS pin. The discharge function is enabled as

soon as the device is disabled (EN pin = low), in thermal shutdown, or in undervoltage lockout. The minimum

supply voltage required for the discharge function to remain active typically is 2 V.

8.4.6 Starting into a Pre-Biased Load

The TPS629210 is capable of starting into a pre-biased output. The device only starts switching when the

internal Soft-Start ramp is equal or higher than the feedback voltage. If the voltage at the feedback pin is biased

to a higher voltage than the nominal value, the TPS629210 does not start switching unless the voltage at the

feedback pin drops to the target.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and

TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

9.1.1 External Component Selection

The external components have to fulfill the needs of the application, but also the stability criteria of the control

loop of the device. The TPS629210 is optimized to work within a range of external components.

9.1.1.1 Programming the Output Voltage

The output voltage of the TPS629210 is adjustable. It can be programmed for output voltages from 0.6 V to 5.5

V, using a resistor divider from VOUT to GND. The voltage at the FB pin is regulated to 600 mV. The value of the

output voltage is set by the selection of the resistor divider from Table 9-4. It is recommended to choose resistor

values which allow a current of at least 2 μA, meaning the value of R2 should not exceed 300 kΩ. Lower resistor

values are recommended for highest accuracy and most robust design.

VOUT

= R²´

-1

VFB

(13)

where

VFB = 0.6 V

9.1.1.2 Inductor Selection

•

The TPS629210 is designed for a nominal 2.2-µH inductor. Larger values can be used to achieve a lower

inductor current ripple but they can have a negative impact on efficiency and transient response. Smaller values

than 2.2 µH will cause a larger inductor current ripple, which causes larger negative inductor current in Forced

PWM mode at low or no output current. Therefore, they are not recommended at large voltages across the

inductor as it is the case for high input voltages and low output voltages. With low output current in Forced PWM

mode, this causes a larger negative inductor current peak that can exceed the negative current limit. At low or

no output current and small inductor values, the output voltage can therefore not be regulated any more. More

detailed information on further LC combinations can be found in Optimizing the TPS62130/40/50/60 Output Filter

Application Report.

The inductor selection is affected by several effects like the following:

•

Inductor ripple current

Output ripple voltage

PWM-to-PFM transition point

Efficiency

In addition, the inductor selected has to be rated for appropriate saturation current and DC resistance (DCR).

Equation 14 calculates the maximum inductor current.

DI_L(max)

I_L(max)= I_OUT(max)

(14)

VIN(max)

DIL(max)

´100ns

(min)

(15)

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where:

•

I_L(max) is the maximum inductor current

ΔI_Lis the peak-to-peak inductor ripple current

L(min) is the minimum effective inductor value

Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation

current of the inductor needed. It is recommended to add a margin of about 20%. A larger inductor value is

also useful to get lower ripple current, but increases the transient response time and size as well. The following

inductors have been used with the TPS629210 and are recommended for use:

Table 9-1. List of Inductors

DIMENSIONS

TYPE

INDUCTANCE [µH]

DCR [mΩ] CURRENT [A]⁽¹⁾

MANUFACTURER

[L×B×H] mm

2.5 × 2.0 × 1.2

3.5 × 3.2 × 3

4 × 4 × 2.1

DFE252012PD-2R2M

XGL3530-222ME

XGL4020-222ME

XGL4020-472ME

2.2 µH, ±20%

2.2 μH, ±20%

2.2 µH, ±20%

4.7 µH, ±20%

2.8

4.0

6.2

4.1

muRata

Coilcraft

19.5

4 × 4 × 2.1

(1) I_SATat 30% drop

The inductor value also determines the load current at which Power Save mode is entered:

I_{load(PSM )}

DI_L

(16)

9.1.1.3 Capacitor Selection

9.1.1.3.1 Output Capacitor

The recommended value for the output capacitor is 22 µF. The architecture of the TPS629210 allows the use

of tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low

output voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get

narrow capacitance variation with temperature, it is recommended to use X7R or X5R dielectric. Using a higher

value has advantages like smaller voltage ripple and a tighter DC output accuracy in Power Save mode (see

Optimizing the TPS62130/40/50/60 Output Filter Application Report).

In Power Save mode, the output voltage ripple depends on the following:

•

Output capacitance

ESR

ESL

Peak inductor current

Using ceramic capacitors provides small ESR, ESL, and low ripple. The output capacitor needs to be as close as

possible to the device.

For large output voltages, the DC bias effect of ceramic capacitors is large and the effective capacitance has to

be observed.

9.1.1.3.2 Input Capacitor

For most applications, 4.7 µF nominal is sufficient and is recommended, though a larger value reduces input

current ripple further. The input capacitor buffers the input voltage for transient events and also decouples the

converter from the supply. A low-ESR multilayer ceramic capacitor (MLCC) is recommended for best filtering and

should be placed between VIN and GND as close as possible to those pins.

Table 9-2. List of Capacitors

TYPE

NOMINAL CAPACITANCE [µF]

VOLTAGE RATING [V]

SIZE

1206

MANUFACTURER

C3216X7R1E475K160AC

C3216X7R1E106K160AC

4.7

TDK

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9.1.1.4 Output Filter and Loop Stability

The TPS629210 is internally compensated to be stable with L-C filter combinations corresponding to a corner

frequency to be calculated with Equation 17:

f_LC

2p L × C

(17)

The LC output filters inductance and capacitance have to be considered together, creating a double pole,

responsible for the corner frequency of the converter. Table 9-3 can be used to simplify the output filter

component selection.

Proven nominal values for inductance and ceramic capacitance are given in Table 9-3 and are recommended

for use. Different values can work, but care has to be taken on the loop stability which is affected. More

information including a detailed LC stability matrix can be found in Optimizing the TPS62130/40/50/60 Output

Filter Application Report.

Table 9-3. Recommended LC Output Filter Combinations

4.7 µF⁽²⁾

10 µF⁽²⁾

22 µF⁽²⁾

47 µF⁽²⁾

100 µF⁽²⁾

200 µF⁽²⁾

(1)

(3)

2.2 µH

4.7 µH

√

(1) This LC combination is the standard value and recommended for most applications.

(2) These values are nominal values, and the effective capcitance was considered to vary by +20% and –50%.

(3) Output capacitance needs to have a ESR of ≥ 10 mΩ for stable operation

Although the TPS629210 is stable without the pole and zero being in a particular location, an external

feedforward capacitor can also be added to adjust their location based on the specific needs of the application.

This can provide better performance in Power Save mode, improved transient response, or both.

A more detailed discussion on the optimization for stability versus transient response can be found in

the Optimizing Transient Response of Internally Compensated DC-DC Converters Application Report and

Feedforward Capacitor to Improve Stability and Bandwidth of TPS621/821-Family Application Report.

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9.2 Typical Application

2.2 µH

VIN

3V œ 17V

VOUT

0.6V œ 5.5V

VIN

VOS

22 ꢀF

4.7 ꢀF

FB/

VSET

MODE/

S-CONF

GND

Figure 9-1. Typical Application Setup

Table 9-4. List of Components

REFERENCE

DESCRIPTION

MANUFACTURER

17-V, 1-A Step-Down Converter

2.2-µH inductor

TPS629210; Texas Instruments

XGL3530-222; Coilcraft

CIN

COUT

4.7 µF, 25 V, Ceramic, 1206

22 µF, 6.3 V, Ceramic, 0805

C3216X7R1E475K160AC, TDK

GCM21BD70J226ME36L, MuRata

Depending on V_OUT; see Section 9.1.1.1

Depending on device setting, see Section 8.3.1

Standard 1% metal film

9.2.1 Design Requirements

The design guidelines provide a component selection to operate the device within the recommended operating

conditions.

9.2.2 Detailed Design Procedure

VOUT

= R²´

-1

VFB

(18)

With VFB = 0.6 V:

Table 9-5. Setting the Output Voltage

NOMINAL OUTPUT VOLTAGE

EXACT OUTPUT VOLTAGE

0.8 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

5 V

51 kΩ

150 kΩ

130 kΩ

100 kΩ

237 kΩ

165 kΩ

137 kΩ

84.5 kΩ

0.804 V

1.200 V

1.500 V

1.803 V

2.502 V

3.311 V

4.995 V

130 kΩ

150 kΩ

475 kΩ

523 kΩ

619 kΩ

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10 Power Supply Recommendations

The power supply to the TPS629210 needs to have a current rating according to the supply voltage, output

voltage, and output current of the TPS629210.

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11 Layout

11.1 Layout Guidelines

A proper layout is critical for the operation of a switched mode power supply, even more so at high switching

frequencies. Therefore, the PCB layout of the TPS629210 demands careful attention to make sure proper

operation and to get the performance specified. A poor layout can lead to issues like the following:

•

Poor regulation (both line and load)

Stability and accuracy weaknesses

Increased EMI radiation

Noise sensitivity

See Figure 11-1 for the recommended layout of the TPS629210, which is designed for common external ground

connections. The input capacitor should be placed as close as possible between the VIN and GND pin of the

TPS629210.

Provide low inductive and resistive paths for loops with high di/dt. Therefore, paths conducting the switched load

current should be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes)

for wires with high dv/dt. Therefore, the input and output capacitance should be placed as close as possible to

the IC pins and parallel wiring over long distances as well as narrow traces should be avoided. Loops which

conduct an alternating current should outline an area as small as possible, as this area is proportional to the

energy radiated.

Sensitive nodes like FB and VOS need to be connected with short wires and not nearby high dv/dt signals

(for example, SW). As they carry information about the output voltage, they should be connected as close as

possible to the actual output voltage (at the output capacitor). The FB resistors, R1 and R2, should be kept

close to the IC and connect directly to those pins and the system ground plane. The same applies for the

S-CONFIG/MODE and VSET programming resitors.

The package uses the pins for power dissipation. Thermal vias on the VIN, GND, and SW pins help to spread

the heat through the PCB.

In case any of the digital inputs (EN, VSET or MODE) need to be tied to the input supply voltage at VIN, the

connection must be made directly at the input capacitor as indicated in the schematics.

The recommended layout is implemented on the EVM and shown in the TPS629210EVM-Q1 User's Guide).

11.2 Layout Example

GND

VOUT

GND

VIN

VOS

S-CONFIG

VIN

Figure 11-1. TPS629210 Layout

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11.3 Thermal Considerations

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires

special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added

heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-

dissipation limits of a given component.

The following are basic approaches for enhancing thermal performance:

•

Improving the power dissipation capability of the PCB design, for example, increasing copper thickness,

thermal vias, number of layers

Introducing airflow in the system

For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics of

Linear and Logic Packages Using JEDEC PCB Designs Application Report and Semiconductor and IC Package

Thermal Metrics Application Report.

The TPS629210 is designed for a maximum operating junction temperature (T_J) of 150°C. Therefore, the

maximum output power is limited by the power losses that can be dissipated over the actual thermal resistance,

given by the package and the surrounding PCB structures. If the thermal resistance of the package is given,

the size of the surrounding copper area and a proper thermal connection of the IC can reduce the thermal

resistance. To get an improved thermal behavior, it is recommended to use top layer metal to connect the device

with wide and thick metal lines. Internal ground layers can connect to vias directly under the IC for improved

thermal performance.

If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation.

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

DCS-Control^™is a trademark of Texas Instruments.

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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21-Sep-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

XPS629210DRLR

ACTIVE

SOT-5X3

DRL

4000

TBD

Call TI

-40 to 150

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS629210 :

Addendum-Page 1

PACKAGE OPTION ADDENDUM

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21-Sep-2021

Automotive : TPS629210-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

PACKAGE OUTLINE

DRL0008A

SOT-5X3 - 0.6 mm max height

PLASTIC SMALL OUTLINE

1.3

1.1

PIN 1

ID AREA

6X 0.5

2.2

2.0

2X 1.5

NOTE 3

0.27

0.17

1.7

1.5

0.05

0.00

0.1

C A B

0.05

0.6 MAX

SEATING PLANE

0.05 C

0.18

0.08

SYMM

0.4

0.2

SYMM

4224486/C 03/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, interlead flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

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EXAMPLE BOARD LAYOUT

DRL0008A

SOT-5X3 - 0.6 mm max height

PLASTIC SMALL OUTLINE

8X (0.67)

SYMM

8X (0.3)

SYMM

6X (0.5)

(R0.05) TYP

(1.48)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:30X

0.05 MIN

AROUND

0.05 MAX

AROUND

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDERMASK DETAILS

4224486/C 03/2021

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

DRL0008A

SOT-5X3 - 0.6 mm max height

PLASTIC SMALL OUTLINE

8X (0.67)

SYMM

8X (0.3)

SYMM

6X (0.5)

(R0.05) TYP

(1.48)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE:30X

4224486/C 03/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

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